[PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Alexander Stein]

Hi Marek,

Am Freitag, 16. Dezember 2022, 13:58:13 CET schrieb Marek Vasut:
> On 12/16/22 13:41, Alexander Stein wrote:
> > Hi,
> 
> Hi,
> 
> > thanks for the new update.
> > 
> > Am Mittwoch, 14. Dezember 2022, 13:58:49 CET schrieb Jagan Teki:
> >> This series supports common bridge support for Samsung MIPI DSIM
> >> which is used in Exynos and i.MX8MM SoC's.
> >> 
> >> The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.
> >> 
> >> Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge
> >> 
> >> Patch 0005 - 0006: optional PHY, PMS_P offset
> >> 
> >> Patch 0007       : introduce hw_type
> >> 
> >> Patch 0008	 : fixing host init
> >> 
> >> Patch 0009	 : atomic_check
> >> 
> >> Patch 0010	 : input_bus_flags
> >> 
> >> Patch 0011	 : atomic_get_input_bus_fmts
> >> 
> >> Patch 0012 - 0013: component vs bridge
> >> 
> >> Patch 0014	 : DSIM bridge
> >> 
> >> Patch 0015 - 0016: i.MX8M Mini/Nano
> >> 
> >> Patch 0017 - 0018: i.MX8M Plus
> > 
> > Tested using LVDS bridges and works on:
> > * imx8mp-tqma8mpql-mba8mpxl (i.MX8M Plus)
> > * imx8mm-tqma8mqml-mba8mx (i.MX8M Mini)
> > * imx8mn-tqma8mqnl-mba8mx (i.MX8M Nano)
> > 
> > But I noticed that tqma8mqml and tqma8mqnl only have a stable output if I
> > specify 'data-lanes = <0 1 2>' (not <0 1 2 3>!) on the DSI-LVDS-Bridge (TI
> > SN65DSI83) input endpoint, e.g.
> > 
> > dsi_lvds_bridge: bridge@2d {
> > 
> > 	compatible = "ti,sn65dsi83";
> > 	reg = <0x2d>;
> > 	enable-gpios = <&gpio_delays 0 130000 0>;
> > 	vcc-supply = <&reg_sn65dsi83_1v8>;
> > 	status = "okay";
> > 	ports {
> > 	
> > 		#address-cells = <1>;
> > 		#size-cells = <0>;
> > 		port@0 {
> > 		
> > 			reg = <0>;
> > 			lvds_bridge_in: endpoint {
> > 			
> > 				data-lanes = <0 1 2>;
> > 				remote-endpoint = <&mipi_dsi_out>;
> > 			
> > 			};
> > 		
> > 		};
> > 		port@2 {
> > 		
> > 			reg = <2>;
> > 			lvds_bridge_out: endpoint {
> > 			
> > 				remote-endpoint = <&panel_in_lvds0>;
> > 			
> > 			};
> > 		
> > 		};
> > 	
> > 	};
> > 
> > };
> > 
> > I have no idea if this is on the DSIM side or the DSI-LVDS bridge side.
> > Register 0xe5 on sn65dsi83 shows that CHA_LPP_ERR and CHA_SOT_BIT_ERR
> > error
> > bits are set, indicating there are low level protocol and SoT leader
> > sequence bit errors. I can't find any significant difference in sn65dsi83
> > driver compared to downstream-kernel, so I would assume something in DSIM
> > driver is different.
> 
> Make sure the HS clock rate expected by the DSI83 bridge chip and the
> one generated by the DSIM bridge from PMS PLL match. There is currently
> no negotiation of this frequency and both sides divine it on their own.
> 
> See sn65dsi83_get_dsi_range() and samsung_dsim_set_pll().

Oh, nice, thanks for the pointer. When setting
> samsung,burst-clock-frequency = <668250000>;
in imx8mm.dtsi
I get a non-flickering display using 4 lanes. Although admittedly this is just 
random guessing. I'm not sure which clock exactly has to be in the range 
CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is configured for 
205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, esc_clk 
= 16706250

AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from DT 
properties, while SN65DSI84 is using display mode and number of lanes.

Is it expected that the DSIM PLL frequencies are set in DT for a specific 
bridge/display setup?

Best regards,
Alexander

[PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Alexander Stein]

Hi Marek,

Am Freitag, 16. Dezember 2022, 13:58:13 CET schrieb Marek Vasut:
> On 12/16/22 13:41, Alexander Stein wrote:
> > Hi,
> 
> Hi,
> 
> > thanks for the new update.
> > 
> > Am Mittwoch, 14. Dezember 2022, 13:58:49 CET schrieb Jagan Teki:
> >> This series supports common bridge support for Samsung MIPI DSIM
> >> which is used in Exynos and i.MX8MM SoC's.
> >> 
> >> The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.
> >> 
> >> Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge
> >> 
> >> Patch 0005 - 0006: optional PHY, PMS_P offset
> >> 
> >> Patch 0007       : introduce hw_type
> >> 
> >> Patch 0008	 : fixing host init
> >> 
> >> Patch 0009	 : atomic_check
> >> 
> >> Patch 0010	 : input_bus_flags
> >> 
> >> Patch 0011	 : atomic_get_input_bus_fmts
> >> 
> >> Patch 0012 - 0013: component vs bridge
> >> 
> >> Patch 0014	 : DSIM bridge
> >> 
> >> Patch 0015 - 0016: i.MX8M Mini/Nano
> >> 
> >> Patch 0017 - 0018: i.MX8M Plus
> > 
> > Tested using LVDS bridges and works on:
> > * imx8mp-tqma8mpql-mba8mpxl (i.MX8M Plus)
> > * imx8mm-tqma8mqml-mba8mx (i.MX8M Mini)
> > * imx8mn-tqma8mqnl-mba8mx (i.MX8M Nano)
> > 
> > But I noticed that tqma8mqml and tqma8mqnl only have a stable output if I
> > specify 'data-lanes = <0 1 2>' (not <0 1 2 3>!) on the DSI-LVDS-Bridge (TI
> > SN65DSI83) input endpoint, e.g.
> > 
> > dsi_lvds_bridge: bridge@2d {
> > 
> > 	compatible = "ti,sn65dsi83";
> > 	reg = <0x2d>;
> > 	enable-gpios = <&gpio_delays 0 130000 0>;
> > 	vcc-supply = <&reg_sn65dsi83_1v8>;
> > 	status = "okay";
> > 	ports {
> > 	
> > 		#address-cells = <1>;
> > 		#size-cells = <0>;
> > 		port@0 {
> > 		
> > 			reg = <0>;
> > 			lvds_bridge_in: endpoint {
> > 			
> > 				data-lanes = <0 1 2>;
> > 				remote-endpoint = <&mipi_dsi_out>;
> > 			
> > 			};
> > 		
> > 		};
> > 		port@2 {
> > 		
> > 			reg = <2>;
> > 			lvds_bridge_out: endpoint {
> > 			
> > 				remote-endpoint = <&panel_in_lvds0>;
> > 			
> > 			};
> > 		
> > 		};
> > 	
> > 	};
> > 
> > };
> > 
> > I have no idea if this is on the DSIM side or the DSI-LVDS bridge side.
> > Register 0xe5 on sn65dsi83 shows that CHA_LPP_ERR and CHA_SOT_BIT_ERR
> > error
> > bits are set, indicating there are low level protocol and SoT leader
> > sequence bit errors. I can't find any significant difference in sn65dsi83
> > driver compared to downstream-kernel, so I would assume something in DSIM
> > driver is different.
> 
> Make sure the HS clock rate expected by the DSI83 bridge chip and the
> one generated by the DSIM bridge from PMS PLL match. There is currently
> no negotiation of this frequency and both sides divine it on their own.
> 
> See sn65dsi83_get_dsi_range() and samsung_dsim_set_pll().

Oh, nice, thanks for the pointer. When setting
> samsung,burst-clock-frequency = <668250000>;
in imx8mm.dtsi
I get a non-flickering display using 4 lanes. Although admittedly this is just 
random guessing. I'm not sure which clock exactly has to be in the range 
CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is configured for 
205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, esc_clk 
= 16706250

AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from DT 
properties, while SN65DSI84 is using display mode and number of lanes.

Is it expected that the DSIM PLL frequencies are set in DT for a specific 
bridge/display setup?

Best regards,
Alexander

[PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Alexander Stein]

Hi Marek,

Am Freitag, 16. Dezember 2022, 13:58:13 CET schrieb Marek Vasut:
> On 12/16/22 13:41, Alexander Stein wrote:
> > Hi,
> 
> Hi,
> 
> > thanks for the new update.
> > 
> > Am Mittwoch, 14. Dezember 2022, 13:58:49 CET schrieb Jagan Teki:
> >> This series supports common bridge support for Samsung MIPI DSIM
> >> which is used in Exynos and i.MX8MM SoC's.
> >> 
> >> The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.
> >> 
> >> Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge
> >> 
> >> Patch 0005 - 0006: optional PHY, PMS_P offset
> >> 
> >> Patch 0007       : introduce hw_type
> >> 
> >> Patch 0008	 : fixing host init
> >> 
> >> Patch 0009	 : atomic_check
> >> 
> >> Patch 0010	 : input_bus_flags
> >> 
> >> Patch 0011	 : atomic_get_input_bus_fmts
> >> 
> >> Patch 0012 - 0013: component vs bridge
> >> 
> >> Patch 0014	 : DSIM bridge
> >> 
> >> Patch 0015 - 0016: i.MX8M Mini/Nano
> >> 
> >> Patch 0017 - 0018: i.MX8M Plus
> > 
> > Tested using LVDS bridges and works on:
> > * imx8mp-tqma8mpql-mba8mpxl (i.MX8M Plus)
> > * imx8mm-tqma8mqml-mba8mx (i.MX8M Mini)
> > * imx8mn-tqma8mqnl-mba8mx (i.MX8M Nano)
> > 
> > But I noticed that tqma8mqml and tqma8mqnl only have a stable output if I
> > specify 'data-lanes = <0 1 2>' (not <0 1 2 3>!) on the DSI-LVDS-Bridge (TI
> > SN65DSI83) input endpoint, e.g.
> > 
> > dsi_lvds_bridge: bridge@2d {
> > 
> > 	compatible = "ti,sn65dsi83";
> > 	reg = <0x2d>;
> > 	enable-gpios = <&gpio_delays 0 130000 0>;
> > 	vcc-supply = <&reg_sn65dsi83_1v8>;
> > 	status = "okay";
> > 	ports {
> > 	
> > 		#address-cells = <1>;
> > 		#size-cells = <0>;
> > 		port@0 {
> > 		
> > 			reg = <0>;
> > 			lvds_bridge_in: endpoint {
> > 			
> > 				data-lanes = <0 1 2>;
> > 				remote-endpoint = <&mipi_dsi_out>;
> > 			
> > 			};
> > 		
> > 		};
> > 		port@2 {
> > 		
> > 			reg = <2>;
> > 			lvds_bridge_out: endpoint {
> > 			
> > 				remote-endpoint = <&panel_in_lvds0>;
> > 			
> > 			};
> > 		
> > 		};
> > 	
> > 	};
> > 
> > };
> > 
> > I have no idea if this is on the DSIM side or the DSI-LVDS bridge side.
> > Register 0xe5 on sn65dsi83 shows that CHA_LPP_ERR and CHA_SOT_BIT_ERR
> > error
> > bits are set, indicating there are low level protocol and SoT leader
> > sequence bit errors. I can't find any significant difference in sn65dsi83
> > driver compared to downstream-kernel, so I would assume something in DSIM
> > driver is different.
> 
> Make sure the HS clock rate expected by the DSI83 bridge chip and the
> one generated by the DSIM bridge from PMS PLL match. There is currently
> no negotiation of this frequency and both sides divine it on their own.
> 
> See sn65dsi83_get_dsi_range() and samsung_dsim_set_pll().

Oh, nice, thanks for the pointer. When setting
> samsung,burst-clock-frequency = <668250000>;
in imx8mm.dtsi
I get a non-flickering display using 4 lanes. Although admittedly this is just 
random guessing. I'm not sure which clock exactly has to be in the range 
CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is configured for 
205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, esc_clk 
= 16706250

AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from DT 
properties, while SN65DSI84 is using display mode and number of lanes.

Is it expected that the DSIM PLL frequencies are set in DT for a specific 
bridge/display setup?

Best regards,
Alexander


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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 12/16/22 14:25, Alexander Stein wrote:
Hi,

[...]

> Oh, nice, thanks for the pointer. When setting
>> samsung,burst-clock-frequency = <668250000>;
> in imx8mm.dtsi
> I get a non-flickering display using 4 lanes. Although admittedly this is just
> random guessing. I'm not sure which clock exactly has to be in the range
> CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is configured for
> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, esc_clk
> = 16706250

If I recall it right, minimum PLL frequency is:

fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz

the link frequency is then

fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)

So DSI83 should be in the range of 80..85 MHz input clock if I calculate 
this right. Can you check what is the value of mode->clock, the 
mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83 
sm65dsi83_get_dsi_range() ?

> AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from DT
> properties, while SN65DSI84 is using display mode and number of lanes.
> 
> Is it expected that the DSIM PLL frequencies are set in DT for a specific
> bridge/display setup?

No, there should be negotiation between the host and bridge/panel, I 
tried to propose two variants, but they were all rejected.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 12/16/22 14:25, Alexander Stein wrote:
Hi,

[...]

> Oh, nice, thanks for the pointer. When setting
>> samsung,burst-clock-frequency = <668250000>;
> in imx8mm.dtsi
> I get a non-flickering display using 4 lanes. Although admittedly this is just
> random guessing. I'm not sure which clock exactly has to be in the range
> CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is configured for
> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, esc_clk
> = 16706250

If I recall it right, minimum PLL frequency is:

fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz

the link frequency is then

fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)

So DSI83 should be in the range of 80..85 MHz input clock if I calculate 
this right. Can you check what is the value of mode->clock, the 
mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83 
sm65dsi83_get_dsi_range() ?

> AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from DT
> properties, while SN65DSI84 is using display mode and number of lanes.
> 
> Is it expected that the DSIM PLL frequencies are set in DT for a specific
> bridge/display setup?

No, there should be negotiation between the host and bridge/panel, I 
tried to propose two variants, but they were all rejected.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 12/16/22 14:25, Alexander Stein wrote:
Hi,

[...]

> Oh, nice, thanks for the pointer. When setting
>> samsung,burst-clock-frequency = <668250000>;
> in imx8mm.dtsi
> I get a non-flickering display using 4 lanes. Although admittedly this is just
> random guessing. I'm not sure which clock exactly has to be in the range
> CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is configured for
> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, esc_clk
> = 16706250

If I recall it right, minimum PLL frequency is:

fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz

the link frequency is then

fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)

So DSI83 should be in the range of 80..85 MHz input clock if I calculate 
this right. Can you check what is the value of mode->clock, the 
mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83 
sm65dsi83_get_dsi_range() ?

> AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from DT
> properties, while SN65DSI84 is using display mode and number of lanes.
> 
> Is it expected that the DSIM PLL frequencies are set in DT for a specific
> bridge/display setup?

No, there should be negotiation between the host and bridge/panel, I 
tried to propose two variants, but they were all rejected.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Adam Ford]

On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
>
> On 12/16/22 14:25, Alexander Stein wrote:
> Hi,
>
> [...]
>
> > Oh, nice, thanks for the pointer. When setting
> >> samsung,burst-clock-frequency = <668250000>;
> > in imx8mm.dtsi
> > I get a non-flickering display using 4 lanes. Although admittedly this is just
> > random guessing. I'm not sure which clock exactly has to be in the range
> > CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is configured for
> > 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
> >> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
> >> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, esc_clk
> > = 16706250
>
> If I recall it right, minimum PLL frequency is:
>
> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
>
> the link frequency is then
>
> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
>
> So DSI83 should be in the range of 80..85 MHz input clock if I calculate
> this right. Can you check what is the value of mode->clock, the
> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
> sm65dsi83_get_dsi_range() ?
>
> > AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from DT
> > properties, while SN65DSI84 is using display mode and number of lanes.
> >
> > Is it expected that the DSIM PLL frequencies are set in DT for a specific
> > bridge/display setup?
>
> No, there should be negotiation between the host and bridge/panel, I
> tried to propose two variants, but they were all rejected.

For one of Jagan's previous revisions, I added some code to let the
PHY auto adjust the frequencies instead of being fixed.  NXP had this
in their downstream kernel, but with this patch and another, I was
able to set a variety of pixel clocks from my HDMI monitor and my
DSI83. I haven't had time to re-base my work on Jagan's latest work,
but you can link to the patch I did for the older stuff here:

https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb88ab4b67e4
and
https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef639813475241936f

I've been traveling a lot lately, so I haven't had time to evaluate
his series, but I hope to get something like those re-based once the
DSI stuff has been accepted.

adam

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Adam Ford]

On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
>
> On 12/16/22 14:25, Alexander Stein wrote:
> Hi,
>
> [...]
>
> > Oh, nice, thanks for the pointer. When setting
> >> samsung,burst-clock-frequency = <668250000>;
> > in imx8mm.dtsi
> > I get a non-flickering display using 4 lanes. Although admittedly this is just
> > random guessing. I'm not sure which clock exactly has to be in the range
> > CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is configured for
> > 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
> >> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
> >> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, esc_clk
> > = 16706250
>
> If I recall it right, minimum PLL frequency is:
>
> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
>
> the link frequency is then
>
> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
>
> So DSI83 should be in the range of 80..85 MHz input clock if I calculate
> this right. Can you check what is the value of mode->clock, the
> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
> sm65dsi83_get_dsi_range() ?
>
> > AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from DT
> > properties, while SN65DSI84 is using display mode and number of lanes.
> >
> > Is it expected that the DSIM PLL frequencies are set in DT for a specific
> > bridge/display setup?
>
> No, there should be negotiation between the host and bridge/panel, I
> tried to propose two variants, but they were all rejected.

For one of Jagan's previous revisions, I added some code to let the
PHY auto adjust the frequencies instead of being fixed.  NXP had this
in their downstream kernel, but with this patch and another, I was
able to set a variety of pixel clocks from my HDMI monitor and my
DSI83. I haven't had time to re-base my work on Jagan's latest work,
but you can link to the patch I did for the older stuff here:

https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb88ab4b67e4
and
https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef639813475241936f

I've been traveling a lot lately, so I haven't had time to evaluate
his series, but I hope to get something like those re-based once the
DSI stuff has been accepted.

adam

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Adam Ford]

On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
>
> On 12/16/22 14:25, Alexander Stein wrote:
> Hi,
>
> [...]
>
> > Oh, nice, thanks for the pointer. When setting
> >> samsung,burst-clock-frequency = <668250000>;
> > in imx8mm.dtsi
> > I get a non-flickering display using 4 lanes. Although admittedly this is just
> > random guessing. I'm not sure which clock exactly has to be in the range
> > CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is configured for
> > 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
> >> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
> >> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, esc_clk
> > = 16706250
>
> If I recall it right, minimum PLL frequency is:
>
> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
>
> the link frequency is then
>
> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
>
> So DSI83 should be in the range of 80..85 MHz input clock if I calculate
> this right. Can you check what is the value of mode->clock, the
> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
> sm65dsi83_get_dsi_range() ?
>
> > AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from DT
> > properties, while SN65DSI84 is using display mode and number of lanes.
> >
> > Is it expected that the DSIM PLL frequencies are set in DT for a specific
> > bridge/display setup?
>
> No, there should be negotiation between the host and bridge/panel, I
> tried to propose two variants, but they were all rejected.

For one of Jagan's previous revisions, I added some code to let the
PHY auto adjust the frequencies instead of being fixed.  NXP had this
in their downstream kernel, but with this patch and another, I was
able to set a variety of pixel clocks from my HDMI monitor and my
DSI83. I haven't had time to re-base my work on Jagan's latest work,
but you can link to the patch I did for the older stuff here:

https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb88ab4b67e4
and
https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef639813475241936f

I've been traveling a lot lately, so I haven't had time to evaluate
his series, but I hope to get something like those re-based once the
DSI stuff has been accepted.

adam

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 12/18/22 05:23, Adam Ford wrote:
> On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 12/16/22 14:25, Alexander Stein wrote:
>> Hi,
>>
>> [...]
>>
>>> Oh, nice, thanks for the pointer. When setting
>>>> samsung,burst-clock-frequency = <668250000>;
>>> in imx8mm.dtsi
>>> I get a non-flickering display using 4 lanes. Although admittedly this is just
>>> random guessing. I'm not sure which clock exactly has to be in the range
>>> CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is configured for
>>> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
>>>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
>>>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, esc_clk
>>> = 16706250
>>
>> If I recall it right, minimum PLL frequency is:
>>
>> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
>>
>> the link frequency is then
>>
>> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
>>
>> So DSI83 should be in the range of 80..85 MHz input clock if I calculate
>> this right. Can you check what is the value of mode->clock, the
>> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
>> sm65dsi83_get_dsi_range() ?
>>
>>> AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from DT
>>> properties, while SN65DSI84 is using display mode and number of lanes.
>>>
>>> Is it expected that the DSIM PLL frequencies are set in DT for a specific
>>> bridge/display setup?
>>
>> No, there should be negotiation between the host and bridge/panel, I
>> tried to propose two variants, but they were all rejected.
> 
> For one of Jagan's previous revisions, I added some code to let the
> PHY auto adjust the frequencies instead of being fixed.  NXP had this
> in their downstream kernel, but with this patch and another, I was
> able to set a variety of pixel clocks from my HDMI monitor and my
> DSI83. I haven't had time to re-base my work on Jagan's latest work,
> but you can link to the patch I did for the older stuff here:
> 
> https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb88ab4b67e4
> and
> https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef639813475241936f
> 
> I've been traveling a lot lately, so I haven't had time to evaluate
> his series, but I hope to get something like those re-based once the
> DSI stuff has been accepted.

I have these two attempts, both rejected:

https://patchwork.freedesktop.org/patch/475207/
https://patchwork.freedesktop.org/patch/496049/

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 12/18/22 05:23, Adam Ford wrote:
> On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 12/16/22 14:25, Alexander Stein wrote:
>> Hi,
>>
>> [...]
>>
>>> Oh, nice, thanks for the pointer. When setting
>>>> samsung,burst-clock-frequency = <668250000>;
>>> in imx8mm.dtsi
>>> I get a non-flickering display using 4 lanes. Although admittedly this is just
>>> random guessing. I'm not sure which clock exactly has to be in the range
>>> CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is configured for
>>> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
>>>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
>>>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, esc_clk
>>> = 16706250
>>
>> If I recall it right, minimum PLL frequency is:
>>
>> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
>>
>> the link frequency is then
>>
>> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
>>
>> So DSI83 should be in the range of 80..85 MHz input clock if I calculate
>> this right. Can you check what is the value of mode->clock, the
>> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
>> sm65dsi83_get_dsi_range() ?
>>
>>> AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from DT
>>> properties, while SN65DSI84 is using display mode and number of lanes.
>>>
>>> Is it expected that the DSIM PLL frequencies are set in DT for a specific
>>> bridge/display setup?
>>
>> No, there should be negotiation between the host and bridge/panel, I
>> tried to propose two variants, but they were all rejected.
> 
> For one of Jagan's previous revisions, I added some code to let the
> PHY auto adjust the frequencies instead of being fixed.  NXP had this
> in their downstream kernel, but with this patch and another, I was
> able to set a variety of pixel clocks from my HDMI monitor and my
> DSI83. I haven't had time to re-base my work on Jagan's latest work,
> but you can link to the patch I did for the older stuff here:
> 
> https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb88ab4b67e4
> and
> https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef639813475241936f
> 
> I've been traveling a lot lately, so I haven't had time to evaluate
> his series, but I hope to get something like those re-based once the
> DSI stuff has been accepted.

I have these two attempts, both rejected:

https://patchwork.freedesktop.org/patch/475207/
https://patchwork.freedesktop.org/patch/496049/

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 12/18/22 05:23, Adam Ford wrote:
> On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 12/16/22 14:25, Alexander Stein wrote:
>> Hi,
>>
>> [...]
>>
>>> Oh, nice, thanks for the pointer. When setting
>>>> samsung,burst-clock-frequency = <668250000>;
>>> in imx8mm.dtsi
>>> I get a non-flickering display using 4 lanes. Although admittedly this is just
>>> random guessing. I'm not sure which clock exactly has to be in the range
>>> CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is configured for
>>> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
>>>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
>>>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, esc_clk
>>> = 16706250
>>
>> If I recall it right, minimum PLL frequency is:
>>
>> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
>>
>> the link frequency is then
>>
>> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
>>
>> So DSI83 should be in the range of 80..85 MHz input clock if I calculate
>> this right. Can you check what is the value of mode->clock, the
>> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
>> sm65dsi83_get_dsi_range() ?
>>
>>> AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from DT
>>> properties, while SN65DSI84 is using display mode and number of lanes.
>>>
>>> Is it expected that the DSIM PLL frequencies are set in DT for a specific
>>> bridge/display setup?
>>
>> No, there should be negotiation between the host and bridge/panel, I
>> tried to propose two variants, but they were all rejected.
> 
> For one of Jagan's previous revisions, I added some code to let the
> PHY auto adjust the frequencies instead of being fixed.  NXP had this
> in their downstream kernel, but with this patch and another, I was
> able to set a variety of pixel clocks from my HDMI monitor and my
> DSI83. I haven't had time to re-base my work on Jagan's latest work,
> but you can link to the patch I did for the older stuff here:
> 
> https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb88ab4b67e4
> and
> https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef639813475241936f
> 
> I've been traveling a lot lately, so I haven't had time to evaluate
> his series, but I hope to get something like those re-based once the
> DSI stuff has been accepted.

I have these two attempts, both rejected:

https://patchwork.freedesktop.org/patch/475207/
https://patchwork.freedesktop.org/patch/496049/

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Adam Ford]

On Sat, Dec 17, 2022 at 10:33 PM Marek Vasut <marex@denx.de> wrote:
>
> On 12/18/22 05:23, Adam Ford wrote:
> > On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 12/16/22 14:25, Alexander Stein wrote:
> >> Hi,
> >>
> >> [...]
> >>
> >>> Oh, nice, thanks for the pointer. When setting
> >>>> samsung,burst-clock-frequency = <668250000>;
> >>> in imx8mm.dtsi
> >>> I get a non-flickering display using 4 lanes. Although admittedly this is just
> >>> random guessing. I'm not sure which clock exactly has to be in the range
> >>> CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is configured for
> >>> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
> >>>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
> >>>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, esc_clk
> >>> = 16706250
> >>
> >> If I recall it right, minimum PLL frequency is:
> >>
> >> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
> >>
> >> the link frequency is then
> >>
> >> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
> >>
> >> So DSI83 should be in the range of 80..85 MHz input clock if I calculate
> >> this right. Can you check what is the value of mode->clock, the
> >> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
> >> sm65dsi83_get_dsi_range() ?
> >>
> >>> AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from DT
> >>> properties, while SN65DSI84 is using display mode and number of lanes.
> >>>
> >>> Is it expected that the DSIM PLL frequencies are set in DT for a specific
> >>> bridge/display setup?
> >>
> >> No, there should be negotiation between the host and bridge/panel, I
> >> tried to propose two variants, but they were all rejected.
> >
> > For one of Jagan's previous revisions, I added some code to let the
> > PHY auto adjust the frequencies instead of being fixed.  NXP had this
> > in their downstream kernel, but with this patch and another, I was
> > able to set a variety of pixel clocks from my HDMI monitor and my
> > DSI83. I haven't had time to re-base my work on Jagan's latest work,
> > but you can link to the patch I did for the older stuff here:
> >
> > https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb88ab4b67e4
> > and
> > https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef639813475241936f
> >
> > I've been traveling a lot lately, so I haven't had time to evaluate
> > his series, but I hope to get something like those re-based once the
> > DSI stuff has been accepted.
>
> I have these two attempts, both rejected:
>
> https://patchwork.freedesktop.org/patch/475207/
> https://patchwork.freedesktop.org/patch/496049/

I have some patches re-based to Jagan's latest branch.  It doesn't
impact any drivers other than the new samsung-dsim driver, and it
doesn't touch any of the drm helper functions either.  It adjusts hs
clock based on the connected device.  I am not sure what the impact
will have on the attached Exynos devices, so I am expecting some
iterations.  Right now it's working with my DSI83 chip, but I need to
get it working with my adv7535 part as well.  On the older branch, I
was able to sync the ad7535 with a variety of resolutions using
different pixel clock rates.

Once I get it working again with my adv7535 and cleaned up, I'll
submit the patches to the drm group, and I'll CC you, Jagan and Marek
Szyprowski with a reference to Jagan's series so people wanting to try
it can apply it to his branch.

adam

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Adam Ford]

On Sat, Dec 17, 2022 at 10:33 PM Marek Vasut <marex@denx.de> wrote:
>
> On 12/18/22 05:23, Adam Ford wrote:
> > On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 12/16/22 14:25, Alexander Stein wrote:
> >> Hi,
> >>
> >> [...]
> >>
> >>> Oh, nice, thanks for the pointer. When setting
> >>>> samsung,burst-clock-frequency = <668250000>;
> >>> in imx8mm.dtsi
> >>> I get a non-flickering display using 4 lanes. Although admittedly this is just
> >>> random guessing. I'm not sure which clock exactly has to be in the range
> >>> CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is configured for
> >>> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
> >>>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
> >>>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, esc_clk
> >>> = 16706250
> >>
> >> If I recall it right, minimum PLL frequency is:
> >>
> >> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
> >>
> >> the link frequency is then
> >>
> >> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
> >>
> >> So DSI83 should be in the range of 80..85 MHz input clock if I calculate
> >> this right. Can you check what is the value of mode->clock, the
> >> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
> >> sm65dsi83_get_dsi_range() ?
> >>
> >>> AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from DT
> >>> properties, while SN65DSI84 is using display mode and number of lanes.
> >>>
> >>> Is it expected that the DSIM PLL frequencies are set in DT for a specific
> >>> bridge/display setup?
> >>
> >> No, there should be negotiation between the host and bridge/panel, I
> >> tried to propose two variants, but they were all rejected.
> >
> > For one of Jagan's previous revisions, I added some code to let the
> > PHY auto adjust the frequencies instead of being fixed.  NXP had this
> > in their downstream kernel, but with this patch and another, I was
> > able to set a variety of pixel clocks from my HDMI monitor and my
> > DSI83. I haven't had time to re-base my work on Jagan's latest work,
> > but you can link to the patch I did for the older stuff here:
> >
> > https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb88ab4b67e4
> > and
> > https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef639813475241936f
> >
> > I've been traveling a lot lately, so I haven't had time to evaluate
> > his series, but I hope to get something like those re-based once the
> > DSI stuff has been accepted.
>
> I have these two attempts, both rejected:
>
> https://patchwork.freedesktop.org/patch/475207/
> https://patchwork.freedesktop.org/patch/496049/

I have some patches re-based to Jagan's latest branch.  It doesn't
impact any drivers other than the new samsung-dsim driver, and it
doesn't touch any of the drm helper functions either.  It adjusts hs
clock based on the connected device.  I am not sure what the impact
will have on the attached Exynos devices, so I am expecting some
iterations.  Right now it's working with my DSI83 chip, but I need to
get it working with my adv7535 part as well.  On the older branch, I
was able to sync the ad7535 with a variety of resolutions using
different pixel clock rates.

Once I get it working again with my adv7535 and cleaned up, I'll
submit the patches to the drm group, and I'll CC you, Jagan and Marek
Szyprowski with a reference to Jagan's series so people wanting to try
it can apply it to his branch.

adam

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Adam Ford]

On Sat, Dec 17, 2022 at 10:33 PM Marek Vasut <marex@denx.de> wrote:
>
> On 12/18/22 05:23, Adam Ford wrote:
> > On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 12/16/22 14:25, Alexander Stein wrote:
> >> Hi,
> >>
> >> [...]
> >>
> >>> Oh, nice, thanks for the pointer. When setting
> >>>> samsung,burst-clock-frequency = <668250000>;
> >>> in imx8mm.dtsi
> >>> I get a non-flickering display using 4 lanes. Although admittedly this is just
> >>> random guessing. I'm not sure which clock exactly has to be in the range
> >>> CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is configured for
> >>> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
> >>>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
> >>>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, esc_clk
> >>> = 16706250
> >>
> >> If I recall it right, minimum PLL frequency is:
> >>
> >> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
> >>
> >> the link frequency is then
> >>
> >> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
> >>
> >> So DSI83 should be in the range of 80..85 MHz input clock if I calculate
> >> this right. Can you check what is the value of mode->clock, the
> >> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
> >> sm65dsi83_get_dsi_range() ?
> >>
> >>> AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from DT
> >>> properties, while SN65DSI84 is using display mode and number of lanes.
> >>>
> >>> Is it expected that the DSIM PLL frequencies are set in DT for a specific
> >>> bridge/display setup?
> >>
> >> No, there should be negotiation between the host and bridge/panel, I
> >> tried to propose two variants, but they were all rejected.
> >
> > For one of Jagan's previous revisions, I added some code to let the
> > PHY auto adjust the frequencies instead of being fixed.  NXP had this
> > in their downstream kernel, but with this patch and another, I was
> > able to set a variety of pixel clocks from my HDMI monitor and my
> > DSI83. I haven't had time to re-base my work on Jagan's latest work,
> > but you can link to the patch I did for the older stuff here:
> >
> > https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb88ab4b67e4
> > and
> > https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef639813475241936f
> >
> > I've been traveling a lot lately, so I haven't had time to evaluate
> > his series, but I hope to get something like those re-based once the
> > DSI stuff has been accepted.
>
> I have these two attempts, both rejected:
>
> https://patchwork.freedesktop.org/patch/475207/
> https://patchwork.freedesktop.org/patch/496049/

I have some patches re-based to Jagan's latest branch.  It doesn't
impact any drivers other than the new samsung-dsim driver, and it
doesn't touch any of the drm helper functions either.  It adjusts hs
clock based on the connected device.  I am not sure what the impact
will have on the attached Exynos devices, so I am expecting some
iterations.  Right now it's working with my DSI83 chip, but I need to
get it working with my adv7535 part as well.  On the older branch, I
was able to sync the ad7535 with a variety of resolutions using
different pixel clock rates.

Once I get it working again with my adv7535 and cleaned up, I'll
submit the patches to the drm group, and I'll CC you, Jagan and Marek
Szyprowski with a reference to Jagan's series so people wanting to try
it can apply it to his branch.

adam

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 12/18/22 23:24, Adam Ford wrote:
> On Sat, Dec 17, 2022 at 10:33 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 12/18/22 05:23, Adam Ford wrote:
>>> On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
>>>>
>>>> On 12/16/22 14:25, Alexander Stein wrote:
>>>> Hi,
>>>>
>>>> [...]
>>>>
>>>>> Oh, nice, thanks for the pointer. When setting
>>>>>> samsung,burst-clock-frequency = <668250000>;
>>>>> in imx8mm.dtsi
>>>>> I get a non-flickering display using 4 lanes. Although admittedly this is just
>>>>> random guessing. I'm not sure which clock exactly has to be in the range
>>>>> CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is configured for
>>>>> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
>>>>>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
>>>>>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, esc_clk
>>>>> = 16706250
>>>>
>>>> If I recall it right, minimum PLL frequency is:
>>>>
>>>> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
>>>>
>>>> the link frequency is then
>>>>
>>>> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
>>>>
>>>> So DSI83 should be in the range of 80..85 MHz input clock if I calculate
>>>> this right. Can you check what is the value of mode->clock, the
>>>> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
>>>> sm65dsi83_get_dsi_range() ?
>>>>
>>>>> AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from DT
>>>>> properties, while SN65DSI84 is using display mode and number of lanes.
>>>>>
>>>>> Is it expected that the DSIM PLL frequencies are set in DT for a specific
>>>>> bridge/display setup?
>>>>
>>>> No, there should be negotiation between the host and bridge/panel, I
>>>> tried to propose two variants, but they were all rejected.
>>>
>>> For one of Jagan's previous revisions, I added some code to let the
>>> PHY auto adjust the frequencies instead of being fixed.  NXP had this
>>> in their downstream kernel, but with this patch and another, I was
>>> able to set a variety of pixel clocks from my HDMI monitor and my
>>> DSI83. I haven't had time to re-base my work on Jagan's latest work,
>>> but you can link to the patch I did for the older stuff here:
>>>
>>> https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb88ab4b67e4
>>> and
>>> https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef639813475241936f
>>>
>>> I've been traveling a lot lately, so I haven't had time to evaluate
>>> his series, but I hope to get something like those re-based once the
>>> DSI stuff has been accepted.
>>
>> I have these two attempts, both rejected:
>>
>> https://patchwork.freedesktop.org/patch/475207/
>> https://patchwork.freedesktop.org/patch/496049/
> 
> I have some patches re-based to Jagan's latest branch.  It doesn't
> impact any drivers other than the new samsung-dsim driver, and it
> doesn't touch any of the drm helper functions either.  It adjusts hs
> clock based on the connected device.  I am not sure what the impact
> will have on the attached Exynos devices, so I am expecting some
> iterations.  Right now it's working with my DSI83 chip, but I need to
> get it working with my adv7535 part as well.  On the older branch, I
> was able to sync the ad7535 with a variety of resolutions using
> different pixel clock rates.
> 
> Once I get it working again with my adv7535 and cleaned up, I'll
> submit the patches to the drm group, and I'll CC you, Jagan and Marek
> Szyprowski with a reference to Jagan's series so people wanting to try
> it can apply it to his branch.

The negotiation has to happen between the host and the bridge/panel, 
otherwise you won't be able to support bridge/panel devices which 
require specific clock rate on the DSI. Only the bridge/panel driver 
knows about such requirement.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 12/18/22 23:24, Adam Ford wrote:
> On Sat, Dec 17, 2022 at 10:33 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 12/18/22 05:23, Adam Ford wrote:
>>> On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
>>>>
>>>> On 12/16/22 14:25, Alexander Stein wrote:
>>>> Hi,
>>>>
>>>> [...]
>>>>
>>>>> Oh, nice, thanks for the pointer. When setting
>>>>>> samsung,burst-clock-frequency = <668250000>;
>>>>> in imx8mm.dtsi
>>>>> I get a non-flickering display using 4 lanes. Although admittedly this is just
>>>>> random guessing. I'm not sure which clock exactly has to be in the range
>>>>> CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is configured for
>>>>> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
>>>>>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
>>>>>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, esc_clk
>>>>> = 16706250
>>>>
>>>> If I recall it right, minimum PLL frequency is:
>>>>
>>>> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
>>>>
>>>> the link frequency is then
>>>>
>>>> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
>>>>
>>>> So DSI83 should be in the range of 80..85 MHz input clock if I calculate
>>>> this right. Can you check what is the value of mode->clock, the
>>>> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
>>>> sm65dsi83_get_dsi_range() ?
>>>>
>>>>> AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from DT
>>>>> properties, while SN65DSI84 is using display mode and number of lanes.
>>>>>
>>>>> Is it expected that the DSIM PLL frequencies are set in DT for a specific
>>>>> bridge/display setup?
>>>>
>>>> No, there should be negotiation between the host and bridge/panel, I
>>>> tried to propose two variants, but they were all rejected.
>>>
>>> For one of Jagan's previous revisions, I added some code to let the
>>> PHY auto adjust the frequencies instead of being fixed.  NXP had this
>>> in their downstream kernel, but with this patch and another, I was
>>> able to set a variety of pixel clocks from my HDMI monitor and my
>>> DSI83. I haven't had time to re-base my work on Jagan's latest work,
>>> but you can link to the patch I did for the older stuff here:
>>>
>>> https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb88ab4b67e4
>>> and
>>> https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef639813475241936f
>>>
>>> I've been traveling a lot lately, so I haven't had time to evaluate
>>> his series, but I hope to get something like those re-based once the
>>> DSI stuff has been accepted.
>>
>> I have these two attempts, both rejected:
>>
>> https://patchwork.freedesktop.org/patch/475207/
>> https://patchwork.freedesktop.org/patch/496049/
> 
> I have some patches re-based to Jagan's latest branch.  It doesn't
> impact any drivers other than the new samsung-dsim driver, and it
> doesn't touch any of the drm helper functions either.  It adjusts hs
> clock based on the connected device.  I am not sure what the impact
> will have on the attached Exynos devices, so I am expecting some
> iterations.  Right now it's working with my DSI83 chip, but I need to
> get it working with my adv7535 part as well.  On the older branch, I
> was able to sync the ad7535 with a variety of resolutions using
> different pixel clock rates.
> 
> Once I get it working again with my adv7535 and cleaned up, I'll
> submit the patches to the drm group, and I'll CC you, Jagan and Marek
> Szyprowski with a reference to Jagan's series so people wanting to try
> it can apply it to his branch.

The negotiation has to happen between the host and the bridge/panel, 
otherwise you won't be able to support bridge/panel devices which 
require specific clock rate on the DSI. Only the bridge/panel driver 
knows about such requirement.

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linux-arm-kernel mailing list
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 12/18/22 23:24, Adam Ford wrote:
> On Sat, Dec 17, 2022 at 10:33 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 12/18/22 05:23, Adam Ford wrote:
>>> On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
>>>>
>>>> On 12/16/22 14:25, Alexander Stein wrote:
>>>> Hi,
>>>>
>>>> [...]
>>>>
>>>>> Oh, nice, thanks for the pointer. When setting
>>>>>> samsung,burst-clock-frequency = <668250000>;
>>>>> in imx8mm.dtsi
>>>>> I get a non-flickering display using 4 lanes. Although admittedly this is just
>>>>> random guessing. I'm not sure which clock exactly has to be in the range
>>>>> CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is configured for
>>>>> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
>>>>>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
>>>>>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, esc_clk
>>>>> = 16706250
>>>>
>>>> If I recall it right, minimum PLL frequency is:
>>>>
>>>> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
>>>>
>>>> the link frequency is then
>>>>
>>>> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
>>>>
>>>> So DSI83 should be in the range of 80..85 MHz input clock if I calculate
>>>> this right. Can you check what is the value of mode->clock, the
>>>> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
>>>> sm65dsi83_get_dsi_range() ?
>>>>
>>>>> AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from DT
>>>>> properties, while SN65DSI84 is using display mode and number of lanes.
>>>>>
>>>>> Is it expected that the DSIM PLL frequencies are set in DT for a specific
>>>>> bridge/display setup?
>>>>
>>>> No, there should be negotiation between the host and bridge/panel, I
>>>> tried to propose two variants, but they were all rejected.
>>>
>>> For one of Jagan's previous revisions, I added some code to let the
>>> PHY auto adjust the frequencies instead of being fixed.  NXP had this
>>> in their downstream kernel, but with this patch and another, I was
>>> able to set a variety of pixel clocks from my HDMI monitor and my
>>> DSI83. I haven't had time to re-base my work on Jagan's latest work,
>>> but you can link to the patch I did for the older stuff here:
>>>
>>> https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb88ab4b67e4
>>> and
>>> https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef639813475241936f
>>>
>>> I've been traveling a lot lately, so I haven't had time to evaluate
>>> his series, but I hope to get something like those re-based once the
>>> DSI stuff has been accepted.
>>
>> I have these two attempts, both rejected:
>>
>> https://patchwork.freedesktop.org/patch/475207/
>> https://patchwork.freedesktop.org/patch/496049/
> 
> I have some patches re-based to Jagan's latest branch.  It doesn't
> impact any drivers other than the new samsung-dsim driver, and it
> doesn't touch any of the drm helper functions either.  It adjusts hs
> clock based on the connected device.  I am not sure what the impact
> will have on the attached Exynos devices, so I am expecting some
> iterations.  Right now it's working with my DSI83 chip, but I need to
> get it working with my adv7535 part as well.  On the older branch, I
> was able to sync the ad7535 with a variety of resolutions using
> different pixel clock rates.
> 
> Once I get it working again with my adv7535 and cleaned up, I'll
> submit the patches to the drm group, and I'll CC you, Jagan and Marek
> Szyprowski with a reference to Jagan's series so people wanting to try
> it can apply it to his branch.

The negotiation has to happen between the host and the bridge/panel, 
otherwise you won't be able to support bridge/panel devices which 
require specific clock rate on the DSI. Only the bridge/panel driver 
knows about such requirement.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Alexander Stein]

Hi Marek,

Am Sonntag, 18. Dezember 2022, 00:55:57 CET schrieb Marek Vasut:
> On 12/16/22 14:25, Alexander Stein wrote:
> Hi,
> 
> [...]
> 
> > Oh, nice, thanks for the pointer. When setting
> > 
> >> samsung,burst-clock-frequency = <668250000>;
> > 
> > in imx8mm.dtsi
> > I get a non-flickering display using 4 lanes. Although admittedly this is
> > just random guessing. I'm not sure which clock exactly has to be in the
> > range CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is
> > configured for> 
> > 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
> >> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
> >> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250,
> >> esc_clk
> > 
> > = 16706250
> 
> If I recall it right, minimum PLL frequency is:
> 
> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
> 
> the link frequency is then
> 
> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)

Mh, there is something bogus about this. Right now the PLL freq is set 
depending on 'samsung,burst-clock-frequency' property. But this actually is 
somehow depending on the number of lanes I configure. From the debug output 
hs_clk and PLL freq are identical. AFAICS there is also no divider from PLL to 
hs_clk in the register map.

> So DSI83 should be in the range of 80..85 MHz input clock if I calculate
> this right. Can you check what is the value of mode->clock, the
> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
> sm65dsi83_get_dsi_range() ?

A working setup on a tianma,tm070jvhg33 display (1280x800) is:
> samsung-dsim 32e10000.dsi: PLL freq 891000000, (p 3, m 99, s 0)
> samsung-dsim 32e10000.dsi: hs_clk = 891000000, byte_clk = 111375000, esc_clk 
= 18562500
> sn65dsi83 2-002d: mode->clock: 68200
> sn65dsi83 2-002d: mode bpp: 24
> sn65dsi83 2-002d: ctx->dsi->lanes: 3
> sn65dsi83 2-002d: samsung_dsim_set_pll: 0x37

Calculating backwards, sn64dsi83 is expecting a clock in the range of 275-280 
MHz. But I fail to see a corresponding clock in the DSIM PLL configuration.

Best regards,
Alexander

> > AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from
> > DT
> > properties, while SN65DSI84 is using display mode and number of lanes.
> > 
> > Is it expected that the DSIM PLL frequencies are set in DT for a specific
> > bridge/display setup?
> 
> No, there should be negotiation between the host and bridge/panel, I
> tried to propose two variants, but they were all rejected.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Alexander Stein]

Hi Marek,

Am Sonntag, 18. Dezember 2022, 00:55:57 CET schrieb Marek Vasut:
> On 12/16/22 14:25, Alexander Stein wrote:
> Hi,
> 
> [...]
> 
> > Oh, nice, thanks for the pointer. When setting
> > 
> >> samsung,burst-clock-frequency = <668250000>;
> > 
> > in imx8mm.dtsi
> > I get a non-flickering display using 4 lanes. Although admittedly this is
> > just random guessing. I'm not sure which clock exactly has to be in the
> > range CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is
> > configured for> 
> > 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
> >> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
> >> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250,
> >> esc_clk
> > 
> > = 16706250
> 
> If I recall it right, minimum PLL frequency is:
> 
> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
> 
> the link frequency is then
> 
> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)

Mh, there is something bogus about this. Right now the PLL freq is set 
depending on 'samsung,burst-clock-frequency' property. But this actually is 
somehow depending on the number of lanes I configure. From the debug output 
hs_clk and PLL freq are identical. AFAICS there is also no divider from PLL to 
hs_clk in the register map.

> So DSI83 should be in the range of 80..85 MHz input clock if I calculate
> this right. Can you check what is the value of mode->clock, the
> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
> sm65dsi83_get_dsi_range() ?

A working setup on a tianma,tm070jvhg33 display (1280x800) is:
> samsung-dsim 32e10000.dsi: PLL freq 891000000, (p 3, m 99, s 0)
> samsung-dsim 32e10000.dsi: hs_clk = 891000000, byte_clk = 111375000, esc_clk 
= 18562500
> sn65dsi83 2-002d: mode->clock: 68200
> sn65dsi83 2-002d: mode bpp: 24
> sn65dsi83 2-002d: ctx->dsi->lanes: 3
> sn65dsi83 2-002d: samsung_dsim_set_pll: 0x37

Calculating backwards, sn64dsi83 is expecting a clock in the range of 275-280 
MHz. But I fail to see a corresponding clock in the DSIM PLL configuration.

Best regards,
Alexander

> > AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from
> > DT
> > properties, while SN65DSI84 is using display mode and number of lanes.
> > 
> > Is it expected that the DSIM PLL frequencies are set in DT for a specific
> > bridge/display setup?
> 
> No, there should be negotiation between the host and bridge/panel, I
> tried to propose two variants, but they were all rejected.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Alexander Stein]

Hi Marek,

Am Sonntag, 18. Dezember 2022, 00:55:57 CET schrieb Marek Vasut:
> On 12/16/22 14:25, Alexander Stein wrote:
> Hi,
> 
> [...]
> 
> > Oh, nice, thanks for the pointer. When setting
> > 
> >> samsung,burst-clock-frequency = <668250000>;
> > 
> > in imx8mm.dtsi
> > I get a non-flickering display using 4 lanes. Although admittedly this is
> > just random guessing. I'm not sure which clock exactly has to be in the
> > range CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is
> > configured for> 
> > 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
> >> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
> >> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250,
> >> esc_clk
> > 
> > = 16706250
> 
> If I recall it right, minimum PLL frequency is:
> 
> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
> 
> the link frequency is then
> 
> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)

Mh, there is something bogus about this. Right now the PLL freq is set 
depending on 'samsung,burst-clock-frequency' property. But this actually is 
somehow depending on the number of lanes I configure. From the debug output 
hs_clk and PLL freq are identical. AFAICS there is also no divider from PLL to 
hs_clk in the register map.

> So DSI83 should be in the range of 80..85 MHz input clock if I calculate
> this right. Can you check what is the value of mode->clock, the
> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
> sm65dsi83_get_dsi_range() ?

A working setup on a tianma,tm070jvhg33 display (1280x800) is:
> samsung-dsim 32e10000.dsi: PLL freq 891000000, (p 3, m 99, s 0)
> samsung-dsim 32e10000.dsi: hs_clk = 891000000, byte_clk = 111375000, esc_clk 
= 18562500
> sn65dsi83 2-002d: mode->clock: 68200
> sn65dsi83 2-002d: mode bpp: 24
> sn65dsi83 2-002d: ctx->dsi->lanes: 3
> sn65dsi83 2-002d: samsung_dsim_set_pll: 0x37

Calculating backwards, sn64dsi83 is expecting a clock in the range of 275-280 
MHz. But I fail to see a corresponding clock in the DSIM PLL configuration.

Best regards,
Alexander

> > AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from
> > DT
> > properties, while SN65DSI84 is using display mode and number of lanes.
> > 
> > Is it expected that the DSIM PLL frequencies are set in DT for a specific
> > bridge/display setup?
> 
> No, there should be negotiation between the host and bridge/panel, I
> tried to propose two variants, but they were all rejected.





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Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Alexander Stein]

Hi,

Am Sonntag, 18. Dezember 2022, 23:28:20 CET schrieb Marek Vasut:
> On 12/18/22 23:24, Adam Ford wrote:
> > On Sat, Dec 17, 2022 at 10:33 PM Marek Vasut <marex@denx.de> wrote:
> >> On 12/18/22 05:23, Adam Ford wrote:
> >>> On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
> >>>> On 12/16/22 14:25, Alexander Stein wrote:
> >>>> Hi,
> >>>> 
> >>>> [...]
> >>>> 
> >>>>> Oh, nice, thanks for the pointer. When setting
> >>>>> 
> >>>>>> samsung,burst-clock-frequency = <668250000>;
> >>>>> 
> >>>>> in imx8mm.dtsi
> >>>>> I get a non-flickering display using 4 lanes. Although admittedly this
> >>>>> is just random guessing. I'm not sure which clock exactly has to be
> >>>>> in the range CHA_DSI_CLK_RANGE is configured to. With 4 lanes
> >>>>> SN65DSI84 is configured for>>>>> 
> >>>>> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
> >>>>>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
> >>>>>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250,
> >>>>>> esc_clk
> >>>>> 
> >>>>> = 16706250
> >>>> 
> >>>> If I recall it right, minimum PLL frequency is:
> >>>> 
> >>>> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
> >>>> 
> >>>> the link frequency is then
> >>>> 
> >>>> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
> >>>> 
> >>>> So DSI83 should be in the range of 80..85 MHz input clock if I
> >>>> calculate
> >>>> this right. Can you check what is the value of mode->clock, the
> >>>> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
> >>>> sm65dsi83_get_dsi_range() ?
> >>>> 
> >>>>> AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just
> >>>>> from DT
> >>>>> properties, while SN65DSI84 is using display mode and number of lanes.
> >>>>> 
> >>>>> Is it expected that the DSIM PLL frequencies are set in DT for a
> >>>>> specific
> >>>>> bridge/display setup?
> >>>> 
> >>>> No, there should be negotiation between the host and bridge/panel, I
> >>>> tried to propose two variants, but they were all rejected.
> >>> 
> >>> For one of Jagan's previous revisions, I added some code to let the
> >>> PHY auto adjust the frequencies instead of being fixed.  NXP had this
> >>> in their downstream kernel, but with this patch and another, I was
> >>> able to set a variety of pixel clocks from my HDMI monitor and my
> >>> DSI83. I haven't had time to re-base my work on Jagan's latest work,
> >>> but you can link to the patch I did for the older stuff here:
> >>> 
> >>> https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb8
> >>> 8ab4b67e4 and
> >>> https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef6398134
> >>> 75241936f
> >>> 
> >>> I've been traveling a lot lately, so I haven't had time to evaluate
> >>> his series, but I hope to get something like those re-based once the
> >>> DSI stuff has been accepted.
> >> 
> >> I have these two attempts, both rejected:
> >> 
> >> https://patchwork.freedesktop.org/patch/475207/
> >> https://patchwork.freedesktop.org/patch/496049/
> > 
> > I have some patches re-based to Jagan's latest branch.  It doesn't
> > impact any drivers other than the new samsung-dsim driver, and it
> > doesn't touch any of the drm helper functions either.  It adjusts hs
> > clock based on the connected device.  I am not sure what the impact
> > will have on the attached Exynos devices, so I am expecting some
> > iterations.  Right now it's working with my DSI83 chip, but I need to
> > get it working with my adv7535 part as well.  On the older branch, I
> > was able to sync the ad7535 with a variety of resolutions using
> > different pixel clock rates.
> > 
> > Once I get it working again with my adv7535 and cleaned up, I'll
> > submit the patches to the drm group, and I'll CC you, Jagan and Marek
> > Szyprowski with a reference to Jagan's series so people wanting to try
> > it can apply it to his branch.
> 
> The negotiation has to happen between the host and the bridge/panel,
> otherwise you won't be able to support bridge/panel devices which
> require specific clock rate on the DSI. Only the bridge/panel driver
> knows about such requirement.

AFAICS using Adam's patch the dynamic DPHY config is done in atomic_pre_enable 
callback. So at this point the negotiation has to be finished already.
Wouldn't it be possible to setup 'dsi->format' within a atomic_check for 
samsung_dsim? But I don't know how you would get the expected clock frequency 
from the downward bridge.

Best regards,
Alexander

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Alexander Stein]

Hi,

Am Sonntag, 18. Dezember 2022, 23:28:20 CET schrieb Marek Vasut:
> On 12/18/22 23:24, Adam Ford wrote:
> > On Sat, Dec 17, 2022 at 10:33 PM Marek Vasut <marex@denx.de> wrote:
> >> On 12/18/22 05:23, Adam Ford wrote:
> >>> On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
> >>>> On 12/16/22 14:25, Alexander Stein wrote:
> >>>> Hi,
> >>>> 
> >>>> [...]
> >>>> 
> >>>>> Oh, nice, thanks for the pointer. When setting
> >>>>> 
> >>>>>> samsung,burst-clock-frequency = <668250000>;
> >>>>> 
> >>>>> in imx8mm.dtsi
> >>>>> I get a non-flickering display using 4 lanes. Although admittedly this
> >>>>> is just random guessing. I'm not sure which clock exactly has to be
> >>>>> in the range CHA_DSI_CLK_RANGE is configured to. With 4 lanes
> >>>>> SN65DSI84 is configured for>>>>> 
> >>>>> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
> >>>>>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
> >>>>>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250,
> >>>>>> esc_clk
> >>>>> 
> >>>>> = 16706250
> >>>> 
> >>>> If I recall it right, minimum PLL frequency is:
> >>>> 
> >>>> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
> >>>> 
> >>>> the link frequency is then
> >>>> 
> >>>> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
> >>>> 
> >>>> So DSI83 should be in the range of 80..85 MHz input clock if I
> >>>> calculate
> >>>> this right. Can you check what is the value of mode->clock, the
> >>>> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
> >>>> sm65dsi83_get_dsi_range() ?
> >>>> 
> >>>>> AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just
> >>>>> from DT
> >>>>> properties, while SN65DSI84 is using display mode and number of lanes.
> >>>>> 
> >>>>> Is it expected that the DSIM PLL frequencies are set in DT for a
> >>>>> specific
> >>>>> bridge/display setup?
> >>>> 
> >>>> No, there should be negotiation between the host and bridge/panel, I
> >>>> tried to propose two variants, but they were all rejected.
> >>> 
> >>> For one of Jagan's previous revisions, I added some code to let the
> >>> PHY auto adjust the frequencies instead of being fixed.  NXP had this
> >>> in their downstream kernel, but with this patch and another, I was
> >>> able to set a variety of pixel clocks from my HDMI monitor and my
> >>> DSI83. I haven't had time to re-base my work on Jagan's latest work,
> >>> but you can link to the patch I did for the older stuff here:
> >>> 
> >>> https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb8
> >>> 8ab4b67e4 and
> >>> https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef6398134
> >>> 75241936f
> >>> 
> >>> I've been traveling a lot lately, so I haven't had time to evaluate
> >>> his series, but I hope to get something like those re-based once the
> >>> DSI stuff has been accepted.
> >> 
> >> I have these two attempts, both rejected:
> >> 
> >> https://patchwork.freedesktop.org/patch/475207/
> >> https://patchwork.freedesktop.org/patch/496049/
> > 
> > I have some patches re-based to Jagan's latest branch.  It doesn't
> > impact any drivers other than the new samsung-dsim driver, and it
> > doesn't touch any of the drm helper functions either.  It adjusts hs
> > clock based on the connected device.  I am not sure what the impact
> > will have on the attached Exynos devices, so I am expecting some
> > iterations.  Right now it's working with my DSI83 chip, but I need to
> > get it working with my adv7535 part as well.  On the older branch, I
> > was able to sync the ad7535 with a variety of resolutions using
> > different pixel clock rates.
> > 
> > Once I get it working again with my adv7535 and cleaned up, I'll
> > submit the patches to the drm group, and I'll CC you, Jagan and Marek
> > Szyprowski with a reference to Jagan's series so people wanting to try
> > it can apply it to his branch.
> 
> The negotiation has to happen between the host and the bridge/panel,
> otherwise you won't be able to support bridge/panel devices which
> require specific clock rate on the DSI. Only the bridge/panel driver
> knows about such requirement.

AFAICS using Adam's patch the dynamic DPHY config is done in atomic_pre_enable 
callback. So at this point the negotiation has to be finished already.
Wouldn't it be possible to setup 'dsi->format' within a atomic_check for 
samsung_dsim? But I don't know how you would get the expected clock frequency 
from the downward bridge.

Best regards,
Alexander

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Alexander Stein]

Hi,

Am Sonntag, 18. Dezember 2022, 23:28:20 CET schrieb Marek Vasut:
> On 12/18/22 23:24, Adam Ford wrote:
> > On Sat, Dec 17, 2022 at 10:33 PM Marek Vasut <marex@denx.de> wrote:
> >> On 12/18/22 05:23, Adam Ford wrote:
> >>> On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
> >>>> On 12/16/22 14:25, Alexander Stein wrote:
> >>>> Hi,
> >>>> 
> >>>> [...]
> >>>> 
> >>>>> Oh, nice, thanks for the pointer. When setting
> >>>>> 
> >>>>>> samsung,burst-clock-frequency = <668250000>;
> >>>>> 
> >>>>> in imx8mm.dtsi
> >>>>> I get a non-flickering display using 4 lanes. Although admittedly this
> >>>>> is just random guessing. I'm not sure which clock exactly has to be
> >>>>> in the range CHA_DSI_CLK_RANGE is configured to. With 4 lanes
> >>>>> SN65DSI84 is configured for>>>>> 
> >>>>> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
> >>>>>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
> >>>>>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250,
> >>>>>> esc_clk
> >>>>> 
> >>>>> = 16706250
> >>>> 
> >>>> If I recall it right, minimum PLL frequency is:
> >>>> 
> >>>> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
> >>>> 
> >>>> the link frequency is then
> >>>> 
> >>>> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
> >>>> 
> >>>> So DSI83 should be in the range of 80..85 MHz input clock if I
> >>>> calculate
> >>>> this right. Can you check what is the value of mode->clock, the
> >>>> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
> >>>> sm65dsi83_get_dsi_range() ?
> >>>> 
> >>>>> AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just
> >>>>> from DT
> >>>>> properties, while SN65DSI84 is using display mode and number of lanes.
> >>>>> 
> >>>>> Is it expected that the DSIM PLL frequencies are set in DT for a
> >>>>> specific
> >>>>> bridge/display setup?
> >>>> 
> >>>> No, there should be negotiation between the host and bridge/panel, I
> >>>> tried to propose two variants, but they were all rejected.
> >>> 
> >>> For one of Jagan's previous revisions, I added some code to let the
> >>> PHY auto adjust the frequencies instead of being fixed.  NXP had this
> >>> in their downstream kernel, but with this patch and another, I was
> >>> able to set a variety of pixel clocks from my HDMI monitor and my
> >>> DSI83. I haven't had time to re-base my work on Jagan's latest work,
> >>> but you can link to the patch I did for the older stuff here:
> >>> 
> >>> https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb8
> >>> 8ab4b67e4 and
> >>> https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef6398134
> >>> 75241936f
> >>> 
> >>> I've been traveling a lot lately, so I haven't had time to evaluate
> >>> his series, but I hope to get something like those re-based once the
> >>> DSI stuff has been accepted.
> >> 
> >> I have these two attempts, both rejected:
> >> 
> >> https://patchwork.freedesktop.org/patch/475207/
> >> https://patchwork.freedesktop.org/patch/496049/
> > 
> > I have some patches re-based to Jagan's latest branch.  It doesn't
> > impact any drivers other than the new samsung-dsim driver, and it
> > doesn't touch any of the drm helper functions either.  It adjusts hs
> > clock based on the connected device.  I am not sure what the impact
> > will have on the attached Exynos devices, so I am expecting some
> > iterations.  Right now it's working with my DSI83 chip, but I need to
> > get it working with my adv7535 part as well.  On the older branch, I
> > was able to sync the ad7535 with a variety of resolutions using
> > different pixel clock rates.
> > 
> > Once I get it working again with my adv7535 and cleaned up, I'll
> > submit the patches to the drm group, and I'll CC you, Jagan and Marek
> > Szyprowski with a reference to Jagan's series so people wanting to try
> > it can apply it to his branch.
> 
> The negotiation has to happen between the host and the bridge/panel,
> otherwise you won't be able to support bridge/panel devices which
> require specific clock rate on the DSI. Only the bridge/panel driver
> knows about such requirement.

AFAICS using Adam's patch the dynamic DPHY config is done in atomic_pre_enable 
callback. So at this point the negotiation has to be finished already.
Wouldn't it be possible to setup 'dsi->format' within a atomic_check for 
samsung_dsim? But I don't know how you would get the expected clock frequency 
from the downward bridge.

Best regards,
Alexander



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Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 1/3/23 10:51, Alexander Stein wrote:
> Hi Marek,
> 
> Am Sonntag, 18. Dezember 2022, 00:55:57 CET schrieb Marek Vasut:
>> On 12/16/22 14:25, Alexander Stein wrote:
>> Hi,
>>
>> [...]
>>
>>> Oh, nice, thanks for the pointer. When setting
>>>
>>>> samsung,burst-clock-frequency = <668250000>;
>>>
>>> in imx8mm.dtsi
>>> I get a non-flickering display using 4 lanes. Although admittedly this is
>>> just random guessing. I'm not sure which clock exactly has to be in the
>>> range CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is
>>> configured for>
>>> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
>>>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
>>>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250,
>>>> esc_clk
>>>
>>> = 16706250
>>
>> If I recall it right, minimum PLL frequency is:
>>
>> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
>>
>> the link frequency is then
>>
>> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
> 
> Mh, there is something bogus about this. Right now the PLL freq is set
> depending on 'samsung,burst-clock-frequency' property. But this actually is
> somehow depending on the number of lanes I configure. From the debug output
> hs_clk and PLL freq are identical. AFAICS there is also no divider from PLL to
> hs_clk in the register map.

Could it be that samsung,burst-clock-frequency is fPMS / 2 ?

>> So DSI83 should be in the range of 80..85 MHz input clock if I calculate
>> this right. Can you check what is the value of mode->clock, the
>> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
>> sm65dsi83_get_dsi_range() ?
> 
> A working setup on a tianma,tm070jvhg33 display (1280x800) is:
>> samsung-dsim 32e10000.dsi: PLL freq 891000000, (p 3, m 99, s 0)
>> samsung-dsim 32e10000.dsi: hs_clk = 891000000, byte_clk = 111375000, esc_clk
> = 18562500
>> sn65dsi83 2-002d: mode->clock: 68200
>> sn65dsi83 2-002d: mode bpp: 24
>> sn65dsi83 2-002d: ctx->dsi->lanes: 3
>> sn65dsi83 2-002d: samsung_dsim_set_pll: 0x37
> 
> Calculating backwards, sn64dsi83 is expecting a clock in the range of 275-280
> MHz. But I fail to see a corresponding clock in the DSIM PLL configuration.

294.9 MHz, no ? 1280x800x24x60x1.2 / 3 / 2 = 294.9 .

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 1/3/23 10:51, Alexander Stein wrote:
> Hi Marek,
> 
> Am Sonntag, 18. Dezember 2022, 00:55:57 CET schrieb Marek Vasut:
>> On 12/16/22 14:25, Alexander Stein wrote:
>> Hi,
>>
>> [...]
>>
>>> Oh, nice, thanks for the pointer. When setting
>>>
>>>> samsung,burst-clock-frequency = <668250000>;
>>>
>>> in imx8mm.dtsi
>>> I get a non-flickering display using 4 lanes. Although admittedly this is
>>> just random guessing. I'm not sure which clock exactly has to be in the
>>> range CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is
>>> configured for>
>>> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
>>>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
>>>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250,
>>>> esc_clk
>>>
>>> = 16706250
>>
>> If I recall it right, minimum PLL frequency is:
>>
>> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
>>
>> the link frequency is then
>>
>> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
> 
> Mh, there is something bogus about this. Right now the PLL freq is set
> depending on 'samsung,burst-clock-frequency' property. But this actually is
> somehow depending on the number of lanes I configure. From the debug output
> hs_clk and PLL freq are identical. AFAICS there is also no divider from PLL to
> hs_clk in the register map.

Could it be that samsung,burst-clock-frequency is fPMS / 2 ?

>> So DSI83 should be in the range of 80..85 MHz input clock if I calculate
>> this right. Can you check what is the value of mode->clock, the
>> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
>> sm65dsi83_get_dsi_range() ?
> 
> A working setup on a tianma,tm070jvhg33 display (1280x800) is:
>> samsung-dsim 32e10000.dsi: PLL freq 891000000, (p 3, m 99, s 0)
>> samsung-dsim 32e10000.dsi: hs_clk = 891000000, byte_clk = 111375000, esc_clk
> = 18562500
>> sn65dsi83 2-002d: mode->clock: 68200
>> sn65dsi83 2-002d: mode bpp: 24
>> sn65dsi83 2-002d: ctx->dsi->lanes: 3
>> sn65dsi83 2-002d: samsung_dsim_set_pll: 0x37
> 
> Calculating backwards, sn64dsi83 is expecting a clock in the range of 275-280
> MHz. But I fail to see a corresponding clock in the DSIM PLL configuration.

294.9 MHz, no ? 1280x800x24x60x1.2 / 3 / 2 = 294.9 .

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 1/3/23 10:51, Alexander Stein wrote:
> Hi Marek,
> 
> Am Sonntag, 18. Dezember 2022, 00:55:57 CET schrieb Marek Vasut:
>> On 12/16/22 14:25, Alexander Stein wrote:
>> Hi,
>>
>> [...]
>>
>>> Oh, nice, thanks for the pointer. When setting
>>>
>>>> samsung,burst-clock-frequency = <668250000>;
>>>
>>> in imx8mm.dtsi
>>> I get a non-flickering display using 4 lanes. Although admittedly this is
>>> just random guessing. I'm not sure which clock exactly has to be in the
>>> range CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is
>>> configured for>
>>> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
>>>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
>>>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250,
>>>> esc_clk
>>>
>>> = 16706250
>>
>> If I recall it right, minimum PLL frequency is:
>>
>> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
>>
>> the link frequency is then
>>
>> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
> 
> Mh, there is something bogus about this. Right now the PLL freq is set
> depending on 'samsung,burst-clock-frequency' property. But this actually is
> somehow depending on the number of lanes I configure. From the debug output
> hs_clk and PLL freq are identical. AFAICS there is also no divider from PLL to
> hs_clk in the register map.

Could it be that samsung,burst-clock-frequency is fPMS / 2 ?

>> So DSI83 should be in the range of 80..85 MHz input clock if I calculate
>> this right. Can you check what is the value of mode->clock, the
>> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
>> sm65dsi83_get_dsi_range() ?
> 
> A working setup on a tianma,tm070jvhg33 display (1280x800) is:
>> samsung-dsim 32e10000.dsi: PLL freq 891000000, (p 3, m 99, s 0)
>> samsung-dsim 32e10000.dsi: hs_clk = 891000000, byte_clk = 111375000, esc_clk
> = 18562500
>> sn65dsi83 2-002d: mode->clock: 68200
>> sn65dsi83 2-002d: mode bpp: 24
>> sn65dsi83 2-002d: ctx->dsi->lanes: 3
>> sn65dsi83 2-002d: samsung_dsim_set_pll: 0x37
> 
> Calculating backwards, sn64dsi83 is expecting a clock in the range of 275-280
> MHz. But I fail to see a corresponding clock in the DSIM PLL configuration.

294.9 MHz, no ? 1280x800x24x60x1.2 / 3 / 2 = 294.9 .

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Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 1/3/23 11:59, Alexander Stein wrote:
> Hi,
> 
> Am Sonntag, 18. Dezember 2022, 23:28:20 CET schrieb Marek Vasut:
>> On 12/18/22 23:24, Adam Ford wrote:
>>> On Sat, Dec 17, 2022 at 10:33 PM Marek Vasut <marex@denx.de> wrote:
>>>> On 12/18/22 05:23, Adam Ford wrote:
>>>>> On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
>>>>>> On 12/16/22 14:25, Alexander Stein wrote:
>>>>>> Hi,
>>>>>>
>>>>>> [...]
>>>>>>
>>>>>>> Oh, nice, thanks for the pointer. When setting
>>>>>>>
>>>>>>>> samsung,burst-clock-frequency = <668250000>;
>>>>>>>
>>>>>>> in imx8mm.dtsi
>>>>>>> I get a non-flickering display using 4 lanes. Although admittedly this
>>>>>>> is just random guessing. I'm not sure which clock exactly has to be
>>>>>>> in the range CHA_DSI_CLK_RANGE is configured to. With 4 lanes
>>>>>>> SN65DSI84 is configured for>>>>>
>>>>>>> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
>>>>>>>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
>>>>>>>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250,
>>>>>>>> esc_clk
>>>>>>>
>>>>>>> = 16706250
>>>>>>
>>>>>> If I recall it right, minimum PLL frequency is:
>>>>>>
>>>>>> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
>>>>>>
>>>>>> the link frequency is then
>>>>>>
>>>>>> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
>>>>>>
>>>>>> So DSI83 should be in the range of 80..85 MHz input clock if I
>>>>>> calculate
>>>>>> this right. Can you check what is the value of mode->clock, the
>>>>>> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
>>>>>> sm65dsi83_get_dsi_range() ?
>>>>>>
>>>>>>> AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just
>>>>>>> from DT
>>>>>>> properties, while SN65DSI84 is using display mode and number of lanes.
>>>>>>>
>>>>>>> Is it expected that the DSIM PLL frequencies are set in DT for a
>>>>>>> specific
>>>>>>> bridge/display setup?
>>>>>>
>>>>>> No, there should be negotiation between the host and bridge/panel, I
>>>>>> tried to propose two variants, but they were all rejected.
>>>>>
>>>>> For one of Jagan's previous revisions, I added some code to let the
>>>>> PHY auto adjust the frequencies instead of being fixed.  NXP had this
>>>>> in their downstream kernel, but with this patch and another, I was
>>>>> able to set a variety of pixel clocks from my HDMI monitor and my
>>>>> DSI83. I haven't had time to re-base my work on Jagan's latest work,
>>>>> but you can link to the patch I did for the older stuff here:
>>>>>
>>>>> https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb8
>>>>> 8ab4b67e4 and
>>>>> https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef6398134
>>>>> 75241936f
>>>>>
>>>>> I've been traveling a lot lately, so I haven't had time to evaluate
>>>>> his series, but I hope to get something like those re-based once the
>>>>> DSI stuff has been accepted.
>>>>
>>>> I have these two attempts, both rejected:
>>>>
>>>> https://patchwork.freedesktop.org/patch/475207/
>>>> https://patchwork.freedesktop.org/patch/496049/
>>>
>>> I have some patches re-based to Jagan's latest branch.  It doesn't
>>> impact any drivers other than the new samsung-dsim driver, and it
>>> doesn't touch any of the drm helper functions either.  It adjusts hs
>>> clock based on the connected device.  I am not sure what the impact
>>> will have on the attached Exynos devices, so I am expecting some
>>> iterations.  Right now it's working with my DSI83 chip, but I need to
>>> get it working with my adv7535 part as well.  On the older branch, I
>>> was able to sync the ad7535 with a variety of resolutions using
>>> different pixel clock rates.
>>>
>>> Once I get it working again with my adv7535 and cleaned up, I'll
>>> submit the patches to the drm group, and I'll CC you, Jagan and Marek
>>> Szyprowski with a reference to Jagan's series so people wanting to try
>>> it can apply it to his branch.
>>
>> The negotiation has to happen between the host and the bridge/panel,
>> otherwise you won't be able to support bridge/panel devices which
>> require specific clock rate on the DSI. Only the bridge/panel driver
>> knows about such requirement.
> 
> AFAICS using Adam's patch the dynamic DPHY config is done in atomic_pre_enable
> callback. So at this point the negotiation has to be finished already.
> Wouldn't it be possible to setup 'dsi->format' within a atomic_check for
> samsung_dsim? But I don't know how you would get the expected clock frequency
> from the downward bridge.

Maybe Maxime can comment on this ?

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 1/3/23 11:59, Alexander Stein wrote:
> Hi,
> 
> Am Sonntag, 18. Dezember 2022, 23:28:20 CET schrieb Marek Vasut:
>> On 12/18/22 23:24, Adam Ford wrote:
>>> On Sat, Dec 17, 2022 at 10:33 PM Marek Vasut <marex@denx.de> wrote:
>>>> On 12/18/22 05:23, Adam Ford wrote:
>>>>> On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
>>>>>> On 12/16/22 14:25, Alexander Stein wrote:
>>>>>> Hi,
>>>>>>
>>>>>> [...]
>>>>>>
>>>>>>> Oh, nice, thanks for the pointer. When setting
>>>>>>>
>>>>>>>> samsung,burst-clock-frequency = <668250000>;
>>>>>>>
>>>>>>> in imx8mm.dtsi
>>>>>>> I get a non-flickering display using 4 lanes. Although admittedly this
>>>>>>> is just random guessing. I'm not sure which clock exactly has to be
>>>>>>> in the range CHA_DSI_CLK_RANGE is configured to. With 4 lanes
>>>>>>> SN65DSI84 is configured for>>>>>
>>>>>>> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
>>>>>>>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
>>>>>>>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250,
>>>>>>>> esc_clk
>>>>>>>
>>>>>>> = 16706250
>>>>>>
>>>>>> If I recall it right, minimum PLL frequency is:
>>>>>>
>>>>>> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
>>>>>>
>>>>>> the link frequency is then
>>>>>>
>>>>>> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
>>>>>>
>>>>>> So DSI83 should be in the range of 80..85 MHz input clock if I
>>>>>> calculate
>>>>>> this right. Can you check what is the value of mode->clock, the
>>>>>> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
>>>>>> sm65dsi83_get_dsi_range() ?
>>>>>>
>>>>>>> AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just
>>>>>>> from DT
>>>>>>> properties, while SN65DSI84 is using display mode and number of lanes.
>>>>>>>
>>>>>>> Is it expected that the DSIM PLL frequencies are set in DT for a
>>>>>>> specific
>>>>>>> bridge/display setup?
>>>>>>
>>>>>> No, there should be negotiation between the host and bridge/panel, I
>>>>>> tried to propose two variants, but they were all rejected.
>>>>>
>>>>> For one of Jagan's previous revisions, I added some code to let the
>>>>> PHY auto adjust the frequencies instead of being fixed.  NXP had this
>>>>> in their downstream kernel, but with this patch and another, I was
>>>>> able to set a variety of pixel clocks from my HDMI monitor and my
>>>>> DSI83. I haven't had time to re-base my work on Jagan's latest work,
>>>>> but you can link to the patch I did for the older stuff here:
>>>>>
>>>>> https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb8
>>>>> 8ab4b67e4 and
>>>>> https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef6398134
>>>>> 75241936f
>>>>>
>>>>> I've been traveling a lot lately, so I haven't had time to evaluate
>>>>> his series, but I hope to get something like those re-based once the
>>>>> DSI stuff has been accepted.
>>>>
>>>> I have these two attempts, both rejected:
>>>>
>>>> https://patchwork.freedesktop.org/patch/475207/
>>>> https://patchwork.freedesktop.org/patch/496049/
>>>
>>> I have some patches re-based to Jagan's latest branch.  It doesn't
>>> impact any drivers other than the new samsung-dsim driver, and it
>>> doesn't touch any of the drm helper functions either.  It adjusts hs
>>> clock based on the connected device.  I am not sure what the impact
>>> will have on the attached Exynos devices, so I am expecting some
>>> iterations.  Right now it's working with my DSI83 chip, but I need to
>>> get it working with my adv7535 part as well.  On the older branch, I
>>> was able to sync the ad7535 with a variety of resolutions using
>>> different pixel clock rates.
>>>
>>> Once I get it working again with my adv7535 and cleaned up, I'll
>>> submit the patches to the drm group, and I'll CC you, Jagan and Marek
>>> Szyprowski with a reference to Jagan's series so people wanting to try
>>> it can apply it to his branch.
>>
>> The negotiation has to happen between the host and the bridge/panel,
>> otherwise you won't be able to support bridge/panel devices which
>> require specific clock rate on the DSI. Only the bridge/panel driver
>> knows about such requirement.
> 
> AFAICS using Adam's patch the dynamic DPHY config is done in atomic_pre_enable
> callback. So at this point the negotiation has to be finished already.
> Wouldn't it be possible to setup 'dsi->format' within a atomic_check for
> samsung_dsim? But I don't know how you would get the expected clock frequency
> from the downward bridge.

Maybe Maxime can comment on this ?

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 1/3/23 11:59, Alexander Stein wrote:
> Hi,
> 
> Am Sonntag, 18. Dezember 2022, 23:28:20 CET schrieb Marek Vasut:
>> On 12/18/22 23:24, Adam Ford wrote:
>>> On Sat, Dec 17, 2022 at 10:33 PM Marek Vasut <marex@denx.de> wrote:
>>>> On 12/18/22 05:23, Adam Ford wrote:
>>>>> On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
>>>>>> On 12/16/22 14:25, Alexander Stein wrote:
>>>>>> Hi,
>>>>>>
>>>>>> [...]
>>>>>>
>>>>>>> Oh, nice, thanks for the pointer. When setting
>>>>>>>
>>>>>>>> samsung,burst-clock-frequency = <668250000>;
>>>>>>>
>>>>>>> in imx8mm.dtsi
>>>>>>> I get a non-flickering display using 4 lanes. Although admittedly this
>>>>>>> is just random guessing. I'm not sure which clock exactly has to be
>>>>>>> in the range CHA_DSI_CLK_RANGE is configured to. With 4 lanes
>>>>>>> SN65DSI84 is configured for>>>>>
>>>>>>> 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
>>>>>>>> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
>>>>>>>> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250,
>>>>>>>> esc_clk
>>>>>>>
>>>>>>> = 16706250
>>>>>>
>>>>>> If I recall it right, minimum PLL frequency is:
>>>>>>
>>>>>> fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
>>>>>>
>>>>>> the link frequency is then
>>>>>>
>>>>>> fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
>>>>>>
>>>>>> So DSI83 should be in the range of 80..85 MHz input clock if I
>>>>>> calculate
>>>>>> this right. Can you check what is the value of mode->clock, the
>>>>>> mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
>>>>>> sm65dsi83_get_dsi_range() ?
>>>>>>
>>>>>>> AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just
>>>>>>> from DT
>>>>>>> properties, while SN65DSI84 is using display mode and number of lanes.
>>>>>>>
>>>>>>> Is it expected that the DSIM PLL frequencies are set in DT for a
>>>>>>> specific
>>>>>>> bridge/display setup?
>>>>>>
>>>>>> No, there should be negotiation between the host and bridge/panel, I
>>>>>> tried to propose two variants, but they were all rejected.
>>>>>
>>>>> For one of Jagan's previous revisions, I added some code to let the
>>>>> PHY auto adjust the frequencies instead of being fixed.  NXP had this
>>>>> in their downstream kernel, but with this patch and another, I was
>>>>> able to set a variety of pixel clocks from my HDMI monitor and my
>>>>> DSI83. I haven't had time to re-base my work on Jagan's latest work,
>>>>> but you can link to the patch I did for the older stuff here:
>>>>>
>>>>> https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb8
>>>>> 8ab4b67e4 and
>>>>> https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef6398134
>>>>> 75241936f
>>>>>
>>>>> I've been traveling a lot lately, so I haven't had time to evaluate
>>>>> his series, but I hope to get something like those re-based once the
>>>>> DSI stuff has been accepted.
>>>>
>>>> I have these two attempts, both rejected:
>>>>
>>>> https://patchwork.freedesktop.org/patch/475207/
>>>> https://patchwork.freedesktop.org/patch/496049/
>>>
>>> I have some patches re-based to Jagan's latest branch.  It doesn't
>>> impact any drivers other than the new samsung-dsim driver, and it
>>> doesn't touch any of the drm helper functions either.  It adjusts hs
>>> clock based on the connected device.  I am not sure what the impact
>>> will have on the attached Exynos devices, so I am expecting some
>>> iterations.  Right now it's working with my DSI83 chip, but I need to
>>> get it working with my adv7535 part as well.  On the older branch, I
>>> was able to sync the ad7535 with a variety of resolutions using
>>> different pixel clock rates.
>>>
>>> Once I get it working again with my adv7535 and cleaned up, I'll
>>> submit the patches to the drm group, and I'll CC you, Jagan and Marek
>>> Szyprowski with a reference to Jagan's series so people wanting to try
>>> it can apply it to his branch.
>>
>> The negotiation has to happen between the host and the bridge/panel,
>> otherwise you won't be able to support bridge/panel devices which
>> require specific clock rate on the DSI. Only the bridge/panel driver
>> knows about such requirement.
> 
> AFAICS using Adam's patch the dynamic DPHY config is done in atomic_pre_enable
> callback. So at this point the negotiation has to be finished already.
> Wouldn't it be possible to setup 'dsi->format' within a atomic_check for
> samsung_dsim? But I don't know how you would get the expected clock frequency
> from the downward bridge.

Maybe Maxime can comment on this ?

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Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Maxime Ripard]

On Wed, Jan 04, 2023 at 04:08:47PM +0100, Marek Vasut wrote:
> On 1/3/23 11:59, Alexander Stein wrote:
> > Hi,
> > 
> > Am Sonntag, 18. Dezember 2022, 23:28:20 CET schrieb Marek Vasut:
> > > On 12/18/22 23:24, Adam Ford wrote:
> > > > On Sat, Dec 17, 2022 at 10:33 PM Marek Vasut <marex@denx.de> wrote:
> > > > > On 12/18/22 05:23, Adam Ford wrote:
> > > > > > On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
> > > > > > > On 12/16/22 14:25, Alexander Stein wrote:
> > > > > > > Hi,
> > > > > > > 
> > > > > > > [...]
> > > > > > > 
> > > > > > > > Oh, nice, thanks for the pointer. When setting
> > > > > > > > 
> > > > > > > > > samsung,burst-clock-frequency = <668250000>;
> > > > > > > > 
> > > > > > > > in imx8mm.dtsi
> > > > > > > > I get a non-flickering display using 4 lanes. Although admittedly this
> > > > > > > > is just random guessing. I'm not sure which clock exactly has to be
> > > > > > > > in the range CHA_DSI_CLK_RANGE is configured to. With 4 lanes
> > > > > > > > SN65DSI84 is configured for>>>>>
> > > > > > > > 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
> > > > > > > > > samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
> > > > > > > > > samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250,
> > > > > > > > > esc_clk
> > > > > > > > 
> > > > > > > > = 16706250
> > > > > > > 
> > > > > > > If I recall it right, minimum PLL frequency is:
> > > > > > > 
> > > > > > > fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
> > > > > > > 
> > > > > > > the link frequency is then
> > > > > > > 
> > > > > > > fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
> > > > > > > 
> > > > > > > So DSI83 should be in the range of 80..85 MHz input clock if I
> > > > > > > calculate
> > > > > > > this right. Can you check what is the value of mode->clock, the
> > > > > > > mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
> > > > > > > sm65dsi83_get_dsi_range() ?
> > > > > > > 
> > > > > > > > AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just
> > > > > > > > from DT
> > > > > > > > properties, while SN65DSI84 is using display mode and number of lanes.
> > > > > > > > 
> > > > > > > > Is it expected that the DSIM PLL frequencies are set in DT for a
> > > > > > > > specific
> > > > > > > > bridge/display setup?
> > > > > > > 
> > > > > > > No, there should be negotiation between the host and bridge/panel, I
> > > > > > > tried to propose two variants, but they were all rejected.
> > > > > > 
> > > > > > For one of Jagan's previous revisions, I added some code to let the
> > > > > > PHY auto adjust the frequencies instead of being fixed.  NXP had this
> > > > > > in their downstream kernel, but with this patch and another, I was
> > > > > > able to set a variety of pixel clocks from my HDMI monitor and my
> > > > > > DSI83. I haven't had time to re-base my work on Jagan's latest work,
> > > > > > but you can link to the patch I did for the older stuff here:
> > > > > > 
> > > > > > https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb8
> > > > > > 8ab4b67e4 and
> > > > > > https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef6398134
> > > > > > 75241936f
> > > > > > 
> > > > > > I've been traveling a lot lately, so I haven't had time to evaluate
> > > > > > his series, but I hope to get something like those re-based once the
> > > > > > DSI stuff has been accepted.
> > > > > 
> > > > > I have these two attempts, both rejected:
> > > > > 
> > > > > https://patchwork.freedesktop.org/patch/475207/
> > > > > https://patchwork.freedesktop.org/patch/496049/
> > > > 
> > > > I have some patches re-based to Jagan's latest branch.  It doesn't
> > > > impact any drivers other than the new samsung-dsim driver, and it
> > > > doesn't touch any of the drm helper functions either.  It adjusts hs
> > > > clock based on the connected device.  I am not sure what the impact
> > > > will have on the attached Exynos devices, so I am expecting some
> > > > iterations.  Right now it's working with my DSI83 chip, but I need to
> > > > get it working with my adv7535 part as well.  On the older branch, I
> > > > was able to sync the ad7535 with a variety of resolutions using
> > > > different pixel clock rates.
> > > > 
> > > > Once I get it working again with my adv7535 and cleaned up, I'll
> > > > submit the patches to the drm group, and I'll CC you, Jagan and Marek
> > > > Szyprowski with a reference to Jagan's series so people wanting to try
> > > > it can apply it to his branch.
> > > 
> > > The negotiation has to happen between the host and the bridge/panel,
> > > otherwise you won't be able to support bridge/panel devices which
> > > require specific clock rate on the DSI. Only the bridge/panel driver
> > > knows about such requirement.
> > 
> > AFAICS using Adam's patch the dynamic DPHY config is done in atomic_pre_enable
> > callback. So at this point the negotiation has to be finished already.
> > Wouldn't it be possible to setup 'dsi->format' within a atomic_check for
> > samsung_dsim? But I don't know how you would get the expected clock frequency
> > from the downward bridge.

I have zero context there, so I'm not sure what proposals have been made
already, but why isn't it possible to do it the other way around and
make the bridge ask the upstream driver if it can provide the clock
frequency the bridge require?

It's pretty much how the common clock framework works too: you set the
rate on the leaf clock, and it propagates upwards in your tree,
adjusting for any constraint we have along the way.

It does need to happen at atomic_check time though, otherwise it would
be terrible for anyone attempting to use that driver.

Maxime

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Maxime Ripard]

On Wed, Jan 04, 2023 at 04:08:47PM +0100, Marek Vasut wrote:
> On 1/3/23 11:59, Alexander Stein wrote:
> > Hi,
> > 
> > Am Sonntag, 18. Dezember 2022, 23:28:20 CET schrieb Marek Vasut:
> > > On 12/18/22 23:24, Adam Ford wrote:
> > > > On Sat, Dec 17, 2022 at 10:33 PM Marek Vasut <marex@denx.de> wrote:
> > > > > On 12/18/22 05:23, Adam Ford wrote:
> > > > > > On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
> > > > > > > On 12/16/22 14:25, Alexander Stein wrote:
> > > > > > > Hi,
> > > > > > > 
> > > > > > > [...]
> > > > > > > 
> > > > > > > > Oh, nice, thanks for the pointer. When setting
> > > > > > > > 
> > > > > > > > > samsung,burst-clock-frequency = <668250000>;
> > > > > > > > 
> > > > > > > > in imx8mm.dtsi
> > > > > > > > I get a non-flickering display using 4 lanes. Although admittedly this
> > > > > > > > is just random guessing. I'm not sure which clock exactly has to be
> > > > > > > > in the range CHA_DSI_CLK_RANGE is configured to. With 4 lanes
> > > > > > > > SN65DSI84 is configured for>>>>>
> > > > > > > > 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
> > > > > > > > > samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
> > > > > > > > > samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250,
> > > > > > > > > esc_clk
> > > > > > > > 
> > > > > > > > = 16706250
> > > > > > > 
> > > > > > > If I recall it right, minimum PLL frequency is:
> > > > > > > 
> > > > > > > fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
> > > > > > > 
> > > > > > > the link frequency is then
> > > > > > > 
> > > > > > > fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
> > > > > > > 
> > > > > > > So DSI83 should be in the range of 80..85 MHz input clock if I
> > > > > > > calculate
> > > > > > > this right. Can you check what is the value of mode->clock, the
> > > > > > > mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
> > > > > > > sm65dsi83_get_dsi_range() ?
> > > > > > > 
> > > > > > > > AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just
> > > > > > > > from DT
> > > > > > > > properties, while SN65DSI84 is using display mode and number of lanes.
> > > > > > > > 
> > > > > > > > Is it expected that the DSIM PLL frequencies are set in DT for a
> > > > > > > > specific
> > > > > > > > bridge/display setup?
> > > > > > > 
> > > > > > > No, there should be negotiation between the host and bridge/panel, I
> > > > > > > tried to propose two variants, but they were all rejected.
> > > > > > 
> > > > > > For one of Jagan's previous revisions, I added some code to let the
> > > > > > PHY auto adjust the frequencies instead of being fixed.  NXP had this
> > > > > > in their downstream kernel, but with this patch and another, I was
> > > > > > able to set a variety of pixel clocks from my HDMI monitor and my
> > > > > > DSI83. I haven't had time to re-base my work on Jagan's latest work,
> > > > > > but you can link to the patch I did for the older stuff here:
> > > > > > 
> > > > > > https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb8
> > > > > > 8ab4b67e4 and
> > > > > > https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef6398134
> > > > > > 75241936f
> > > > > > 
> > > > > > I've been traveling a lot lately, so I haven't had time to evaluate
> > > > > > his series, but I hope to get something like those re-based once the
> > > > > > DSI stuff has been accepted.
> > > > > 
> > > > > I have these two attempts, both rejected:
> > > > > 
> > > > > https://patchwork.freedesktop.org/patch/475207/
> > > > > https://patchwork.freedesktop.org/patch/496049/
> > > > 
> > > > I have some patches re-based to Jagan's latest branch.  It doesn't
> > > > impact any drivers other than the new samsung-dsim driver, and it
> > > > doesn't touch any of the drm helper functions either.  It adjusts hs
> > > > clock based on the connected device.  I am not sure what the impact
> > > > will have on the attached Exynos devices, so I am expecting some
> > > > iterations.  Right now it's working with my DSI83 chip, but I need to
> > > > get it working with my adv7535 part as well.  On the older branch, I
> > > > was able to sync the ad7535 with a variety of resolutions using
> > > > different pixel clock rates.
> > > > 
> > > > Once I get it working again with my adv7535 and cleaned up, I'll
> > > > submit the patches to the drm group, and I'll CC you, Jagan and Marek
> > > > Szyprowski with a reference to Jagan's series so people wanting to try
> > > > it can apply it to his branch.
> > > 
> > > The negotiation has to happen between the host and the bridge/panel,
> > > otherwise you won't be able to support bridge/panel devices which
> > > require specific clock rate on the DSI. Only the bridge/panel driver
> > > knows about such requirement.
> > 
> > AFAICS using Adam's patch the dynamic DPHY config is done in atomic_pre_enable
> > callback. So at this point the negotiation has to be finished already.
> > Wouldn't it be possible to setup 'dsi->format' within a atomic_check for
> > samsung_dsim? But I don't know how you would get the expected clock frequency
> > from the downward bridge.

I have zero context there, so I'm not sure what proposals have been made
already, but why isn't it possible to do it the other way around and
make the bridge ask the upstream driver if it can provide the clock
frequency the bridge require?

It's pretty much how the common clock framework works too: you set the
rate on the leaf clock, and it propagates upwards in your tree,
adjusting for any constraint we have along the way.

It does need to happen at atomic_check time though, otherwise it would
be terrible for anyone attempting to use that driver.

Maxime

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Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Maxime Ripard]

On Wed, Jan 04, 2023 at 04:08:47PM +0100, Marek Vasut wrote:
> On 1/3/23 11:59, Alexander Stein wrote:
> > Hi,
> > 
> > Am Sonntag, 18. Dezember 2022, 23:28:20 CET schrieb Marek Vasut:
> > > On 12/18/22 23:24, Adam Ford wrote:
> > > > On Sat, Dec 17, 2022 at 10:33 PM Marek Vasut <marex@denx.de> wrote:
> > > > > On 12/18/22 05:23, Adam Ford wrote:
> > > > > > On Sat, Dec 17, 2022 at 5:56 PM Marek Vasut <marex@denx.de> wrote:
> > > > > > > On 12/16/22 14:25, Alexander Stein wrote:
> > > > > > > Hi,
> > > > > > > 
> > > > > > > [...]
> > > > > > > 
> > > > > > > > Oh, nice, thanks for the pointer. When setting
> > > > > > > > 
> > > > > > > > > samsung,burst-clock-frequency = <668250000>;
> > > > > > > > 
> > > > > > > > in imx8mm.dtsi
> > > > > > > > I get a non-flickering display using 4 lanes. Although admittedly this
> > > > > > > > is just random guessing. I'm not sure which clock exactly has to be
> > > > > > > > in the range CHA_DSI_CLK_RANGE is configured to. With 4 lanes
> > > > > > > > SN65DSI84 is configured for>>>>>
> > > > > > > > 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM:
> > > > > > > > > samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0)
> > > > > > > > > samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250,
> > > > > > > > > esc_clk
> > > > > > > > 
> > > > > > > > = 16706250
> > > > > > > 
> > > > > > > If I recall it right, minimum PLL frequency is:
> > > > > > > 
> > > > > > > fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz
> > > > > > > 
> > > > > > > the link frequency is then
> > > > > > > 
> > > > > > > fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane)
> > > > > > > 
> > > > > > > So DSI83 should be in the range of 80..85 MHz input clock if I
> > > > > > > calculate
> > > > > > > this right. Can you check what is the value of mode->clock, the
> > > > > > > mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83
> > > > > > > sm65dsi83_get_dsi_range() ?
> > > > > > > 
> > > > > > > > AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just
> > > > > > > > from DT
> > > > > > > > properties, while SN65DSI84 is using display mode and number of lanes.
> > > > > > > > 
> > > > > > > > Is it expected that the DSIM PLL frequencies are set in DT for a
> > > > > > > > specific
> > > > > > > > bridge/display setup?
> > > > > > > 
> > > > > > > No, there should be negotiation between the host and bridge/panel, I
> > > > > > > tried to propose two variants, but they were all rejected.
> > > > > > 
> > > > > > For one of Jagan's previous revisions, I added some code to let the
> > > > > > PHY auto adjust the frequencies instead of being fixed.  NXP had this
> > > > > > in their downstream kernel, but with this patch and another, I was
> > > > > > able to set a variety of pixel clocks from my HDMI monitor and my
> > > > > > DSI83. I haven't had time to re-base my work on Jagan's latest work,
> > > > > > but you can link to the patch I did for the older stuff here:
> > > > > > 
> > > > > > https://github.com/aford173/linux/commit/e845274b0f22ba3b24813ffd6bb3cb8
> > > > > > 8ab4b67e4 and
> > > > > > https://github.com/aford173/linux/commit/3f90057eb608f96d106029ef6398134
> > > > > > 75241936f
> > > > > > 
> > > > > > I've been traveling a lot lately, so I haven't had time to evaluate
> > > > > > his series, but I hope to get something like those re-based once the
> > > > > > DSI stuff has been accepted.
> > > > > 
> > > > > I have these two attempts, both rejected:
> > > > > 
> > > > > https://patchwork.freedesktop.org/patch/475207/
> > > > > https://patchwork.freedesktop.org/patch/496049/
> > > > 
> > > > I have some patches re-based to Jagan's latest branch.  It doesn't
> > > > impact any drivers other than the new samsung-dsim driver, and it
> > > > doesn't touch any of the drm helper functions either.  It adjusts hs
> > > > clock based on the connected device.  I am not sure what the impact
> > > > will have on the attached Exynos devices, so I am expecting some
> > > > iterations.  Right now it's working with my DSI83 chip, but I need to
> > > > get it working with my adv7535 part as well.  On the older branch, I
> > > > was able to sync the ad7535 with a variety of resolutions using
> > > > different pixel clock rates.
> > > > 
> > > > Once I get it working again with my adv7535 and cleaned up, I'll
> > > > submit the patches to the drm group, and I'll CC you, Jagan and Marek
> > > > Szyprowski with a reference to Jagan's series so people wanting to try
> > > > it can apply it to his branch.
> > > 
> > > The negotiation has to happen between the host and the bridge/panel,
> > > otherwise you won't be able to support bridge/panel devices which
> > > require specific clock rate on the DSI. Only the bridge/panel driver
> > > knows about such requirement.
> > 
> > AFAICS using Adam's patch the dynamic DPHY config is done in atomic_pre_enable
> > callback. So at this point the negotiation has to be finished already.
> > Wouldn't it be possible to setup 'dsi->format' within a atomic_check for
> > samsung_dsim? But I don't know how you would get the expected clock frequency
> > from the downward bridge.

I have zero context there, so I'm not sure what proposals have been made
already, but why isn't it possible to do it the other way around and
make the bridge ask the upstream driver if it can provide the clock
frequency the bridge require?

It's pretty much how the common clock framework works too: you set the
rate on the leaf clock, and it propagates upwards in your tree,
adjusting for any constraint we have along the way.

It does need to happen at atomic_check time though, otherwise it would
be terrible for anyone attempting to use that driver.

Maxime

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

Hi Marek,

On Fri, Jan 20, 2023 at 8:36 PM Marek Vasut <marex@denx.de> wrote:
>
> On 1/20/23 15:41, Jagan Teki wrote:
> > Hi Fabio,
>
> Hello all,
>
> > On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
> >>
> >> Hi Jagan,
> >>
> >> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >>
> >>> There are two patch series prior to this need to apply.
> >>>
> >>> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
> >>> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
> >>
> >> Would it make sense to re-submit these two patches as part of your series?
> >
> > The previous version's comment was to separate them from the DSIM series.
>
> Hmmmmm, seems like those first two patches got stuck. I fixed up the
> malformed Fixes: line (it was split across two lines and had angular
> brackets around it) and picked the first series via drm-misc-next .
>
> Can you send a subsequent patch to convert the DSIM_* macros to BIT()
> macro , since checkpatch --strict complains about it ?

Fyi: I sent the v11 series for this with RESEND prefix.

Let me know if you have any further comments on this.

Thanks,
Jagan.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

Hi Marek,

On Fri, Jan 20, 2023 at 8:36 PM Marek Vasut <marex@denx.de> wrote:
>
> On 1/20/23 15:41, Jagan Teki wrote:
> > Hi Fabio,
>
> Hello all,
>
> > On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
> >>
> >> Hi Jagan,
> >>
> >> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >>
> >>> There are two patch series prior to this need to apply.
> >>>
> >>> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
> >>> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
> >>
> >> Would it make sense to re-submit these two patches as part of your series?
> >
> > The previous version's comment was to separate them from the DSIM series.
>
> Hmmmmm, seems like those first two patches got stuck. I fixed up the
> malformed Fixes: line (it was split across two lines and had angular
> brackets around it) and picked the first series via drm-misc-next .
>
> Can you send a subsequent patch to convert the DSIM_* macros to BIT()
> macro , since checkpatch --strict complains about it ?

Fyi: I sent the v11 series for this with RESEND prefix.

Let me know if you have any further comments on this.

Thanks,
Jagan.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

Hi Marek,

On Fri, Jan 20, 2023 at 8:36 PM Marek Vasut <marex@denx.de> wrote:
>
> On 1/20/23 15:41, Jagan Teki wrote:
> > Hi Fabio,
>
> Hello all,
>
> > On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
> >>
> >> Hi Jagan,
> >>
> >> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >>
> >>> There are two patch series prior to this need to apply.
> >>>
> >>> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
> >>> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
> >>
> >> Would it make sense to re-submit these two patches as part of your series?
> >
> > The previous version's comment was to separate them from the DSIM series.
>
> Hmmmmm, seems like those first two patches got stuck. I fixed up the
> malformed Fixes: line (it was split across two lines and had angular
> brackets around it) and picked the first series via drm-misc-next .
>
> Can you send a subsequent patch to convert the DSIM_* macros to BIT()
> macro , since checkpatch --strict complains about it ?

Fyi: I sent the v11 series for this with RESEND prefix.

Let me know if you have any further comments on this.

Thanks,
Jagan.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

On Sat, Jan 21, 2023 at 12:29 AM Dave Stevenson
<dave.stevenson@raspberrypi.com> wrote:
>
> Hi Marek & Jagan
>
> On Fri, 20 Jan 2023 at 15:06, Marek Vasut <marex@denx.de> wrote:
> >
> > On 1/20/23 15:41, Jagan Teki wrote:
> > > Hi Fabio,
> >
> > Hello all,
> >
> > > On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
> > >>
> > >> Hi Jagan,
> > >>
> > >> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> > >>
> > >>> There are two patch series prior to this need to apply.
> > >>>
> > >>> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
> > >>> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
> > >>
> > >> Would it make sense to re-submit these two patches as part of your series?
> > >
> > > The previous version's comment was to separate them from the DSIM series.
> >
> > Hmmmmm, seems like those first two patches got stuck. I fixed up the
> > malformed Fixes: line (it was split across two lines and had angular
> > brackets around it) and picked the first series via drm-misc-next .
> >
> > Can you send a subsequent patch to convert the DSIM_* macros to BIT()
> > macro , since checkpatch --strict complains about it ?
> >
> > For the second series, you likely want a RB from Maxime Ripard and Dave
> > Stevenson first about the probe order handling.
>
> Not sure what I can add for "Enable prepare_prev_first flag for
> samsung-s6e panels" and "tc358764: Enable pre_enable_prev_first flag"
> as I have no datasheet for those devices.
> On the basis that they are wanting the DSI host to be in LP-11 before
> prepare/pre_enable, then setting the flag is the right thing. More
> than happy to say
> Acked-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> to those two (I can't find them quickly in my mail to respond directly).
>
> I have just sent a separate response on the third patch.

Fyi: please check my answers on that thread.

Thanks,
Jagan.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

On Sat, Jan 21, 2023 at 12:29 AM Dave Stevenson
<dave.stevenson@raspberrypi.com> wrote:
>
> Hi Marek & Jagan
>
> On Fri, 20 Jan 2023 at 15:06, Marek Vasut <marex@denx.de> wrote:
> >
> > On 1/20/23 15:41, Jagan Teki wrote:
> > > Hi Fabio,
> >
> > Hello all,
> >
> > > On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
> > >>
> > >> Hi Jagan,
> > >>
> > >> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> > >>
> > >>> There are two patch series prior to this need to apply.
> > >>>
> > >>> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
> > >>> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
> > >>
> > >> Would it make sense to re-submit these two patches as part of your series?
> > >
> > > The previous version's comment was to separate them from the DSIM series.
> >
> > Hmmmmm, seems like those first two patches got stuck. I fixed up the
> > malformed Fixes: line (it was split across two lines and had angular
> > brackets around it) and picked the first series via drm-misc-next .
> >
> > Can you send a subsequent patch to convert the DSIM_* macros to BIT()
> > macro , since checkpatch --strict complains about it ?
> >
> > For the second series, you likely want a RB from Maxime Ripard and Dave
> > Stevenson first about the probe order handling.
>
> Not sure what I can add for "Enable prepare_prev_first flag for
> samsung-s6e panels" and "tc358764: Enable pre_enable_prev_first flag"
> as I have no datasheet for those devices.
> On the basis that they are wanting the DSI host to be in LP-11 before
> prepare/pre_enable, then setting the flag is the right thing. More
> than happy to say
> Acked-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> to those two (I can't find them quickly in my mail to respond directly).
>
> I have just sent a separate response on the third patch.

Fyi: please check my answers on that thread.

Thanks,
Jagan.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

On Sat, Jan 21, 2023 at 12:29 AM Dave Stevenson
<dave.stevenson@raspberrypi.com> wrote:
>
> Hi Marek & Jagan
>
> On Fri, 20 Jan 2023 at 15:06, Marek Vasut <marex@denx.de> wrote:
> >
> > On 1/20/23 15:41, Jagan Teki wrote:
> > > Hi Fabio,
> >
> > Hello all,
> >
> > > On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
> > >>
> > >> Hi Jagan,
> > >>
> > >> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> > >>
> > >>> There are two patch series prior to this need to apply.
> > >>>
> > >>> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
> > >>> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
> > >>
> > >> Would it make sense to re-submit these two patches as part of your series?
> > >
> > > The previous version's comment was to separate them from the DSIM series.
> >
> > Hmmmmm, seems like those first two patches got stuck. I fixed up the
> > malformed Fixes: line (it was split across two lines and had angular
> > brackets around it) and picked the first series via drm-misc-next .
> >
> > Can you send a subsequent patch to convert the DSIM_* macros to BIT()
> > macro , since checkpatch --strict complains about it ?
> >
> > For the second series, you likely want a RB from Maxime Ripard and Dave
> > Stevenson first about the probe order handling.
>
> Not sure what I can add for "Enable prepare_prev_first flag for
> samsung-s6e panels" and "tc358764: Enable pre_enable_prev_first flag"
> as I have no datasheet for those devices.
> On the basis that they are wanting the DSI host to be in LP-11 before
> prepare/pre_enable, then setting the flag is the right thing. More
> than happy to say
> Acked-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> to those two (I can't find them quickly in my mail to respond directly).
>
> I have just sent a separate response on the third patch.

Fyi: please check my answers on that thread.

Thanks,
Jagan.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 1/20/23 19:54, Jagan Teki wrote:
> On Fri, Jan 20, 2023 at 8:36 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 1/20/23 15:41, Jagan Teki wrote:
>>> Hi Fabio,
>>
>> Hello all,
>>
>>> On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
>>>>
>>>> Hi Jagan,
>>>>
>>>> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>>>>
>>>>> There are two patch series prior to this need to apply.
>>>>>
>>>>> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
>>>>> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
>>>>
>>>> Would it make sense to re-submit these two patches as part of your series?
>>>
>>> The previous version's comment was to separate them from the DSIM series.
>>
>> Hmmmmm, seems like those first two patches got stuck. I fixed up the
>> malformed Fixes: line (it was split across two lines and had angular
>> brackets around it) and picked the first series via drm-misc-next .
> 
> Thanks.
> 
> We have another series for Exynos, prior to DSIM
> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
> 
>>
>> Can you send a subsequent patch to convert the DSIM_* macros to BIT()
>> macro , since checkpatch --strict complains about it ?
> 
> Okay.
> 
>>
>> For the second series, you likely want a RB from Maxime Ripard and Dave
>> Stevenson first about the probe order handling.
> 
> Do you mean for 01/18 and 02/18 patches?

I mean

https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 1/20/23 19:54, Jagan Teki wrote:
> On Fri, Jan 20, 2023 at 8:36 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 1/20/23 15:41, Jagan Teki wrote:
>>> Hi Fabio,
>>
>> Hello all,
>>
>>> On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
>>>>
>>>> Hi Jagan,
>>>>
>>>> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>>>>
>>>>> There are two patch series prior to this need to apply.
>>>>>
>>>>> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
>>>>> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
>>>>
>>>> Would it make sense to re-submit these two patches as part of your series?
>>>
>>> The previous version's comment was to separate them from the DSIM series.
>>
>> Hmmmmm, seems like those first two patches got stuck. I fixed up the
>> malformed Fixes: line (it was split across two lines and had angular
>> brackets around it) and picked the first series via drm-misc-next .
> 
> Thanks.
> 
> We have another series for Exynos, prior to DSIM
> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
> 
>>
>> Can you send a subsequent patch to convert the DSIM_* macros to BIT()
>> macro , since checkpatch --strict complains about it ?
> 
> Okay.
> 
>>
>> For the second series, you likely want a RB from Maxime Ripard and Dave
>> Stevenson first about the probe order handling.
> 
> Do you mean for 01/18 and 02/18 patches?

I mean

https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 1/20/23 19:54, Jagan Teki wrote:
> On Fri, Jan 20, 2023 at 8:36 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 1/20/23 15:41, Jagan Teki wrote:
>>> Hi Fabio,
>>
>> Hello all,
>>
>>> On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
>>>>
>>>> Hi Jagan,
>>>>
>>>> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>>>>
>>>>> There are two patch series prior to this need to apply.
>>>>>
>>>>> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
>>>>> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
>>>>
>>>> Would it make sense to re-submit these two patches as part of your series?
>>>
>>> The previous version's comment was to separate them from the DSIM series.
>>
>> Hmmmmm, seems like those first two patches got stuck. I fixed up the
>> malformed Fixes: line (it was split across two lines and had angular
>> brackets around it) and picked the first series via drm-misc-next .
> 
> Thanks.
> 
> We have another series for Exynos, prior to DSIM
> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
> 
>>
>> Can you send a subsequent patch to convert the DSIM_* macros to BIT()
>> macro , since checkpatch --strict complains about it ?
> 
> Okay.
> 
>>
>> For the second series, you likely want a RB from Maxime Ripard and Dave
>> Stevenson first about the probe order handling.
> 
> Do you mean for 01/18 and 02/18 patches?

I mean

https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/

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Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Dave Stevenson]

Hi Marek & Jagan

On Fri, 20 Jan 2023 at 15:06, Marek Vasut <marex@denx.de> wrote:
>
> On 1/20/23 15:41, Jagan Teki wrote:
> > Hi Fabio,
>
> Hello all,
>
> > On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
> >>
> >> Hi Jagan,
> >>
> >> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >>
> >>> There are two patch series prior to this need to apply.
> >>>
> >>> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
> >>> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
> >>
> >> Would it make sense to re-submit these two patches as part of your series?
> >
> > The previous version's comment was to separate them from the DSIM series.
>
> Hmmmmm, seems like those first two patches got stuck. I fixed up the
> malformed Fixes: line (it was split across two lines and had angular
> brackets around it) and picked the first series via drm-misc-next .
>
> Can you send a subsequent patch to convert the DSIM_* macros to BIT()
> macro , since checkpatch --strict complains about it ?
>
> For the second series, you likely want a RB from Maxime Ripard and Dave
> Stevenson first about the probe order handling.

Not sure what I can add for "Enable prepare_prev_first flag for
samsung-s6e panels" and "tc358764: Enable pre_enable_prev_first flag"
as I have no datasheet for those devices.
On the basis that they are wanting the DSI host to be in LP-11 before
prepare/pre_enable, then setting the flag is the right thing. More
than happy to say
Acked-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
to those two (I can't find them quickly in my mail to respond directly).

I have just sent a separate response on the third patch.

  Dave

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Dave Stevenson]

Hi Marek & Jagan

On Fri, 20 Jan 2023 at 15:06, Marek Vasut <marex@denx.de> wrote:
>
> On 1/20/23 15:41, Jagan Teki wrote:
> > Hi Fabio,
>
> Hello all,
>
> > On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
> >>
> >> Hi Jagan,
> >>
> >> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >>
> >>> There are two patch series prior to this need to apply.
> >>>
> >>> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
> >>> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
> >>
> >> Would it make sense to re-submit these two patches as part of your series?
> >
> > The previous version's comment was to separate them from the DSIM series.
>
> Hmmmmm, seems like those first two patches got stuck. I fixed up the
> malformed Fixes: line (it was split across two lines and had angular
> brackets around it) and picked the first series via drm-misc-next .
>
> Can you send a subsequent patch to convert the DSIM_* macros to BIT()
> macro , since checkpatch --strict complains about it ?
>
> For the second series, you likely want a RB from Maxime Ripard and Dave
> Stevenson first about the probe order handling.

Not sure what I can add for "Enable prepare_prev_first flag for
samsung-s6e panels" and "tc358764: Enable pre_enable_prev_first flag"
as I have no datasheet for those devices.
On the basis that they are wanting the DSI host to be in LP-11 before
prepare/pre_enable, then setting the flag is the right thing. More
than happy to say
Acked-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
to those two (I can't find them quickly in my mail to respond directly).

I have just sent a separate response on the third patch.

  Dave

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Dave Stevenson]

Hi Marek & Jagan

On Fri, 20 Jan 2023 at 15:06, Marek Vasut <marex@denx.de> wrote:
>
> On 1/20/23 15:41, Jagan Teki wrote:
> > Hi Fabio,
>
> Hello all,
>
> > On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
> >>
> >> Hi Jagan,
> >>
> >> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >>
> >>> There are two patch series prior to this need to apply.
> >>>
> >>> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
> >>> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
> >>
> >> Would it make sense to re-submit these two patches as part of your series?
> >
> > The previous version's comment was to separate them from the DSIM series.
>
> Hmmmmm, seems like those first two patches got stuck. I fixed up the
> malformed Fixes: line (it was split across two lines and had angular
> brackets around it) and picked the first series via drm-misc-next .
>
> Can you send a subsequent patch to convert the DSIM_* macros to BIT()
> macro , since checkpatch --strict complains about it ?
>
> For the second series, you likely want a RB from Maxime Ripard and Dave
> Stevenson first about the probe order handling.

Not sure what I can add for "Enable prepare_prev_first flag for
samsung-s6e panels" and "tc358764: Enable pre_enable_prev_first flag"
as I have no datasheet for those devices.
On the basis that they are wanting the DSI host to be in LP-11 before
prepare/pre_enable, then setting the flag is the right thing. More
than happy to say
Acked-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
to those two (I can't find them quickly in my mail to respond directly).

I have just sent a separate response on the third patch.

  Dave

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Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

On Fri, Jan 20, 2023 at 8:36 PM Marek Vasut <marex@denx.de> wrote:
>
> On 1/20/23 15:41, Jagan Teki wrote:
> > Hi Fabio,
>
> Hello all,
>
> > On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
> >>
> >> Hi Jagan,
> >>
> >> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >>
> >>> There are two patch series prior to this need to apply.
> >>>
> >>> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
> >>> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
> >>
> >> Would it make sense to re-submit these two patches as part of your series?
> >
> > The previous version's comment was to separate them from the DSIM series.
>
> Hmmmmm, seems like those first two patches got stuck. I fixed up the
> malformed Fixes: line (it was split across two lines and had angular
> brackets around it) and picked the first series via drm-misc-next .

Thanks.

We have another series for Exynos, prior to DSIM
https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/

>
> Can you send a subsequent patch to convert the DSIM_* macros to BIT()
> macro , since checkpatch --strict complains about it ?

Okay.

>
> For the second series, you likely want a RB from Maxime Ripard and Dave
> Stevenson first about the probe order handling.

Do you mean for 01/18 and 02/18 patches?

Jagan.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

On Fri, Jan 20, 2023 at 8:36 PM Marek Vasut <marex@denx.de> wrote:
>
> On 1/20/23 15:41, Jagan Teki wrote:
> > Hi Fabio,
>
> Hello all,
>
> > On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
> >>
> >> Hi Jagan,
> >>
> >> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >>
> >>> There are two patch series prior to this need to apply.
> >>>
> >>> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
> >>> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
> >>
> >> Would it make sense to re-submit these two patches as part of your series?
> >
> > The previous version's comment was to separate them from the DSIM series.
>
> Hmmmmm, seems like those first two patches got stuck. I fixed up the
> malformed Fixes: line (it was split across two lines and had angular
> brackets around it) and picked the first series via drm-misc-next .

Thanks.

We have another series for Exynos, prior to DSIM
https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/

>
> Can you send a subsequent patch to convert the DSIM_* macros to BIT()
> macro , since checkpatch --strict complains about it ?

Okay.

>
> For the second series, you likely want a RB from Maxime Ripard and Dave
> Stevenson first about the probe order handling.

Do you mean for 01/18 and 02/18 patches?

Jagan.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

On Fri, Jan 20, 2023 at 8:36 PM Marek Vasut <marex@denx.de> wrote:
>
> On 1/20/23 15:41, Jagan Teki wrote:
> > Hi Fabio,
>
> Hello all,
>
> > On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
> >>
> >> Hi Jagan,
> >>
> >> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >>
> >>> There are two patch series prior to this need to apply.
> >>>
> >>> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
> >>> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
> >>
> >> Would it make sense to re-submit these two patches as part of your series?
> >
> > The previous version's comment was to separate them from the DSIM series.
>
> Hmmmmm, seems like those first two patches got stuck. I fixed up the
> malformed Fixes: line (it was split across two lines and had angular
> brackets around it) and picked the first series via drm-misc-next .

Thanks.

We have another series for Exynos, prior to DSIM
https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/

>
> Can you send a subsequent patch to convert the DSIM_* macros to BIT()
> macro , since checkpatch --strict complains about it ?

Okay.

>
> For the second series, you likely want a RB from Maxime Ripard and Dave
> Stevenson first about the probe order handling.

Do you mean for 01/18 and 02/18 patches?

Jagan.

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Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 1/20/23 15:41, Jagan Teki wrote:
> Hi Fabio,

Hello all,

> On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
>>
>> Hi Jagan,
>>
>> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>>
>>> There are two patch series prior to this need to apply.
>>>
>>> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
>>> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
>>
>> Would it make sense to re-submit these two patches as part of your series?
> 
> The previous version's comment was to separate them from the DSIM series.

Hmmmmm, seems like those first two patches got stuck. I fixed up the 
malformed Fixes: line (it was split across two lines and had angular 
brackets around it) and picked the first series via drm-misc-next .

Can you send a subsequent patch to convert the DSIM_* macros to BIT() 
macro , since checkpatch --strict complains about it ?

For the second series, you likely want a RB from Maxime Ripard and Dave 
Stevenson first about the probe order handling.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 1/20/23 15:41, Jagan Teki wrote:
> Hi Fabio,

Hello all,

> On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
>>
>> Hi Jagan,
>>
>> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>>
>>> There are two patch series prior to this need to apply.
>>>
>>> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
>>> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
>>
>> Would it make sense to re-submit these two patches as part of your series?
> 
> The previous version's comment was to separate them from the DSIM series.

Hmmmmm, seems like those first two patches got stuck. I fixed up the 
malformed Fixes: line (it was split across two lines and had angular 
brackets around it) and picked the first series via drm-misc-next .

Can you send a subsequent patch to convert the DSIM_* macros to BIT() 
macro , since checkpatch --strict complains about it ?

For the second series, you likely want a RB from Maxime Ripard and Dave 
Stevenson first about the probe order handling.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 1/20/23 15:41, Jagan Teki wrote:
> Hi Fabio,

Hello all,

> On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
>>
>> Hi Jagan,
>>
>> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>>
>>> There are two patch series prior to this need to apply.
>>>
>>> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
>>> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
>>
>> Would it make sense to re-submit these two patches as part of your series?
> 
> The previous version's comment was to separate them from the DSIM series.

Hmmmmm, seems like those first two patches got stuck. I fixed up the 
malformed Fixes: line (it was split across two lines and had angular 
brackets around it) and picked the first series via drm-misc-next .

Can you send a subsequent patch to convert the DSIM_* macros to BIT() 
macro , since checkpatch --strict complains about it ?

For the second series, you likely want a RB from Maxime Ripard and Dave 
Stevenson first about the probe order handling.

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Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

Hi Fabio,

On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Jagan,
>
> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> > There are two patch series prior to this need to apply.
> >
> > https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
> > https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
>
> Would it make sense to re-submit these two patches as part of your series?

The previous version's comment was to separate them from the DSIM series.

Jagan.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

Hi Fabio,

On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Jagan,
>
> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> > There are two patch series prior to this need to apply.
> >
> > https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
> > https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
>
> Would it make sense to re-submit these two patches as part of your series?

The previous version's comment was to separate them from the DSIM series.

Jagan.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

Hi Fabio,

On Fri, Jan 20, 2023 at 5:36 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Jagan,
>
> On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> > There are two patch series prior to this need to apply.
> >
> > https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
> > https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/
>
> Would it make sense to re-submit these two patches as part of your series?

The previous version's comment was to separate them from the DSIM series.

Jagan.

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Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Fabio Estevam]

Hi Jagan,

On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:

> There are two patch series prior to this need to apply.
>
> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/

Would it make sense to re-submit these two patches as part of your series?

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Fabio Estevam]

Hi Jagan,

On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:

> There are two patch series prior to this need to apply.
>
> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/

Would it make sense to re-submit these two patches as part of your series?

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Fabio Estevam]

Hi Jagan,

On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki <jagan@amarulasolutions.com> wrote:

> There are two patch series prior to this need to apply.
>
> https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
> https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/

Would it make sense to re-submit these two patches as part of your series?

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Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

Hi Fabio,

On Thu, Jan 19, 2023 at 10:57 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Jagan,
>
> On Thu, Jan 5, 2023 at 7:24 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> > Does anyone have any other comments on this? I would like to send v11
> > with a few nits on v10. Please let me know.
>
> What is blocking this series to be applied?

There are two patch series prior to this need to apply.

https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/

Regarding this series, the patch 09/18 commit message has "FIXME" this
need to remove.
https://patchwork.kernel.org/project/dri-devel/patch/20221214125907.376148-10-jagan@amarulasolutions.com/

I think it is possible to remove it while applying otherwise I will
resend this patch alone or in series again.

Jagan.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

Hi Fabio,

On Thu, Jan 19, 2023 at 10:57 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Jagan,
>
> On Thu, Jan 5, 2023 at 7:24 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> > Does anyone have any other comments on this? I would like to send v11
> > with a few nits on v10. Please let me know.
>
> What is blocking this series to be applied?

There are two patch series prior to this need to apply.

https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/

Regarding this series, the patch 09/18 commit message has "FIXME" this
need to remove.
https://patchwork.kernel.org/project/dri-devel/patch/20221214125907.376148-10-jagan@amarulasolutions.com/

I think it is possible to remove it while applying otherwise I will
resend this patch alone or in series again.

Jagan.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

Hi Fabio,

On Thu, Jan 19, 2023 at 10:57 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Jagan,
>
> On Thu, Jan 5, 2023 at 7:24 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> > Does anyone have any other comments on this? I would like to send v11
> > with a few nits on v10. Please let me know.
>
> What is blocking this series to be applied?

There are two patch series prior to this need to apply.

https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-jagan@amarulasolutions.com/
https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-jagan@amarulasolutions.com/

Regarding this series, the patch 09/18 commit message has "FIXME" this
need to remove.
https://patchwork.kernel.org/project/dri-devel/patch/20221214125907.376148-10-jagan@amarulasolutions.com/

I think it is possible to remove it while applying otherwise I will
resend this patch alone or in series again.

Jagan.

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Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Fabio Estevam]

Hi Jagan,

On Thu, Jan 5, 2023 at 7:24 AM Jagan Teki <jagan@amarulasolutions.com> wrote:

> Does anyone have any other comments on this? I would like to send v11
> with a few nits on v10. Please let me know.

What is blocking this series to be applied?

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Fabio Estevam]

Hi Jagan,

On Thu, Jan 5, 2023 at 7:24 AM Jagan Teki <jagan@amarulasolutions.com> wrote:

> Does anyone have any other comments on this? I would like to send v11
> with a few nits on v10. Please let me know.

What is blocking this series to be applied?

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Fabio Estevam]

Hi Jagan,

On Thu, Jan 5, 2023 at 7:24 AM Jagan Teki <jagan@amarulasolutions.com> wrote:

> Does anyone have any other comments on this? I would like to send v11
> with a few nits on v10. Please let me know.

What is blocking this series to be applied?

_______________________________________________
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Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Fabio Estevam]

On Fri, Jan 6, 2023 at 11:34 AM Adam Ford <aford173@gmail.com> wrote:

> I got it working on an LVDS display that I have, but I didn't get it
> working on the HDMI bridge.  Since we have a few tested-by people,
> it'd be nice to see this integrated so we can work on ading more
> functionality

Agreed. Hopefully, this series can be applied soon so we don't miss
another cycle.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Fabio Estevam]

On Fri, Jan 6, 2023 at 11:34 AM Adam Ford <aford173@gmail.com> wrote:

> I got it working on an LVDS display that I have, but I didn't get it
> working on the HDMI bridge.  Since we have a few tested-by people,
> it'd be nice to see this integrated so we can work on ading more
> functionality

Agreed. Hopefully, this series can be applied soon so we don't miss
another cycle.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Fabio Estevam]

On Fri, Jan 6, 2023 at 11:34 AM Adam Ford <aford173@gmail.com> wrote:

> I got it working on an LVDS display that I have, but I didn't get it
> working on the HDMI bridge.  Since we have a few tested-by people,
> it'd be nice to see this integrated so we can work on ading more
> functionality

Agreed. Hopefully, this series can be applied soon so we don't miss
another cycle.

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Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Adam Ford]

On Thu, Jan 5, 2023 at 4:24 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> On Wed, Dec 14, 2022 at 6:29 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >
> > This series supports common bridge support for Samsung MIPI DSIM
> > which is used in Exynos and i.MX8MM SoC's.
> >
> > The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.
> >
> > Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge
> >
> > Patch 0005 - 0006: optional PHY, PMS_P offset
> >
> > Patch 0007       : introduce hw_type
> >
> > Patch 0008       : fixing host init
> >
> > Patch 0009       : atomic_check
> >
> > Patch 0010       : input_bus_flags
> >
> > Patch 0011       : atomic_get_input_bus_fmts
> >
> > Patch 0012 - 0013: component vs bridge
> >
> > Patch 0014       : DSIM bridge
> >
> > Patch 0015 - 0016: i.MX8M Mini/Nano
> >
> > Patch 0017 - 0018: i.MX8M Plus
> >
> > Changes for v10:
> > - rebase on drm-misc-next
> > - add drm_of_dsi_find_panel_or_bridge
> > - add devm_drm_of_dsi_get_bridge
> > - fix host initialization (Thanks to Marek Szyprowski)
> > - rearrange the tiny patches for easy to review
> > - update simple names for enum hw_type
> > - add is_hw_exynos macro
> > - rework on commit messages
> >
> > Changes for v9:
> > - rebase on drm-misc-next
> > - drop drm bridge attach fix for Exynos
> > - added prepare_prev_first flag
> > - added pre_enable_prev_first flag
> > - fix bridge chain order for exynos
> > - added fix for Exynos host init for first DSI transfer
> > - added MEDIA_BUS_FMT_FIXED
> > - return MEDIA_BUS_FMT_RGB888_1X24 output_fmt if supported output_fmt
> >   list is unsupported.
> > - added MEDIA_BUS_FMT_YUYV10_1X20
> > - added MEDIA_BUS_FMT_YUYV12_1X24
> >
> > Changes for v8:
> > * fixed comment lines
> > * fixed commit messages
> > * fixed video mode bits
> > * collect Marek Ack
> > * fixed video mode bit names
> > * update input formats logic
> > * added imx8mplus support
> >
> > Changes for v7:
> > * fix the drm bridge attach chain for exynos drm dsi driver
> > * fix the hw_type checking logic
> >
> > Changes for v6:
> > * handle previous bridge for exynos dsi while attaching bridge
> >
> > Changes for v5:
> > * bridge changes to support multi-arch
> > * updated and clear commit messages
> > * add hw_type via plat data
> > * removed unneeded quirk
> > * rebased on linux-next
> >
> > Changes for v4:
> > * include Inki Dae in MAINTAINERS
> > * remove dsi_driver probe in exynos_drm_drv to support multi-arch build
> > * update init handling to ensure host init done on first cmd transfer
> >
> > Changes for v3:
> > * fix the mult-arch build
> > * fix dsi host init
> > * updated commit messages
> >
> > Changes for v2:
> > * fix bridge handling
> > * fix dsi host init
> > * correct the commit messages
> >
> > Tested in Engicam i.Core MX8M Mini SoM.
> >
> > Repo:
> > https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v10
> >
> > v9:
> > https://lore.kernel.org/all/20221209152343.180139-1-jagan@amarulasolutions.com/
> >
> > Any inputs?
> > Jagan.
> >
> > Jagan Teki (16):
> >   drm: of: Lookup if child node has DSI panel or bridge
> >   drm: bridge: panel: Add devm_drm_of_dsi_get_bridge helper
> >   drm: exynos: dsi: Drop explicit call to bridge detach
> >   drm: exynos: dsi: Switch to devm_drm_of_dsi_get_bridge
> >   drm: exynos: dsi: Mark PHY as optional
> >   drm: exynos: dsi: Add platform PLL_P (PMS_P) offset
> >   drm: exynos: dsi: Introduce hw_type platform data
> >   drm: exynos: dsi: Add atomic check
> >   drm: exynos: dsi: Add input_bus_flags
> >   drm: exynos: dsi: Add atomic_get_input_bus_fmts
> >   drm: exynos: dsi: Consolidate component and bridge
> >   drm: exynos: dsi: Add Exynos based host irq hooks
> >   drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge
> >   dt-bindings: display: exynos: dsim: Add NXP i.MX8M Mini/Nano support
> >   drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support
> >   dt-bindings: display: exynos: dsim: Add NXP i.MX8M Plus support
> >
> > Marek Szyprowski (1):
> >   drm: exynos: dsi: Handle proper host initialization
> >
> > Marek Vasut (1):
> >   drm: bridge: samsung-dsim: Add i.MX8M Plus support
>
> Does anyone have any other comments on this? I would like to send v11
> with a few nits on v10. Please let me know.

I got it working on an LVDS display that I have, but I didn't get it
working on the HDMI bridge.  Since we have a few tested-by people,
it'd be nice to see this integrated so we can work on ading more
functionality

adam
>
> Thanks,
> Jagan.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Adam Ford]

On Thu, Jan 5, 2023 at 4:24 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> On Wed, Dec 14, 2022 at 6:29 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >
> > This series supports common bridge support for Samsung MIPI DSIM
> > which is used in Exynos and i.MX8MM SoC's.
> >
> > The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.
> >
> > Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge
> >
> > Patch 0005 - 0006: optional PHY, PMS_P offset
> >
> > Patch 0007       : introduce hw_type
> >
> > Patch 0008       : fixing host init
> >
> > Patch 0009       : atomic_check
> >
> > Patch 0010       : input_bus_flags
> >
> > Patch 0011       : atomic_get_input_bus_fmts
> >
> > Patch 0012 - 0013: component vs bridge
> >
> > Patch 0014       : DSIM bridge
> >
> > Patch 0015 - 0016: i.MX8M Mini/Nano
> >
> > Patch 0017 - 0018: i.MX8M Plus
> >
> > Changes for v10:
> > - rebase on drm-misc-next
> > - add drm_of_dsi_find_panel_or_bridge
> > - add devm_drm_of_dsi_get_bridge
> > - fix host initialization (Thanks to Marek Szyprowski)
> > - rearrange the tiny patches for easy to review
> > - update simple names for enum hw_type
> > - add is_hw_exynos macro
> > - rework on commit messages
> >
> > Changes for v9:
> > - rebase on drm-misc-next
> > - drop drm bridge attach fix for Exynos
> > - added prepare_prev_first flag
> > - added pre_enable_prev_first flag
> > - fix bridge chain order for exynos
> > - added fix for Exynos host init for first DSI transfer
> > - added MEDIA_BUS_FMT_FIXED
> > - return MEDIA_BUS_FMT_RGB888_1X24 output_fmt if supported output_fmt
> >   list is unsupported.
> > - added MEDIA_BUS_FMT_YUYV10_1X20
> > - added MEDIA_BUS_FMT_YUYV12_1X24
> >
> > Changes for v8:
> > * fixed comment lines
> > * fixed commit messages
> > * fixed video mode bits
> > * collect Marek Ack
> > * fixed video mode bit names
> > * update input formats logic
> > * added imx8mplus support
> >
> > Changes for v7:
> > * fix the drm bridge attach chain for exynos drm dsi driver
> > * fix the hw_type checking logic
> >
> > Changes for v6:
> > * handle previous bridge for exynos dsi while attaching bridge
> >
> > Changes for v5:
> > * bridge changes to support multi-arch
> > * updated and clear commit messages
> > * add hw_type via plat data
> > * removed unneeded quirk
> > * rebased on linux-next
> >
> > Changes for v4:
> > * include Inki Dae in MAINTAINERS
> > * remove dsi_driver probe in exynos_drm_drv to support multi-arch build
> > * update init handling to ensure host init done on first cmd transfer
> >
> > Changes for v3:
> > * fix the mult-arch build
> > * fix dsi host init
> > * updated commit messages
> >
> > Changes for v2:
> > * fix bridge handling
> > * fix dsi host init
> > * correct the commit messages
> >
> > Tested in Engicam i.Core MX8M Mini SoM.
> >
> > Repo:
> > https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v10
> >
> > v9:
> > https://lore.kernel.org/all/20221209152343.180139-1-jagan@amarulasolutions.com/
> >
> > Any inputs?
> > Jagan.
> >
> > Jagan Teki (16):
> >   drm: of: Lookup if child node has DSI panel or bridge
> >   drm: bridge: panel: Add devm_drm_of_dsi_get_bridge helper
> >   drm: exynos: dsi: Drop explicit call to bridge detach
> >   drm: exynos: dsi: Switch to devm_drm_of_dsi_get_bridge
> >   drm: exynos: dsi: Mark PHY as optional
> >   drm: exynos: dsi: Add platform PLL_P (PMS_P) offset
> >   drm: exynos: dsi: Introduce hw_type platform data
> >   drm: exynos: dsi: Add atomic check
> >   drm: exynos: dsi: Add input_bus_flags
> >   drm: exynos: dsi: Add atomic_get_input_bus_fmts
> >   drm: exynos: dsi: Consolidate component and bridge
> >   drm: exynos: dsi: Add Exynos based host irq hooks
> >   drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge
> >   dt-bindings: display: exynos: dsim: Add NXP i.MX8M Mini/Nano support
> >   drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support
> >   dt-bindings: display: exynos: dsim: Add NXP i.MX8M Plus support
> >
> > Marek Szyprowski (1):
> >   drm: exynos: dsi: Handle proper host initialization
> >
> > Marek Vasut (1):
> >   drm: bridge: samsung-dsim: Add i.MX8M Plus support
>
> Does anyone have any other comments on this? I would like to send v11
> with a few nits on v10. Please let me know.

I got it working on an LVDS display that I have, but I didn't get it
working on the HDMI bridge.  Since we have a few tested-by people,
it'd be nice to see this integrated so we can work on ading more
functionality

adam
>
> Thanks,
> Jagan.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Adam Ford]

On Thu, Jan 5, 2023 at 4:24 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> On Wed, Dec 14, 2022 at 6:29 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >
> > This series supports common bridge support for Samsung MIPI DSIM
> > which is used in Exynos and i.MX8MM SoC's.
> >
> > The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.
> >
> > Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge
> >
> > Patch 0005 - 0006: optional PHY, PMS_P offset
> >
> > Patch 0007       : introduce hw_type
> >
> > Patch 0008       : fixing host init
> >
> > Patch 0009       : atomic_check
> >
> > Patch 0010       : input_bus_flags
> >
> > Patch 0011       : atomic_get_input_bus_fmts
> >
> > Patch 0012 - 0013: component vs bridge
> >
> > Patch 0014       : DSIM bridge
> >
> > Patch 0015 - 0016: i.MX8M Mini/Nano
> >
> > Patch 0017 - 0018: i.MX8M Plus
> >
> > Changes for v10:
> > - rebase on drm-misc-next
> > - add drm_of_dsi_find_panel_or_bridge
> > - add devm_drm_of_dsi_get_bridge
> > - fix host initialization (Thanks to Marek Szyprowski)
> > - rearrange the tiny patches for easy to review
> > - update simple names for enum hw_type
> > - add is_hw_exynos macro
> > - rework on commit messages
> >
> > Changes for v9:
> > - rebase on drm-misc-next
> > - drop drm bridge attach fix for Exynos
> > - added prepare_prev_first flag
> > - added pre_enable_prev_first flag
> > - fix bridge chain order for exynos
> > - added fix for Exynos host init for first DSI transfer
> > - added MEDIA_BUS_FMT_FIXED
> > - return MEDIA_BUS_FMT_RGB888_1X24 output_fmt if supported output_fmt
> >   list is unsupported.
> > - added MEDIA_BUS_FMT_YUYV10_1X20
> > - added MEDIA_BUS_FMT_YUYV12_1X24
> >
> > Changes for v8:
> > * fixed comment lines
> > * fixed commit messages
> > * fixed video mode bits
> > * collect Marek Ack
> > * fixed video mode bit names
> > * update input formats logic
> > * added imx8mplus support
> >
> > Changes for v7:
> > * fix the drm bridge attach chain for exynos drm dsi driver
> > * fix the hw_type checking logic
> >
> > Changes for v6:
> > * handle previous bridge for exynos dsi while attaching bridge
> >
> > Changes for v5:
> > * bridge changes to support multi-arch
> > * updated and clear commit messages
> > * add hw_type via plat data
> > * removed unneeded quirk
> > * rebased on linux-next
> >
> > Changes for v4:
> > * include Inki Dae in MAINTAINERS
> > * remove dsi_driver probe in exynos_drm_drv to support multi-arch build
> > * update init handling to ensure host init done on first cmd transfer
> >
> > Changes for v3:
> > * fix the mult-arch build
> > * fix dsi host init
> > * updated commit messages
> >
> > Changes for v2:
> > * fix bridge handling
> > * fix dsi host init
> > * correct the commit messages
> >
> > Tested in Engicam i.Core MX8M Mini SoM.
> >
> > Repo:
> > https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v10
> >
> > v9:
> > https://lore.kernel.org/all/20221209152343.180139-1-jagan@amarulasolutions.com/
> >
> > Any inputs?
> > Jagan.
> >
> > Jagan Teki (16):
> >   drm: of: Lookup if child node has DSI panel or bridge
> >   drm: bridge: panel: Add devm_drm_of_dsi_get_bridge helper
> >   drm: exynos: dsi: Drop explicit call to bridge detach
> >   drm: exynos: dsi: Switch to devm_drm_of_dsi_get_bridge
> >   drm: exynos: dsi: Mark PHY as optional
> >   drm: exynos: dsi: Add platform PLL_P (PMS_P) offset
> >   drm: exynos: dsi: Introduce hw_type platform data
> >   drm: exynos: dsi: Add atomic check
> >   drm: exynos: dsi: Add input_bus_flags
> >   drm: exynos: dsi: Add atomic_get_input_bus_fmts
> >   drm: exynos: dsi: Consolidate component and bridge
> >   drm: exynos: dsi: Add Exynos based host irq hooks
> >   drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge
> >   dt-bindings: display: exynos: dsim: Add NXP i.MX8M Mini/Nano support
> >   drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support
> >   dt-bindings: display: exynos: dsim: Add NXP i.MX8M Plus support
> >
> > Marek Szyprowski (1):
> >   drm: exynos: dsi: Handle proper host initialization
> >
> > Marek Vasut (1):
> >   drm: bridge: samsung-dsim: Add i.MX8M Plus support
>
> Does anyone have any other comments on this? I would like to send v11
> with a few nits on v10. Please let me know.

I got it working on an LVDS display that I have, but I didn't get it
working on the HDMI bridge.  Since we have a few tested-by people,
it'd be nice to see this integrated so we can work on ading more
functionality

adam
>
> Thanks,
> Jagan.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

On Wed, Dec 14, 2022 at 6:29 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> This series supports common bridge support for Samsung MIPI DSIM
> which is used in Exynos and i.MX8MM SoC's.
>
> The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.
>
> Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge
>
> Patch 0005 - 0006: optional PHY, PMS_P offset
>
> Patch 0007       : introduce hw_type
>
> Patch 0008       : fixing host init
>
> Patch 0009       : atomic_check
>
> Patch 0010       : input_bus_flags
>
> Patch 0011       : atomic_get_input_bus_fmts
>
> Patch 0012 - 0013: component vs bridge
>
> Patch 0014       : DSIM bridge
>
> Patch 0015 - 0016: i.MX8M Mini/Nano
>
> Patch 0017 - 0018: i.MX8M Plus
>
> Changes for v10:
> - rebase on drm-misc-next
> - add drm_of_dsi_find_panel_or_bridge
> - add devm_drm_of_dsi_get_bridge
> - fix host initialization (Thanks to Marek Szyprowski)
> - rearrange the tiny patches for easy to review
> - update simple names for enum hw_type
> - add is_hw_exynos macro
> - rework on commit messages
>
> Changes for v9:
> - rebase on drm-misc-next
> - drop drm bridge attach fix for Exynos
> - added prepare_prev_first flag
> - added pre_enable_prev_first flag
> - fix bridge chain order for exynos
> - added fix for Exynos host init for first DSI transfer
> - added MEDIA_BUS_FMT_FIXED
> - return MEDIA_BUS_FMT_RGB888_1X24 output_fmt if supported output_fmt
>   list is unsupported.
> - added MEDIA_BUS_FMT_YUYV10_1X20
> - added MEDIA_BUS_FMT_YUYV12_1X24
>
> Changes for v8:
> * fixed comment lines
> * fixed commit messages
> * fixed video mode bits
> * collect Marek Ack
> * fixed video mode bit names
> * update input formats logic
> * added imx8mplus support
>
> Changes for v7:
> * fix the drm bridge attach chain for exynos drm dsi driver
> * fix the hw_type checking logic
>
> Changes for v6:
> * handle previous bridge for exynos dsi while attaching bridge
>
> Changes for v5:
> * bridge changes to support multi-arch
> * updated and clear commit messages
> * add hw_type via plat data
> * removed unneeded quirk
> * rebased on linux-next
>
> Changes for v4:
> * include Inki Dae in MAINTAINERS
> * remove dsi_driver probe in exynos_drm_drv to support multi-arch build
> * update init handling to ensure host init done on first cmd transfer
>
> Changes for v3:
> * fix the mult-arch build
> * fix dsi host init
> * updated commit messages
>
> Changes for v2:
> * fix bridge handling
> * fix dsi host init
> * correct the commit messages
>
> Tested in Engicam i.Core MX8M Mini SoM.
>
> Repo:
> https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v10
>
> v9:
> https://lore.kernel.org/all/20221209152343.180139-1-jagan@amarulasolutions.com/
>
> Any inputs?
> Jagan.
>
> Jagan Teki (16):
>   drm: of: Lookup if child node has DSI panel or bridge
>   drm: bridge: panel: Add devm_drm_of_dsi_get_bridge helper
>   drm: exynos: dsi: Drop explicit call to bridge detach
>   drm: exynos: dsi: Switch to devm_drm_of_dsi_get_bridge
>   drm: exynos: dsi: Mark PHY as optional
>   drm: exynos: dsi: Add platform PLL_P (PMS_P) offset
>   drm: exynos: dsi: Introduce hw_type platform data
>   drm: exynos: dsi: Add atomic check
>   drm: exynos: dsi: Add input_bus_flags
>   drm: exynos: dsi: Add atomic_get_input_bus_fmts
>   drm: exynos: dsi: Consolidate component and bridge
>   drm: exynos: dsi: Add Exynos based host irq hooks
>   drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge
>   dt-bindings: display: exynos: dsim: Add NXP i.MX8M Mini/Nano support
>   drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support
>   dt-bindings: display: exynos: dsim: Add NXP i.MX8M Plus support
>
> Marek Szyprowski (1):
>   drm: exynos: dsi: Handle proper host initialization
>
> Marek Vasut (1):
>   drm: bridge: samsung-dsim: Add i.MX8M Plus support

Does anyone have any other comments on this? I would like to send v11
with a few nits on v10. Please let me know.

Thanks,
Jagan.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

On Wed, Dec 14, 2022 at 6:29 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> This series supports common bridge support for Samsung MIPI DSIM
> which is used in Exynos and i.MX8MM SoC's.
>
> The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.
>
> Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge
>
> Patch 0005 - 0006: optional PHY, PMS_P offset
>
> Patch 0007       : introduce hw_type
>
> Patch 0008       : fixing host init
>
> Patch 0009       : atomic_check
>
> Patch 0010       : input_bus_flags
>
> Patch 0011       : atomic_get_input_bus_fmts
>
> Patch 0012 - 0013: component vs bridge
>
> Patch 0014       : DSIM bridge
>
> Patch 0015 - 0016: i.MX8M Mini/Nano
>
> Patch 0017 - 0018: i.MX8M Plus
>
> Changes for v10:
> - rebase on drm-misc-next
> - add drm_of_dsi_find_panel_or_bridge
> - add devm_drm_of_dsi_get_bridge
> - fix host initialization (Thanks to Marek Szyprowski)
> - rearrange the tiny patches for easy to review
> - update simple names for enum hw_type
> - add is_hw_exynos macro
> - rework on commit messages
>
> Changes for v9:
> - rebase on drm-misc-next
> - drop drm bridge attach fix for Exynos
> - added prepare_prev_first flag
> - added pre_enable_prev_first flag
> - fix bridge chain order for exynos
> - added fix for Exynos host init for first DSI transfer
> - added MEDIA_BUS_FMT_FIXED
> - return MEDIA_BUS_FMT_RGB888_1X24 output_fmt if supported output_fmt
>   list is unsupported.
> - added MEDIA_BUS_FMT_YUYV10_1X20
> - added MEDIA_BUS_FMT_YUYV12_1X24
>
> Changes for v8:
> * fixed comment lines
> * fixed commit messages
> * fixed video mode bits
> * collect Marek Ack
> * fixed video mode bit names
> * update input formats logic
> * added imx8mplus support
>
> Changes for v7:
> * fix the drm bridge attach chain for exynos drm dsi driver
> * fix the hw_type checking logic
>
> Changes for v6:
> * handle previous bridge for exynos dsi while attaching bridge
>
> Changes for v5:
> * bridge changes to support multi-arch
> * updated and clear commit messages
> * add hw_type via plat data
> * removed unneeded quirk
> * rebased on linux-next
>
> Changes for v4:
> * include Inki Dae in MAINTAINERS
> * remove dsi_driver probe in exynos_drm_drv to support multi-arch build
> * update init handling to ensure host init done on first cmd transfer
>
> Changes for v3:
> * fix the mult-arch build
> * fix dsi host init
> * updated commit messages
>
> Changes for v2:
> * fix bridge handling
> * fix dsi host init
> * correct the commit messages
>
> Tested in Engicam i.Core MX8M Mini SoM.
>
> Repo:
> https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v10
>
> v9:
> https://lore.kernel.org/all/20221209152343.180139-1-jagan@amarulasolutions.com/
>
> Any inputs?
> Jagan.
>
> Jagan Teki (16):
>   drm: of: Lookup if child node has DSI panel or bridge
>   drm: bridge: panel: Add devm_drm_of_dsi_get_bridge helper
>   drm: exynos: dsi: Drop explicit call to bridge detach
>   drm: exynos: dsi: Switch to devm_drm_of_dsi_get_bridge
>   drm: exynos: dsi: Mark PHY as optional
>   drm: exynos: dsi: Add platform PLL_P (PMS_P) offset
>   drm: exynos: dsi: Introduce hw_type platform data
>   drm: exynos: dsi: Add atomic check
>   drm: exynos: dsi: Add input_bus_flags
>   drm: exynos: dsi: Add atomic_get_input_bus_fmts
>   drm: exynos: dsi: Consolidate component and bridge
>   drm: exynos: dsi: Add Exynos based host irq hooks
>   drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge
>   dt-bindings: display: exynos: dsim: Add NXP i.MX8M Mini/Nano support
>   drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support
>   dt-bindings: display: exynos: dsim: Add NXP i.MX8M Plus support
>
> Marek Szyprowski (1):
>   drm: exynos: dsi: Handle proper host initialization
>
> Marek Vasut (1):
>   drm: bridge: samsung-dsim: Add i.MX8M Plus support

Does anyone have any other comments on this? I would like to send v11
with a few nits on v10. Please let me know.

Thanks,
Jagan.

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

On Wed, Dec 14, 2022 at 6:29 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> This series supports common bridge support for Samsung MIPI DSIM
> which is used in Exynos and i.MX8MM SoC's.
>
> The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.
>
> Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge
>
> Patch 0005 - 0006: optional PHY, PMS_P offset
>
> Patch 0007       : introduce hw_type
>
> Patch 0008       : fixing host init
>
> Patch 0009       : atomic_check
>
> Patch 0010       : input_bus_flags
>
> Patch 0011       : atomic_get_input_bus_fmts
>
> Patch 0012 - 0013: component vs bridge
>
> Patch 0014       : DSIM bridge
>
> Patch 0015 - 0016: i.MX8M Mini/Nano
>
> Patch 0017 - 0018: i.MX8M Plus
>
> Changes for v10:
> - rebase on drm-misc-next
> - add drm_of_dsi_find_panel_or_bridge
> - add devm_drm_of_dsi_get_bridge
> - fix host initialization (Thanks to Marek Szyprowski)
> - rearrange the tiny patches for easy to review
> - update simple names for enum hw_type
> - add is_hw_exynos macro
> - rework on commit messages
>
> Changes for v9:
> - rebase on drm-misc-next
> - drop drm bridge attach fix for Exynos
> - added prepare_prev_first flag
> - added pre_enable_prev_first flag
> - fix bridge chain order for exynos
> - added fix for Exynos host init for first DSI transfer
> - added MEDIA_BUS_FMT_FIXED
> - return MEDIA_BUS_FMT_RGB888_1X24 output_fmt if supported output_fmt
>   list is unsupported.
> - added MEDIA_BUS_FMT_YUYV10_1X20
> - added MEDIA_BUS_FMT_YUYV12_1X24
>
> Changes for v8:
> * fixed comment lines
> * fixed commit messages
> * fixed video mode bits
> * collect Marek Ack
> * fixed video mode bit names
> * update input formats logic
> * added imx8mplus support
>
> Changes for v7:
> * fix the drm bridge attach chain for exynos drm dsi driver
> * fix the hw_type checking logic
>
> Changes for v6:
> * handle previous bridge for exynos dsi while attaching bridge
>
> Changes for v5:
> * bridge changes to support multi-arch
> * updated and clear commit messages
> * add hw_type via plat data
> * removed unneeded quirk
> * rebased on linux-next
>
> Changes for v4:
> * include Inki Dae in MAINTAINERS
> * remove dsi_driver probe in exynos_drm_drv to support multi-arch build
> * update init handling to ensure host init done on first cmd transfer
>
> Changes for v3:
> * fix the mult-arch build
> * fix dsi host init
> * updated commit messages
>
> Changes for v2:
> * fix bridge handling
> * fix dsi host init
> * correct the commit messages
>
> Tested in Engicam i.Core MX8M Mini SoM.
>
> Repo:
> https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v10
>
> v9:
> https://lore.kernel.org/all/20221209152343.180139-1-jagan@amarulasolutions.com/
>
> Any inputs?
> Jagan.
>
> Jagan Teki (16):
>   drm: of: Lookup if child node has DSI panel or bridge
>   drm: bridge: panel: Add devm_drm_of_dsi_get_bridge helper
>   drm: exynos: dsi: Drop explicit call to bridge detach
>   drm: exynos: dsi: Switch to devm_drm_of_dsi_get_bridge
>   drm: exynos: dsi: Mark PHY as optional
>   drm: exynos: dsi: Add platform PLL_P (PMS_P) offset
>   drm: exynos: dsi: Introduce hw_type platform data
>   drm: exynos: dsi: Add atomic check
>   drm: exynos: dsi: Add input_bus_flags
>   drm: exynos: dsi: Add atomic_get_input_bus_fmts
>   drm: exynos: dsi: Consolidate component and bridge
>   drm: exynos: dsi: Add Exynos based host irq hooks
>   drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge
>   dt-bindings: display: exynos: dsim: Add NXP i.MX8M Mini/Nano support
>   drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support
>   dt-bindings: display: exynos: dsim: Add NXP i.MX8M Plus support
>
> Marek Szyprowski (1):
>   drm: exynos: dsi: Handle proper host initialization
>
> Marek Vasut (1):
>   drm: bridge: samsung-dsim: Add i.MX8M Plus support

Does anyone have any other comments on this? I would like to send v11
with a few nits on v10. Please let me know.

Thanks,
Jagan.

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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 12/16/22 13:41, Alexander Stein wrote:
> Hi,

Hi,

> thanks for the new update.
> 
> Am Mittwoch, 14. Dezember 2022, 13:58:49 CET schrieb Jagan Teki:
>> This series supports common bridge support for Samsung MIPI DSIM
>> which is used in Exynos and i.MX8MM SoC's.
>>
>> The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.
>>
>> Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge
>>
>> Patch 0005 - 0006: optional PHY, PMS_P offset
>>
>> Patch 0007       : introduce hw_type
>>
>> Patch 0008	 : fixing host init
>>
>> Patch 0009	 : atomic_check
>>
>> Patch 0010	 : input_bus_flags
>>
>> Patch 0011	 : atomic_get_input_bus_fmts
>>
>> Patch 0012 - 0013: component vs bridge
>>
>> Patch 0014	 : DSIM bridge
>>
>> Patch 0015 - 0016: i.MX8M Mini/Nano
>>
>> Patch 0017 - 0018: i.MX8M Plus
> 
> Tested using LVDS bridges and works on:
> * imx8mp-tqma8mpql-mba8mpxl (i.MX8M Plus)
> * imx8mm-tqma8mqml-mba8mx (i.MX8M Mini)
> * imx8mn-tqma8mqnl-mba8mx (i.MX8M Nano)
> 
> But I noticed that tqma8mqml and tqma8mqnl only have a stable output if I
> specify 'data-lanes = <0 1 2>' (not <0 1 2 3>!) on the DSI-LVDS-Bridge (TI
> SN65DSI83) input endpoint, e.g.
> 
> dsi_lvds_bridge: bridge@2d {
> 	compatible = "ti,sn65dsi83";
> 	reg = <0x2d>;
> 	enable-gpios = <&gpio_delays 0 130000 0>;
> 	vcc-supply = <&reg_sn65dsi83_1v8>;
> 	status = "okay";
> 	ports {
> 		#address-cells = <1>;
> 		#size-cells = <0>;
> 		port@0 {
> 			reg = <0>;
> 			lvds_bridge_in: endpoint {
> 				data-lanes = <0 1 2>;
> 				remote-endpoint = <&mipi_dsi_out>;
> 			};
> 		};
> 		port@2 {
> 			reg = <2>;
> 			lvds_bridge_out: endpoint {
> 				remote-endpoint = <&panel_in_lvds0>;
> 			};
> 		};
> 	};
> };
> 
> I have no idea if this is on the DSIM side or the DSI-LVDS bridge side.
> Register 0xe5 on sn65dsi83 shows that CHA_LPP_ERR and CHA_SOT_BIT_ERR error
> bits are set, indicating there are low level protocol and SoT leader sequence
> bit errors. I can't find any significant difference in sn65dsi83 driver
> compared to downstream-kernel, so I would assume something in DSIM driver is
> different.

Make sure the HS clock rate expected by the DSI83 bridge chip and the 
one generated by the DSIM bridge from PMS PLL match. There is currently 
no negotiation of this frequency and both sides divine it on their own.

See sn65dsi83_get_dsi_range() and samsung_dsim_set_pll().

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 12/16/22 13:41, Alexander Stein wrote:
> Hi,

Hi,

> thanks for the new update.
> 
> Am Mittwoch, 14. Dezember 2022, 13:58:49 CET schrieb Jagan Teki:
>> This series supports common bridge support for Samsung MIPI DSIM
>> which is used in Exynos and i.MX8MM SoC's.
>>
>> The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.
>>
>> Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge
>>
>> Patch 0005 - 0006: optional PHY, PMS_P offset
>>
>> Patch 0007       : introduce hw_type
>>
>> Patch 0008	 : fixing host init
>>
>> Patch 0009	 : atomic_check
>>
>> Patch 0010	 : input_bus_flags
>>
>> Patch 0011	 : atomic_get_input_bus_fmts
>>
>> Patch 0012 - 0013: component vs bridge
>>
>> Patch 0014	 : DSIM bridge
>>
>> Patch 0015 - 0016: i.MX8M Mini/Nano
>>
>> Patch 0017 - 0018: i.MX8M Plus
> 
> Tested using LVDS bridges and works on:
> * imx8mp-tqma8mpql-mba8mpxl (i.MX8M Plus)
> * imx8mm-tqma8mqml-mba8mx (i.MX8M Mini)
> * imx8mn-tqma8mqnl-mba8mx (i.MX8M Nano)
> 
> But I noticed that tqma8mqml and tqma8mqnl only have a stable output if I
> specify 'data-lanes = <0 1 2>' (not <0 1 2 3>!) on the DSI-LVDS-Bridge (TI
> SN65DSI83) input endpoint, e.g.
> 
> dsi_lvds_bridge: bridge@2d {
> 	compatible = "ti,sn65dsi83";
> 	reg = <0x2d>;
> 	enable-gpios = <&gpio_delays 0 130000 0>;
> 	vcc-supply = <&reg_sn65dsi83_1v8>;
> 	status = "okay";
> 	ports {
> 		#address-cells = <1>;
> 		#size-cells = <0>;
> 		port@0 {
> 			reg = <0>;
> 			lvds_bridge_in: endpoint {
> 				data-lanes = <0 1 2>;
> 				remote-endpoint = <&mipi_dsi_out>;
> 			};
> 		};
> 		port@2 {
> 			reg = <2>;
> 			lvds_bridge_out: endpoint {
> 				remote-endpoint = <&panel_in_lvds0>;
> 			};
> 		};
> 	};
> };
> 
> I have no idea if this is on the DSIM side or the DSI-LVDS bridge side.
> Register 0xe5 on sn65dsi83 shows that CHA_LPP_ERR and CHA_SOT_BIT_ERR error
> bits are set, indicating there are low level protocol and SoT leader sequence
> bit errors. I can't find any significant difference in sn65dsi83 driver
> compared to downstream-kernel, so I would assume something in DSIM driver is
> different.

Make sure the HS clock rate expected by the DSI83 bridge chip and the 
one generated by the DSIM bridge from PMS PLL match. There is currently 
no negotiation of this frequency and both sides divine it on their own.

See sn65dsi83_get_dsi_range() and samsung_dsim_set_pll().

Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Marek Vasut]

On 12/16/22 13:41, Alexander Stein wrote:
> Hi,

Hi,

> thanks for the new update.
> 
> Am Mittwoch, 14. Dezember 2022, 13:58:49 CET schrieb Jagan Teki:
>> This series supports common bridge support for Samsung MIPI DSIM
>> which is used in Exynos and i.MX8MM SoC's.
>>
>> The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.
>>
>> Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge
>>
>> Patch 0005 - 0006: optional PHY, PMS_P offset
>>
>> Patch 0007       : introduce hw_type
>>
>> Patch 0008	 : fixing host init
>>
>> Patch 0009	 : atomic_check
>>
>> Patch 0010	 : input_bus_flags
>>
>> Patch 0011	 : atomic_get_input_bus_fmts
>>
>> Patch 0012 - 0013: component vs bridge
>>
>> Patch 0014	 : DSIM bridge
>>
>> Patch 0015 - 0016: i.MX8M Mini/Nano
>>
>> Patch 0017 - 0018: i.MX8M Plus
> 
> Tested using LVDS bridges and works on:
> * imx8mp-tqma8mpql-mba8mpxl (i.MX8M Plus)
> * imx8mm-tqma8mqml-mba8mx (i.MX8M Mini)
> * imx8mn-tqma8mqnl-mba8mx (i.MX8M Nano)
> 
> But I noticed that tqma8mqml and tqma8mqnl only have a stable output if I
> specify 'data-lanes = <0 1 2>' (not <0 1 2 3>!) on the DSI-LVDS-Bridge (TI
> SN65DSI83) input endpoint, e.g.
> 
> dsi_lvds_bridge: bridge@2d {
> 	compatible = "ti,sn65dsi83";
> 	reg = <0x2d>;
> 	enable-gpios = <&gpio_delays 0 130000 0>;
> 	vcc-supply = <&reg_sn65dsi83_1v8>;
> 	status = "okay";
> 	ports {
> 		#address-cells = <1>;
> 		#size-cells = <0>;
> 		port@0 {
> 			reg = <0>;
> 			lvds_bridge_in: endpoint {
> 				data-lanes = <0 1 2>;
> 				remote-endpoint = <&mipi_dsi_out>;
> 			};
> 		};
> 		port@2 {
> 			reg = <2>;
> 			lvds_bridge_out: endpoint {
> 				remote-endpoint = <&panel_in_lvds0>;
> 			};
> 		};
> 	};
> };
> 
> I have no idea if this is on the DSIM side or the DSI-LVDS bridge side.
> Register 0xe5 on sn65dsi83 shows that CHA_LPP_ERR and CHA_SOT_BIT_ERR error
> bits are set, indicating there are low level protocol and SoT leader sequence
> bit errors. I can't find any significant difference in sn65dsi83 driver
> compared to downstream-kernel, so I would assume something in DSIM driver is
> different.

Make sure the HS clock rate expected by the DSI83 bridge chip and the 
one generated by the DSIM bridge from PMS PLL match. There is currently 
no negotiation of this frequency and both sides divine it on their own.

See sn65dsi83_get_dsi_range() and samsung_dsim_set_pll().

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Alexander Stein]

Hi,

thanks for the new update.

Am Mittwoch, 14. Dezember 2022, 13:58:49 CET schrieb Jagan Teki:
> This series supports common bridge support for Samsung MIPI DSIM
> which is used in Exynos and i.MX8MM SoC's.
> 
> The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.
> 
> Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge
> 
> Patch 0005 - 0006: optional PHY, PMS_P offset
> 
> Patch 0007       : introduce hw_type
> 
> Patch 0008	 : fixing host init
> 
> Patch 0009	 : atomic_check
> 
> Patch 0010	 : input_bus_flags
> 
> Patch 0011	 : atomic_get_input_bus_fmts
> 
> Patch 0012 - 0013: component vs bridge
> 
> Patch 0014	 : DSIM bridge
> 
> Patch 0015 - 0016: i.MX8M Mini/Nano
> 
> Patch 0017 - 0018: i.MX8M Plus

Tested using LVDS bridges and works on:
* imx8mp-tqma8mpql-mba8mpxl (i.MX8M Plus)
* imx8mm-tqma8mqml-mba8mx (i.MX8M Mini)
* imx8mn-tqma8mqnl-mba8mx (i.MX8M Nano)

But I noticed that tqma8mqml and tqma8mqnl only have a stable output if I 
specify 'data-lanes = <0 1 2>' (not <0 1 2 3>!) on the DSI-LVDS-Bridge (TI 
SN65DSI83) input endpoint, e.g. 

dsi_lvds_bridge: bridge@2d {
	compatible = "ti,sn65dsi83";
	reg = <0x2d>;
	enable-gpios = <&gpio_delays 0 130000 0>;
	vcc-supply = <&reg_sn65dsi83_1v8>;
	status = "okay";
	ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
			reg = <0>;
			lvds_bridge_in: endpoint {
				data-lanes = <0 1 2>;
				remote-endpoint = <&mipi_dsi_out>;
			};
		};
		port@2 {
			reg = <2>;
			lvds_bridge_out: endpoint {
				remote-endpoint = <&panel_in_lvds0>;
			};
		};
	};
};

I have no idea if this is on the DSIM side or the DSI-LVDS bridge side. 
Register 0xe5 on sn65dsi83 shows that CHA_LPP_ERR and CHA_SOT_BIT_ERR error 
bits are set, indicating there are low level protocol and SoT leader sequence 
bit errors. I can't find any significant difference in sn65dsi83 driver 
compared to downstream-kernel, so I would assume something in DSIM driver is 
different.

Best regards,
Alexander

> Changes for v10:
> - rebase on drm-misc-next
> - add drm_of_dsi_find_panel_or_bridge
> - add devm_drm_of_dsi_get_bridge
> - fix host initialization (Thanks to Marek Szyprowski)
> - rearrange the tiny patches for easy to review
> - update simple names for enum hw_type
> - add is_hw_exynos macro
> - rework on commit messages
> 
> Changes for v9:
> - rebase on drm-misc-next
> - drop drm bridge attach fix for Exynos
> - added prepare_prev_first flag
> - added pre_enable_prev_first flag
> - fix bridge chain order for exynos
> - added fix for Exynos host init for first DSI transfer
> - added MEDIA_BUS_FMT_FIXED
> - return MEDIA_BUS_FMT_RGB888_1X24 output_fmt if supported output_fmt
>   list is unsupported.
> - added MEDIA_BUS_FMT_YUYV10_1X20
> - added MEDIA_BUS_FMT_YUYV12_1X24
> 
> Changes for v8:
> * fixed comment lines
> * fixed commit messages
> * fixed video mode bits
> * collect Marek Ack
> * fixed video mode bit names
> * update input formats logic
> * added imx8mplus support
> 
> Changes for v7:
> * fix the drm bridge attach chain for exynos drm dsi driver
> * fix the hw_type checking logic
> 
> Changes for v6:
> * handle previous bridge for exynos dsi while attaching bridge
> 
> Changes for v5:
> * bridge changes to support multi-arch
> * updated and clear commit messages
> * add hw_type via plat data
> * removed unneeded quirk
> * rebased on linux-next
> 
> Changes for v4:
> * include Inki Dae in MAINTAINERS
> * remove dsi_driver probe in exynos_drm_drv to support multi-arch build
> * update init handling to ensure host init done on first cmd transfer
> 
> Changes for v3:
> * fix the mult-arch build
> * fix dsi host init
> * updated commit messages
> 
> Changes for v2:
> * fix bridge handling
> * fix dsi host init
> * correct the commit messages
> 
> Tested in Engicam i.Core MX8M Mini SoM.
> 
> Repo:
> https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v10
> 
> v9:
> https://lore.kernel.org/all/20221209152343.180139-1-jagan@amarulasolutions.c
> om/
> 
> Any inputs?
> Jagan.
> 
> Jagan Teki (16):
>   drm: of: Lookup if child node has DSI panel or bridge
>   drm: bridge: panel: Add devm_drm_of_dsi_get_bridge helper
>   drm: exynos: dsi: Drop explicit call to bridge detach
>   drm: exynos: dsi: Switch to devm_drm_of_dsi_get_bridge
>   drm: exynos: dsi: Mark PHY as optional
>   drm: exynos: dsi: Add platform PLL_P (PMS_P) offset
>   drm: exynos: dsi: Introduce hw_type platform data
>   drm: exynos: dsi: Add atomic check
>   drm: exynos: dsi: Add input_bus_flags
>   drm: exynos: dsi: Add atomic_get_input_bus_fmts
>   drm: exynos: dsi: Consolidate component and bridge
>   drm: exynos: dsi: Add Exynos based host irq hooks
>   drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge
>   dt-bindings: display: exynos: dsim: Add NXP i.MX8M Mini/Nano support
>   drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support
>   dt-bindings: display: exynos: dsim: Add NXP i.MX8M Plus support
> 
> Marek Szyprowski (1):
>   drm: exynos: dsi: Handle proper host initialization
> 
> Marek Vasut (1):
>   drm: bridge: samsung-dsim: Add i.MX8M Plus support
> 
>  .../bindings/display/exynos/exynos_dsim.txt   |    2 +
>  MAINTAINERS                                   |    9 +
>  drivers/gpu/drm/bridge/Kconfig                |   12 +
>  drivers/gpu/drm/bridge/Makefile               |    1 +
>  drivers/gpu/drm/bridge/panel.c                |   34 +
>  drivers/gpu/drm/bridge/samsung-dsim.c         | 1883 +++++++++++++++++
>  drivers/gpu/drm/drm_of.c                      |  113 +-
>  drivers/gpu/drm/exynos/Kconfig                |    1 +
>  drivers/gpu/drm/exynos/exynos_drm_dsi.c       | 1793 +---------------
>  include/drm/bridge/samsung-dsim.h             |  119 ++
>  include/drm/drm_bridge.h                      |    2 +
>  include/drm/drm_of.h                          |   12 +
>  12 files changed, 2285 insertions(+), 1696 deletions(-)
>  create mode 100644 drivers/gpu/drm/bridge/samsung-dsim.c
>  create mode 100644 include/drm/bridge/samsung-dsim.h

[PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Alexander Stein]

Hi,

thanks for the new update.

Am Mittwoch, 14. Dezember 2022, 13:58:49 CET schrieb Jagan Teki:
> This series supports common bridge support for Samsung MIPI DSIM
> which is used in Exynos and i.MX8MM SoC's.
> 
> The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.
> 
> Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge
> 
> Patch 0005 - 0006: optional PHY, PMS_P offset
> 
> Patch 0007       : introduce hw_type
> 
> Patch 0008	 : fixing host init
> 
> Patch 0009	 : atomic_check
> 
> Patch 0010	 : input_bus_flags
> 
> Patch 0011	 : atomic_get_input_bus_fmts
> 
> Patch 0012 - 0013: component vs bridge
> 
> Patch 0014	 : DSIM bridge
> 
> Patch 0015 - 0016: i.MX8M Mini/Nano
> 
> Patch 0017 - 0018: i.MX8M Plus

Tested using LVDS bridges and works on:
* imx8mp-tqma8mpql-mba8mpxl (i.MX8M Plus)
* imx8mm-tqma8mqml-mba8mx (i.MX8M Mini)
* imx8mn-tqma8mqnl-mba8mx (i.MX8M Nano)

But I noticed that tqma8mqml and tqma8mqnl only have a stable output if I 
specify 'data-lanes = <0 1 2>' (not <0 1 2 3>!) on the DSI-LVDS-Bridge (TI 
SN65DSI83) input endpoint, e.g. 

dsi_lvds_bridge: bridge@2d {
	compatible = "ti,sn65dsi83";
	reg = <0x2d>;
	enable-gpios = <&gpio_delays 0 130000 0>;
	vcc-supply = <&reg_sn65dsi83_1v8>;
	status = "okay";
	ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
			reg = <0>;
			lvds_bridge_in: endpoint {
				data-lanes = <0 1 2>;
				remote-endpoint = <&mipi_dsi_out>;
			};
		};
		port@2 {
			reg = <2>;
			lvds_bridge_out: endpoint {
				remote-endpoint = <&panel_in_lvds0>;
			};
		};
	};
};

I have no idea if this is on the DSIM side or the DSI-LVDS bridge side. 
Register 0xe5 on sn65dsi83 shows that CHA_LPP_ERR and CHA_SOT_BIT_ERR error 
bits are set, indicating there are low level protocol and SoT leader sequence 
bit errors. I can't find any significant difference in sn65dsi83 driver 
compared to downstream-kernel, so I would assume something in DSIM driver is 
different.

Best regards,
Alexander

> Changes for v10:
> - rebase on drm-misc-next
> - add drm_of_dsi_find_panel_or_bridge
> - add devm_drm_of_dsi_get_bridge
> - fix host initialization (Thanks to Marek Szyprowski)
> - rearrange the tiny patches for easy to review
> - update simple names for enum hw_type
> - add is_hw_exynos macro
> - rework on commit messages
> 
> Changes for v9:
> - rebase on drm-misc-next
> - drop drm bridge attach fix for Exynos
> - added prepare_prev_first flag
> - added pre_enable_prev_first flag
> - fix bridge chain order for exynos
> - added fix for Exynos host init for first DSI transfer
> - added MEDIA_BUS_FMT_FIXED
> - return MEDIA_BUS_FMT_RGB888_1X24 output_fmt if supported output_fmt
>   list is unsupported.
> - added MEDIA_BUS_FMT_YUYV10_1X20
> - added MEDIA_BUS_FMT_YUYV12_1X24
> 
> Changes for v8:
> * fixed comment lines
> * fixed commit messages
> * fixed video mode bits
> * collect Marek Ack
> * fixed video mode bit names
> * update input formats logic
> * added imx8mplus support
> 
> Changes for v7:
> * fix the drm bridge attach chain for exynos drm dsi driver
> * fix the hw_type checking logic
> 
> Changes for v6:
> * handle previous bridge for exynos dsi while attaching bridge
> 
> Changes for v5:
> * bridge changes to support multi-arch
> * updated and clear commit messages
> * add hw_type via plat data
> * removed unneeded quirk
> * rebased on linux-next
> 
> Changes for v4:
> * include Inki Dae in MAINTAINERS
> * remove dsi_driver probe in exynos_drm_drv to support multi-arch build
> * update init handling to ensure host init done on first cmd transfer
> 
> Changes for v3:
> * fix the mult-arch build
> * fix dsi host init
> * updated commit messages
> 
> Changes for v2:
> * fix bridge handling
> * fix dsi host init
> * correct the commit messages
> 
> Tested in Engicam i.Core MX8M Mini SoM.
> 
> Repo:
> https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v10
> 
> v9:
> https://lore.kernel.org/all/20221209152343.180139-1-jagan@amarulasolutions.c
> om/
> 
> Any inputs?
> Jagan.
> 
> Jagan Teki (16):
>   drm: of: Lookup if child node has DSI panel or bridge
>   drm: bridge: panel: Add devm_drm_of_dsi_get_bridge helper
>   drm: exynos: dsi: Drop explicit call to bridge detach
>   drm: exynos: dsi: Switch to devm_drm_of_dsi_get_bridge
>   drm: exynos: dsi: Mark PHY as optional
>   drm: exynos: dsi: Add platform PLL_P (PMS_P) offset
>   drm: exynos: dsi: Introduce hw_type platform data
>   drm: exynos: dsi: Add atomic check
>   drm: exynos: dsi: Add input_bus_flags
>   drm: exynos: dsi: Add atomic_get_input_bus_fmts
>   drm: exynos: dsi: Consolidate component and bridge
>   drm: exynos: dsi: Add Exynos based host irq hooks
>   drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge
>   dt-bindings: display: exynos: dsim: Add NXP i.MX8M Mini/Nano support
>   drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support
>   dt-bindings: display: exynos: dsim: Add NXP i.MX8M Plus support
> 
> Marek Szyprowski (1):
>   drm: exynos: dsi: Handle proper host initialization
> 
> Marek Vasut (1):
>   drm: bridge: samsung-dsim: Add i.MX8M Plus support
> 
>  .../bindings/display/exynos/exynos_dsim.txt   |    2 +
>  MAINTAINERS                                   |    9 +
>  drivers/gpu/drm/bridge/Kconfig                |   12 +
>  drivers/gpu/drm/bridge/Makefile               |    1 +
>  drivers/gpu/drm/bridge/panel.c                |   34 +
>  drivers/gpu/drm/bridge/samsung-dsim.c         | 1883 +++++++++++++++++
>  drivers/gpu/drm/drm_of.c                      |  113 +-
>  drivers/gpu/drm/exynos/Kconfig                |    1 +
>  drivers/gpu/drm/exynos/exynos_drm_dsi.c       | 1793 +---------------
>  include/drm/bridge/samsung-dsim.h             |  119 ++
>  include/drm/drm_bridge.h                      |    2 +
>  include/drm/drm_of.h                          |   12 +
>  12 files changed, 2285 insertions(+), 1696 deletions(-)
>  create mode 100644 drivers/gpu/drm/bridge/samsung-dsim.c
>  create mode 100644 include/drm/bridge/samsung-dsim.h

[PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Alexander Stein]

Hi,

thanks for the new update.

Am Mittwoch, 14. Dezember 2022, 13:58:49 CET schrieb Jagan Teki:
> This series supports common bridge support for Samsung MIPI DSIM
> which is used in Exynos and i.MX8MM SoC's.
> 
> The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.
> 
> Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge
> 
> Patch 0005 - 0006: optional PHY, PMS_P offset
> 
> Patch 0007       : introduce hw_type
> 
> Patch 0008	 : fixing host init
> 
> Patch 0009	 : atomic_check
> 
> Patch 0010	 : input_bus_flags
> 
> Patch 0011	 : atomic_get_input_bus_fmts
> 
> Patch 0012 - 0013: component vs bridge
> 
> Patch 0014	 : DSIM bridge
> 
> Patch 0015 - 0016: i.MX8M Mini/Nano
> 
> Patch 0017 - 0018: i.MX8M Plus

Tested using LVDS bridges and works on:
* imx8mp-tqma8mpql-mba8mpxl (i.MX8M Plus)
* imx8mm-tqma8mqml-mba8mx (i.MX8M Mini)
* imx8mn-tqma8mqnl-mba8mx (i.MX8M Nano)

But I noticed that tqma8mqml and tqma8mqnl only have a stable output if I 
specify 'data-lanes = <0 1 2>' (not <0 1 2 3>!) on the DSI-LVDS-Bridge (TI 
SN65DSI83) input endpoint, e.g. 

dsi_lvds_bridge: bridge@2d {
	compatible = "ti,sn65dsi83";
	reg = <0x2d>;
	enable-gpios = <&gpio_delays 0 130000 0>;
	vcc-supply = <&reg_sn65dsi83_1v8>;
	status = "okay";
	ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
			reg = <0>;
			lvds_bridge_in: endpoint {
				data-lanes = <0 1 2>;
				remote-endpoint = <&mipi_dsi_out>;
			};
		};
		port@2 {
			reg = <2>;
			lvds_bridge_out: endpoint {
				remote-endpoint = <&panel_in_lvds0>;
			};
		};
	};
};

I have no idea if this is on the DSIM side or the DSI-LVDS bridge side. 
Register 0xe5 on sn65dsi83 shows that CHA_LPP_ERR and CHA_SOT_BIT_ERR error 
bits are set, indicating there are low level protocol and SoT leader sequence 
bit errors. I can't find any significant difference in sn65dsi83 driver 
compared to downstream-kernel, so I would assume something in DSIM driver is 
different.

Best regards,
Alexander

> Changes for v10:
> - rebase on drm-misc-next
> - add drm_of_dsi_find_panel_or_bridge
> - add devm_drm_of_dsi_get_bridge
> - fix host initialization (Thanks to Marek Szyprowski)
> - rearrange the tiny patches for easy to review
> - update simple names for enum hw_type
> - add is_hw_exynos macro
> - rework on commit messages
> 
> Changes for v9:
> - rebase on drm-misc-next
> - drop drm bridge attach fix for Exynos
> - added prepare_prev_first flag
> - added pre_enable_prev_first flag
> - fix bridge chain order for exynos
> - added fix for Exynos host init for first DSI transfer
> - added MEDIA_BUS_FMT_FIXED
> - return MEDIA_BUS_FMT_RGB888_1X24 output_fmt if supported output_fmt
>   list is unsupported.
> - added MEDIA_BUS_FMT_YUYV10_1X20
> - added MEDIA_BUS_FMT_YUYV12_1X24
> 
> Changes for v8:
> * fixed comment lines
> * fixed commit messages
> * fixed video mode bits
> * collect Marek Ack
> * fixed video mode bit names
> * update input formats logic
> * added imx8mplus support
> 
> Changes for v7:
> * fix the drm bridge attach chain for exynos drm dsi driver
> * fix the hw_type checking logic
> 
> Changes for v6:
> * handle previous bridge for exynos dsi while attaching bridge
> 
> Changes for v5:
> * bridge changes to support multi-arch
> * updated and clear commit messages
> * add hw_type via plat data
> * removed unneeded quirk
> * rebased on linux-next
> 
> Changes for v4:
> * include Inki Dae in MAINTAINERS
> * remove dsi_driver probe in exynos_drm_drv to support multi-arch build
> * update init handling to ensure host init done on first cmd transfer
> 
> Changes for v3:
> * fix the mult-arch build
> * fix dsi host init
> * updated commit messages
> 
> Changes for v2:
> * fix bridge handling
> * fix dsi host init
> * correct the commit messages
> 
> Tested in Engicam i.Core MX8M Mini SoM.
> 
> Repo:
> https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v10
> 
> v9:
> https://lore.kernel.org/all/20221209152343.180139-1-jagan@amarulasolutions.c
> om/
> 
> Any inputs?
> Jagan.
> 
> Jagan Teki (16):
>   drm: of: Lookup if child node has DSI panel or bridge
>   drm: bridge: panel: Add devm_drm_of_dsi_get_bridge helper
>   drm: exynos: dsi: Drop explicit call to bridge detach
>   drm: exynos: dsi: Switch to devm_drm_of_dsi_get_bridge
>   drm: exynos: dsi: Mark PHY as optional
>   drm: exynos: dsi: Add platform PLL_P (PMS_P) offset
>   drm: exynos: dsi: Introduce hw_type platform data
>   drm: exynos: dsi: Add atomic check
>   drm: exynos: dsi: Add input_bus_flags
>   drm: exynos: dsi: Add atomic_get_input_bus_fmts
>   drm: exynos: dsi: Consolidate component and bridge
>   drm: exynos: dsi: Add Exynos based host irq hooks
>   drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge
>   dt-bindings: display: exynos: dsim: Add NXP i.MX8M Mini/Nano support
>   drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support
>   dt-bindings: display: exynos: dsim: Add NXP i.MX8M Plus support
> 
> Marek Szyprowski (1):
>   drm: exynos: dsi: Handle proper host initialization
> 
> Marek Vasut (1):
>   drm: bridge: samsung-dsim: Add i.MX8M Plus support
> 
>  .../bindings/display/exynos/exynos_dsim.txt   |    2 +
>  MAINTAINERS                                   |    9 +
>  drivers/gpu/drm/bridge/Kconfig                |   12 +
>  drivers/gpu/drm/bridge/Makefile               |    1 +
>  drivers/gpu/drm/bridge/panel.c                |   34 +
>  drivers/gpu/drm/bridge/samsung-dsim.c         | 1883 +++++++++++++++++
>  drivers/gpu/drm/drm_of.c                      |  113 +-
>  drivers/gpu/drm/exynos/Kconfig                |    1 +
>  drivers/gpu/drm/exynos/exynos_drm_dsi.c       | 1793 +---------------
>  include/drm/bridge/samsung-dsim.h             |  119 ++
>  include/drm/drm_bridge.h                      |    2 +
>  include/drm/drm_of.h                          |   12 +
>  12 files changed, 2285 insertions(+), 1696 deletions(-)
>  create mode 100644 drivers/gpu/drm/bridge/samsung-dsim.c
>  create mode 100644 include/drm/bridge/samsung-dsim.h


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[PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

This series supports common bridge support for Samsung MIPI DSIM
which is used in Exynos and i.MX8MM SoC's.

The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.

Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge

Patch 0005 - 0006: optional PHY, PMS_P offset

Patch 0007       : introduce hw_type

Patch 0008	 : fixing host init

Patch 0009	 : atomic_check

Patch 0010	 : input_bus_flags

Patch 0011	 : atomic_get_input_bus_fmts

Patch 0012 - 0013: component vs bridge

Patch 0014	 : DSIM bridge

Patch 0015 - 0016: i.MX8M Mini/Nano

Patch 0017 - 0018: i.MX8M Plus

Changes for v10:
- rebase on drm-misc-next
- add drm_of_dsi_find_panel_or_bridge
- add devm_drm_of_dsi_get_bridge
- fix host initialization (Thanks to Marek Szyprowski)
- rearrange the tiny patches for easy to review
- update simple names for enum hw_type
- add is_hw_exynos macro
- rework on commit messages

Changes for v9:
- rebase on drm-misc-next
- drop drm bridge attach fix for Exynos
- added prepare_prev_first flag
- added pre_enable_prev_first flag
- fix bridge chain order for exynos
- added fix for Exynos host init for first DSI transfer
- added MEDIA_BUS_FMT_FIXED
- return MEDIA_BUS_FMT_RGB888_1X24 output_fmt if supported output_fmt
  list is unsupported.
- added MEDIA_BUS_FMT_YUYV10_1X20
- added MEDIA_BUS_FMT_YUYV12_1X24

Changes for v8:
* fixed comment lines
* fixed commit messages
* fixed video mode bits
* collect Marek Ack
* fixed video mode bit names
* update input formats logic
* added imx8mplus support

Changes for v7:
* fix the drm bridge attach chain for exynos drm dsi driver
* fix the hw_type checking logic

Changes for v6:
* handle previous bridge for exynos dsi while attaching bridge 

Changes for v5:
* bridge changes to support multi-arch
* updated and clear commit messages
* add hw_type via plat data
* removed unneeded quirk
* rebased on linux-next

Changes for v4:
* include Inki Dae in MAINTAINERS
* remove dsi_driver probe in exynos_drm_drv to support multi-arch build
* update init handling to ensure host init done on first cmd transfer

Changes for v3:
* fix the mult-arch build
* fix dsi host init
* updated commit messages

Changes for v2:
* fix bridge handling
* fix dsi host init
* correct the commit messages

Tested in Engicam i.Core MX8M Mini SoM.

Repo:
https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v10

v9:
https://lore.kernel.org/all/20221209152343.180139-1-jagan@amarulasolutions.com/

Any inputs?
Jagan.

Jagan Teki (16):
  drm: of: Lookup if child node has DSI panel or bridge
  drm: bridge: panel: Add devm_drm_of_dsi_get_bridge helper
  drm: exynos: dsi: Drop explicit call to bridge detach
  drm: exynos: dsi: Switch to devm_drm_of_dsi_get_bridge
  drm: exynos: dsi: Mark PHY as optional
  drm: exynos: dsi: Add platform PLL_P (PMS_P) offset
  drm: exynos: dsi: Introduce hw_type platform data
  drm: exynos: dsi: Add atomic check
  drm: exynos: dsi: Add input_bus_flags
  drm: exynos: dsi: Add atomic_get_input_bus_fmts
  drm: exynos: dsi: Consolidate component and bridge
  drm: exynos: dsi: Add Exynos based host irq hooks
  drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge
  dt-bindings: display: exynos: dsim: Add NXP i.MX8M Mini/Nano support
  drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support
  dt-bindings: display: exynos: dsim: Add NXP i.MX8M Plus support

Marek Szyprowski (1):
  drm: exynos: dsi: Handle proper host initialization

Marek Vasut (1):
  drm: bridge: samsung-dsim: Add i.MX8M Plus support

 .../bindings/display/exynos/exynos_dsim.txt   |    2 +
 MAINTAINERS                                   |    9 +
 drivers/gpu/drm/bridge/Kconfig                |   12 +
 drivers/gpu/drm/bridge/Makefile               |    1 +
 drivers/gpu/drm/bridge/panel.c                |   34 +
 drivers/gpu/drm/bridge/samsung-dsim.c         | 1883 +++++++++++++++++
 drivers/gpu/drm/drm_of.c                      |  113 +-
 drivers/gpu/drm/exynos/Kconfig                |    1 +
 drivers/gpu/drm/exynos/exynos_drm_dsi.c       | 1793 +---------------
 include/drm/bridge/samsung-dsim.h             |  119 ++
 include/drm/drm_bridge.h                      |    2 +
 include/drm/drm_of.h                          |   12 +
 12 files changed, 2285 insertions(+), 1696 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/samsung-dsim.c
 create mode 100644 include/drm/bridge/samsung-dsim.h

-- 
2.25.1

[PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

This series supports common bridge support for Samsung MIPI DSIM
which is used in Exynos and i.MX8MM SoC's.

The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.

Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge

Patch 0005 - 0006: optional PHY, PMS_P offset

Patch 0007       : introduce hw_type

Patch 0008	 : fixing host init

Patch 0009	 : atomic_check

Patch 0010	 : input_bus_flags

Patch 0011	 : atomic_get_input_bus_fmts

Patch 0012 - 0013: component vs bridge

Patch 0014	 : DSIM bridge

Patch 0015 - 0016: i.MX8M Mini/Nano

Patch 0017 - 0018: i.MX8M Plus

Changes for v10:
- rebase on drm-misc-next
- add drm_of_dsi_find_panel_or_bridge
- add devm_drm_of_dsi_get_bridge
- fix host initialization (Thanks to Marek Szyprowski)
- rearrange the tiny patches for easy to review
- update simple names for enum hw_type
- add is_hw_exynos macro
- rework on commit messages

Changes for v9:
- rebase on drm-misc-next
- drop drm bridge attach fix for Exynos
- added prepare_prev_first flag
- added pre_enable_prev_first flag
- fix bridge chain order for exynos
- added fix for Exynos host init for first DSI transfer
- added MEDIA_BUS_FMT_FIXED
- return MEDIA_BUS_FMT_RGB888_1X24 output_fmt if supported output_fmt
  list is unsupported.
- added MEDIA_BUS_FMT_YUYV10_1X20
- added MEDIA_BUS_FMT_YUYV12_1X24

Changes for v8:
* fixed comment lines
* fixed commit messages
* fixed video mode bits
* collect Marek Ack
* fixed video mode bit names
* update input formats logic
* added imx8mplus support

Changes for v7:
* fix the drm bridge attach chain for exynos drm dsi driver
* fix the hw_type checking logic

Changes for v6:
* handle previous bridge for exynos dsi while attaching bridge 

Changes for v5:
* bridge changes to support multi-arch
* updated and clear commit messages
* add hw_type via plat data
* removed unneeded quirk
* rebased on linux-next

Changes for v4:
* include Inki Dae in MAINTAINERS
* remove dsi_driver probe in exynos_drm_drv to support multi-arch build
* update init handling to ensure host init done on first cmd transfer

Changes for v3:
* fix the mult-arch build
* fix dsi host init
* updated commit messages

Changes for v2:
* fix bridge handling
* fix dsi host init
* correct the commit messages

Tested in Engicam i.Core MX8M Mini SoM.

Repo:
https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v10

v9:
https://lore.kernel.org/all/20221209152343.180139-1-jagan@amarulasolutions.com/

Any inputs?
Jagan.

Jagan Teki (16):
  drm: of: Lookup if child node has DSI panel or bridge
  drm: bridge: panel: Add devm_drm_of_dsi_get_bridge helper
  drm: exynos: dsi: Drop explicit call to bridge detach
  drm: exynos: dsi: Switch to devm_drm_of_dsi_get_bridge
  drm: exynos: dsi: Mark PHY as optional
  drm: exynos: dsi: Add platform PLL_P (PMS_P) offset
  drm: exynos: dsi: Introduce hw_type platform data
  drm: exynos: dsi: Add atomic check
  drm: exynos: dsi: Add input_bus_flags
  drm: exynos: dsi: Add atomic_get_input_bus_fmts
  drm: exynos: dsi: Consolidate component and bridge
  drm: exynos: dsi: Add Exynos based host irq hooks
  drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge
  dt-bindings: display: exynos: dsim: Add NXP i.MX8M Mini/Nano support
  drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support
  dt-bindings: display: exynos: dsim: Add NXP i.MX8M Plus support

Marek Szyprowski (1):
  drm: exynos: dsi: Handle proper host initialization

Marek Vasut (1):
  drm: bridge: samsung-dsim: Add i.MX8M Plus support

 .../bindings/display/exynos/exynos_dsim.txt   |    2 +
 MAINTAINERS                                   |    9 +
 drivers/gpu/drm/bridge/Kconfig                |   12 +
 drivers/gpu/drm/bridge/Makefile               |    1 +
 drivers/gpu/drm/bridge/panel.c                |   34 +
 drivers/gpu/drm/bridge/samsung-dsim.c         | 1883 +++++++++++++++++
 drivers/gpu/drm/drm_of.c                      |  113 +-
 drivers/gpu/drm/exynos/Kconfig                |    1 +
 drivers/gpu/drm/exynos/exynos_drm_dsi.c       | 1793 +---------------
 include/drm/bridge/samsung-dsim.h             |  119 ++
 include/drm/drm_bridge.h                      |    2 +
 include/drm/drm_of.h                          |   12 +
 12 files changed, 2285 insertions(+), 1696 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/samsung-dsim.c
 create mode 100644 include/drm/bridge/samsung-dsim.h

-- 
2.25.1

[PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge

[Jagan Teki]

This series supports common bridge support for Samsung MIPI DSIM
which is used in Exynos and i.MX8MM SoC's.

The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.

Patch 0001 - 0004: adding devm_drm_of_dsi_get_bridge

Patch 0005 - 0006: optional PHY, PMS_P offset

Patch 0007       : introduce hw_type

Patch 0008	 : fixing host init

Patch 0009	 : atomic_check

Patch 0010	 : input_bus_flags

Patch 0011	 : atomic_get_input_bus_fmts

Patch 0012 - 0013: component vs bridge

Patch 0014	 : DSIM bridge

Patch 0015 - 0016: i.MX8M Mini/Nano

Patch 0017 - 0018: i.MX8M Plus

Changes for v10:
- rebase on drm-misc-next
- add drm_of_dsi_find_panel_or_bridge
- add devm_drm_of_dsi_get_bridge
- fix host initialization (Thanks to Marek Szyprowski)
- rearrange the tiny patches for easy to review
- update simple names for enum hw_type
- add is_hw_exynos macro
- rework on commit messages

Changes for v9:
- rebase on drm-misc-next
- drop drm bridge attach fix for Exynos
- added prepare_prev_first flag
- added pre_enable_prev_first flag
- fix bridge chain order for exynos
- added fix for Exynos host init for first DSI transfer
- added MEDIA_BUS_FMT_FIXED
- return MEDIA_BUS_FMT_RGB888_1X24 output_fmt if supported output_fmt
  list is unsupported.
- added MEDIA_BUS_FMT_YUYV10_1X20
- added MEDIA_BUS_FMT_YUYV12_1X24

Changes for v8:
* fixed comment lines
* fixed commit messages
* fixed video mode bits
* collect Marek Ack
* fixed video mode bit names
* update input formats logic
* added imx8mplus support

Changes for v7:
* fix the drm bridge attach chain for exynos drm dsi driver
* fix the hw_type checking logic

Changes for v6:
* handle previous bridge for exynos dsi while attaching bridge 

Changes for v5:
* bridge changes to support multi-arch
* updated and clear commit messages
* add hw_type via plat data
* removed unneeded quirk
* rebased on linux-next

Changes for v4:
* include Inki Dae in MAINTAINERS
* remove dsi_driver probe in exynos_drm_drv to support multi-arch build
* update init handling to ensure host init done on first cmd transfer

Changes for v3:
* fix the mult-arch build
* fix dsi host init
* updated commit messages

Changes for v2:
* fix bridge handling
* fix dsi host init
* correct the commit messages

Tested in Engicam i.Core MX8M Mini SoM.

Repo:
https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v10

v9:
https://lore.kernel.org/all/20221209152343.180139-1-jagan@amarulasolutions.com/

Any inputs?
Jagan.

Jagan Teki (16):
  drm: of: Lookup if child node has DSI panel or bridge
  drm: bridge: panel: Add devm_drm_of_dsi_get_bridge helper
  drm: exynos: dsi: Drop explicit call to bridge detach
  drm: exynos: dsi: Switch to devm_drm_of_dsi_get_bridge
  drm: exynos: dsi: Mark PHY as optional
  drm: exynos: dsi: Add platform PLL_P (PMS_P) offset
  drm: exynos: dsi: Introduce hw_type platform data
  drm: exynos: dsi: Add atomic check
  drm: exynos: dsi: Add input_bus_flags
  drm: exynos: dsi: Add atomic_get_input_bus_fmts
  drm: exynos: dsi: Consolidate component and bridge
  drm: exynos: dsi: Add Exynos based host irq hooks
  drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge
  dt-bindings: display: exynos: dsim: Add NXP i.MX8M Mini/Nano support
  drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support
  dt-bindings: display: exynos: dsim: Add NXP i.MX8M Plus support

Marek Szyprowski (1):
  drm: exynos: dsi: Handle proper host initialization

Marek Vasut (1):
  drm: bridge: samsung-dsim: Add i.MX8M Plus support

 .../bindings/display/exynos/exynos_dsim.txt   |    2 +
 MAINTAINERS                                   |    9 +
 drivers/gpu/drm/bridge/Kconfig                |   12 +
 drivers/gpu/drm/bridge/Makefile               |    1 +
 drivers/gpu/drm/bridge/panel.c                |   34 +
 drivers/gpu/drm/bridge/samsung-dsim.c         | 1883 +++++++++++++++++
 drivers/gpu/drm/drm_of.c                      |  113 +-
 drivers/gpu/drm/exynos/Kconfig                |    1 +
 drivers/gpu/drm/exynos/exynos_drm_dsi.c       | 1793 +---------------
 include/drm/bridge/samsung-dsim.h             |  119 ++
 include/drm/drm_bridge.h                      |    2 +
 include/drm/drm_of.h                          |   12 +
 12 files changed, 2285 insertions(+), 1696 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/samsung-dsim.c
 create mode 100644 include/drm/bridge/samsung-dsim.h

-- 
2.25.1


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