From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Leo Yan <leo.yan@linaro.org>, Mike Leach <mike.leach@linaro.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
John Garry <john.garry@huawei.com>, Will Deacon <will@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Mark Rutland <mark.rutland@arm.com>, Jiri Olsa <jolsa@redhat.com>,
Namhyung Kim <namhyung@kernel.org>,
Daniel Kiss <Daniel.Kiss@arm.com>,
Denis Nikitin <denik@chromium.org>,
Coresight ML <coresight@lists.linaro.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Al Grant <al.grant@arm.com>
Subject: Re: [PATCH v1 1/7] coresight: etm-perf: Add support for PID tracing for kernel at EL2
Date: Tue, 12 Jan 2021 11:03:02 +0000 [thread overview]
Message-ID: <aa4ffdd3-120f-4970-e1fc-279419c85f1c@arm.com> (raw)
In-Reply-To: <20210112085826.GC18965@leoy-ThinkPad-X240s>
On 1/12/21 8:58 AM, Leo Yan wrote:
> Hi Mike,
>
> On Mon, Jan 11, 2021 at 04:22:39PM +0000, Mike Leach wrote:
>
> [...]
>
>>> diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h
>>> index b0e35eec6499..927c6285ce5d 100644
>>> --- a/include/linux/coresight-pmu.h
>>> +++ b/include/linux/coresight-pmu.h
>>> @@ -11,16 +11,19 @@
>>> #define CORESIGHT_ETM_PMU_SEED 0x10
>>>
>>> /* ETMv3.5/PTM's ETMCR config bit */
>>> -#define ETM_OPT_CYCACC 12
>>> -#define ETM_OPT_CTXTID 14
>>> -#define ETM_OPT_TS 28
>>> -#define ETM_OPT_RETSTK 29
>>> +#define ETM_OPT_CYCACC 12
>>> +#define ETM_OPT_CTXTID 14
>>> +#define ETM_OPT_CTXTID_IN_VMID 15
>>
>> Minor issue here - ETMv3.x / PTM cannot trace CXTID in VMID so this
>> may better be named ETM4_OPT_CTXTID_IN_VMID, rather than be grouped
>> with the ETM3.5 options?
>
> I looked into this suggestion but found it's complex than I assumed.
> This config bits are not only used for ETMv3.x / PTM, it's also used
> as an configuration interface between user space in Perf and kernel
> drivers.
>
Exactly. I believe this problematic. We are stuckwith using the ETM3.x/PTM
config bits for the CS_ETM pmu, which is a bit wierd and the allocation of
the config bits are sparse. The problem with changing them now, will break
older perf tools decoding a perf.data from a newer kernel. I believe we are
stuck with this.
I would recommend simply updating the comment to reflect that, thats the
generic CS PMU ABI for configuration which was initially based on ETM3.x.
Suzuki
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Leo Yan <leo.yan@linaro.org>, Mike Leach <mike.leach@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>, Al Grant <al.grant@arm.com>,
Denis Nikitin <denik@chromium.org>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@redhat.com>,
Coresight ML <coresight@lists.linaro.org>,
John Garry <john.garry@huawei.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Namhyung Kim <namhyung@kernel.org>, Will Deacon <will@kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Daniel Kiss <Daniel.Kiss@arm.com>
Subject: Re: [PATCH v1 1/7] coresight: etm-perf: Add support for PID tracing for kernel at EL2
Date: Tue, 12 Jan 2021 11:03:02 +0000 [thread overview]
Message-ID: <aa4ffdd3-120f-4970-e1fc-279419c85f1c@arm.com> (raw)
In-Reply-To: <20210112085826.GC18965@leoy-ThinkPad-X240s>
On 1/12/21 8:58 AM, Leo Yan wrote:
> Hi Mike,
>
> On Mon, Jan 11, 2021 at 04:22:39PM +0000, Mike Leach wrote:
>
> [...]
>
>>> diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h
>>> index b0e35eec6499..927c6285ce5d 100644
>>> --- a/include/linux/coresight-pmu.h
>>> +++ b/include/linux/coresight-pmu.h
>>> @@ -11,16 +11,19 @@
>>> #define CORESIGHT_ETM_PMU_SEED 0x10
>>>
>>> /* ETMv3.5/PTM's ETMCR config bit */
>>> -#define ETM_OPT_CYCACC 12
>>> -#define ETM_OPT_CTXTID 14
>>> -#define ETM_OPT_TS 28
>>> -#define ETM_OPT_RETSTK 29
>>> +#define ETM_OPT_CYCACC 12
>>> +#define ETM_OPT_CTXTID 14
>>> +#define ETM_OPT_CTXTID_IN_VMID 15
>>
>> Minor issue here - ETMv3.x / PTM cannot trace CXTID in VMID so this
>> may better be named ETM4_OPT_CTXTID_IN_VMID, rather than be grouped
>> with the ETM3.5 options?
>
> I looked into this suggestion but found it's complex than I assumed.
> This config bits are not only used for ETMv3.x / PTM, it's also used
> as an configuration interface between user space in Perf and kernel
> drivers.
>
Exactly. I believe this problematic. We are stuckwith using the ETM3.x/PTM
config bits for the CS_ETM pmu, which is a bit wierd and the allocation of
the config bits are sparse. The problem with changing them now, will break
older perf tools decoding a perf.data from a newer kernel. I believe we are
stuck with this.
I would recommend simply updating the comment to reflect that, thats the
generic CS PMU ABI for configuration which was initially based on ETM3.x.
Suzuki
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next prev parent reply other threads:[~2021-01-12 11:04 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-09 7:44 [PATCH v1 0/7] coresight: etm-perf: Fix pid tracing with VHE Leo Yan
2021-01-09 7:44 ` Leo Yan
2021-01-09 7:44 ` [PATCH v1 1/7] coresight: etm-perf: Add support for PID tracing for kernel at EL2 Leo Yan
2021-01-09 7:44 ` Leo Yan
2021-01-09 10:05 ` kernel test robot
2021-01-10 1:24 ` [PATCH] " Suzuki K Poulose
2021-01-10 1:41 ` Leo Yan
2021-01-10 22:34 ` Suzuki K Poulose
2021-01-11 0:05 ` Leo Yan
2021-01-09 11:24 ` [PATCH v1 1/7] " kernel test robot
2021-01-11 16:22 ` Mike Leach
2021-01-11 16:22 ` Mike Leach
2021-01-12 7:22 ` Leo Yan
2021-01-12 7:22 ` Leo Yan
2021-01-12 8:58 ` Leo Yan
2021-01-12 8:58 ` Leo Yan
2021-01-12 11:03 ` Suzuki K Poulose [this message]
2021-01-12 11:03 ` Suzuki K Poulose
2021-01-12 11:23 ` Mike Leach
2021-01-12 11:23 ` Mike Leach
2021-01-12 14:14 ` Leo Yan
2021-01-12 14:14 ` Leo Yan
2021-01-12 23:43 ` Mike Leach
2021-01-12 23:43 ` Mike Leach
2021-01-15 22:30 ` Mathieu Poirier
2021-01-15 22:30 ` Mathieu Poirier
2021-01-19 7:05 ` Suzuki K Poulose
2021-01-19 7:05 ` Suzuki K Poulose
2021-01-09 7:44 ` [PATCH v1 2/7] perf cs_etm: Use pid tracing explicitly instead of contextid Leo Yan
2021-01-09 7:44 ` Leo Yan
2021-01-15 22:44 ` Mathieu Poirier
2021-01-15 22:44 ` Mathieu Poirier
2021-01-19 2:32 ` Leo Yan
2021-01-19 2:32 ` Leo Yan
2021-01-09 7:44 ` [PATCH v1 3/7] perf cs-etm: Calculate per CPU metadata array size Leo Yan
2021-01-09 7:44 ` Leo Yan
2021-01-11 7:28 ` Suzuki K Poulose
2021-01-11 7:28 ` Suzuki K Poulose
2021-01-11 12:09 ` Mike Leach
2021-01-11 12:09 ` Mike Leach
2021-01-11 15:06 ` Leo Yan
2021-01-11 15:06 ` Leo Yan
2021-01-13 0:00 ` Mike Leach
2021-01-13 0:00 ` Mike Leach
2021-01-13 2:27 ` Leo Yan
2021-01-13 2:27 ` Leo Yan
2021-01-15 22:46 ` Mathieu Poirier
2021-01-15 22:46 ` Mathieu Poirier
2021-01-16 0:50 ` Leo Yan
2021-01-16 0:50 ` Leo Yan
2021-01-09 7:44 ` [PATCH v1 4/7] perf cs-etm: Add PID format into metadata Leo Yan
2021-01-09 7:44 ` Leo Yan
2021-01-11 9:45 ` Suzuki K Poulose
2021-01-11 9:45 ` Suzuki K Poulose
2021-01-11 13:12 ` Leo Yan
2021-01-11 13:12 ` Leo Yan
2021-01-09 7:44 ` [PATCH v1 5/7] perf cs-etm: Fixup PID_FMT when it is zero Leo Yan
2021-01-09 7:44 ` Leo Yan
2021-01-11 9:47 ` Suzuki K Poulose
2021-01-11 9:47 ` Suzuki K Poulose
2021-01-09 7:44 ` [PATCH v1 6/7] perf cs-etm: Add helper cs_etm__get_pid_fmt() Leo Yan
2021-01-09 7:44 ` Leo Yan
2021-01-11 9:55 ` Suzuki K Poulose
2021-01-11 9:55 ` Suzuki K Poulose
2021-01-09 7:44 ` [PATCH v1 7/7] perf cs-etm: Detect pid in VMID for kernel running at EL2 Leo Yan
2021-01-09 7:44 ` Leo Yan
2021-01-11 10:07 ` Suzuki K Poulose
2021-01-11 10:07 ` Suzuki K Poulose
2021-01-11 13:10 ` Leo Yan
2021-01-11 13:10 ` Leo Yan
2021-01-11 18:16 ` [PATCH v1 0/7] coresight: etm-perf: Fix pid tracing with VHE Mathieu Poirier
2021-01-11 18:16 ` Mathieu Poirier
2021-01-12 7:23 ` Leo Yan
2021-01-12 7:23 ` Leo Yan
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