[PATCH 1/7] arm: mach-imx: Update MAC fuse for i.MX8MP

[PATCH 1/7] arm: mach-imx: Update MAC fuse for i.MX8MP

[Ye Li]

i.MX8MP has two ENET controllers, have to update the function to
enable loading two MAC addresses.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 arch/arm/mach-imx/mac.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/mac.c b/arch/arm/mach-imx/mac.c
index 3b1496b..9bb63d2 100644
--- a/arch/arm/mach-imx/mac.c
+++ b/arch/arm/mach-imx/mac.c
@@ -31,7 +31,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 
 	offset = is_mx6() ? MAC_FUSE_MX6_OFFSET : MAC_FUSE_MX7_OFFSET;
 	fuse = (struct imx_mac_fuse *)(ulong)(OCOTP_BASE_ADDR + offset);
-	has_second_mac = is_mx7() || is_mx6sx() || is_mx6ul() || is_mx6ull();
+	has_second_mac = is_mx7() || is_mx6sx() || is_mx6ul() || is_mx6ull() || is_imx8mp();
 
 	if (has_second_mac && dev_id == 1) {
 		u32 value = readl(&fuse->mac_addr2);
-- 
2.7.4

[PATCH 2/7] arm: mach-imx: Allow to build mac.c for EQoS driver

[Ye Li]

i.MX8MP has one DWC EQoS controller, so allow to build mac.c when
only this driver is enabled.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 arch/arm/mach-imx/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 0ef2695..74a2a2a 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
 endif
 obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
 obj-$(CONFIG_FEC_MXC) += mac.o
+obj-$(CONFIG_DWC_ETH_QOS) += mac.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 obj-$(CONFIG_IMX_HAB) += hab.o
 obj-y += cpu.o
-- 
2.7.4

[PATCH 3/7] arm: dts: imx8mp-evk: Enable the EQoS ethernet port

[Ye Li]

i.MX8MP EVK has two ethernet ports. Add relevant nodes and properties
for EQoS port to the EVK DTS file.
In -u-boot.dtsi, change the u-boot eqos compatible string, add PHY
reset gpio and remove assigned clocks as not supported in CCF.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 arch/arm/dts/imx8mp-evk-u-boot.dtsi | 13 ++++++++++++
 arch/arm/dts/imx8mp-evk.dts         | 40 +++++++++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+)

diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index 2abcf1f..ab849eb 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -111,6 +111,19 @@
 	u-boot,dm-spl;
 };
 
+&eqos {
+	compatible = "fsl,imx-eqos";
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
+};
+
+&ethphy0 {
+	reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <15000>;
+	reset-post-delay-us = <100000>;
+};
+
 &fec {
 	phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
 	phy-reset-duration = <15>;
diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts
index b10dce8..f846d69 100644
--- a/arch/arm/dts/imx8mp-evk.dts
+++ b/arch/arm/dts/imx8mp-evk.dts
@@ -74,6 +74,26 @@
 	status = "okay";
 };
 
+&eqos {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eqos>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			eee-broken-1000t;
+		};
+	};
+};
+
 &flexcan2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flexcan2>;
@@ -160,6 +180,26 @@
 };
 
 &iomuxc {
+	pinctrl_eqos: eqosgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC	0x3
+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO	0x3
+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91
+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91
+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91
+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91
+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x1f
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x1f
+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x1f
+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x1f
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22		0x19
+		>;
+	};
+
 	pinctrl_fec: fecgrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
-- 
2.7.4

[PATCH 4/7] imx8mp_evk: Fix incorrect cascade for FEC and EQOS setup

[Ye Li]

The setup functions should be independent for two ethernet controllers

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 board/freescale/imx8mp_evk/imx8mp_evk.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c
index 89cc17c..bc4753c 100644
--- a/board/freescale/imx8mp_evk/imx8mp_evk.c
+++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
@@ -101,9 +101,10 @@ int board_init(void)
 
 	if (CONFIG_IS_ENABLED(FEC_MXC)) {
 		setup_fec();
+	}
 
-		if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
-			ret = setup_eqos();
+	if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) {
+		ret = setup_eqos();
 	}
 
 	return ret;
-- 
2.7.4

[PATCH 5/7] imx8mp_evk: Remove EQoS PHY reset codes

[Ye Li]

Since we uses the DTS and PHY reset gpio in EQoS driver to do the
reset, remove the duplicated codes from board file.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 board/freescale/imx8mp_evk/imx8mp_evk.c | 19 -------------------
 1 file changed, 19 deletions(-)

diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c
index bc4753c..62096c2 100644
--- a/board/freescale/imx8mp_evk/imx8mp_evk.c
+++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
@@ -54,30 +54,11 @@ static void setup_fec(void)
 	setbits_le32(&gpr->gpr[1], BIT(22));
 }
 
-#define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
-static iomux_v3_cfg_t const eqos_rst_pads[] = {
-	MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_iomux_eqos(void)
-{
-	imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
-					 ARRAY_SIZE(eqos_rst_pads));
-
-	gpio_request(EQOS_RST_PAD, "eqos_rst");
-	gpio_direction_output(EQOS_RST_PAD, 0);
-	mdelay(15);
-	gpio_direction_output(EQOS_RST_PAD, 1);
-	mdelay(100);
-}
-
 static int setup_eqos(void)
 {
 	struct iomuxc_gpr_base_regs *gpr =
 		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 
-	setup_iomux_eqos();
-
 	/* set INTF as RGMII, enable RGMII TXC clock */
 	clrsetbits_le32(&gpr->gpr[1],
 			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
-- 
2.7.4

[PATCH 6/7] imx8mp_evk: Delete noncached memory config

[Ye Li]

DWC EQOS driver has removed to use noncached memory, so delete
the configuration from iMX8MP EVK head file.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 include/configs/imx8mp_evk.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index a6569d5..59e50fe 100644
--- a/include/configs/imx8mp_evk.h
+++ b/include/configs/imx8mp_evk.h
@@ -49,9 +49,6 @@
 #define FEC_QUIRK_ENET_MAC
 
 #define DWC_NET_PHYADDR			1
-#ifdef CONFIG_DWC_ETH_QOS
-#define CONFIG_SYS_NONCACHED_MEMORY     (1 * SZ_1M)     /* 1M */
-#endif
 
 #define PHY_ANEG_TIMEOUT 20000
 
-- 
2.7.4

[PATCH 7/7] imx8mp_evk: Enable the DWC EQoS iMX driver

[Ye Li]

Enable the EQoS i.MX driver in defconfig, also enable the PHYLIB
to facilitate the case that only has FEC enabled.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 configs/imx8mp_evk_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index 2c6fc16..41e6b2f 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -72,9 +72,12 @@ CONFIG_MMC_HS400_ES_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHY_REALTEK=y
+CONFIG_PHYLIB=y
 CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_PHY_GIGE=y
 CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
-- 
2.7.4

Re: [PATCH 1/7] arm: mach-imx: Update MAC fuse for i.MX8MP

[Marcel Ziswiler]

On Mon, 2021-08-16 at 18:44 +0800, Ye Li wrote:
> i.MX8MP has two ENET controllers, have to update the function to
> enable loading two MAC addresses.
> 
> Signed-off-by: Ye Li <ye.li@nxp.com>

Whole series.

Tested on iMX8MP_EVK and Verdin iMX8M Plus on Verdin development board.
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

I will post the Verdin iMX8M Plus support shortly.

> ---
>  arch/arm/mach-imx/mac.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-imx/mac.c b/arch/arm/mach-imx/mac.c
> index 3b1496b..9bb63d2 100644
> --- a/arch/arm/mach-imx/mac.c
> +++ b/arch/arm/mach-imx/mac.c
> @@ -31,7 +31,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
>  
>         offset = is_mx6() ? MAC_FUSE_MX6_OFFSET : MAC_FUSE_MX7_OFFSET;
>         fuse = (struct imx_mac_fuse *)(ulong)(OCOTP_BASE_ADDR + offset);
> -       has_second_mac = is_mx7() || is_mx6sx() || is_mx6ul() || is_mx6ull();
> +       has_second_mac = is_mx7() || is_mx6sx() || is_mx6ul() || is_mx6ull() || is_imx8mp();
>  
>         if (has_second_mac && dev_id == 1) {
>                 u32 value = readl(&fuse->mac_addr2);

[PATCH 7/7] imx8mp_evk: Enable the DWC EQoS iMX driver

[sbabic]

> Enable the EQoS i.MX driver in defconfig, also enable the PHYLIB
> to facilitate the case that only has FEC enabled.
> Signed-off-by: Ye Li <ye.li@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 4/7] imx8mp_evk: Fix incorrect cascade for FEC and EQOS setup

[sbabic]

> The setup functions should be independent for two ethernet controllers
> Signed-off-by: Ye Li <ye.li@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 5/7] imx8mp_evk: Remove EQoS PHY reset codes

[sbabic]

> Since we uses the DTS and PHY reset gpio in EQoS driver to do the
> reset, remove the duplicated codes from board file.
> Signed-off-by: Ye Li <ye.li@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 3/7] arm: dts: imx8mp-evk: Enable the EQoS ethernet port

[sbabic]

> i.MX8MP EVK has two ethernet ports. Add relevant nodes and properties
> for EQoS port to the EVK DTS file.
> In -u-boot.dtsi, change the u-boot eqos compatible string, add PHY
> reset gpio and remove assigned clocks as not supported in CCF.
> Signed-off-by: Ye Li <ye.li@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 6/7] imx8mp_evk: Delete noncached memory config

[sbabic]

> DWC EQOS driver has removed to use noncached memory, so delete
> the configuration from iMX8MP EVK head file.
> Signed-off-by: Ye Li <ye.li@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 1/7] arm: mach-imx: Update MAC fuse for i.MX8MP

[sbabic]

> i.MX8MP has two ENET controllers, have to update the function to
> enable loading two MAC addresses.
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 2/7] arm: mach-imx: Allow to build mac.c for EQoS driver

[sbabic]

> i.MX8MP has one DWC EQoS controller, so allow to build mac.c when
> only this driver is enabled.
> Signed-off-by: Ye Li <ye.li@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================