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From: Eric Auger <eauger@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	Shashi Mallela <shashi.mallela@linaro.org>
Cc: "Michael S. Tsirkin" <mst@redhat.com>,
	Radoslaw Biernacki <rad@semihalf.com>,
	QEMU Developers <qemu-devel@nongnu.org>,
	qemu-arm <qemu-arm@nongnu.org>,
	Igor Mammedov <imammedo@redhat.com>,
	Leif Lindholm <leif@nuviainc.com>
Subject: Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing
Date: Tue, 6 Jul 2021 11:27:23 +0200	[thread overview]
Message-ID: <ad4f6ee9-baa3-c328-a412-62301c5228e2@redhat.com> (raw)
In-Reply-To: <CAFEAcA-e9-oBgK9wi6DOp5SGGd4vm-3sQY-fFn7HdTM842D1mg@mail.gmail.com>

Hi,

On 7/5/21 4:07 PM, Peter Maydell wrote:
> On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <shashi.mallela@linaro.org> wrote:
>>
>> Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
>> translation which triggers an LPI via INT command as well as write
>> to GITS_TRANSLATER register,defined enum to differentiate between ITS
>> command interrupt trigger and GITS_TRANSLATER based interrupt trigger.
>> Each of these commands make use of other functionalities implemented to
>> get device table entry,collection table entry or interrupt translation
>> table entry required for their processing.
>>
>> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
>> ---
>>  hw/intc/arm_gicv3_its.c            | 361 ++++++++++++++++++++++++++++-
>>  hw/intc/gicv3_internal.h           |  26 +++
>>  include/hw/intc/arm_gicv3_common.h |   2 +
>>  3 files changed, 388 insertions(+), 1 deletion(-)
> 
>> +/*
>> + * This function handles the processing of following commands based on
>> + * the ItsCmdType parameter passed:-
>> + * 1. trigerring of lpi interrupt translation via ITS INT command
>> + * 2. trigerring of lpi interrupt translation via gits_translater register
>> + * 3. handling of ITS CLEAR command
>> + * 4. handling of ITS DISCARD command
>> + */
> 
> "triggering"
> 
>>  #define DEVID_SHIFT                  32
>>  #define DEVID_MASK                MAKE_64BIT_MASK(32, 32)
> 
>> @@ -347,6 +368,11 @@ FIELD(MAPC, RDBASE, 16, 32)
>>   * vPEID = 16 bits
>>   */
>>  #define ITS_ITT_ENTRY_SIZE            0xC
>> +#define ITE_ENTRY_INTTYPE_SHIFT        1
>> +#define ITE_ENTRY_INTID_SHIFT          2
>> +#define ITE_ENTRY_INTID_MASK         ((1ULL << 24) - 1)
>> +#define ITE_ENTRY_INTSP_SHIFT          26
>> +#define ITE_ENTRY_ICID_MASK          ((1ULL << 16) - 1)
> 
> This is still using a MASK value that's at the bottom of the
> integer, not in its shifted location.
There are other locations, pointed out by former comments, where this
kind of unusual masking scheme is used but well...

Thanks

Eric

> 
> Otherwise
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> 
> thanks
> -- PMM
> 



  reply	other threads:[~2021-07-06  9:28 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-30 15:31 [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Shashi Mallela
2021-06-30 15:31 ` [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework Shashi Mallela
2021-07-05 14:58   ` Peter Maydell
2021-07-05 15:55     ` shashi.mallela
2021-07-05 16:25       ` Peter Maydell
2021-07-05 17:04         ` shashi.mallela
2021-07-05 18:58           ` Peter Maydell
2021-07-07  2:08             ` shashi.mallela
2021-07-06  7:44   ` Eric Auger
2021-07-07  2:06     ` shashi.mallela
2021-06-30 15:31 ` [PATCH v5 02/10] hw/intc: GICv3 ITS register definitions added Shashi Mallela
2021-07-06  9:29   ` Eric Auger
2021-07-08 17:27     ` Eric Auger
2021-08-05 21:14       ` shashi.mallela
2021-06-30 15:31 ` [PATCH v5 03/10] hw/intc: GICv3 ITS command queue framework Shashi Mallela
2021-07-06  9:31   ` Eric Auger
2021-06-30 15:31 ` [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing Shashi Mallela
2021-07-05 14:07   ` Peter Maydell
2021-07-06  9:27     ` Eric Auger [this message]
2021-07-07  2:02       ` shashi.mallela
2021-07-05 14:54   ` Peter Maydell
2021-07-06  0:47     ` shashi.mallela
2021-07-06  3:25       ` shashi.mallela
2021-07-06  9:19         ` Peter Maydell
2021-07-06 12:46           ` shashi.mallela
2021-07-06 13:27             ` Peter Maydell
2021-07-07  2:08               ` shashi.mallela
2021-07-06 10:04         ` Eric Auger
2021-07-06 10:07           ` Peter Maydell
2021-07-06 10:05   ` Eric Auger
2021-06-30 15:31 ` [PATCH v5 05/10] hw/intc: GICv3 ITS Feature enablement Shashi Mallela
2021-07-05 14:20   ` Peter Maydell
2021-06-30 15:31 ` [PATCH v5 06/10] hw/intc: GICv3 redistributor ITS processing Shashi Mallela
2021-07-05 14:43   ` Peter Maydell
2021-06-30 15:31 ` [PATCH v5 07/10] hw/arm/sbsa-ref: add ITS support in SBSA GIC Shashi Mallela
2021-07-05 14:59   ` Peter Maydell
2021-06-30 15:31 ` [PATCH v5 08/10] tests/data/acpi/virt: Add IORT files for ITS Shashi Mallela
2021-06-30 15:31 ` [PATCH v5 09/10] hw/arm/virt: add ITS support in virt GIC Shashi Mallela
2021-06-30 15:31 ` [PATCH v5 10/10] tests/data/acpi/virt: Update IORT files for ITS Shashi Mallela
2021-07-05 15:02   ` Peter Maydell
2021-07-05 15:05 ` [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Peter Maydell

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