Re: arch/x86/Kconfig selects invalid HAVE_READQ, HAVE_WRITEQ vars

From: Roland Dreier <rdreier@cisco.com>
To: Ingo Molnar <mingo@elte.hu>
Cc: "H. Peter Anvin" <hpa@zytor.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	"Robert P. J. Day" <rpjday@crashcourse.ca>,
	Hitoshi Mitake <h.mitake@gmail.com>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: arch/x86/Kconfig selects invalid HAVE_READQ, HAVE_WRITEQ vars
Date: Sun, 19 Apr 2009 17:56:58 -0700	[thread overview]
Message-ID: <adaskk4ywf9.fsf@cisco.com> (raw)
In-Reply-To: <20090419223519.GA27706@elte.hu> (Ingo Molnar's message of "Mon, 20 Apr 2009 00:35:19 +0200")

 > Also, atomicity might not be possible to guarantee on the bus level: 
 > say the device sits on a 32-bit PCI bus. (No matter what instruction 
 > the CPU gets, a readq/writeq there has to be done as two 32-bit bus 
 > accesses.)

Well, the conventional PCI devices I know of with 64-bit registers were
PCI-X cards, keyed so they would only fit into a 64-bit slot.  And of
course there is no such thing as 32-bit PCI Express.

 > (Also, even a genuine 64-bit device might be bridged over 32-bit 
 > pathways so a driver cannot really assume atomicity on that level.)

I have never even heard of a system with a 64-bit PCI slot that went
through a 32-bit pathway -- in fact I'm not sure how one could build
that.

But yes, for example on 32-bit PowerPC I don't think it's possible to
generate a 64-bit bus transaction in general.  So if a device requires
such a cycle then it simply can't work on such a system.  But there is
also the case where racing accesses to other registers must be avoided
(the mthca example I gave in my previous example) where the current
32-bit x86 definition is broken, but it could be fixed in a
driver-specific version that used a spinlock.

 - R.