From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Xingyu Wu <xingyu.wu@starfivetech.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Conor Dooley <conor@kernel.org>,
Emil Renner Berthing <kernel@esmil.dk>
Cc: Rob Herring <robh+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
William Qiu <william.qiu@starfivetech.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v2 4/6] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
Date: Sun, 19 Mar 2023 13:25:32 +0100 [thread overview]
Message-ID: <bf3a25e8-7076-d023-3b67-4d6c65790bba@linaro.org> (raw)
In-Reply-To: <20230316030514.137427-5-xingyu.wu@starfivetech.com>
On 16/03/2023 04:05, Xingyu Wu wrote:
> Add PLL clock inputs from PLL clock generator.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Xingyu Wu <xingyu.wu@starfivetech.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Conor Dooley <conor@kernel.org>,
Emil Renner Berthing <kernel@esmil.dk>
Cc: Rob Herring <robh+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
William Qiu <william.qiu@starfivetech.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v2 4/6] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
Date: Sun, 19 Mar 2023 13:25:32 +0100 [thread overview]
Message-ID: <bf3a25e8-7076-d023-3b67-4d6c65790bba@linaro.org> (raw)
In-Reply-To: <20230316030514.137427-5-xingyu.wu@starfivetech.com>
On 16/03/2023 04:05, Xingyu Wu wrote:
> Add PLL clock inputs from PLL clock generator.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
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next prev parent reply other threads:[~2023-03-19 12:25 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-16 3:05 [PATCH v2 0/6] Add PLL clocks driver for StarFive JH7110 SoC Xingyu Wu
2023-03-16 3:05 ` Xingyu Wu
2023-03-16 3:05 ` [PATCH v2 1/6] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-03-16 3:05 ` Xingyu Wu
2023-03-19 12:25 ` Krzysztof Kozlowski
2023-03-19 12:25 ` Krzysztof Kozlowski
2023-03-20 2:41 ` Xingyu Wu
2023-03-20 2:41 ` Xingyu Wu
2023-03-16 3:05 ` [PATCH v2 2/6] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-03-16 3:05 ` Xingyu Wu
2023-03-16 3:05 ` [PATCH v2 3/6] dt-bindings: soc: starfive: syscon: Add optional patternProperties Xingyu Wu
2023-03-16 3:05 ` Xingyu Wu
2023-03-19 12:28 ` Krzysztof Kozlowski
2023-03-19 12:28 ` Krzysztof Kozlowski
2023-03-20 3:54 ` Xingyu Wu
2023-03-20 3:54 ` Xingyu Wu
2023-03-20 6:37 ` Krzysztof Kozlowski
2023-03-20 6:37 ` Krzysztof Kozlowski
2023-03-20 7:29 ` Xingyu Wu
2023-03-20 7:29 ` Xingyu Wu
2023-03-20 7:40 ` Krzysztof Kozlowski
2023-03-20 7:40 ` Krzysztof Kozlowski
2023-03-20 8:26 ` Xingyu Wu
2023-03-20 8:26 ` Xingyu Wu
2023-03-20 8:36 ` Krzysztof Kozlowski
2023-03-20 8:36 ` Krzysztof Kozlowski
2023-03-20 9:16 ` Xingyu Wu
2023-03-20 9:16 ` Xingyu Wu
2023-03-16 3:05 ` [PATCH v2 4/6] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu
2023-03-16 3:05 ` Xingyu Wu
2023-03-19 12:25 ` Krzysztof Kozlowski [this message]
2023-03-19 12:25 ` Krzysztof Kozlowski
2023-03-16 3:05 ` [PATCH v2 5/6] clk: starfive: jh7110-sys: Modify PLL clocks source Xingyu Wu
2023-03-16 3:05 ` Xingyu Wu
2023-03-16 3:05 ` [PATCH v2 6/6] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node Xingyu Wu
2023-03-16 3:05 ` Xingyu Wu
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