[PATCH v4 00/19] Introduce support for MediaTek MT8192 Google Chromebooks

[PATCH v4 00/19] Introduce support for MediaTek MT8192 Google Chromebooks

[Nícolas F. R. A. Prado]

This series introduces Devicetrees for the MT8192-based Asurada platform
as well as Asurada Spherion and Asurada Hayato boards.

Support for the boards is added to the extent that is currently enabled
in the mt8192.dtsi, and using only properties already merged in the
dt-bindings, as to not add any dependencies to this series.

This series was peer-reviewed internally before submission.

Series tested on next-20220629.

v3: https://lore.kernel.org/all/20220512205602.158273-1-nfraprado@collabora.com/
v2: https://lore.kernel.org/all/20220505194550.3094656-1-nfraprado@collabora.com/
v1: https://lore.kernel.org/all/20220316151327.564214-1-nfraprado@collabora.com/

Changes in v4:
- Added patches 17-19 enabling MMC, SCP and SPI NOR flash
- Switched mediatek,drive-strength-adv for drive-strength-microamp
- Switched mediatek,pull-up-adv for bias-pull-up
- Updated Vgpu minimum voltage to appropriate value

Changes in v3:
- Renamed regulator nodes to be generic
- Fixed keyboard layout for Hayato

Changes in v2:
- Added patches 1-2 for Mediatek board dt-bindings
- Added patches 13-16 enabling hardware for Asurada that has since been
  enabled on mt8192.dtsi

Nícolas F. R. A. Prado (19):
  dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-spherion
  dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato
  arm64: dts: mediatek: Introduce MT8192-based Asurada board family
  arm64: dts: mediatek: asurada: Document GPIO names
  arm64: dts: mediatek: asurada: Add system-wide power supplies
  arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses
  arm64: dts: mediatek: asurada: Add ChromeOS EC
  arm64: dts: mediatek: asurada: Add keyboard mapping for the top row
  arm64: dts: mediatek: asurada: Add Cr50 TPM
  arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad
  arm64: dts: mediatek: asurada: Add I2C touchscreen
  arm64: dts: mediatek: spherion: Add keyboard backlight
  arm64: dts: mediatek: asurada: Enable XHCI
  arm64: dts: mediatek: asurada: Enable PCIe and add WiFi
  arm64: dts: mediatek: asurada: Add MT6359 PMIC
  arm64: dts: mediatek: asurada: Add SPMI regulators
  arm64: dts: mediatek: asurada: Enable MMC
  arm64: dts: mediatek: asurada: Enable SCP
  arm64: dts: mediatek: asurada: Add SPI NOR flash memory

 .../devicetree/bindings/arm/mediatek.yaml     |  13 +
 arch/arm64/boot/dts/mediatek/Makefile         |   2 +
 .../dts/mediatek/mt8192-asurada-hayato-r1.dts |  47 +
 .../mediatek/mt8192-asurada-spherion-r0.dts   |  62 ++
 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 959 ++++++++++++++++++
 5 files changed, 1083 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi

-- 
2.36.1

[PATCH v4 00/19] Introduce support for MediaTek MT8192 Google Chromebooks

[Nícolas F. R. A. Prado]

This series introduces Devicetrees for the MT8192-based Asurada platform
as well as Asurada Spherion and Asurada Hayato boards.

Support for the boards is added to the extent that is currently enabled
in the mt8192.dtsi, and using only properties already merged in the
dt-bindings, as to not add any dependencies to this series.

This series was peer-reviewed internally before submission.

Series tested on next-20220629.

v3: https://lore.kernel.org/all/20220512205602.158273-1-nfraprado@collabora.com/
v2: https://lore.kernel.org/all/20220505194550.3094656-1-nfraprado@collabora.com/
v1: https://lore.kernel.org/all/20220316151327.564214-1-nfraprado@collabora.com/

Changes in v4:
- Added patches 17-19 enabling MMC, SCP and SPI NOR flash
- Switched mediatek,drive-strength-adv for drive-strength-microamp
- Switched mediatek,pull-up-adv for bias-pull-up
- Updated Vgpu minimum voltage to appropriate value

Changes in v3:
- Renamed regulator nodes to be generic
- Fixed keyboard layout for Hayato

Changes in v2:
- Added patches 1-2 for Mediatek board dt-bindings
- Added patches 13-16 enabling hardware for Asurada that has since been
  enabled on mt8192.dtsi

Nícolas F. R. A. Prado (19):
  dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-spherion
  dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato
  arm64: dts: mediatek: Introduce MT8192-based Asurada board family
  arm64: dts: mediatek: asurada: Document GPIO names
  arm64: dts: mediatek: asurada: Add system-wide power supplies
  arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses
  arm64: dts: mediatek: asurada: Add ChromeOS EC
  arm64: dts: mediatek: asurada: Add keyboard mapping for the top row
  arm64: dts: mediatek: asurada: Add Cr50 TPM
  arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad
  arm64: dts: mediatek: asurada: Add I2C touchscreen
  arm64: dts: mediatek: spherion: Add keyboard backlight
  arm64: dts: mediatek: asurada: Enable XHCI
  arm64: dts: mediatek: asurada: Enable PCIe and add WiFi
  arm64: dts: mediatek: asurada: Add MT6359 PMIC
  arm64: dts: mediatek: asurada: Add SPMI regulators
  arm64: dts: mediatek: asurada: Enable MMC
  arm64: dts: mediatek: asurada: Enable SCP
  arm64: dts: mediatek: asurada: Add SPI NOR flash memory

 .../devicetree/bindings/arm/mediatek.yaml     |  13 +
 arch/arm64/boot/dts/mediatek/Makefile         |   2 +
 .../dts/mediatek/mt8192-asurada-hayato-r1.dts |  47 +
 .../mediatek/mt8192-asurada-spherion-r0.dts   |  62 ++
 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 959 ++++++++++++++++++
 5 files changed, 1083 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi

-- 
2.36.1


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[PATCH v4 01/19] dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-spherion

[Nícolas F. R. A. Prado]

Add binding for the Google Spherion board, which is used for Acer
Chromebook 514 (CB514-2H).

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>

---

(no changes since v2)

Changes in v2:
- Added this patch

 Documentation/devicetree/bindings/arm/mediatek.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index 5a29b7b381ef..1f9535097a60 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -131,6 +131,14 @@ properties:
           - enum:
               - mediatek,mt8183-evb
           - const: mediatek,mt8183
+      - description: Google Spherion (Acer Chromebook 514)
+        items:
+          - const: google,spherion-rev3
+          - const: google,spherion-rev2
+          - const: google,spherion-rev1
+          - const: google,spherion-rev0
+          - const: google,spherion
+          - const: mediatek,mt8192
       - items:
           - enum:
               - mediatek,mt8186-evb
-- 
2.36.1

[PATCH v4 01/19] dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-spherion

[Nícolas F. R. A. Prado]

Add binding for the Google Spherion board, which is used for Acer
Chromebook 514 (CB514-2H).

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>

---

(no changes since v2)

Changes in v2:
- Added this patch

 Documentation/devicetree/bindings/arm/mediatek.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index 5a29b7b381ef..1f9535097a60 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -131,6 +131,14 @@ properties:
           - enum:
               - mediatek,mt8183-evb
           - const: mediatek,mt8183
+      - description: Google Spherion (Acer Chromebook 514)
+        items:
+          - const: google,spherion-rev3
+          - const: google,spherion-rev2
+          - const: google,spherion-rev1
+          - const: google,spherion-rev0
+          - const: google,spherion
+          - const: mediatek,mt8192
       - items:
           - enum:
               - mediatek,mt8186-evb
-- 
2.36.1


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[PATCH v4 02/19] dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato

[Nícolas F. R. A. Prado]

Add binding for the Google Hayato board.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>

---

(no changes since v2)

Changes in v2:
- Added this patch

 Documentation/devicetree/bindings/arm/mediatek.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index 1f9535097a60..dd6c6e8011f9 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -131,6 +131,11 @@ properties:
           - enum:
               - mediatek,mt8183-evb
           - const: mediatek,mt8183
+      - description: Google Hayato
+        items:
+          - const: google,hayato-rev1
+          - const: google,hayato
+          - const: mediatek,mt8192
       - description: Google Spherion (Acer Chromebook 514)
         items:
           - const: google,spherion-rev3
-- 
2.36.1

[PATCH v4 02/19] dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato

[Nícolas F. R. A. Prado]

Add binding for the Google Hayato board.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>

---

(no changes since v2)

Changes in v2:
- Added this patch

 Documentation/devicetree/bindings/arm/mediatek.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index 1f9535097a60..dd6c6e8011f9 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -131,6 +131,11 @@ properties:
           - enum:
               - mediatek,mt8183-evb
           - const: mediatek,mt8183
+      - description: Google Hayato
+        items:
+          - const: google,hayato-rev1
+          - const: google,hayato
+          - const: mediatek,mt8192
       - description: Google Spherion (Acer Chromebook 514)
         items:
           - const: google,spherion-rev3
-- 
2.36.1


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[PATCH v4 03/19] arm64: dts: mediatek: Introduce MT8192-based Asurada board family

[Nícolas F. R. A. Prado]

Introduce the MT8192 Asurada Chromebook platform, including the Asurada
Spherion and Asurada Hayato boards.

This is enough configuration to get serial output working on Spherion
and Hayato.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

(no changes since v2)

Changes in v2:
- Changed model name prefix from Mediatek to Google on Hayato and
  Spherion dts

 arch/arm64/boot/dts/mediatek/Makefile         |  2 ++
 .../dts/mediatek/mt8192-asurada-hayato-r1.dts | 11 ++++++++
 .../mediatek/mt8192-asurada-spherion-r0.dts   | 13 ++++++++++
 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 26 +++++++++++++++++++
 4 files changed, 52 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 50a2c58c5f56..b52058965a0d 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -38,6 +38,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
new file mode 100644
index 000000000000..00c76709a055
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2020 Google LLC
+ */
+/dts-v1/;
+#include "mt8192-asurada.dtsi"
+
+/ {
+	model = "Google Hayato rev1";
+	compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
new file mode 100644
index 000000000000..d384d584bbcf
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+/dts-v1/;
+#include "mt8192-asurada.dtsi"
+
+/ {
+	model = "Google Spherion (rev0 - 3)";
+	compatible = "google,spherion-rev3", "google,spherion-rev2",
+		     "google,spherion-rev1", "google,spherion-rev0",
+		     "google,spherion", "mediatek,mt8192";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
new file mode 100644
index 000000000000..277bd38943fe
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ * Author: Seiya Wang <seiya.wang@mediatek.com>
+ */
+/dts-v1/;
+#include "mt8192.dtsi"
+
+/ {
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0 0x40000000 0 0x80000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
-- 
2.36.1

[PATCH v4 03/19] arm64: dts: mediatek: Introduce MT8192-based Asurada board family

[Nícolas F. R. A. Prado]

Introduce the MT8192 Asurada Chromebook platform, including the Asurada
Spherion and Asurada Hayato boards.

This is enough configuration to get serial output working on Spherion
and Hayato.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

(no changes since v2)

Changes in v2:
- Changed model name prefix from Mediatek to Google on Hayato and
  Spherion dts

 arch/arm64/boot/dts/mediatek/Makefile         |  2 ++
 .../dts/mediatek/mt8192-asurada-hayato-r1.dts | 11 ++++++++
 .../mediatek/mt8192-asurada-spherion-r0.dts   | 13 ++++++++++
 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 26 +++++++++++++++++++
 4 files changed, 52 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 50a2c58c5f56..b52058965a0d 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -38,6 +38,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
new file mode 100644
index 000000000000..00c76709a055
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2020 Google LLC
+ */
+/dts-v1/;
+#include "mt8192-asurada.dtsi"
+
+/ {
+	model = "Google Hayato rev1";
+	compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
new file mode 100644
index 000000000000..d384d584bbcf
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+/dts-v1/;
+#include "mt8192-asurada.dtsi"
+
+/ {
+	model = "Google Spherion (rev0 - 3)";
+	compatible = "google,spherion-rev3", "google,spherion-rev2",
+		     "google,spherion-rev1", "google,spherion-rev0",
+		     "google,spherion", "mediatek,mt8192";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
new file mode 100644
index 000000000000..277bd38943fe
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ * Author: Seiya Wang <seiya.wang@mediatek.com>
+ */
+/dts-v1/;
+#include "mt8192.dtsi"
+
+/ {
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0 0x40000000 0 0x80000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
-- 
2.36.1


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[PATCH v4 04/19] arm64: dts: mediatek: asurada: Document GPIO names

[Nícolas F. R. A. Prado]

Add the gpio-line-names property to gpio-controller in order to
document the usage of GPIOs on the Asurada platform.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
---

(no changes since v1)

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 228 ++++++++++++++++++
 1 file changed, 228 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 277bd38943fe..e10636298639 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -21,6 +21,234 @@ memory@40000000 {
 	};
 };
 
+&pio {
+	/* 220 lines */
+	gpio-line-names = "I2S_DP_LRCK",
+			  "IS_DP_BCLK",
+			  "I2S_DP_MCLK",
+			  "I2S_DP_DATAOUT",
+			  "SAR0_INT_ODL",
+			  "EC_AP_INT_ODL",
+			  "EDPBRDG_INT_ODL",
+			  "DPBRDG_INT_ODL",
+			  "DPBRDG_PWREN",
+			  "DPBRDG_RST_ODL",
+			  "I2S_HP_MCLK",
+			  "I2S_HP_BCK",
+			  "I2S_HP_LRCK",
+			  "I2S_HP_DATAIN",
+			  /*
+			   * AP_FLASH_WP_L is crossystem ABI. Schematics
+			   * call it AP_FLASH_WP_ODL.
+			   */
+			  "AP_FLASH_WP_L",
+			  "TRACKPAD_INT_ODL",
+			  "EC_AP_HPD_OD",
+			  "SD_CD_ODL",
+			  "HP_INT_ODL_ALC",
+			  "EN_PP1000_DPBRDG",
+			  "AP_GPIO20",
+			  "TOUCH_INT_L_1V8",
+			  "UART_BT_WAKE_ODL",
+			  "AP_GPIO23",
+			  "AP_SPI_FLASH_CS_L",
+			  "AP_SPI_FLASH_CLK",
+			  "EN_PP3300_DPBRDG_DX",
+			  "AP_SPI_FLASH_MOSI",
+			  "AP_SPI_FLASH_MISO",
+			  "I2S_HP_DATAOUT",
+			  "AP_GPIO30",
+			  "I2S_SPKR_MCLK",
+			  "I2S_SPKR_BCLK",
+			  "I2S_SPKR_LRCK",
+			  "I2S_SPKR_DATAIN",
+			  "I2S_SPKR_DATAOUT",
+			  "AP_SPI_H1_TPM_CLK",
+			  "AP_SPI_H1_TPM_CS_L",
+			  "AP_SPI_H1_TPM_MISO",
+			  "AP_SPI_H1_TPM_MOSI",
+			  "BL_PWM",
+			  "EDPBRDG_PWREN",
+			  "EDPBRDG_RST_ODL",
+			  "EN_PP3300_HUB",
+			  "HUB_RST_L",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "SD_CLK",
+			  "SD_CMD",
+			  "SD_DATA3",
+			  "SD_DATA0",
+			  "SD_DATA2",
+			  "SD_DATA1",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "PCIE_WAKE_ODL",
+			  "PCIE_RST_L",
+			  "PCIE_CLKREQ_ODL",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "SPMI_SCL",
+			  "SPMI_SDA",
+			  "AP_GOOD",
+			  "UART_DBG_TX_AP_RX",
+			  "UART_AP_TX_DBG_RX",
+			  "UART_AP_TX_BT_RX",
+			  "UART_BT_TX_AP_RX",
+			  "MIPI_DPI_D0_R",
+			  "MIPI_DPI_D1_R",
+			  "MIPI_DPI_D2_R",
+			  "MIPI_DPI_D3_R",
+			  "MIPI_DPI_D4_R",
+			  "MIPI_DPI_D5_R",
+			  "MIPI_DPI_D6_R",
+			  "MIPI_DPI_D7_R",
+			  "MIPI_DPI_D8_R",
+			  "MIPI_DPI_D9_R",
+			  "MIPI_DPI_D10_R",
+			  "",
+			  "",
+			  "MIPI_DPI_DE_R",
+			  "MIPI_DPI_D11_R",
+			  "MIPI_DPI_VSYNC_R",
+			  "MIPI_DPI_CLK_R",
+			  "MIPI_DPI_HSYNC_R",
+			  "PCM_BT_DATAIN",
+			  "PCM_BT_SYNC",
+			  "PCM_BT_DATAOUT",
+			  "PCM_BT_CLK",
+			  "AP_I2C_AUDIO_SCL",
+			  "AP_I2C_AUDIO_SDA",
+			  "SCP_I2C_SCL",
+			  "SCP_I2C_SDA",
+			  "AP_I2C_WLAN_SCL",
+			  "AP_I2C_WLAN_SDA",
+			  "AP_I2C_DPBRDG_SCL",
+			  "AP_I2C_DPBRDG_SDA",
+			  "EN_PP1800_DPBRDG_DX",
+			  "EN_PP3300_EDP_DX",
+			  "EN_PP1800_EDPBRDG_DX",
+			  "EN_PP1000_EDPBRDG",
+			  "SCP_JTAG0_TDO",
+			  "SCP_JTAG0_TDI",
+			  "SCP_JTAG0_TMS",
+			  "SCP_JTAG0_TCK",
+			  "SCP_JTAG0_TRSTN",
+			  "EN_PP3000_VMC_PMU",
+			  "EN_PP3300_DISPLAY_DX",
+			  "TOUCH_RST_L_1V8",
+			  "TOUCH_REPORT_DISABLE",
+			  "",
+			  "",
+			  "AP_I2C_TRACKPAD_SCL_1V8",
+			  "AP_I2C_TRACKPAD_SDA_1V8",
+			  "EN_PP3300_WLAN",
+			  "BT_KILL_L",
+			  "WIFI_KILL_L",
+			  "SET_VMC_VOLT_AT_1V8",
+			  "EN_SPK",
+			  "AP_WARM_RST_REQ",
+			  "",
+			  "",
+			  "EN_PP3000_SD_S3",
+			  "AP_EDP_BKLTEN",
+			  "",
+			  "",
+			  "",
+			  "AP_SPI_EC_CLK",
+			  "AP_SPI_EC_CS_L",
+			  "AP_SPI_EC_MISO",
+			  "AP_SPI_EC_MOSI",
+			  "AP_I2C_EDPBRDG_SCL",
+			  "AP_I2C_EDPBRDG_SDA",
+			  "MT6315_PROC_INT",
+			  "MT6315_GPU_INT",
+			  "UART_SERVO_TX_SCP_RX",
+			  "UART_SCP_TX_SERVO_RX",
+			  "BT_RTS_AP_CTS",
+			  "AP_RTS_BT_CTS",
+			  "UART_AP_WAKE_BT_ODL",
+			  "WLAN_ALERT_ODL",
+			  "EC_IN_RW_ODL",
+			  "H1_AP_INT_ODL",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "MSDC0_CMD",
+			  "MSDC0_DAT0",
+			  "MSDC0_DAT2",
+			  "MSDC0_DAT4",
+			  "MSDC0_DAT6",
+			  "MSDC0_DAT1",
+			  "MSDC0_DAT5",
+			  "MSDC0_DAT7",
+			  "MSDC0_DSL",
+			  "MSDC0_CLK",
+			  "MSDC0_DAT3",
+			  "MSDC0_RST_L",
+			  "SCP_VREQ_VAO",
+			  "AUD_DAT_MOSI2",
+			  "AUD_NLE_MOSI1",
+			  "AUD_NLE_MOSI0",
+			  "AUD_DAT_MISO2",
+			  "AP_I2C_SAR_SDA",
+			  "AP_I2C_SAR_SCL",
+			  "AP_I2C_PWR_SCL",
+			  "AP_I2C_PWR_SDA",
+			  "AP_I2C_TS_SCL_1V8",
+			  "AP_I2C_TS_SDA_1V8",
+			  "SRCLKENA0",
+			  "SRCLKENA1",
+			  "AP_EC_WATCHDOG_L",
+			  "PWRAP_SPI0_MI",
+			  "PWRAP_SPI0_CSN",
+			  "PWRAP_SPI0_MO",
+			  "PWRAP_SPI0_CK",
+			  "AP_RTC_CLK32K",
+			  "AUD_CLK_MOSI",
+			  "AUD_SYNC_MOSI",
+			  "AUD_DAT_MOSI0",
+			  "AUD_DAT_MOSI1",
+			  "AUD_DAT_MISO0",
+			  "AUD_DAT_MISO1";
+};
+
 &uart0 {
 	status = "okay";
 };
-- 
2.36.1

[PATCH v4 04/19] arm64: dts: mediatek: asurada: Document GPIO names

[Nícolas F. R. A. Prado]

Add the gpio-line-names property to gpio-controller in order to
document the usage of GPIOs on the Asurada platform.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
---

(no changes since v1)

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 228 ++++++++++++++++++
 1 file changed, 228 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 277bd38943fe..e10636298639 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -21,6 +21,234 @@ memory@40000000 {
 	};
 };
 
+&pio {
+	/* 220 lines */
+	gpio-line-names = "I2S_DP_LRCK",
+			  "IS_DP_BCLK",
+			  "I2S_DP_MCLK",
+			  "I2S_DP_DATAOUT",
+			  "SAR0_INT_ODL",
+			  "EC_AP_INT_ODL",
+			  "EDPBRDG_INT_ODL",
+			  "DPBRDG_INT_ODL",
+			  "DPBRDG_PWREN",
+			  "DPBRDG_RST_ODL",
+			  "I2S_HP_MCLK",
+			  "I2S_HP_BCK",
+			  "I2S_HP_LRCK",
+			  "I2S_HP_DATAIN",
+			  /*
+			   * AP_FLASH_WP_L is crossystem ABI. Schematics
+			   * call it AP_FLASH_WP_ODL.
+			   */
+			  "AP_FLASH_WP_L",
+			  "TRACKPAD_INT_ODL",
+			  "EC_AP_HPD_OD",
+			  "SD_CD_ODL",
+			  "HP_INT_ODL_ALC",
+			  "EN_PP1000_DPBRDG",
+			  "AP_GPIO20",
+			  "TOUCH_INT_L_1V8",
+			  "UART_BT_WAKE_ODL",
+			  "AP_GPIO23",
+			  "AP_SPI_FLASH_CS_L",
+			  "AP_SPI_FLASH_CLK",
+			  "EN_PP3300_DPBRDG_DX",
+			  "AP_SPI_FLASH_MOSI",
+			  "AP_SPI_FLASH_MISO",
+			  "I2S_HP_DATAOUT",
+			  "AP_GPIO30",
+			  "I2S_SPKR_MCLK",
+			  "I2S_SPKR_BCLK",
+			  "I2S_SPKR_LRCK",
+			  "I2S_SPKR_DATAIN",
+			  "I2S_SPKR_DATAOUT",
+			  "AP_SPI_H1_TPM_CLK",
+			  "AP_SPI_H1_TPM_CS_L",
+			  "AP_SPI_H1_TPM_MISO",
+			  "AP_SPI_H1_TPM_MOSI",
+			  "BL_PWM",
+			  "EDPBRDG_PWREN",
+			  "EDPBRDG_RST_ODL",
+			  "EN_PP3300_HUB",
+			  "HUB_RST_L",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "SD_CLK",
+			  "SD_CMD",
+			  "SD_DATA3",
+			  "SD_DATA0",
+			  "SD_DATA2",
+			  "SD_DATA1",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "PCIE_WAKE_ODL",
+			  "PCIE_RST_L",
+			  "PCIE_CLKREQ_ODL",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "SPMI_SCL",
+			  "SPMI_SDA",
+			  "AP_GOOD",
+			  "UART_DBG_TX_AP_RX",
+			  "UART_AP_TX_DBG_RX",
+			  "UART_AP_TX_BT_RX",
+			  "UART_BT_TX_AP_RX",
+			  "MIPI_DPI_D0_R",
+			  "MIPI_DPI_D1_R",
+			  "MIPI_DPI_D2_R",
+			  "MIPI_DPI_D3_R",
+			  "MIPI_DPI_D4_R",
+			  "MIPI_DPI_D5_R",
+			  "MIPI_DPI_D6_R",
+			  "MIPI_DPI_D7_R",
+			  "MIPI_DPI_D8_R",
+			  "MIPI_DPI_D9_R",
+			  "MIPI_DPI_D10_R",
+			  "",
+			  "",
+			  "MIPI_DPI_DE_R",
+			  "MIPI_DPI_D11_R",
+			  "MIPI_DPI_VSYNC_R",
+			  "MIPI_DPI_CLK_R",
+			  "MIPI_DPI_HSYNC_R",
+			  "PCM_BT_DATAIN",
+			  "PCM_BT_SYNC",
+			  "PCM_BT_DATAOUT",
+			  "PCM_BT_CLK",
+			  "AP_I2C_AUDIO_SCL",
+			  "AP_I2C_AUDIO_SDA",
+			  "SCP_I2C_SCL",
+			  "SCP_I2C_SDA",
+			  "AP_I2C_WLAN_SCL",
+			  "AP_I2C_WLAN_SDA",
+			  "AP_I2C_DPBRDG_SCL",
+			  "AP_I2C_DPBRDG_SDA",
+			  "EN_PP1800_DPBRDG_DX",
+			  "EN_PP3300_EDP_DX",
+			  "EN_PP1800_EDPBRDG_DX",
+			  "EN_PP1000_EDPBRDG",
+			  "SCP_JTAG0_TDO",
+			  "SCP_JTAG0_TDI",
+			  "SCP_JTAG0_TMS",
+			  "SCP_JTAG0_TCK",
+			  "SCP_JTAG0_TRSTN",
+			  "EN_PP3000_VMC_PMU",
+			  "EN_PP3300_DISPLAY_DX",
+			  "TOUCH_RST_L_1V8",
+			  "TOUCH_REPORT_DISABLE",
+			  "",
+			  "",
+			  "AP_I2C_TRACKPAD_SCL_1V8",
+			  "AP_I2C_TRACKPAD_SDA_1V8",
+			  "EN_PP3300_WLAN",
+			  "BT_KILL_L",
+			  "WIFI_KILL_L",
+			  "SET_VMC_VOLT_AT_1V8",
+			  "EN_SPK",
+			  "AP_WARM_RST_REQ",
+			  "",
+			  "",
+			  "EN_PP3000_SD_S3",
+			  "AP_EDP_BKLTEN",
+			  "",
+			  "",
+			  "",
+			  "AP_SPI_EC_CLK",
+			  "AP_SPI_EC_CS_L",
+			  "AP_SPI_EC_MISO",
+			  "AP_SPI_EC_MOSI",
+			  "AP_I2C_EDPBRDG_SCL",
+			  "AP_I2C_EDPBRDG_SDA",
+			  "MT6315_PROC_INT",
+			  "MT6315_GPU_INT",
+			  "UART_SERVO_TX_SCP_RX",
+			  "UART_SCP_TX_SERVO_RX",
+			  "BT_RTS_AP_CTS",
+			  "AP_RTS_BT_CTS",
+			  "UART_AP_WAKE_BT_ODL",
+			  "WLAN_ALERT_ODL",
+			  "EC_IN_RW_ODL",
+			  "H1_AP_INT_ODL",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "MSDC0_CMD",
+			  "MSDC0_DAT0",
+			  "MSDC0_DAT2",
+			  "MSDC0_DAT4",
+			  "MSDC0_DAT6",
+			  "MSDC0_DAT1",
+			  "MSDC0_DAT5",
+			  "MSDC0_DAT7",
+			  "MSDC0_DSL",
+			  "MSDC0_CLK",
+			  "MSDC0_DAT3",
+			  "MSDC0_RST_L",
+			  "SCP_VREQ_VAO",
+			  "AUD_DAT_MOSI2",
+			  "AUD_NLE_MOSI1",
+			  "AUD_NLE_MOSI0",
+			  "AUD_DAT_MISO2",
+			  "AP_I2C_SAR_SDA",
+			  "AP_I2C_SAR_SCL",
+			  "AP_I2C_PWR_SCL",
+			  "AP_I2C_PWR_SDA",
+			  "AP_I2C_TS_SCL_1V8",
+			  "AP_I2C_TS_SDA_1V8",
+			  "SRCLKENA0",
+			  "SRCLKENA1",
+			  "AP_EC_WATCHDOG_L",
+			  "PWRAP_SPI0_MI",
+			  "PWRAP_SPI0_CSN",
+			  "PWRAP_SPI0_MO",
+			  "PWRAP_SPI0_CK",
+			  "AP_RTC_CLK32K",
+			  "AUD_CLK_MOSI",
+			  "AUD_SYNC_MOSI",
+			  "AUD_DAT_MOSI0",
+			  "AUD_DAT_MOSI1",
+			  "AUD_DAT_MISO0",
+			  "AUD_DAT_MISO1";
+};
+
 &uart0 {
 	status = "okay";
 };
-- 
2.36.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 05/19] arm64: dts: mediatek: asurada: Add system-wide power supplies

[Nícolas F. R. A. Prado]

Add system-wide power supplies present on all of the boards in the
Asurada family.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

---

(no changes since v3)

Changes in v3:
- Renamed nodes to be generic

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 64 +++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index e10636298639..ca55dd095e80 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -19,6 +19,70 @@ memory@40000000 {
 		device_type = "memory";
 		reg = <0 0x40000000 0 0x80000000>;
 	};
+
+	/* system wide LDO 1.8V power rail */
+	pp1800_ldo_g: regulator-1v8-g {
+		compatible = "regulator-fixed";
+		regulator-name = "pp1800_ldo_g";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&pp3300_g>;
+	};
+
+	/* system wide switching 3.3V power rail */
+	pp3300_g: regulator-3v3-g {
+		compatible = "regulator-fixed";
+		regulator-name = "pp3300_g";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&ppvar_sys>;
+	};
+
+	/* system wide LDO 3.3V power rail */
+	pp3300_ldo_z: regulator-3v3-z {
+		compatible = "regulator-fixed";
+		regulator-name = "pp3300_ldo_z";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&ppvar_sys>;
+	};
+
+	/* separately switched 3.3V power rail */
+	pp3300_u: regulator-3v3-u {
+		compatible = "regulator-fixed";
+		regulator-name = "pp3300_u";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		/* enable pin wired to GPIO controlled by EC */
+		vin-supply = <&pp3300_g>;
+	};
+
+	/* system wide switching 5.0V power rail */
+	pp5000_a: regulator-5v0-a {
+		compatible = "regulator-fixed";
+		regulator-name = "pp5000_a";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&ppvar_sys>;
+	};
+
+	/* system wide semi-regulated power rail from battery or USB */
+	ppvar_sys: regulator-var-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "ppvar_sys";
+		regulator-always-on;
+		regulator-boot-on;
+	};
 };
 
 &pio {
-- 
2.36.1

[PATCH v4 05/19] arm64: dts: mediatek: asurada: Add system-wide power supplies

[Nícolas F. R. A. Prado]

Add system-wide power supplies present on all of the boards in the
Asurada family.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

---

(no changes since v3)

Changes in v3:
- Renamed nodes to be generic

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 64 +++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index e10636298639..ca55dd095e80 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -19,6 +19,70 @@ memory@40000000 {
 		device_type = "memory";
 		reg = <0 0x40000000 0 0x80000000>;
 	};
+
+	/* system wide LDO 1.8V power rail */
+	pp1800_ldo_g: regulator-1v8-g {
+		compatible = "regulator-fixed";
+		regulator-name = "pp1800_ldo_g";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&pp3300_g>;
+	};
+
+	/* system wide switching 3.3V power rail */
+	pp3300_g: regulator-3v3-g {
+		compatible = "regulator-fixed";
+		regulator-name = "pp3300_g";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&ppvar_sys>;
+	};
+
+	/* system wide LDO 3.3V power rail */
+	pp3300_ldo_z: regulator-3v3-z {
+		compatible = "regulator-fixed";
+		regulator-name = "pp3300_ldo_z";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&ppvar_sys>;
+	};
+
+	/* separately switched 3.3V power rail */
+	pp3300_u: regulator-3v3-u {
+		compatible = "regulator-fixed";
+		regulator-name = "pp3300_u";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		/* enable pin wired to GPIO controlled by EC */
+		vin-supply = <&pp3300_g>;
+	};
+
+	/* system wide switching 5.0V power rail */
+	pp5000_a: regulator-5v0-a {
+		compatible = "regulator-fixed";
+		regulator-name = "pp5000_a";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&ppvar_sys>;
+	};
+
+	/* system wide semi-regulated power rail from battery or USB */
+	ppvar_sys: regulator-var-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "ppvar_sys";
+		regulator-always-on;
+		regulator-boot-on;
+	};
 };
 
 &pio {
-- 
2.36.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 06/19] arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses

[Nícolas F. R. A. Prado]

The Asurada platform has five I2C controllers and two SPI controllers
that are used. In preparation for enabling the devices connected to
these controllers, enable and configure their busses.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

Changes in v4:
- Switched mediatek,drive-strength-adv for drive-strength-microamp
- Switched mediatek,pull-up-adv for bias-pull-up

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 126 ++++++++++++++++++
 1 file changed, 126 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index ca55dd095e80..72dc974fe6fc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -85,6 +85,47 @@ ppvar_sys: regulator-var-sys {
 	};
 };
 
+&i2c0 {
+	status = "okay";
+
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+};
+
+&i2c1 {
+	status = "okay";
+
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+};
+
+&i2c2 {
+	status = "okay";
+
+	clock-frequency = <400000>;
+	clock-stretch-ns = <12600>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
+};
+
+&i2c3 {
+	status = "okay";
+
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3_pins>;
+};
+
+&i2c7 {
+	status = "okay";
+
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c7_pins>;
+};
+
 &pio {
 	/* 220 lines */
 	gpio-line-names = "I2S_DP_LRCK",
@@ -311,6 +352,91 @@ &pio {
 			  "AUD_DAT_MOSI1",
 			  "AUD_DAT_MISO0",
 			  "AUD_DAT_MISO1";
+
+	i2c0_pins: i2c0-default-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO204__FUNC_SCL0>,
+				 <PINMUX_GPIO205__FUNC_SDA0>;
+			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+			drive-strength-microamp = <1000>;
+		};
+	};
+
+	i2c1_pins: i2c1-default-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO118__FUNC_SCL1>,
+				 <PINMUX_GPIO119__FUNC_SDA1>;
+			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+			drive-strength-microamp = <1000>;
+		};
+	};
+
+	i2c2_pins: i2c2-default-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO141__FUNC_SCL2>,
+				 <PINMUX_GPIO142__FUNC_SDA2>;
+			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+		};
+	};
+
+	i2c3_pins: i2c3-default-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO160__FUNC_SCL3>,
+				 <PINMUX_GPIO161__FUNC_SDA3>;
+			bias-disable;
+			drive-strength-microamp = <1000>;
+		};
+	};
+
+	i2c7_pins: i2c7-default-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO124__FUNC_SCL7>,
+				 <PINMUX_GPIO125__FUNC_SDA7>;
+			bias-disable;
+			drive-strength-microamp = <1000>;
+		};
+	};
+
+	spi1_pins: spi1-default-pins {
+		pins-cs-mosi-clk {
+			pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
+				 <PINMUX_GPIO159__FUNC_SPI1_A_MO>,
+				 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>;
+			bias-disable;
+		};
+
+		pins-miso {
+			pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;
+			bias-pull-down;
+		};
+	};
+
+	spi5_pins: spi5-default-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>,
+				 <PINMUX_GPIO37__FUNC_GPIO37>,
+				 <PINMUX_GPIO39__FUNC_SPI5_A_MO>,
+				 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>;
+			bias-disable;
+		};
+	};
+};
+
+&spi1 {
+	status = "okay";
+
+	mediatek,pad-select = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi1_pins>;
+};
+
+&spi5 {
+	status = "okay";
+
+	cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>;
+	mediatek,pad-select = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi5_pins>;
 };
 
 &uart0 {
-- 
2.36.1

[PATCH v4 06/19] arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses

[Nícolas F. R. A. Prado]

The Asurada platform has five I2C controllers and two SPI controllers
that are used. In preparation for enabling the devices connected to
these controllers, enable and configure their busses.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

Changes in v4:
- Switched mediatek,drive-strength-adv for drive-strength-microamp
- Switched mediatek,pull-up-adv for bias-pull-up

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 126 ++++++++++++++++++
 1 file changed, 126 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index ca55dd095e80..72dc974fe6fc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -85,6 +85,47 @@ ppvar_sys: regulator-var-sys {
 	};
 };
 
+&i2c0 {
+	status = "okay";
+
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+};
+
+&i2c1 {
+	status = "okay";
+
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+};
+
+&i2c2 {
+	status = "okay";
+
+	clock-frequency = <400000>;
+	clock-stretch-ns = <12600>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
+};
+
+&i2c3 {
+	status = "okay";
+
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3_pins>;
+};
+
+&i2c7 {
+	status = "okay";
+
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c7_pins>;
+};
+
 &pio {
 	/* 220 lines */
 	gpio-line-names = "I2S_DP_LRCK",
@@ -311,6 +352,91 @@ &pio {
 			  "AUD_DAT_MOSI1",
 			  "AUD_DAT_MISO0",
 			  "AUD_DAT_MISO1";
+
+	i2c0_pins: i2c0-default-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO204__FUNC_SCL0>,
+				 <PINMUX_GPIO205__FUNC_SDA0>;
+			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+			drive-strength-microamp = <1000>;
+		};
+	};
+
+	i2c1_pins: i2c1-default-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO118__FUNC_SCL1>,
+				 <PINMUX_GPIO119__FUNC_SDA1>;
+			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+			drive-strength-microamp = <1000>;
+		};
+	};
+
+	i2c2_pins: i2c2-default-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO141__FUNC_SCL2>,
+				 <PINMUX_GPIO142__FUNC_SDA2>;
+			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+		};
+	};
+
+	i2c3_pins: i2c3-default-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO160__FUNC_SCL3>,
+				 <PINMUX_GPIO161__FUNC_SDA3>;
+			bias-disable;
+			drive-strength-microamp = <1000>;
+		};
+	};
+
+	i2c7_pins: i2c7-default-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO124__FUNC_SCL7>,
+				 <PINMUX_GPIO125__FUNC_SDA7>;
+			bias-disable;
+			drive-strength-microamp = <1000>;
+		};
+	};
+
+	spi1_pins: spi1-default-pins {
+		pins-cs-mosi-clk {
+			pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
+				 <PINMUX_GPIO159__FUNC_SPI1_A_MO>,
+				 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>;
+			bias-disable;
+		};
+
+		pins-miso {
+			pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;
+			bias-pull-down;
+		};
+	};
+
+	spi5_pins: spi5-default-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>,
+				 <PINMUX_GPIO37__FUNC_GPIO37>,
+				 <PINMUX_GPIO39__FUNC_SPI5_A_MO>,
+				 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>;
+			bias-disable;
+		};
+	};
+};
+
+&spi1 {
+	status = "okay";
+
+	mediatek,pad-select = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi1_pins>;
+};
+
+&spi5 {
+	status = "okay";
+
+	cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>;
+	mediatek,pad-select = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi5_pins>;
 };
 
 &uart0 {
-- 
2.36.1


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 07/19] arm64: dts: mediatek: asurada: Add ChromeOS EC

[Nícolas F. R. A. Prado]

Add support for the ChromeOS Embedded Controller present on the Asurada
platform. It is connected through the SPI1 bus and offers several
functionalities: base detection, PWM controller, I2C tunneling,
regulators, Type-C connector management, keyboard and Smart Battery
Metrics (SBS).

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

(no changes since v2)

Changes in v2:
- Renamed PWM subnode to avoid dt-binding warning (ec-pwm -> pwm)

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 79 +++++++++++++++++++
 1 file changed, 79 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 72dc974fe6fc..07405dea4d9d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -353,6 +353,14 @@ &pio {
 			  "AUD_DAT_MISO0",
 			  "AUD_DAT_MISO1";
 
+	cros_ec_int: cros-ec-irq-default-pins {
+		pins-ec-ap-int-odl {
+			pinmux = <PINMUX_GPIO5__FUNC_GPIO5>;
+			input-enable;
+			bias-pull-up;
+		};
+	};
+
 	i2c0_pins: i2c0-default-pins {
 		pins-bus {
 			pinmux = <PINMUX_GPIO204__FUNC_SCL0>,
@@ -428,6 +436,74 @@ &spi1 {
 	mediatek,pad-select = <0>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi1_pins>;
+
+	cros_ec: ec@0 {
+		compatible = "google,cros-ec-spi";
+		reg = <0>;
+		interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>;
+		spi-max-frequency = <3000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cros_ec_int>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		base_detection: cbas {
+			compatible = "google,cros-cbas";
+		};
+
+		cros_ec_pwm: pwm {
+			compatible = "google,cros-ec-pwm";
+			#pwm-cells = <1>;
+
+			status = "disabled";
+		};
+
+		i2c_tunnel: i2c-tunnel {
+			compatible = "google,cros-ec-i2c-tunnel";
+			google,remote-bus = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mt6360_ldo3_reg: regulator@0 {
+			compatible = "google,cros-ec-regulator";
+			reg = <0>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		mt6360_ldo5_reg: regulator@1 {
+			compatible = "google,cros-ec-regulator";
+			reg = <1>;
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		typec {
+			compatible = "google,cros-ec-typec";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			usb_c0: connector@0 {
+				compatible = "usb-c-connector";
+				reg = <0>;
+				label = "left";
+				power-role = "dual";
+				data-role = "host";
+				try-power-role = "source";
+			};
+
+			usb_c1: connector@1 {
+				compatible = "usb-c-connector";
+				reg = <1>;
+				label = "right";
+				power-role = "dual";
+				data-role = "host";
+				try-power-role = "source";
+			};
+		};
+	};
 };
 
 &spi5 {
@@ -442,3 +518,6 @@ &spi5 {
 &uart0 {
 	status = "okay";
 };
+
+#include <arm/cros-ec-keyboard.dtsi>
+#include <arm/cros-ec-sbs.dtsi>
-- 
2.36.1

[PATCH v4 07/19] arm64: dts: mediatek: asurada: Add ChromeOS EC

[Nícolas F. R. A. Prado]

Add support for the ChromeOS Embedded Controller present on the Asurada
platform. It is connected through the SPI1 bus and offers several
functionalities: base detection, PWM controller, I2C tunneling,
regulators, Type-C connector management, keyboard and Smart Battery
Metrics (SBS).

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

(no changes since v2)

Changes in v2:
- Renamed PWM subnode to avoid dt-binding warning (ec-pwm -> pwm)

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 79 +++++++++++++++++++
 1 file changed, 79 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 72dc974fe6fc..07405dea4d9d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -353,6 +353,14 @@ &pio {
 			  "AUD_DAT_MISO0",
 			  "AUD_DAT_MISO1";
 
+	cros_ec_int: cros-ec-irq-default-pins {
+		pins-ec-ap-int-odl {
+			pinmux = <PINMUX_GPIO5__FUNC_GPIO5>;
+			input-enable;
+			bias-pull-up;
+		};
+	};
+
 	i2c0_pins: i2c0-default-pins {
 		pins-bus {
 			pinmux = <PINMUX_GPIO204__FUNC_SCL0>,
@@ -428,6 +436,74 @@ &spi1 {
 	mediatek,pad-select = <0>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi1_pins>;
+
+	cros_ec: ec@0 {
+		compatible = "google,cros-ec-spi";
+		reg = <0>;
+		interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>;
+		spi-max-frequency = <3000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cros_ec_int>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		base_detection: cbas {
+			compatible = "google,cros-cbas";
+		};
+
+		cros_ec_pwm: pwm {
+			compatible = "google,cros-ec-pwm";
+			#pwm-cells = <1>;
+
+			status = "disabled";
+		};
+
+		i2c_tunnel: i2c-tunnel {
+			compatible = "google,cros-ec-i2c-tunnel";
+			google,remote-bus = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mt6360_ldo3_reg: regulator@0 {
+			compatible = "google,cros-ec-regulator";
+			reg = <0>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		mt6360_ldo5_reg: regulator@1 {
+			compatible = "google,cros-ec-regulator";
+			reg = <1>;
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		typec {
+			compatible = "google,cros-ec-typec";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			usb_c0: connector@0 {
+				compatible = "usb-c-connector";
+				reg = <0>;
+				label = "left";
+				power-role = "dual";
+				data-role = "host";
+				try-power-role = "source";
+			};
+
+			usb_c1: connector@1 {
+				compatible = "usb-c-connector";
+				reg = <1>;
+				label = "right";
+				power-role = "dual";
+				data-role = "host";
+				try-power-role = "source";
+			};
+		};
+	};
 };
 
 &spi5 {
@@ -442,3 +518,6 @@ &spi5 {
 &uart0 {
 	status = "okay";
 };
+
+#include <arm/cros-ec-keyboard.dtsi>
+#include <arm/cros-ec-sbs.dtsi>
-- 
2.36.1


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[PATCH v4 08/19] arm64: dts: mediatek: asurada: Add keyboard mapping for the top row

[Nícolas F. R. A. Prado]

Chromebooks' embedded keyboards differ from standard layouts for the
top row in that they have shortcuts in place of the standard function
keys. Map these keys to achieve the functionality that is pictured on
the printouts.

There's a minor difference between the keys present on Hayato, which
uses an older layout, and Spherion, which uses a newer one.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

(no changes since v3)

Changes in v3:
- Moved keyboard layout definition to hayato and spherion dts files,
  instead of common one in asurada dtsi
- Changed hayato layout to be the same as older Chromebooks like Kevin
- Switched KEY_ZOOM for KEY_FULL_SCREEN, just for semantics
- Updated commit message

 .../dts/mediatek/mt8192-asurada-hayato-r1.dts | 29 +++++++++++++++++++
 .../mediatek/mt8192-asurada-spherion-r0.dts   | 29 +++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
index 00c76709a055..ca18fcf2ad4f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
@@ -9,3 +9,32 @@ / {
 	model = "Google Hayato rev1";
 	compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192";
 };
+
+&keyboard_controller {
+	function-row-physmap = <
+		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */
+		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */
+		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */
+		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */
+		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */
+		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */
+		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */
+		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */
+		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */
+		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */
+	>;
+	linux,keymap = <
+		MATRIX_KEY(0x00, 0x02, KEY_BACK)
+		MATRIX_KEY(0x03, 0x02, KEY_FORWARD)
+		MATRIX_KEY(0x02, 0x02, KEY_REFRESH)
+		MATRIX_KEY(0x01, 0x02, KEY_FULL_SCREEN)
+		MATRIX_KEY(0x03, 0x04, KEY_SCALE)
+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
+		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)
+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
+
+		CROS_STD_MAIN_KEYMAP
+	>;
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
index d384d584bbcf..30b03895de41 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
@@ -11,3 +11,32 @@ / {
 		     "google,spherion-rev1", "google,spherion-rev0",
 		     "google,spherion", "mediatek,mt8192";
 };
+
+&keyboard_controller {
+	function-row-physmap = <
+		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */
+		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */
+		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */
+		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */
+		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */
+		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */
+		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */
+		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */
+		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */
+		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */
+	>;
+	linux,keymap = <
+		MATRIX_KEY(0x00, 0x02, KEY_BACK)
+		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
+		MATRIX_KEY(0x02, 0x02, KEY_FULL_SCREEN)
+		MATRIX_KEY(0x01, 0x02, KEY_SCALE)
+		MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
+		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)
+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
+
+		CROS_STD_MAIN_KEYMAP
+	>;
+};
-- 
2.36.1

[PATCH v4 08/19] arm64: dts: mediatek: asurada: Add keyboard mapping for the top row

[Nícolas F. R. A. Prado]

Chromebooks' embedded keyboards differ from standard layouts for the
top row in that they have shortcuts in place of the standard function
keys. Map these keys to achieve the functionality that is pictured on
the printouts.

There's a minor difference between the keys present on Hayato, which
uses an older layout, and Spherion, which uses a newer one.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

(no changes since v3)

Changes in v3:
- Moved keyboard layout definition to hayato and spherion dts files,
  instead of common one in asurada dtsi
- Changed hayato layout to be the same as older Chromebooks like Kevin
- Switched KEY_ZOOM for KEY_FULL_SCREEN, just for semantics
- Updated commit message

 .../dts/mediatek/mt8192-asurada-hayato-r1.dts | 29 +++++++++++++++++++
 .../mediatek/mt8192-asurada-spherion-r0.dts   | 29 +++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
index 00c76709a055..ca18fcf2ad4f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
@@ -9,3 +9,32 @@ / {
 	model = "Google Hayato rev1";
 	compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192";
 };
+
+&keyboard_controller {
+	function-row-physmap = <
+		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */
+		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */
+		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */
+		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */
+		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */
+		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */
+		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */
+		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */
+		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */
+		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */
+	>;
+	linux,keymap = <
+		MATRIX_KEY(0x00, 0x02, KEY_BACK)
+		MATRIX_KEY(0x03, 0x02, KEY_FORWARD)
+		MATRIX_KEY(0x02, 0x02, KEY_REFRESH)
+		MATRIX_KEY(0x01, 0x02, KEY_FULL_SCREEN)
+		MATRIX_KEY(0x03, 0x04, KEY_SCALE)
+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
+		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)
+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
+
+		CROS_STD_MAIN_KEYMAP
+	>;
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
index d384d584bbcf..30b03895de41 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
@@ -11,3 +11,32 @@ / {
 		     "google,spherion-rev1", "google,spherion-rev0",
 		     "google,spherion", "mediatek,mt8192";
 };
+
+&keyboard_controller {
+	function-row-physmap = <
+		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */
+		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */
+		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */
+		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */
+		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */
+		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */
+		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */
+		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */
+		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */
+		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */
+	>;
+	linux,keymap = <
+		MATRIX_KEY(0x00, 0x02, KEY_BACK)
+		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
+		MATRIX_KEY(0x02, 0x02, KEY_FULL_SCREEN)
+		MATRIX_KEY(0x01, 0x02, KEY_SCALE)
+		MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
+		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)
+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
+
+		CROS_STD_MAIN_KEYMAP
+	>;
+};
-- 
2.36.1


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[PATCH v4 09/19] arm64: dts: mediatek: asurada: Add Cr50 TPM

[Nícolas F. R. A. Prado]

The Asurada platform has a Google Security Chip connected to the SPI5
bus. It runs the cr50 firmware and provides TPM functionality. Add
support for it.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
---

(no changes since v1)

 .../arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 07405dea4d9d..fe626535ee5d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -5,6 +5,7 @@
  */
 /dts-v1/;
 #include "mt8192.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	aliases {
@@ -353,6 +354,13 @@ &pio {
 			  "AUD_DAT_MISO0",
 			  "AUD_DAT_MISO1";
 
+	cr50_int: cr50-irq-default-pins {
+		pins-gsc-ap-int-odl {
+			pinmux = <PINMUX_GPIO171__FUNC_GPIO171>;
+			input-enable;
+		};
+	};
+
 	cros_ec_int: cros-ec-irq-default-pins {
 		pins-ec-ap-int-odl {
 			pinmux = <PINMUX_GPIO5__FUNC_GPIO5>;
@@ -513,6 +521,15 @@ &spi5 {
 	mediatek,pad-select = <0>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi5_pins>;
+
+	cr50@0 {
+		compatible = "google,cr50";
+		reg = <0>;
+		interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>;
+		spi-max-frequency = <1000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cr50_int>;
+	};
 };
 
 &uart0 {
-- 
2.36.1

[PATCH v4 09/19] arm64: dts: mediatek: asurada: Add Cr50 TPM

[Nícolas F. R. A. Prado]

The Asurada platform has a Google Security Chip connected to the SPI5
bus. It runs the cr50 firmware and provides TPM functionality. Add
support for it.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
---

(no changes since v1)

 .../arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 07405dea4d9d..fe626535ee5d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -5,6 +5,7 @@
  */
 /dts-v1/;
 #include "mt8192.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	aliases {
@@ -353,6 +354,13 @@ &pio {
 			  "AUD_DAT_MISO0",
 			  "AUD_DAT_MISO1";
 
+	cr50_int: cr50-irq-default-pins {
+		pins-gsc-ap-int-odl {
+			pinmux = <PINMUX_GPIO171__FUNC_GPIO171>;
+			input-enable;
+		};
+	};
+
 	cros_ec_int: cros-ec-irq-default-pins {
 		pins-ec-ap-int-odl {
 			pinmux = <PINMUX_GPIO5__FUNC_GPIO5>;
@@ -513,6 +521,15 @@ &spi5 {
 	mediatek,pad-select = <0>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi5_pins>;
+
+	cr50@0 {
+		compatible = "google,cr50";
+		reg = <0>;
+		interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>;
+		spi-max-frequency = <1000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cr50_int>;
+	};
 };
 
 &uart0 {
-- 
2.36.1


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[PATCH v4 10/19] arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad

[Nícolas F. R. A. Prado]

Add support for the Elan eKTH3000 i2c trackpad present on Asurada. It is
connected to the I2C2 bus and has address 0x15.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

Changes in v4:
- Switched mediatek,pull-up-adv for bias-pull-up

 .../boot/dts/mediatek/mt8192-asurada.dtsi      | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index fe626535ee5d..4de4235cb768 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -109,6 +109,16 @@ &i2c2 {
 	clock-stretch-ns = <12600>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c2_pins>;
+
+	trackpad@15 {
+		compatible = "elan,ekth3000";
+		reg = <0x15>;
+		interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&trackpad_pins>;
+		vcc-supply = <&pp3300_u>;
+		wakeup-source;
+	};
 };
 
 &i2c3 {
@@ -436,6 +446,14 @@ pins-bus {
 			bias-disable;
 		};
 	};
+
+	trackpad_pins: trackpad-default-pins {
+		pins-int-n {
+			pinmux = <PINMUX_GPIO15__FUNC_GPIO15>;
+			input-enable;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+		};
+	};
 };
 
 &spi1 {
-- 
2.36.1

[PATCH v4 10/19] arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad

[Nícolas F. R. A. Prado]

Add support for the Elan eKTH3000 i2c trackpad present on Asurada. It is
connected to the I2C2 bus and has address 0x15.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

Changes in v4:
- Switched mediatek,pull-up-adv for bias-pull-up

 .../boot/dts/mediatek/mt8192-asurada.dtsi      | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index fe626535ee5d..4de4235cb768 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -109,6 +109,16 @@ &i2c2 {
 	clock-stretch-ns = <12600>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c2_pins>;
+
+	trackpad@15 {
+		compatible = "elan,ekth3000";
+		reg = <0x15>;
+		interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&trackpad_pins>;
+		vcc-supply = <&pp3300_u>;
+		wakeup-source;
+	};
 };
 
 &i2c3 {
@@ -436,6 +446,14 @@ pins-bus {
 			bias-disable;
 		};
 	};
+
+	trackpad_pins: trackpad-default-pins {
+		pins-int-n {
+			pinmux = <PINMUX_GPIO15__FUNC_GPIO15>;
+			input-enable;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+		};
+	};
 };
 
 &spi1 {
-- 
2.36.1


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[PATCH v4 11/19] arm64: dts: mediatek: asurada: Add I2C touchscreen

[Nícolas F. R. A. Prado]

All machines of the Asurada platform have a touchscreen at address 0x10
in the I2C0 bus, but the devices vary: Spherion has the Elan eKTH3500
touchscreen, while Hayato has a generic HID-over-i2c touchscreen.

Add common support for the touchscreens on the platform and the
specifics in each board file.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
---

(no changes since v1)

 .../dts/mediatek/mt8192-asurada-hayato-r1.dts |  7 ++++++
 .../mediatek/mt8192-asurada-spherion-r0.dts   |  4 +++
 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 25 +++++++++++++++++++
 3 files changed, 36 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
index ca18fcf2ad4f..1e91491945f6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
@@ -38,3 +38,10 @@ MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
 		CROS_STD_MAIN_KEYMAP
 	>;
 };
+
+&touchscreen {
+	compatible = "hid-over-i2c";
+	post-power-on-delay-ms = <10>;
+	hid-descr-addr = <0x0001>;
+	vdd-supply = <&pp3300_u>;
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
index 30b03895de41..42db81e95fae 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
@@ -40,3 +40,7 @@ MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
 		CROS_STD_MAIN_KEYMAP
 	>;
 };
+
+&touchscreen {
+	compatible = "elan,ekth3500";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 4de4235cb768..6eace280c14a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -92,6 +92,13 @@ &i2c0 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c0_pins>;
+
+	touchscreen: touchscreen@10 {
+		reg = <0x10>;
+		interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touchscreen_pins>;
+	};
 };
 
 &i2c1 {
@@ -454,6 +461,24 @@ pins-int-n {
 			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
 		};
 	};
+
+	touchscreen_pins: touchscreen-default-pins {
+		pins-irq {
+			pinmux = <PINMUX_GPIO21__FUNC_GPIO21>;
+			input-enable;
+			bias-pull-up;
+		};
+
+		pins-reset {
+			pinmux = <PINMUX_GPIO137__FUNC_GPIO137>;
+			output-high;
+		};
+
+		pins-report-sw {
+			pinmux = <PINMUX_GPIO138__FUNC_GPIO138>;
+			output-low;
+		};
+	};
 };
 
 &spi1 {
-- 
2.36.1

[PATCH v4 11/19] arm64: dts: mediatek: asurada: Add I2C touchscreen

[Nícolas F. R. A. Prado]

All machines of the Asurada platform have a touchscreen at address 0x10
in the I2C0 bus, but the devices vary: Spherion has the Elan eKTH3500
touchscreen, while Hayato has a generic HID-over-i2c touchscreen.

Add common support for the touchscreens on the platform and the
specifics in each board file.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
---

(no changes since v1)

 .../dts/mediatek/mt8192-asurada-hayato-r1.dts |  7 ++++++
 .../mediatek/mt8192-asurada-spherion-r0.dts   |  4 +++
 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 25 +++++++++++++++++++
 3 files changed, 36 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
index ca18fcf2ad4f..1e91491945f6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
@@ -38,3 +38,10 @@ MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
 		CROS_STD_MAIN_KEYMAP
 	>;
 };
+
+&touchscreen {
+	compatible = "hid-over-i2c";
+	post-power-on-delay-ms = <10>;
+	hid-descr-addr = <0x0001>;
+	vdd-supply = <&pp3300_u>;
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
index 30b03895de41..42db81e95fae 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
@@ -40,3 +40,7 @@ MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
 		CROS_STD_MAIN_KEYMAP
 	>;
 };
+
+&touchscreen {
+	compatible = "elan,ekth3500";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 4de4235cb768..6eace280c14a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -92,6 +92,13 @@ &i2c0 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c0_pins>;
+
+	touchscreen: touchscreen@10 {
+		reg = <0x10>;
+		interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touchscreen_pins>;
+	};
 };
 
 &i2c1 {
@@ -454,6 +461,24 @@ pins-int-n {
 			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
 		};
 	};
+
+	touchscreen_pins: touchscreen-default-pins {
+		pins-irq {
+			pinmux = <PINMUX_GPIO21__FUNC_GPIO21>;
+			input-enable;
+			bias-pull-up;
+		};
+
+		pins-reset {
+			pinmux = <PINMUX_GPIO137__FUNC_GPIO137>;
+			output-high;
+		};
+
+		pins-report-sw {
+			pinmux = <PINMUX_GPIO138__FUNC_GPIO138>;
+			output-low;
+		};
+	};
 };
 
 &spi1 {
-- 
2.36.1


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[PATCH v4 12/19] arm64: dts: mediatek: spherion: Add keyboard backlight

[Nícolas F. R. A. Prado]

The Spherion board has keyboard backlight controlled by the PWM signal
generated by the ChromeOS EC.

Enable PWM output for ChromeOS EC and add a PWM controlled LED node for
the keyboard backlight.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
---

(no changes since v1)

 .../dts/mediatek/mt8192-asurada-spherion-r0.dts  | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
index 42db81e95fae..fa3d9573f37a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
@@ -4,12 +4,28 @@
  */
 /dts-v1/;
 #include "mt8192-asurada.dtsi"
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Google Spherion (rev0 - 3)";
 	compatible = "google,spherion-rev3", "google,spherion-rev2",
 		     "google,spherion-rev1", "google,spherion-rev0",
 		     "google,spherion", "mediatek,mt8192";
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		led {
+			function = LED_FUNCTION_KBD_BACKLIGHT;
+			color = <LED_COLOR_ID_WHITE>;
+			pwms = <&cros_ec_pwm 0>;
+			max-brightness = <1023>;
+		};
+	};
+};
+
+&cros_ec_pwm {
+	status = "okay";
 };
 
 &keyboard_controller {
-- 
2.36.1

[PATCH v4 12/19] arm64: dts: mediatek: spherion: Add keyboard backlight

[Nícolas F. R. A. Prado]

The Spherion board has keyboard backlight controlled by the PWM signal
generated by the ChromeOS EC.

Enable PWM output for ChromeOS EC and add a PWM controlled LED node for
the keyboard backlight.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
---

(no changes since v1)

 .../dts/mediatek/mt8192-asurada-spherion-r0.dts  | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
index 42db81e95fae..fa3d9573f37a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
@@ -4,12 +4,28 @@
  */
 /dts-v1/;
 #include "mt8192-asurada.dtsi"
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Google Spherion (rev0 - 3)";
 	compatible = "google,spherion-rev3", "google,spherion-rev2",
 		     "google,spherion-rev1", "google,spherion-rev0",
 		     "google,spherion", "mediatek,mt8192";
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		led {
+			function = LED_FUNCTION_KBD_BACKLIGHT;
+			color = <LED_COLOR_ID_WHITE>;
+			pwms = <&cros_ec_pwm 0>;
+			max-brightness = <1023>;
+		};
+	};
+};
+
+&cros_ec_pwm {
+	status = "okay";
 };
 
 &keyboard_controller {
-- 
2.36.1


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[PATCH v4 13/19] arm64: dts: mediatek: asurada: Enable XHCI

[Nícolas F. R. A. Prado]

Enable XHCI controller on the Asurada platform. This allows the use of
the USB ports, and therefore a rootfs can be loaded and a usable shell
reached from a live USB image.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

(no changes since v2)

Changes in v2:
- Added this patch

 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 6eace280c14a..69bb43f7b346 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -579,5 +579,13 @@ &uart0 {
 	status = "okay";
 };
 
+&xhci {
+	status = "okay";
+
+	wakeup-source;
+	vusb33-supply = <&pp3300_g>;
+	vbus-supply = <&pp5000_a>;
+};
+
 #include <arm/cros-ec-keyboard.dtsi>
 #include <arm/cros-ec-sbs.dtsi>
-- 
2.36.1

[PATCH v4 13/19] arm64: dts: mediatek: asurada: Enable XHCI

[Nícolas F. R. A. Prado]

Enable XHCI controller on the Asurada platform. This allows the use of
the USB ports, and therefore a rootfs can be loaded and a usable shell
reached from a live USB image.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

(no changes since v2)

Changes in v2:
- Added this patch

 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 6eace280c14a..69bb43f7b346 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -579,5 +579,13 @@ &uart0 {
 	status = "okay";
 };
 
+&xhci {
+	status = "okay";
+
+	wakeup-source;
+	vusb33-supply = <&pp3300_g>;
+	vbus-supply = <&pp5000_a>;
+};
+
 #include <arm/cros-ec-keyboard.dtsi>
 #include <arm/cros-ec-sbs.dtsi>
-- 
2.36.1


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[PATCH v4 14/19] arm64: dts: mediatek: asurada: Enable PCIe and add WiFi

[Nícolas F. R. A. Prado]

Enable MT8192's PCIe controller and add support for the MT7921e WiFi
card that is present on that bus for the Asurada platform.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

(no changes since v3)

Changes in v3:
- Renamed regulator node to be generic

Changes in v2:
- Added this patch

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 69bb43f7b346..e59c178d3d26 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -66,6 +66,19 @@ pp3300_u: regulator-3v3-u {
 		vin-supply = <&pp3300_g>;
 	};
 
+	pp3300_wlan: regulator-3v3-wlan {
+		compatible = "regulator-fixed";
+		regulator-name = "pp3300_wlan";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pp3300_wlan_pins>;
+		enable-active-high;
+		gpio = <&pio 143 GPIO_ACTIVE_HIGH>;
+	};
+
 	/* system wide switching 5.0V power rail */
 	pp5000_a: regulator-5v0-a {
 		compatible = "regulator-fixed";
@@ -84,6 +97,17 @@ ppvar_sys: regulator-var-sys {
 		regulator-always-on;
 		regulator-boot-on;
 	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi_restricted_dma_region: wifi@c0000000 {
+			compatible = "restricted-dma-pool";
+			reg = <0 0xc0000000 0 0x4000000>;
+		};
+	};
 };
 
 &i2c0 {
@@ -144,6 +168,28 @@ &i2c7 {
 	pinctrl-0 = <&i2c7_pins>;
 };
 
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_pins>;
+
+	pcie0: pcie@0,0 {
+		device_type = "pci";
+		reg = <0x0000 0 0 0 0>;
+		num-lanes = <1>;
+		bus-range = <0x1 0x1>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi: wifi@0,0 {
+			reg = <0x10000 0 0 0 0x100000>,
+			      <0x10000 0 0x100000 0 0x100000>;
+			memory-region = <&wifi_restricted_dma_region>;
+		};
+	};
+};
+
 &pio {
 	/* 220 lines */
 	gpio-line-names = "I2S_DP_LRCK",
@@ -430,6 +476,34 @@ pins-bus {
 		};
 	};
 
+	pcie_pins: pcie-default-pins {
+		pins-pcie-wake {
+			pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>;
+			bias-pull-up;
+		};
+
+		pins-pcie-pereset {
+			pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>;
+		};
+
+		pins-pcie-clkreq {
+			pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>;
+			bias-pull-up;
+		};
+
+		pins-wifi-kill {
+			pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */
+			output-high;
+		};
+	};
+
+	pp3300_wlan_pins: pp3300-wlan-pins {
+		pins-pcie-en-pp3300-wlan {
+			pinmux = <PINMUX_GPIO143__FUNC_GPIO143>;
+			output-high;
+		};
+	};
+
 	spi1_pins: spi1-default-pins {
 		pins-cs-mosi-clk {
 			pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
-- 
2.36.1

[PATCH v4 14/19] arm64: dts: mediatek: asurada: Enable PCIe and add WiFi

[Nícolas F. R. A. Prado]

Enable MT8192's PCIe controller and add support for the MT7921e WiFi
card that is present on that bus for the Asurada platform.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

(no changes since v3)

Changes in v3:
- Renamed regulator node to be generic

Changes in v2:
- Added this patch

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 69bb43f7b346..e59c178d3d26 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -66,6 +66,19 @@ pp3300_u: regulator-3v3-u {
 		vin-supply = <&pp3300_g>;
 	};
 
+	pp3300_wlan: regulator-3v3-wlan {
+		compatible = "regulator-fixed";
+		regulator-name = "pp3300_wlan";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pp3300_wlan_pins>;
+		enable-active-high;
+		gpio = <&pio 143 GPIO_ACTIVE_HIGH>;
+	};
+
 	/* system wide switching 5.0V power rail */
 	pp5000_a: regulator-5v0-a {
 		compatible = "regulator-fixed";
@@ -84,6 +97,17 @@ ppvar_sys: regulator-var-sys {
 		regulator-always-on;
 		regulator-boot-on;
 	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi_restricted_dma_region: wifi@c0000000 {
+			compatible = "restricted-dma-pool";
+			reg = <0 0xc0000000 0 0x4000000>;
+		};
+	};
 };
 
 &i2c0 {
@@ -144,6 +168,28 @@ &i2c7 {
 	pinctrl-0 = <&i2c7_pins>;
 };
 
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_pins>;
+
+	pcie0: pcie@0,0 {
+		device_type = "pci";
+		reg = <0x0000 0 0 0 0>;
+		num-lanes = <1>;
+		bus-range = <0x1 0x1>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi: wifi@0,0 {
+			reg = <0x10000 0 0 0 0x100000>,
+			      <0x10000 0 0x100000 0 0x100000>;
+			memory-region = <&wifi_restricted_dma_region>;
+		};
+	};
+};
+
 &pio {
 	/* 220 lines */
 	gpio-line-names = "I2S_DP_LRCK",
@@ -430,6 +476,34 @@ pins-bus {
 		};
 	};
 
+	pcie_pins: pcie-default-pins {
+		pins-pcie-wake {
+			pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>;
+			bias-pull-up;
+		};
+
+		pins-pcie-pereset {
+			pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>;
+		};
+
+		pins-pcie-clkreq {
+			pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>;
+			bias-pull-up;
+		};
+
+		pins-wifi-kill {
+			pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */
+			output-high;
+		};
+	};
+
+	pp3300_wlan_pins: pp3300-wlan-pins {
+		pins-pcie-en-pp3300-wlan {
+			pinmux = <PINMUX_GPIO143__FUNC_GPIO143>;
+			output-high;
+		};
+	};
+
 	spi1_pins: spi1-default-pins {
 		pins-cs-mosi-clk {
 			pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
-- 
2.36.1


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[PATCH v4 15/19] arm64: dts: mediatek: asurada: Add MT6359 PMIC

[Nícolas F. R. A. Prado]

MT6359 is the primary PMIC present on the Asurada platform. Include its
dtsi and configure properties specific for the platform.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

(no changes since v2)

Changes in v2:
- Added this patch

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 30 +++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index e59c178d3d26..31c9d1f8c80a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -5,6 +5,7 @@
  */
 /dts-v1/;
 #include "mt8192.dtsi"
+#include "mt6359.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -168,6 +169,31 @@ &i2c7 {
 	pinctrl-0 = <&i2c7_pins>;
 };
 
+/* for CORE */
+&mt6359_vgpu11_buck_reg {
+	regulator-always-on;
+};
+
+&mt6359_vgpu11_sshub_buck_reg {
+	regulator-always-on;
+	regulator-min-microvolt = <575000>;
+	regulator-max-microvolt = <575000>;
+};
+
+&mt6359_vrf12_ldo_reg {
+	regulator-always-on;
+};
+
+&mt6359_vufs_ldo_reg {
+	regulator-always-on;
+};
+
+&mt6359codec {
+	mediatek,dmic-mode = <1>; /* one-wire */
+	mediatek,mic-type-0 = <2>; /* DMIC */
+	mediatek,mic-type-2 = <2>; /* DMIC */
+};
+
 &pcie {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie_pins>;
@@ -555,6 +581,10 @@ pins-report-sw {
 	};
 };
 
+&pmic {
+	interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>;
+};
+
 &spi1 {
 	status = "okay";
 
-- 
2.36.1

[PATCH v4 15/19] arm64: dts: mediatek: asurada: Add MT6359 PMIC

[Nícolas F. R. A. Prado]

MT6359 is the primary PMIC present on the Asurada platform. Include its
dtsi and configure properties specific for the platform.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

(no changes since v2)

Changes in v2:
- Added this patch

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 30 +++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index e59c178d3d26..31c9d1f8c80a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -5,6 +5,7 @@
  */
 /dts-v1/;
 #include "mt8192.dtsi"
+#include "mt6359.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -168,6 +169,31 @@ &i2c7 {
 	pinctrl-0 = <&i2c7_pins>;
 };
 
+/* for CORE */
+&mt6359_vgpu11_buck_reg {
+	regulator-always-on;
+};
+
+&mt6359_vgpu11_sshub_buck_reg {
+	regulator-always-on;
+	regulator-min-microvolt = <575000>;
+	regulator-max-microvolt = <575000>;
+};
+
+&mt6359_vrf12_ldo_reg {
+	regulator-always-on;
+};
+
+&mt6359_vufs_ldo_reg {
+	regulator-always-on;
+};
+
+&mt6359codec {
+	mediatek,dmic-mode = <1>; /* one-wire */
+	mediatek,mic-type-0 = <2>; /* DMIC */
+	mediatek,mic-type-2 = <2>; /* DMIC */
+};
+
 &pcie {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie_pins>;
@@ -555,6 +581,10 @@ pins-report-sw {
 	};
 };
 
+&pmic {
+	interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>;
+};
+
 &spi1 {
 	status = "okay";
 
-- 
2.36.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 16/19] arm64: dts: mediatek: asurada: Add SPMI regulators

[Nícolas F. R. A. Prado]

The Asurada platform uses regulators from MT6315 PMICs acessible through
SPMI. Add support for them.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

Changes in v4:
- Updated Vgpu minimum voltage to appropriate value

Changes in v2:
- Added this patch

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 49 +++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 31c9d1f8c80a..d56c73e37633 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -7,6 +7,7 @@
 #include "mt8192.dtsi"
 #include "mt6359.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/spmi/spmi.h>
 
 / {
 	aliases {
@@ -679,6 +680,54 @@ cr50@0 {
 	};
 };
 
+&spmi {
+	#address-cells = <2>;
+	#size-cells = <0>;
+
+	mt6315_6: pmic@6 {
+		compatible = "mediatek,mt6315-regulator";
+		reg = <0x6 SPMI_USID>;
+
+		regulators {
+			mt6315_6_vbuck1: vbuck1 {
+				regulator-compatible = "vbuck1";
+				regulator-name = "Vbcpu";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1193750>;
+				regulator-enable-ramp-delay = <256>;
+				regulator-allowed-modes = <0 1 2>;
+				regulator-always-on;
+			};
+
+			mt6315_6_vbuck3: vbuck3 {
+				regulator-compatible = "vbuck3";
+				regulator-name = "Vlcpu";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1193750>;
+				regulator-enable-ramp-delay = <256>;
+				regulator-allowed-modes = <0 1 2>;
+				regulator-always-on;
+			};
+		};
+	};
+
+	mt6315_7: pmic@7 {
+		compatible = "mediatek,mt6315-regulator";
+		reg = <0x7 SPMI_USID>;
+
+		regulators {
+			mt6315_7_vbuck1: vbuck1 {
+				regulator-compatible = "vbuck1";
+				regulator-name = "Vgpu";
+				regulator-min-microvolt = <606250>;
+				regulator-max-microvolt = <1193750>;
+				regulator-enable-ramp-delay = <256>;
+				regulator-allowed-modes = <0 1 2>;
+			};
+		};
+	};
+};
+
 &uart0 {
 	status = "okay";
 };
-- 
2.36.1

[PATCH v4 16/19] arm64: dts: mediatek: asurada: Add SPMI regulators

[Nícolas F. R. A. Prado]

The Asurada platform uses regulators from MT6315 PMICs acessible through
SPMI. Add support for them.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

---

Changes in v4:
- Updated Vgpu minimum voltage to appropriate value

Changes in v2:
- Added this patch

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 49 +++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 31c9d1f8c80a..d56c73e37633 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -7,6 +7,7 @@
 #include "mt8192.dtsi"
 #include "mt6359.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/spmi/spmi.h>
 
 / {
 	aliases {
@@ -679,6 +680,54 @@ cr50@0 {
 	};
 };
 
+&spmi {
+	#address-cells = <2>;
+	#size-cells = <0>;
+
+	mt6315_6: pmic@6 {
+		compatible = "mediatek,mt6315-regulator";
+		reg = <0x6 SPMI_USID>;
+
+		regulators {
+			mt6315_6_vbuck1: vbuck1 {
+				regulator-compatible = "vbuck1";
+				regulator-name = "Vbcpu";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1193750>;
+				regulator-enable-ramp-delay = <256>;
+				regulator-allowed-modes = <0 1 2>;
+				regulator-always-on;
+			};
+
+			mt6315_6_vbuck3: vbuck3 {
+				regulator-compatible = "vbuck3";
+				regulator-name = "Vlcpu";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1193750>;
+				regulator-enable-ramp-delay = <256>;
+				regulator-allowed-modes = <0 1 2>;
+				regulator-always-on;
+			};
+		};
+	};
+
+	mt6315_7: pmic@7 {
+		compatible = "mediatek,mt6315-regulator";
+		reg = <0x7 SPMI_USID>;
+
+		regulators {
+			mt6315_7_vbuck1: vbuck1 {
+				regulator-compatible = "vbuck1";
+				regulator-name = "Vgpu";
+				regulator-min-microvolt = <606250>;
+				regulator-max-microvolt = <1193750>;
+				regulator-enable-ramp-delay = <256>;
+				regulator-allowed-modes = <0 1 2>;
+			};
+		};
+	};
+};
+
 &uart0 {
 	status = "okay";
 };
-- 
2.36.1


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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 17/19] arm64: dts: mediatek: asurada: Enable MMC

[Nícolas F. R. A. Prado]

Enable both MMC controllers present on Asurada. MMC0 is for
non-removable internal memory, while MMC1 is an SD card slot. MMC1 isn't
used on all machines, but in those cases the CD interrupt is never
triggered and thus it is basically as if it was disabled.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

---

Changes in v4:
- Added this patch

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 149 ++++++++++++++++++
 1 file changed, 149 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index d56c73e37633..7b89f6e552c5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -170,6 +170,46 @@ &i2c7 {
 	pinctrl-0 = <&i2c7_pins>;
 };
 
+&mmc0 {
+	status = "okay";
+
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&mmc0_default_pins>;
+	pinctrl-1 = <&mmc0_uhs_pins>;
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
+	vqmmc-supply = <&mt6359_vufs_ldo_reg>;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	supports-cqe;
+	cap-mmc-hw-reset;
+	mmc-hs400-enhanced-strobe;
+	hs400-ds-delay = <0x12814>;
+	no-sdio;
+	no-sd;
+	non-removable;
+};
+
+&mmc1 {
+	status = "okay";
+
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&mmc1_default_pins>;
+	pinctrl-1 = <&mmc1_uhs_pins>;
+	bus-width = <4>;
+	max-frequency = <200000000>;
+	cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&mt6360_ldo5_reg>;
+	vqmmc-supply = <&mt6360_ldo3_reg>;
+	cap-sd-highspeed;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	no-sdio;
+	no-mmc;
+};
+
 /* for CORE */
 &mt6359_vgpu11_buck_reg {
 	regulator-always-on;
@@ -503,6 +543,115 @@ pins-bus {
 		};
 	};
 
+	mmc0_default_pins: mmc0-default-pins {
+		pins-cmd-dat {
+			pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
+				 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
+				 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
+				 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
+				 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
+				 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
+				 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
+				 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
+				 <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
+			input-enable;
+			drive-strength = <8>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+
+		pins-clk {
+			pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
+			drive-strength = <8>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+
+		pins-rst {
+			pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
+			drive-strength = <8>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
+		};
+	};
+
+	mmc0_uhs_pins: mmc0-uhs-pins {
+		pins-cmd-dat {
+			pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
+				 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
+				 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
+				 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
+				 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
+				 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
+				 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
+				 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
+				 <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
+			input-enable;
+			drive-strength = <10>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+
+		pins-clk {
+			pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
+			drive-strength = <10>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+
+		pins-rst {
+			pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
+			drive-strength = <8>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
+		};
+
+		pins-ds {
+			pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>;
+			drive-strength = <10>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+	};
+
+	mmc1_default_pins: mmc1-default-pins {
+		pins-cmd-dat {
+			pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>,
+				 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>,
+				 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>,
+				 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>,
+				 <PINMUX_GPIO52__FUNC_MSDC1_CMD>;
+			input-enable;
+			drive-strength = <8>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+
+		pins-clk {
+			pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>;
+			drive-strength = <8>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+
+		pins-insert {
+			pinmux = <PINMUX_GPIO17__FUNC_GPIO17>;
+			input-enable;
+			bias-pull-up;
+		};
+	};
+
+	mmc1_uhs_pins: mmc1-uhs-pins {
+		pins-cmd-dat {
+			pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>,
+				 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>,
+				 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>,
+				 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>,
+				 <PINMUX_GPIO52__FUNC_MSDC1_CMD>;
+			input-enable;
+			drive-strength = <8>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+
+		pins-clk {
+			pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>;
+			input-enable;
+			drive-strength = <8>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+	};
+
 	pcie_pins: pcie-default-pins {
 		pins-pcie-wake {
 			pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>;
-- 
2.36.1

[PATCH v4 17/19] arm64: dts: mediatek: asurada: Enable MMC

[Nícolas F. R. A. Prado]

Enable both MMC controllers present on Asurada. MMC0 is for
non-removable internal memory, while MMC1 is an SD card slot. MMC1 isn't
used on all machines, but in those cases the CD interrupt is never
triggered and thus it is basically as if it was disabled.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

---

Changes in v4:
- Added this patch

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 149 ++++++++++++++++++
 1 file changed, 149 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index d56c73e37633..7b89f6e552c5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -170,6 +170,46 @@ &i2c7 {
 	pinctrl-0 = <&i2c7_pins>;
 };
 
+&mmc0 {
+	status = "okay";
+
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&mmc0_default_pins>;
+	pinctrl-1 = <&mmc0_uhs_pins>;
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
+	vqmmc-supply = <&mt6359_vufs_ldo_reg>;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	supports-cqe;
+	cap-mmc-hw-reset;
+	mmc-hs400-enhanced-strobe;
+	hs400-ds-delay = <0x12814>;
+	no-sdio;
+	no-sd;
+	non-removable;
+};
+
+&mmc1 {
+	status = "okay";
+
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&mmc1_default_pins>;
+	pinctrl-1 = <&mmc1_uhs_pins>;
+	bus-width = <4>;
+	max-frequency = <200000000>;
+	cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&mt6360_ldo5_reg>;
+	vqmmc-supply = <&mt6360_ldo3_reg>;
+	cap-sd-highspeed;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	no-sdio;
+	no-mmc;
+};
+
 /* for CORE */
 &mt6359_vgpu11_buck_reg {
 	regulator-always-on;
@@ -503,6 +543,115 @@ pins-bus {
 		};
 	};
 
+	mmc0_default_pins: mmc0-default-pins {
+		pins-cmd-dat {
+			pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
+				 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
+				 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
+				 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
+				 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
+				 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
+				 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
+				 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
+				 <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
+			input-enable;
+			drive-strength = <8>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+
+		pins-clk {
+			pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
+			drive-strength = <8>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+
+		pins-rst {
+			pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
+			drive-strength = <8>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
+		};
+	};
+
+	mmc0_uhs_pins: mmc0-uhs-pins {
+		pins-cmd-dat {
+			pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
+				 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
+				 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
+				 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
+				 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
+				 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
+				 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
+				 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
+				 <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
+			input-enable;
+			drive-strength = <10>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+
+		pins-clk {
+			pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
+			drive-strength = <10>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+
+		pins-rst {
+			pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
+			drive-strength = <8>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
+		};
+
+		pins-ds {
+			pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>;
+			drive-strength = <10>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+	};
+
+	mmc1_default_pins: mmc1-default-pins {
+		pins-cmd-dat {
+			pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>,
+				 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>,
+				 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>,
+				 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>,
+				 <PINMUX_GPIO52__FUNC_MSDC1_CMD>;
+			input-enable;
+			drive-strength = <8>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+
+		pins-clk {
+			pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>;
+			drive-strength = <8>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+
+		pins-insert {
+			pinmux = <PINMUX_GPIO17__FUNC_GPIO17>;
+			input-enable;
+			bias-pull-up;
+		};
+	};
+
+	mmc1_uhs_pins: mmc1-uhs-pins {
+		pins-cmd-dat {
+			pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>,
+				 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>,
+				 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>,
+				 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>,
+				 <PINMUX_GPIO52__FUNC_MSDC1_CMD>;
+			input-enable;
+			drive-strength = <8>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+
+		pins-clk {
+			pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>;
+			input-enable;
+			drive-strength = <8>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+	};
+
 	pcie_pins: pcie-default-pins {
 		pins-pcie-wake {
 			pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>;
-- 
2.36.1


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[PATCH v4 18/19] arm64: dts: mediatek: asurada: Enable SCP

[Nícolas F. R. A. Prado]

Enable support for the SCP co-processor present on MT8192. It is used
as part of the video encoding and decoding processes.

A region of memory is carved out for its use, and remoteproc setup for
communication with the ChromeOS EC.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

---

Changes in v4:
- Added this patch

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 7b89f6e552c5..a5625b3cb317 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -105,6 +105,12 @@ reserved_memory: reserved-memory {
 		#size-cells = <2>;
 		ranges;
 
+		scp_mem_reserved: scp@50000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x50000000 0 0x2900000>;
+			no-map;
+		};
+
 		wifi_restricted_dma_region: wifi@c0000000 {
 			compatible = "restricted-dma-pool";
 			reg = <0 0xc0000000 0 0x4000000>;
@@ -680,6 +686,12 @@ pins-pcie-en-pp3300-wlan {
 		};
 	};
 
+	scp_pins: scp-pins {
+		pins-vreq-vao {
+			pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>;
+		};
+	};
+
 	spi1_pins: spi1-default-pins {
 		pins-cs-mosi-clk {
 			pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
@@ -735,6 +747,20 @@ &pmic {
 	interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>;
 };
 
+&scp {
+	status = "okay";
+
+	firmware-name = "mediatek/mt8192/scp.img";
+	memory-region = <&scp_mem_reserved>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&scp_pins>;
+
+	cros-ec {
+		compatible = "google,cros-ec-rpmsg";
+		mediatek,rpmsg-name = "cros-ec-rpmsg";
+	};
+};
+
 &spi1 {
 	status = "okay";
 
-- 
2.36.1

[PATCH v4 18/19] arm64: dts: mediatek: asurada: Enable SCP

[Nícolas F. R. A. Prado]

Enable support for the SCP co-processor present on MT8192. It is used
as part of the video encoding and decoding processes.

A region of memory is carved out for its use, and remoteproc setup for
communication with the ChromeOS EC.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

---

Changes in v4:
- Added this patch

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 7b89f6e552c5..a5625b3cb317 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -105,6 +105,12 @@ reserved_memory: reserved-memory {
 		#size-cells = <2>;
 		ranges;
 
+		scp_mem_reserved: scp@50000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x50000000 0 0x2900000>;
+			no-map;
+		};
+
 		wifi_restricted_dma_region: wifi@c0000000 {
 			compatible = "restricted-dma-pool";
 			reg = <0 0xc0000000 0 0x4000000>;
@@ -680,6 +686,12 @@ pins-pcie-en-pp3300-wlan {
 		};
 	};
 
+	scp_pins: scp-pins {
+		pins-vreq-vao {
+			pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>;
+		};
+	};
+
 	spi1_pins: spi1-default-pins {
 		pins-cs-mosi-clk {
 			pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
@@ -735,6 +747,20 @@ &pmic {
 	interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>;
 };
 
+&scp {
+	status = "okay";
+
+	firmware-name = "mediatek/mt8192/scp.img";
+	memory-region = <&scp_mem_reserved>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&scp_pins>;
+
+	cros-ec {
+		compatible = "google,cros-ec-rpmsg";
+		mediatek,rpmsg-name = "cros-ec-rpmsg";
+	};
+};
+
 &spi1 {
 	status = "okay";
 
-- 
2.36.1


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[PATCH v4 19/19] arm64: dts: mediatek: asurada: Add SPI NOR flash memory

[Nícolas F. R. A. Prado]

Add support for the SPI NOR flash memory present on the Asurada
platform.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

---

Changes in v4:
- Added this patch

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 40 +++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index a5625b3cb317..4b314435f8fd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -241,6 +241,23 @@ &mt6359codec {
 	mediatek,mic-type-2 = <2>; /* DMIC */
 };
 
+&nor_flash {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&nor_flash_pins>;
+	assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
+	assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>;
+
+	flash@0 {
+		compatible = "winbond,w25q64jwm", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+		spi-rx-bus-width = <2>;
+		spi-tx-bus-width = <2>;
+	};
+};
+
 &pcie {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie_pins>;
@@ -658,6 +675,29 @@ pins-clk {
 		};
 	};
 
+	nor_flash_pins: nor-flash-default-pins {
+		pins-cs-io1 {
+			pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>,
+				 <PINMUX_GPIO28__FUNC_SPINOR_IO1>;
+			input-enable;
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		pins-io0 {
+			pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>;
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		pins-clk {
+			pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>;
+			input-enable;
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+	};
+
 	pcie_pins: pcie-default-pins {
 		pins-pcie-wake {
 			pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>;
-- 
2.36.1

[PATCH v4 19/19] arm64: dts: mediatek: asurada: Add SPI NOR flash memory

[Nícolas F. R. A. Prado]

Add support for the SPI NOR flash memory present on the Asurada
platform.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

---

Changes in v4:
- Added this patch

 .../boot/dts/mediatek/mt8192-asurada.dtsi     | 40 +++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index a5625b3cb317..4b314435f8fd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -241,6 +241,23 @@ &mt6359codec {
 	mediatek,mic-type-2 = <2>; /* DMIC */
 };
 
+&nor_flash {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&nor_flash_pins>;
+	assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
+	assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>;
+
+	flash@0 {
+		compatible = "winbond,w25q64jwm", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+		spi-rx-bus-width = <2>;
+		spi-tx-bus-width = <2>;
+	};
+};
+
 &pcie {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie_pins>;
@@ -658,6 +675,29 @@ pins-clk {
 		};
 	};
 
+	nor_flash_pins: nor-flash-default-pins {
+		pins-cs-io1 {
+			pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>,
+				 <PINMUX_GPIO28__FUNC_SPINOR_IO1>;
+			input-enable;
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		pins-io0 {
+			pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>;
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		pins-clk {
+			pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>;
+			input-enable;
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+	};
+
 	pcie_pins: pcie-default-pins {
 		pins-pcie-wake {
 			pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>;
-- 
2.36.1


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Re: [PATCH v4 17/19] arm64: dts: mediatek: asurada: Enable MMC

[Chen-Yu Tsai]

On Thu, Jun 30, 2022 at 12:00 AM Nícolas F. R. A. Prado
<nfraprado@collabora.com> wrote:
>
> Enable both MMC controllers present on Asurada. MMC0 is for
> non-removable internal memory, while MMC1 is an SD card slot. MMC1 isn't
> used on all machines, but in those cases the CD interrupt is never
> triggered and thus it is basically as if it was disabled.
>
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Tested-by: Chen-Yu Tsai <wenst@chromium.org>

Re: [PATCH v4 17/19] arm64: dts: mediatek: asurada: Enable MMC

[Chen-Yu Tsai]

On Thu, Jun 30, 2022 at 12:00 AM Nícolas F. R. A. Prado
<nfraprado@collabora.com> wrote:
>
> Enable both MMC controllers present on Asurada. MMC0 is for
> non-removable internal memory, while MMC1 is an SD card slot. MMC1 isn't
> used on all machines, but in those cases the CD interrupt is never
> triggered and thus it is basically as if it was disabled.
>
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Tested-by: Chen-Yu Tsai <wenst@chromium.org>

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Re: [PATCH v4 18/19] arm64: dts: mediatek: asurada: Enable SCP

[Chen-Yu Tsai]

On Thu, Jun 30, 2022 at 12:00 AM Nícolas F. R. A. Prado
<nfraprado@collabora.com> wrote:
>
> Enable support for the SCP co-processor present on MT8192. It is used
> as part of the video encoding and decoding processes.
>
> A region of memory is carved out for its use, and remoteproc setup for
> communication with the ChromeOS EC.
>
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Tested-by: Chen-Yu Tsai <wenst@chromium.org>

Re: [PATCH v4 18/19] arm64: dts: mediatek: asurada: Enable SCP

[Chen-Yu Tsai]

On Thu, Jun 30, 2022 at 12:00 AM Nícolas F. R. A. Prado
<nfraprado@collabora.com> wrote:
>
> Enable support for the SCP co-processor present on MT8192. It is used
> as part of the video encoding and decoding processes.
>
> A region of memory is carved out for its use, and remoteproc setup for
> communication with the ChromeOS EC.
>
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Tested-by: Chen-Yu Tsai <wenst@chromium.org>

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Re: [PATCH v4 19/19] arm64: dts: mediatek: asurada: Add SPI NOR flash memory

[Chen-Yu Tsai]

On Thu, Jun 30, 2022 at 12:00 AM Nícolas F. R. A. Prado
<nfraprado@collabora.com> wrote:
>
> Add support for the SPI NOR flash memory present on the Asurada
> platform.
>
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Tested-by: Chen-Yu Tsai <wenst@chromium.org>

Re: [PATCH v4 19/19] arm64: dts: mediatek: asurada: Add SPI NOR flash memory

[Chen-Yu Tsai]

On Thu, Jun 30, 2022 at 12:00 AM Nícolas F. R. A. Prado
<nfraprado@collabora.com> wrote:
>
> Add support for the SPI NOR flash memory present on the Asurada
> platform.
>
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Tested-by: Chen-Yu Tsai <wenst@chromium.org>

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Re: [PATCH v4 00/19] Introduce support for MediaTek MT8192 Google Chromebooks

[Chen-Yu Tsai]

On Thu, Jun 30, 2022 at 12:00 AM Nícolas F. R. A. Prado
<nfraprado@collabora.com> wrote:
>
>
> This series introduces Devicetrees for the MT8192-based Asurada platform
> as well as Asurada Spherion and Asurada Hayato boards.
>
> Support for the boards is added to the extent that is currently enabled
> in the mt8192.dtsi, and using only properties already merged in the
> dt-bindings, as to not add any dependencies to this series.
>
> This series was peer-reviewed internally before submission.
>
> Series tested on next-20220629.

Just FYI I also got the internal display to work after some fixes to
the dtsi [1] and copying the stuff over from the ChromeOS kernel tree.

It might be harder to enable the external display, given that we don't
have a good way of describing the weird design of using the DP bridge
also as a mux. See [2] for ongoing discussion.

ChenYu

[1] https://lore.kernel.org/linux-mediatek/CAGXv+5F_Gi_=vV1NSk0AGRVYCa3Q8+gBaE+nv3OJ1AKe2voOwg@mail.gmail.com/
[2] https://lore.kernel.org/dri-devel/20220622173605.1168416-1-pmalani@chromium.org/

> v3: https://lore.kernel.org/all/20220512205602.158273-1-nfraprado@collabora.com/
> v2: https://lore.kernel.org/all/20220505194550.3094656-1-nfraprado@collabora.com/
> v1: https://lore.kernel.org/all/20220316151327.564214-1-nfraprado@collabora.com/
>
> Changes in v4:
> - Added patches 17-19 enabling MMC, SCP and SPI NOR flash
> - Switched mediatek,drive-strength-adv for drive-strength-microamp
> - Switched mediatek,pull-up-adv for bias-pull-up
> - Updated Vgpu minimum voltage to appropriate value
>
> Changes in v3:
> - Renamed regulator nodes to be generic
> - Fixed keyboard layout for Hayato
>
> Changes in v2:
> - Added patches 1-2 for Mediatek board dt-bindings
> - Added patches 13-16 enabling hardware for Asurada that has since been
>   enabled on mt8192.dtsi
>
> Nícolas F. R. A. Prado (19):
>   dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-spherion
>   dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato
>   arm64: dts: mediatek: Introduce MT8192-based Asurada board family
>   arm64: dts: mediatek: asurada: Document GPIO names
>   arm64: dts: mediatek: asurada: Add system-wide power supplies
>   arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses
>   arm64: dts: mediatek: asurada: Add ChromeOS EC
>   arm64: dts: mediatek: asurada: Add keyboard mapping for the top row
>   arm64: dts: mediatek: asurada: Add Cr50 TPM
>   arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad
>   arm64: dts: mediatek: asurada: Add I2C touchscreen
>   arm64: dts: mediatek: spherion: Add keyboard backlight
>   arm64: dts: mediatek: asurada: Enable XHCI
>   arm64: dts: mediatek: asurada: Enable PCIe and add WiFi
>   arm64: dts: mediatek: asurada: Add MT6359 PMIC
>   arm64: dts: mediatek: asurada: Add SPMI regulators
>   arm64: dts: mediatek: asurada: Enable MMC
>   arm64: dts: mediatek: asurada: Enable SCP
>   arm64: dts: mediatek: asurada: Add SPI NOR flash memory
>
>  .../devicetree/bindings/arm/mediatek.yaml     |  13 +
>  arch/arm64/boot/dts/mediatek/Makefile         |   2 +
>  .../dts/mediatek/mt8192-asurada-hayato-r1.dts |  47 +
>  .../mediatek/mt8192-asurada-spherion-r0.dts   |  62 ++
>  .../boot/dts/mediatek/mt8192-asurada.dtsi     | 959 ++++++++++++++++++
>  5 files changed, 1083 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
>
> --
> 2.36.1
>

Re: [PATCH v4 00/19] Introduce support for MediaTek MT8192 Google Chromebooks

[Chen-Yu Tsai]

On Thu, Jun 30, 2022 at 12:00 AM Nícolas F. R. A. Prado
<nfraprado@collabora.com> wrote:
>
>
> This series introduces Devicetrees for the MT8192-based Asurada platform
> as well as Asurada Spherion and Asurada Hayato boards.
>
> Support for the boards is added to the extent that is currently enabled
> in the mt8192.dtsi, and using only properties already merged in the
> dt-bindings, as to not add any dependencies to this series.
>
> This series was peer-reviewed internally before submission.
>
> Series tested on next-20220629.

Just FYI I also got the internal display to work after some fixes to
the dtsi [1] and copying the stuff over from the ChromeOS kernel tree.

It might be harder to enable the external display, given that we don't
have a good way of describing the weird design of using the DP bridge
also as a mux. See [2] for ongoing discussion.

ChenYu

[1] https://lore.kernel.org/linux-mediatek/CAGXv+5F_Gi_=vV1NSk0AGRVYCa3Q8+gBaE+nv3OJ1AKe2voOwg@mail.gmail.com/
[2] https://lore.kernel.org/dri-devel/20220622173605.1168416-1-pmalani@chromium.org/

> v3: https://lore.kernel.org/all/20220512205602.158273-1-nfraprado@collabora.com/
> v2: https://lore.kernel.org/all/20220505194550.3094656-1-nfraprado@collabora.com/
> v1: https://lore.kernel.org/all/20220316151327.564214-1-nfraprado@collabora.com/
>
> Changes in v4:
> - Added patches 17-19 enabling MMC, SCP and SPI NOR flash
> - Switched mediatek,drive-strength-adv for drive-strength-microamp
> - Switched mediatek,pull-up-adv for bias-pull-up
> - Updated Vgpu minimum voltage to appropriate value
>
> Changes in v3:
> - Renamed regulator nodes to be generic
> - Fixed keyboard layout for Hayato
>
> Changes in v2:
> - Added patches 1-2 for Mediatek board dt-bindings
> - Added patches 13-16 enabling hardware for Asurada that has since been
>   enabled on mt8192.dtsi
>
> Nícolas F. R. A. Prado (19):
>   dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-spherion
>   dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato
>   arm64: dts: mediatek: Introduce MT8192-based Asurada board family
>   arm64: dts: mediatek: asurada: Document GPIO names
>   arm64: dts: mediatek: asurada: Add system-wide power supplies
>   arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses
>   arm64: dts: mediatek: asurada: Add ChromeOS EC
>   arm64: dts: mediatek: asurada: Add keyboard mapping for the top row
>   arm64: dts: mediatek: asurada: Add Cr50 TPM
>   arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad
>   arm64: dts: mediatek: asurada: Add I2C touchscreen
>   arm64: dts: mediatek: spherion: Add keyboard backlight
>   arm64: dts: mediatek: asurada: Enable XHCI
>   arm64: dts: mediatek: asurada: Enable PCIe and add WiFi
>   arm64: dts: mediatek: asurada: Add MT6359 PMIC
>   arm64: dts: mediatek: asurada: Add SPMI regulators
>   arm64: dts: mediatek: asurada: Enable MMC
>   arm64: dts: mediatek: asurada: Enable SCP
>   arm64: dts: mediatek: asurada: Add SPI NOR flash memory
>
>  .../devicetree/bindings/arm/mediatek.yaml     |  13 +
>  arch/arm64/boot/dts/mediatek/Makefile         |   2 +
>  .../dts/mediatek/mt8192-asurada-hayato-r1.dts |  47 +
>  .../mediatek/mt8192-asurada-spherion-r0.dts   |  62 ++
>  .../boot/dts/mediatek/mt8192-asurada.dtsi     | 959 ++++++++++++++++++
>  5 files changed, 1083 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
>
> --
> 2.36.1
>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v4 00/19] Introduce support for MediaTek MT8192 Google Chromebooks

[Nícolas F. R. A. Prado]

On Fri, Jul 01, 2022 at 08:44:53PM +0800, Chen-Yu Tsai wrote:
> On Thu, Jun 30, 2022 at 12:00 AM Nícolas F. R. A. Prado
> <nfraprado@collabora.com> wrote:
> >
> >
> > This series introduces Devicetrees for the MT8192-based Asurada platform
> > as well as Asurada Spherion and Asurada Hayato boards.
> >
> > Support for the boards is added to the extent that is currently enabled
> > in the mt8192.dtsi, and using only properties already merged in the
> > dt-bindings, as to not add any dependencies to this series.
> >
> > This series was peer-reviewed internally before submission.
> >
> > Series tested on next-20220629.
> 
> Just FYI I also got the internal display to work after some fixes to
> the dtsi [1] and copying the stuff over from the ChromeOS kernel tree.
> 
> It might be harder to enable the external display, given that we don't
> have a good way of describing the weird design of using the DP bridge
> also as a mux. See [2] for ongoing discussion.

Hi ChenYu,

I actually have both the internal and external display working on my local
branch [1], but the commits there aren't final, and I'm also following the
Type-C switch discussion to update my commits whenever the binding is settled
on.

I noticed the lack of the mandatory display aliases in the mt8192 series but
somehow missed mentioning that in the review, so thanks for adding that.

Thanks,
Nícolas

[1] https://gitlab.collabora.com/nfraprado/linux/-/commits/mt8192-asurada

> 
> ChenYu
> 
> [1] https://lore.kernel.org/linux-mediatek/CAGXv+5F_Gi_=vV1NSk0AGRVYCa3Q8+gBaE+nv3OJ1AKe2voOwg@mail.gmail.com/
> [2] https://lore.kernel.org/dri-devel/20220622173605.1168416-1-pmalani@chromium.org/
> 
> > v3: https://lore.kernel.org/all/20220512205602.158273-1-nfraprado@collabora.com/
> > v2: https://lore.kernel.org/all/20220505194550.3094656-1-nfraprado@collabora.com/
> > v1: https://lore.kernel.org/all/20220316151327.564214-1-nfraprado@collabora.com/
> >
> > Changes in v4:
> > - Added patches 17-19 enabling MMC, SCP and SPI NOR flash
> > - Switched mediatek,drive-strength-adv for drive-strength-microamp
> > - Switched mediatek,pull-up-adv for bias-pull-up
> > - Updated Vgpu minimum voltage to appropriate value
> >
> > Changes in v3:
> > - Renamed regulator nodes to be generic
> > - Fixed keyboard layout for Hayato
> >
> > Changes in v2:
> > - Added patches 1-2 for Mediatek board dt-bindings
> > - Added patches 13-16 enabling hardware for Asurada that has since been
> >   enabled on mt8192.dtsi
> >
> > Nícolas F. R. A. Prado (19):
> >   dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-spherion
> >   dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato
> >   arm64: dts: mediatek: Introduce MT8192-based Asurada board family
> >   arm64: dts: mediatek: asurada: Document GPIO names
> >   arm64: dts: mediatek: asurada: Add system-wide power supplies
> >   arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses
> >   arm64: dts: mediatek: asurada: Add ChromeOS EC
> >   arm64: dts: mediatek: asurada: Add keyboard mapping for the top row
> >   arm64: dts: mediatek: asurada: Add Cr50 TPM
> >   arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad
> >   arm64: dts: mediatek: asurada: Add I2C touchscreen
> >   arm64: dts: mediatek: spherion: Add keyboard backlight
> >   arm64: dts: mediatek: asurada: Enable XHCI
> >   arm64: dts: mediatek: asurada: Enable PCIe and add WiFi
> >   arm64: dts: mediatek: asurada: Add MT6359 PMIC
> >   arm64: dts: mediatek: asurada: Add SPMI regulators
> >   arm64: dts: mediatek: asurada: Enable MMC
> >   arm64: dts: mediatek: asurada: Enable SCP
> >   arm64: dts: mediatek: asurada: Add SPI NOR flash memory
> >
> >  .../devicetree/bindings/arm/mediatek.yaml     |  13 +
> >  arch/arm64/boot/dts/mediatek/Makefile         |   2 +
> >  .../dts/mediatek/mt8192-asurada-hayato-r1.dts |  47 +
> >  .../mediatek/mt8192-asurada-spherion-r0.dts   |  62 ++
> >  .../boot/dts/mediatek/mt8192-asurada.dtsi     | 959 ++++++++++++++++++
> >  5 files changed, 1083 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> >
> > --
> > 2.36.1
> >

Re: [PATCH v4 00/19] Introduce support for MediaTek MT8192 Google Chromebooks

[Nícolas F. R. A. Prado]

On Fri, Jul 01, 2022 at 08:44:53PM +0800, Chen-Yu Tsai wrote:
> On Thu, Jun 30, 2022 at 12:00 AM Nícolas F. R. A. Prado
> <nfraprado@collabora.com> wrote:
> >
> >
> > This series introduces Devicetrees for the MT8192-based Asurada platform
> > as well as Asurada Spherion and Asurada Hayato boards.
> >
> > Support for the boards is added to the extent that is currently enabled
> > in the mt8192.dtsi, and using only properties already merged in the
> > dt-bindings, as to not add any dependencies to this series.
> >
> > This series was peer-reviewed internally before submission.
> >
> > Series tested on next-20220629.
> 
> Just FYI I also got the internal display to work after some fixes to
> the dtsi [1] and copying the stuff over from the ChromeOS kernel tree.
> 
> It might be harder to enable the external display, given that we don't
> have a good way of describing the weird design of using the DP bridge
> also as a mux. See [2] for ongoing discussion.

Hi ChenYu,

I actually have both the internal and external display working on my local
branch [1], but the commits there aren't final, and I'm also following the
Type-C switch discussion to update my commits whenever the binding is settled
on.

I noticed the lack of the mandatory display aliases in the mt8192 series but
somehow missed mentioning that in the review, so thanks for adding that.

Thanks,
Nícolas

[1] https://gitlab.collabora.com/nfraprado/linux/-/commits/mt8192-asurada

> 
> ChenYu
> 
> [1] https://lore.kernel.org/linux-mediatek/CAGXv+5F_Gi_=vV1NSk0AGRVYCa3Q8+gBaE+nv3OJ1AKe2voOwg@mail.gmail.com/
> [2] https://lore.kernel.org/dri-devel/20220622173605.1168416-1-pmalani@chromium.org/
> 
> > v3: https://lore.kernel.org/all/20220512205602.158273-1-nfraprado@collabora.com/
> > v2: https://lore.kernel.org/all/20220505194550.3094656-1-nfraprado@collabora.com/
> > v1: https://lore.kernel.org/all/20220316151327.564214-1-nfraprado@collabora.com/
> >
> > Changes in v4:
> > - Added patches 17-19 enabling MMC, SCP and SPI NOR flash
> > - Switched mediatek,drive-strength-adv for drive-strength-microamp
> > - Switched mediatek,pull-up-adv for bias-pull-up
> > - Updated Vgpu minimum voltage to appropriate value
> >
> > Changes in v3:
> > - Renamed regulator nodes to be generic
> > - Fixed keyboard layout for Hayato
> >
> > Changes in v2:
> > - Added patches 1-2 for Mediatek board dt-bindings
> > - Added patches 13-16 enabling hardware for Asurada that has since been
> >   enabled on mt8192.dtsi
> >
> > Nícolas F. R. A. Prado (19):
> >   dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-spherion
> >   dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato
> >   arm64: dts: mediatek: Introduce MT8192-based Asurada board family
> >   arm64: dts: mediatek: asurada: Document GPIO names
> >   arm64: dts: mediatek: asurada: Add system-wide power supplies
> >   arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses
> >   arm64: dts: mediatek: asurada: Add ChromeOS EC
> >   arm64: dts: mediatek: asurada: Add keyboard mapping for the top row
> >   arm64: dts: mediatek: asurada: Add Cr50 TPM
> >   arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad
> >   arm64: dts: mediatek: asurada: Add I2C touchscreen
> >   arm64: dts: mediatek: spherion: Add keyboard backlight
> >   arm64: dts: mediatek: asurada: Enable XHCI
> >   arm64: dts: mediatek: asurada: Enable PCIe and add WiFi
> >   arm64: dts: mediatek: asurada: Add MT6359 PMIC
> >   arm64: dts: mediatek: asurada: Add SPMI regulators
> >   arm64: dts: mediatek: asurada: Enable MMC
> >   arm64: dts: mediatek: asurada: Enable SCP
> >   arm64: dts: mediatek: asurada: Add SPI NOR flash memory
> >
> >  .../devicetree/bindings/arm/mediatek.yaml     |  13 +
> >  arch/arm64/boot/dts/mediatek/Makefile         |   2 +
> >  .../dts/mediatek/mt8192-asurada-hayato-r1.dts |  47 +
> >  .../mediatek/mt8192-asurada-spherion-r0.dts   |  62 ++
> >  .../boot/dts/mediatek/mt8192-asurada.dtsi     | 959 ++++++++++++++++++
> >  5 files changed, 1083 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> >
> > --
> > 2.36.1
> >

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v4 00/19] Introduce support for MediaTek MT8192 Google Chromebooks

[Chen-Yu Tsai]

On Fri, Jul 1, 2022 at 11:01 PM Nícolas F. R. A. Prado
<nfraprado@collabora.com> wrote:
>
> On Fri, Jul 01, 2022 at 08:44:53PM +0800, Chen-Yu Tsai wrote:
> > On Thu, Jun 30, 2022 at 12:00 AM Nícolas F. R. A. Prado
> > <nfraprado@collabora.com> wrote:
> > >
> > >
> > > This series introduces Devicetrees for the MT8192-based Asurada platform
> > > as well as Asurada Spherion and Asurada Hayato boards.
> > >
> > > Support for the boards is added to the extent that is currently enabled
> > > in the mt8192.dtsi, and using only properties already merged in the
> > > dt-bindings, as to not add any dependencies to this series.
> > >
> > > This series was peer-reviewed internally before submission.
> > >
> > > Series tested on next-20220629.
> >
> > Just FYI I also got the internal display to work after some fixes to
> > the dtsi [1] and copying the stuff over from the ChromeOS kernel tree.
> >
> > It might be harder to enable the external display, given that we don't
> > have a good way of describing the weird design of using the DP bridge
> > also as a mux. See [2] for ongoing discussion.
>
> Hi ChenYu,
>
> I actually have both the internal and external display working on my local
> branch [1], but the commits there aren't final, and I'm also following the
> Type-C switch discussion to update my commits whenever the binding is settled
> on.

I see. I think the internal display part is more or less final. It should
be worth including it, as it is a fairly visible indication that things
are working.

ChenYu

> I noticed the lack of the mandatory display aliases in the mt8192 series but
> somehow missed mentioning that in the review, so thanks for adding that.
>
> Thanks,
> Nícolas
>
> [1] https://gitlab.collabora.com/nfraprado/linux/-/commits/mt8192-asurada
>
> >
> > ChenYu
> >
> > [1] https://lore.kernel.org/linux-mediatek/CAGXv+5F_Gi_=vV1NSk0AGRVYCa3Q8+gBaE+nv3OJ1AKe2voOwg@mail.gmail.com/
> > [2] https://lore.kernel.org/dri-devel/20220622173605.1168416-1-pmalani@chromium.org/
> >
> > > v3: https://lore.kernel.org/all/20220512205602.158273-1-nfraprado@collabora.com/
> > > v2: https://lore.kernel.org/all/20220505194550.3094656-1-nfraprado@collabora.com/
> > > v1: https://lore.kernel.org/all/20220316151327.564214-1-nfraprado@collabora.com/
> > >
> > > Changes in v4:
> > > - Added patches 17-19 enabling MMC, SCP and SPI NOR flash
> > > - Switched mediatek,drive-strength-adv for drive-strength-microamp
> > > - Switched mediatek,pull-up-adv for bias-pull-up
> > > - Updated Vgpu minimum voltage to appropriate value
> > >
> > > Changes in v3:
> > > - Renamed regulator nodes to be generic
> > > - Fixed keyboard layout for Hayato
> > >
> > > Changes in v2:
> > > - Added patches 1-2 for Mediatek board dt-bindings
> > > - Added patches 13-16 enabling hardware for Asurada that has since been
> > >   enabled on mt8192.dtsi
> > >
> > > Nícolas F. R. A. Prado (19):
> > >   dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-spherion
> > >   dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato
> > >   arm64: dts: mediatek: Introduce MT8192-based Asurada board family
> > >   arm64: dts: mediatek: asurada: Document GPIO names
> > >   arm64: dts: mediatek: asurada: Add system-wide power supplies
> > >   arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses
> > >   arm64: dts: mediatek: asurada: Add ChromeOS EC
> > >   arm64: dts: mediatek: asurada: Add keyboard mapping for the top row
> > >   arm64: dts: mediatek: asurada: Add Cr50 TPM
> > >   arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad
> > >   arm64: dts: mediatek: asurada: Add I2C touchscreen
> > >   arm64: dts: mediatek: spherion: Add keyboard backlight
> > >   arm64: dts: mediatek: asurada: Enable XHCI
> > >   arm64: dts: mediatek: asurada: Enable PCIe and add WiFi
> > >   arm64: dts: mediatek: asurada: Add MT6359 PMIC
> > >   arm64: dts: mediatek: asurada: Add SPMI regulators
> > >   arm64: dts: mediatek: asurada: Enable MMC
> > >   arm64: dts: mediatek: asurada: Enable SCP
> > >   arm64: dts: mediatek: asurada: Add SPI NOR flash memory
> > >
> > >  .../devicetree/bindings/arm/mediatek.yaml     |  13 +
> > >  arch/arm64/boot/dts/mediatek/Makefile         |   2 +
> > >  .../dts/mediatek/mt8192-asurada-hayato-r1.dts |  47 +
> > >  .../mediatek/mt8192-asurada-spherion-r0.dts   |  62 ++
> > >  .../boot/dts/mediatek/mt8192-asurada.dtsi     | 959 ++++++++++++++++++
> > >  5 files changed, 1083 insertions(+)
> > >  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
> > >  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
> > >  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> > >
> > > --
> > > 2.36.1
> > >

Re: [PATCH v4 00/19] Introduce support for MediaTek MT8192 Google Chromebooks

[Chen-Yu Tsai]

On Fri, Jul 1, 2022 at 11:01 PM Nícolas F. R. A. Prado
<nfraprado@collabora.com> wrote:
>
> On Fri, Jul 01, 2022 at 08:44:53PM +0800, Chen-Yu Tsai wrote:
> > On Thu, Jun 30, 2022 at 12:00 AM Nícolas F. R. A. Prado
> > <nfraprado@collabora.com> wrote:
> > >
> > >
> > > This series introduces Devicetrees for the MT8192-based Asurada platform
> > > as well as Asurada Spherion and Asurada Hayato boards.
> > >
> > > Support for the boards is added to the extent that is currently enabled
> > > in the mt8192.dtsi, and using only properties already merged in the
> > > dt-bindings, as to not add any dependencies to this series.
> > >
> > > This series was peer-reviewed internally before submission.
> > >
> > > Series tested on next-20220629.
> >
> > Just FYI I also got the internal display to work after some fixes to
> > the dtsi [1] and copying the stuff over from the ChromeOS kernel tree.
> >
> > It might be harder to enable the external display, given that we don't
> > have a good way of describing the weird design of using the DP bridge
> > also as a mux. See [2] for ongoing discussion.
>
> Hi ChenYu,
>
> I actually have both the internal and external display working on my local
> branch [1], but the commits there aren't final, and I'm also following the
> Type-C switch discussion to update my commits whenever the binding is settled
> on.

I see. I think the internal display part is more or less final. It should
be worth including it, as it is a fairly visible indication that things
are working.

ChenYu

> I noticed the lack of the mandatory display aliases in the mt8192 series but
> somehow missed mentioning that in the review, so thanks for adding that.
>
> Thanks,
> Nícolas
>
> [1] https://gitlab.collabora.com/nfraprado/linux/-/commits/mt8192-asurada
>
> >
> > ChenYu
> >
> > [1] https://lore.kernel.org/linux-mediatek/CAGXv+5F_Gi_=vV1NSk0AGRVYCa3Q8+gBaE+nv3OJ1AKe2voOwg@mail.gmail.com/
> > [2] https://lore.kernel.org/dri-devel/20220622173605.1168416-1-pmalani@chromium.org/
> >
> > > v3: https://lore.kernel.org/all/20220512205602.158273-1-nfraprado@collabora.com/
> > > v2: https://lore.kernel.org/all/20220505194550.3094656-1-nfraprado@collabora.com/
> > > v1: https://lore.kernel.org/all/20220316151327.564214-1-nfraprado@collabora.com/
> > >
> > > Changes in v4:
> > > - Added patches 17-19 enabling MMC, SCP and SPI NOR flash
> > > - Switched mediatek,drive-strength-adv for drive-strength-microamp
> > > - Switched mediatek,pull-up-adv for bias-pull-up
> > > - Updated Vgpu minimum voltage to appropriate value
> > >
> > > Changes in v3:
> > > - Renamed regulator nodes to be generic
> > > - Fixed keyboard layout for Hayato
> > >
> > > Changes in v2:
> > > - Added patches 1-2 for Mediatek board dt-bindings
> > > - Added patches 13-16 enabling hardware for Asurada that has since been
> > >   enabled on mt8192.dtsi
> > >
> > > Nícolas F. R. A. Prado (19):
> > >   dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-spherion
> > >   dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato
> > >   arm64: dts: mediatek: Introduce MT8192-based Asurada board family
> > >   arm64: dts: mediatek: asurada: Document GPIO names
> > >   arm64: dts: mediatek: asurada: Add system-wide power supplies
> > >   arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses
> > >   arm64: dts: mediatek: asurada: Add ChromeOS EC
> > >   arm64: dts: mediatek: asurada: Add keyboard mapping for the top row
> > >   arm64: dts: mediatek: asurada: Add Cr50 TPM
> > >   arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad
> > >   arm64: dts: mediatek: asurada: Add I2C touchscreen
> > >   arm64: dts: mediatek: spherion: Add keyboard backlight
> > >   arm64: dts: mediatek: asurada: Enable XHCI
> > >   arm64: dts: mediatek: asurada: Enable PCIe and add WiFi
> > >   arm64: dts: mediatek: asurada: Add MT6359 PMIC
> > >   arm64: dts: mediatek: asurada: Add SPMI regulators
> > >   arm64: dts: mediatek: asurada: Enable MMC
> > >   arm64: dts: mediatek: asurada: Enable SCP
> > >   arm64: dts: mediatek: asurada: Add SPI NOR flash memory
> > >
> > >  .../devicetree/bindings/arm/mediatek.yaml     |  13 +
> > >  arch/arm64/boot/dts/mediatek/Makefile         |   2 +
> > >  .../dts/mediatek/mt8192-asurada-hayato-r1.dts |  47 +
> > >  .../mediatek/mt8192-asurada-spherion-r0.dts   |  62 ++
> > >  .../boot/dts/mediatek/mt8192-asurada.dtsi     | 959 ++++++++++++++++++
> > >  5 files changed, 1083 insertions(+)
> > >  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
> > >  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
> > >  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> > >
> > > --
> > > 2.36.1
> > >

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Re: [PATCH v4 00/19] Introduce support for MediaTek MT8192 Google Chromebooks

[Nícolas F. R. A. Prado]

On Tue, Jul 05, 2022 at 12:03:08PM +0800, Chen-Yu Tsai wrote:
> On Fri, Jul 1, 2022 at 11:01 PM Nícolas F. R. A. Prado
> <nfraprado@collabora.com> wrote:
> >
> > On Fri, Jul 01, 2022 at 08:44:53PM +0800, Chen-Yu Tsai wrote:
> > > On Thu, Jun 30, 2022 at 12:00 AM Nícolas F. R. A. Prado
> > > <nfraprado@collabora.com> wrote:
> > > >
> > > >
> > > > This series introduces Devicetrees for the MT8192-based Asurada platform
> > > > as well as Asurada Spherion and Asurada Hayato boards.
> > > >
> > > > Support for the boards is added to the extent that is currently enabled
> > > > in the mt8192.dtsi, and using only properties already merged in the
> > > > dt-bindings, as to not add any dependencies to this series.
> > > >
> > > > This series was peer-reviewed internally before submission.
> > > >
> > > > Series tested on next-20220629.
> > >
> > > Just FYI I also got the internal display to work after some fixes to
> > > the dtsi [1] and copying the stuff over from the ChromeOS kernel tree.
> > >
> > > It might be harder to enable the external display, given that we don't
> > > have a good way of describing the weird design of using the DP bridge
> > > also as a mux. See [2] for ongoing discussion.
> >
> > Hi ChenYu,
> >
> > I actually have both the internal and external display working on my local
> > branch [1], but the commits there aren't final, and I'm also following the
> > Type-C switch discussion to update my commits whenever the binding is settled
> > on.
> 
> I see. I think the internal display part is more or less final. It should
> be worth including it, as it is a fairly visible indication that things
> are working.

Yeah, it is final, but not all of the display-related nodes in mt8192.dtsi have
been merged yet [1] and I didn't want to introduce dependencies to the series.

If that series gets merged before this one, I could add the display to this
series as well, but I'm just worried that by introducing new commits with almost
every new series version, this series might never get reviewed and merged, and
this series is pretty big already. So I'd prefer to leave the display for a
following series.

Thanks,
Nícolas

[1] https://lore.kernel.org/all/20220701090547.21429-1-allen-kh.cheng@mediatek.com

> 
> ChenYu
> 
> > I noticed the lack of the mandatory display aliases in the mt8192 series but
> > somehow missed mentioning that in the review, so thanks for adding that.
> >
> > Thanks,
> > Nícolas
> >
> > [1] https://gitlab.collabora.com/nfraprado/linux/-/commits/mt8192-asurada
> >
> > >
> > > ChenYu
> > >
> > > [1] https://lore.kernel.org/linux-mediatek/CAGXv+5F_Gi_=vV1NSk0AGRVYCa3Q8+gBaE+nv3OJ1AKe2voOwg@mail.gmail.com/
> > > [2] https://lore.kernel.org/dri-devel/20220622173605.1168416-1-pmalani@chromium.org/
> > >
> > > > v3: https://lore.kernel.org/all/20220512205602.158273-1-nfraprado@collabora.com/
> > > > v2: https://lore.kernel.org/all/20220505194550.3094656-1-nfraprado@collabora.com/
> > > > v1: https://lore.kernel.org/all/20220316151327.564214-1-nfraprado@collabora.com/
> > > >
> > > > Changes in v4:
> > > > - Added patches 17-19 enabling MMC, SCP and SPI NOR flash
> > > > - Switched mediatek,drive-strength-adv for drive-strength-microamp
> > > > - Switched mediatek,pull-up-adv for bias-pull-up
> > > > - Updated Vgpu minimum voltage to appropriate value
> > > >
> > > > Changes in v3:
> > > > - Renamed regulator nodes to be generic
> > > > - Fixed keyboard layout for Hayato
> > > >
> > > > Changes in v2:
> > > > - Added patches 1-2 for Mediatek board dt-bindings
> > > > - Added patches 13-16 enabling hardware for Asurada that has since been
> > > >   enabled on mt8192.dtsi
> > > >
> > > > Nícolas F. R. A. Prado (19):
> > > >   dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-spherion
> > > >   dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato
> > > >   arm64: dts: mediatek: Introduce MT8192-based Asurada board family
> > > >   arm64: dts: mediatek: asurada: Document GPIO names
> > > >   arm64: dts: mediatek: asurada: Add system-wide power supplies
> > > >   arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses
> > > >   arm64: dts: mediatek: asurada: Add ChromeOS EC
> > > >   arm64: dts: mediatek: asurada: Add keyboard mapping for the top row
> > > >   arm64: dts: mediatek: asurada: Add Cr50 TPM
> > > >   arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad
> > > >   arm64: dts: mediatek: asurada: Add I2C touchscreen
> > > >   arm64: dts: mediatek: spherion: Add keyboard backlight
> > > >   arm64: dts: mediatek: asurada: Enable XHCI
> > > >   arm64: dts: mediatek: asurada: Enable PCIe and add WiFi
> > > >   arm64: dts: mediatek: asurada: Add MT6359 PMIC
> > > >   arm64: dts: mediatek: asurada: Add SPMI regulators
> > > >   arm64: dts: mediatek: asurada: Enable MMC
> > > >   arm64: dts: mediatek: asurada: Enable SCP
> > > >   arm64: dts: mediatek: asurada: Add SPI NOR flash memory
> > > >
> > > >  .../devicetree/bindings/arm/mediatek.yaml     |  13 +
> > > >  arch/arm64/boot/dts/mediatek/Makefile         |   2 +
> > > >  .../dts/mediatek/mt8192-asurada-hayato-r1.dts |  47 +
> > > >  .../mediatek/mt8192-asurada-spherion-r0.dts   |  62 ++
> > > >  .../boot/dts/mediatek/mt8192-asurada.dtsi     | 959 ++++++++++++++++++
> > > >  5 files changed, 1083 insertions(+)
> > > >  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
> > > >  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
> > > >  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> > > >
> > > > --
> > > > 2.36.1
> > > >

Re: [PATCH v4 00/19] Introduce support for MediaTek MT8192 Google Chromebooks

[Nícolas F. R. A. Prado]

On Tue, Jul 05, 2022 at 12:03:08PM +0800, Chen-Yu Tsai wrote:
> On Fri, Jul 1, 2022 at 11:01 PM Nícolas F. R. A. Prado
> <nfraprado@collabora.com> wrote:
> >
> > On Fri, Jul 01, 2022 at 08:44:53PM +0800, Chen-Yu Tsai wrote:
> > > On Thu, Jun 30, 2022 at 12:00 AM Nícolas F. R. A. Prado
> > > <nfraprado@collabora.com> wrote:
> > > >
> > > >
> > > > This series introduces Devicetrees for the MT8192-based Asurada platform
> > > > as well as Asurada Spherion and Asurada Hayato boards.
> > > >
> > > > Support for the boards is added to the extent that is currently enabled
> > > > in the mt8192.dtsi, and using only properties already merged in the
> > > > dt-bindings, as to not add any dependencies to this series.
> > > >
> > > > This series was peer-reviewed internally before submission.
> > > >
> > > > Series tested on next-20220629.
> > >
> > > Just FYI I also got the internal display to work after some fixes to
> > > the dtsi [1] and copying the stuff over from the ChromeOS kernel tree.
> > >
> > > It might be harder to enable the external display, given that we don't
> > > have a good way of describing the weird design of using the DP bridge
> > > also as a mux. See [2] for ongoing discussion.
> >
> > Hi ChenYu,
> >
> > I actually have both the internal and external display working on my local
> > branch [1], but the commits there aren't final, and I'm also following the
> > Type-C switch discussion to update my commits whenever the binding is settled
> > on.
> 
> I see. I think the internal display part is more or less final. It should
> be worth including it, as it is a fairly visible indication that things
> are working.

Yeah, it is final, but not all of the display-related nodes in mt8192.dtsi have
been merged yet [1] and I didn't want to introduce dependencies to the series.

If that series gets merged before this one, I could add the display to this
series as well, but I'm just worried that by introducing new commits with almost
every new series version, this series might never get reviewed and merged, and
this series is pretty big already. So I'd prefer to leave the display for a
following series.

Thanks,
Nícolas

[1] https://lore.kernel.org/all/20220701090547.21429-1-allen-kh.cheng@mediatek.com

> 
> ChenYu
> 
> > I noticed the lack of the mandatory display aliases in the mt8192 series but
> > somehow missed mentioning that in the review, so thanks for adding that.
> >
> > Thanks,
> > Nícolas
> >
> > [1] https://gitlab.collabora.com/nfraprado/linux/-/commits/mt8192-asurada
> >
> > >
> > > ChenYu
> > >
> > > [1] https://lore.kernel.org/linux-mediatek/CAGXv+5F_Gi_=vV1NSk0AGRVYCa3Q8+gBaE+nv3OJ1AKe2voOwg@mail.gmail.com/
> > > [2] https://lore.kernel.org/dri-devel/20220622173605.1168416-1-pmalani@chromium.org/
> > >
> > > > v3: https://lore.kernel.org/all/20220512205602.158273-1-nfraprado@collabora.com/
> > > > v2: https://lore.kernel.org/all/20220505194550.3094656-1-nfraprado@collabora.com/
> > > > v1: https://lore.kernel.org/all/20220316151327.564214-1-nfraprado@collabora.com/
> > > >
> > > > Changes in v4:
> > > > - Added patches 17-19 enabling MMC, SCP and SPI NOR flash
> > > > - Switched mediatek,drive-strength-adv for drive-strength-microamp
> > > > - Switched mediatek,pull-up-adv for bias-pull-up
> > > > - Updated Vgpu minimum voltage to appropriate value
> > > >
> > > > Changes in v3:
> > > > - Renamed regulator nodes to be generic
> > > > - Fixed keyboard layout for Hayato
> > > >
> > > > Changes in v2:
> > > > - Added patches 1-2 for Mediatek board dt-bindings
> > > > - Added patches 13-16 enabling hardware for Asurada that has since been
> > > >   enabled on mt8192.dtsi
> > > >
> > > > Nícolas F. R. A. Prado (19):
> > > >   dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-spherion
> > > >   dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato
> > > >   arm64: dts: mediatek: Introduce MT8192-based Asurada board family
> > > >   arm64: dts: mediatek: asurada: Document GPIO names
> > > >   arm64: dts: mediatek: asurada: Add system-wide power supplies
> > > >   arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses
> > > >   arm64: dts: mediatek: asurada: Add ChromeOS EC
> > > >   arm64: dts: mediatek: asurada: Add keyboard mapping for the top row
> > > >   arm64: dts: mediatek: asurada: Add Cr50 TPM
> > > >   arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad
> > > >   arm64: dts: mediatek: asurada: Add I2C touchscreen
> > > >   arm64: dts: mediatek: spherion: Add keyboard backlight
> > > >   arm64: dts: mediatek: asurada: Enable XHCI
> > > >   arm64: dts: mediatek: asurada: Enable PCIe and add WiFi
> > > >   arm64: dts: mediatek: asurada: Add MT6359 PMIC
> > > >   arm64: dts: mediatek: asurada: Add SPMI regulators
> > > >   arm64: dts: mediatek: asurada: Enable MMC
> > > >   arm64: dts: mediatek: asurada: Enable SCP
> > > >   arm64: dts: mediatek: asurada: Add SPI NOR flash memory
> > > >
> > > >  .../devicetree/bindings/arm/mediatek.yaml     |  13 +
> > > >  arch/arm64/boot/dts/mediatek/Makefile         |   2 +
> > > >  .../dts/mediatek/mt8192-asurada-hayato-r1.dts |  47 +
> > > >  .../mediatek/mt8192-asurada-spherion-r0.dts   |  62 ++
> > > >  .../boot/dts/mediatek/mt8192-asurada.dtsi     | 959 ++++++++++++++++++
> > > >  5 files changed, 1083 insertions(+)
> > > >  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
> > > >  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
> > > >  create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> > > >
> > > > --
> > > > 2.36.1
> > > >

_______________________________________________
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Re: [PATCH v4 00/19] Introduce support for MediaTek MT8192 Google Chromebooks

[AngeloGioacchino Del Regno]

Il 05/07/22 15:56, Nícolas F. R. A. Prado ha scritto:
> On Tue, Jul 05, 2022 at 12:03:08PM +0800, Chen-Yu Tsai wrote:
>> On Fri, Jul 1, 2022 at 11:01 PM Nícolas F. R. A. Prado
>> <nfraprado@collabora.com> wrote:
>>>
>>> On Fri, Jul 01, 2022 at 08:44:53PM +0800, Chen-Yu Tsai wrote:
>>>> On Thu, Jun 30, 2022 at 12:00 AM Nícolas F. R. A. Prado
>>>> <nfraprado@collabora.com> wrote:
>>>>>
>>>>>
>>>>> This series introduces Devicetrees for the MT8192-based Asurada platform
>>>>> as well as Asurada Spherion and Asurada Hayato boards.
>>>>>
>>>>> Support for the boards is added to the extent that is currently enabled
>>>>> in the mt8192.dtsi, and using only properties already merged in the
>>>>> dt-bindings, as to not add any dependencies to this series.
>>>>>
>>>>> This series was peer-reviewed internally before submission.
>>>>>
>>>>> Series tested on next-20220629.
>>>>
>>>> Just FYI I also got the internal display to work after some fixes to
>>>> the dtsi [1] and copying the stuff over from the ChromeOS kernel tree.
>>>>
>>>> It might be harder to enable the external display, given that we don't
>>>> have a good way of describing the weird design of using the DP bridge
>>>> also as a mux. See [2] for ongoing discussion.
>>>
>>> Hi ChenYu,
>>>
>>> I actually have both the internal and external display working on my local
>>> branch [1], but the commits there aren't final, and I'm also following the
>>> Type-C switch discussion to update my commits whenever the binding is settled
>>> on.
>>
>> I see. I think the internal display part is more or less final. It should
>> be worth including it, as it is a fairly visible indication that things
>> are working.
> 
> Yeah, it is final, but not all of the display-related nodes in mt8192.dtsi have
> been merged yet [1] and I didn't want to introduce dependencies to the series.
> 
> If that series gets merged before this one, I could add the display to this
> series as well, but I'm just worried that by introducing new commits with almost
> every new series version, this series might never get reviewed and merged, and
> this series is pretty big already. So I'd prefer to leave the display for a
> following series.
> 
> Thanks,
> Nícolas
> 
> [1] https://lore.kernel.org/all/20220701090547.21429-1-allen-kh.cheng@mediatek.com
> 

Matthias, can you please give an advice on that?

Thank you,
Angelo


>>
>> ChenYu
>>
>>> I noticed the lack of the mandatory display aliases in the mt8192 series but
>>> somehow missed mentioning that in the review, so thanks for adding that.
>>>
>>> Thanks,
>>> Nícolas
>>>
>>> [1] https://gitlab.collabora.com/nfraprado/linux/-/commits/mt8192-asurada
>>>
>>>>
>>>> ChenYu
>>>>
>>>> [1] https://lore.kernel.org/linux-mediatek/CAGXv+5F_Gi_=vV1NSk0AGRVYCa3Q8+gBaE+nv3OJ1AKe2voOwg@mail.gmail.com/
>>>> [2] https://lore.kernel.org/dri-devel/20220622173605.1168416-1-pmalani@chromium.org/
>>>>
>>>>> v3: https://lore.kernel.org/all/20220512205602.158273-1-nfraprado@collabora.com/
>>>>> v2: https://lore.kernel.org/all/20220505194550.3094656-1-nfraprado@collabora.com/
>>>>> v1: https://lore.kernel.org/all/20220316151327.564214-1-nfraprado@collabora.com/
>>>>>
>>>>> Changes in v4:
>>>>> - Added patches 17-19 enabling MMC, SCP and SPI NOR flash
>>>>> - Switched mediatek,drive-strength-adv for drive-strength-microamp
>>>>> - Switched mediatek,pull-up-adv for bias-pull-up
>>>>> - Updated Vgpu minimum voltage to appropriate value
>>>>>
>>>>> Changes in v3:
>>>>> - Renamed regulator nodes to be generic
>>>>> - Fixed keyboard layout for Hayato
>>>>>
>>>>> Changes in v2:
>>>>> - Added patches 1-2 for Mediatek board dt-bindings
>>>>> - Added patches 13-16 enabling hardware for Asurada that has since been
>>>>>    enabled on mt8192.dtsi
>>>>>
>>>>> Nícolas F. R. A. Prado (19):
>>>>>    dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-spherion
>>>>>    dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato
>>>>>    arm64: dts: mediatek: Introduce MT8192-based Asurada board family
>>>>>    arm64: dts: mediatek: asurada: Document GPIO names
>>>>>    arm64: dts: mediatek: asurada: Add system-wide power supplies
>>>>>    arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses
>>>>>    arm64: dts: mediatek: asurada: Add ChromeOS EC
>>>>>    arm64: dts: mediatek: asurada: Add keyboard mapping for the top row
>>>>>    arm64: dts: mediatek: asurada: Add Cr50 TPM
>>>>>    arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad
>>>>>    arm64: dts: mediatek: asurada: Add I2C touchscreen
>>>>>    arm64: dts: mediatek: spherion: Add keyboard backlight
>>>>>    arm64: dts: mediatek: asurada: Enable XHCI
>>>>>    arm64: dts: mediatek: asurada: Enable PCIe and add WiFi
>>>>>    arm64: dts: mediatek: asurada: Add MT6359 PMIC
>>>>>    arm64: dts: mediatek: asurada: Add SPMI regulators
>>>>>    arm64: dts: mediatek: asurada: Enable MMC
>>>>>    arm64: dts: mediatek: asurada: Enable SCP
>>>>>    arm64: dts: mediatek: asurada: Add SPI NOR flash memory
>>>>>
>>>>>   .../devicetree/bindings/arm/mediatek.yaml     |  13 +
>>>>>   arch/arm64/boot/dts/mediatek/Makefile         |   2 +
>>>>>   .../dts/mediatek/mt8192-asurada-hayato-r1.dts |  47 +
>>>>>   .../mediatek/mt8192-asurada-spherion-r0.dts   |  62 ++
>>>>>   .../boot/dts/mediatek/mt8192-asurada.dtsi     | 959 ++++++++++++++++++
>>>>>   5 files changed, 1083 insertions(+)
>>>>>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
>>>>>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
>>>>>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
>>>>>
>>>>> --
>>>>> 2.36.1
>>>>>

Re: [PATCH v4 00/19] Introduce support for MediaTek MT8192 Google Chromebooks

[AngeloGioacchino Del Regno]

Il 05/07/22 15:56, Nícolas F. R. A. Prado ha scritto:
> On Tue, Jul 05, 2022 at 12:03:08PM +0800, Chen-Yu Tsai wrote:
>> On Fri, Jul 1, 2022 at 11:01 PM Nícolas F. R. A. Prado
>> <nfraprado@collabora.com> wrote:
>>>
>>> On Fri, Jul 01, 2022 at 08:44:53PM +0800, Chen-Yu Tsai wrote:
>>>> On Thu, Jun 30, 2022 at 12:00 AM Nícolas F. R. A. Prado
>>>> <nfraprado@collabora.com> wrote:
>>>>>
>>>>>
>>>>> This series introduces Devicetrees for the MT8192-based Asurada platform
>>>>> as well as Asurada Spherion and Asurada Hayato boards.
>>>>>
>>>>> Support for the boards is added to the extent that is currently enabled
>>>>> in the mt8192.dtsi, and using only properties already merged in the
>>>>> dt-bindings, as to not add any dependencies to this series.
>>>>>
>>>>> This series was peer-reviewed internally before submission.
>>>>>
>>>>> Series tested on next-20220629.
>>>>
>>>> Just FYI I also got the internal display to work after some fixes to
>>>> the dtsi [1] and copying the stuff over from the ChromeOS kernel tree.
>>>>
>>>> It might be harder to enable the external display, given that we don't
>>>> have a good way of describing the weird design of using the DP bridge
>>>> also as a mux. See [2] for ongoing discussion.
>>>
>>> Hi ChenYu,
>>>
>>> I actually have both the internal and external display working on my local
>>> branch [1], but the commits there aren't final, and I'm also following the
>>> Type-C switch discussion to update my commits whenever the binding is settled
>>> on.
>>
>> I see. I think the internal display part is more or less final. It should
>> be worth including it, as it is a fairly visible indication that things
>> are working.
> 
> Yeah, it is final, but not all of the display-related nodes in mt8192.dtsi have
> been merged yet [1] and I didn't want to introduce dependencies to the series.
> 
> If that series gets merged before this one, I could add the display to this
> series as well, but I'm just worried that by introducing new commits with almost
> every new series version, this series might never get reviewed and merged, and
> this series is pretty big already. So I'd prefer to leave the display for a
> following series.
> 
> Thanks,
> Nícolas
> 
> [1] https://lore.kernel.org/all/20220701090547.21429-1-allen-kh.cheng@mediatek.com
> 

Matthias, can you please give an advice on that?

Thank you,
Angelo


>>
>> ChenYu
>>
>>> I noticed the lack of the mandatory display aliases in the mt8192 series but
>>> somehow missed mentioning that in the review, so thanks for adding that.
>>>
>>> Thanks,
>>> Nícolas
>>>
>>> [1] https://gitlab.collabora.com/nfraprado/linux/-/commits/mt8192-asurada
>>>
>>>>
>>>> ChenYu
>>>>
>>>> [1] https://lore.kernel.org/linux-mediatek/CAGXv+5F_Gi_=vV1NSk0AGRVYCa3Q8+gBaE+nv3OJ1AKe2voOwg@mail.gmail.com/
>>>> [2] https://lore.kernel.org/dri-devel/20220622173605.1168416-1-pmalani@chromium.org/
>>>>
>>>>> v3: https://lore.kernel.org/all/20220512205602.158273-1-nfraprado@collabora.com/
>>>>> v2: https://lore.kernel.org/all/20220505194550.3094656-1-nfraprado@collabora.com/
>>>>> v1: https://lore.kernel.org/all/20220316151327.564214-1-nfraprado@collabora.com/
>>>>>
>>>>> Changes in v4:
>>>>> - Added patches 17-19 enabling MMC, SCP and SPI NOR flash
>>>>> - Switched mediatek,drive-strength-adv for drive-strength-microamp
>>>>> - Switched mediatek,pull-up-adv for bias-pull-up
>>>>> - Updated Vgpu minimum voltage to appropriate value
>>>>>
>>>>> Changes in v3:
>>>>> - Renamed regulator nodes to be generic
>>>>> - Fixed keyboard layout for Hayato
>>>>>
>>>>> Changes in v2:
>>>>> - Added patches 1-2 for Mediatek board dt-bindings
>>>>> - Added patches 13-16 enabling hardware for Asurada that has since been
>>>>>    enabled on mt8192.dtsi
>>>>>
>>>>> Nícolas F. R. A. Prado (19):
>>>>>    dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-spherion
>>>>>    dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato
>>>>>    arm64: dts: mediatek: Introduce MT8192-based Asurada board family
>>>>>    arm64: dts: mediatek: asurada: Document GPIO names
>>>>>    arm64: dts: mediatek: asurada: Add system-wide power supplies
>>>>>    arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses
>>>>>    arm64: dts: mediatek: asurada: Add ChromeOS EC
>>>>>    arm64: dts: mediatek: asurada: Add keyboard mapping for the top row
>>>>>    arm64: dts: mediatek: asurada: Add Cr50 TPM
>>>>>    arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad
>>>>>    arm64: dts: mediatek: asurada: Add I2C touchscreen
>>>>>    arm64: dts: mediatek: spherion: Add keyboard backlight
>>>>>    arm64: dts: mediatek: asurada: Enable XHCI
>>>>>    arm64: dts: mediatek: asurada: Enable PCIe and add WiFi
>>>>>    arm64: dts: mediatek: asurada: Add MT6359 PMIC
>>>>>    arm64: dts: mediatek: asurada: Add SPMI regulators
>>>>>    arm64: dts: mediatek: asurada: Enable MMC
>>>>>    arm64: dts: mediatek: asurada: Enable SCP
>>>>>    arm64: dts: mediatek: asurada: Add SPI NOR flash memory
>>>>>
>>>>>   .../devicetree/bindings/arm/mediatek.yaml     |  13 +
>>>>>   arch/arm64/boot/dts/mediatek/Makefile         |   2 +
>>>>>   .../dts/mediatek/mt8192-asurada-hayato-r1.dts |  47 +
>>>>>   .../mediatek/mt8192-asurada-spherion-r0.dts   |  62 ++
>>>>>   .../boot/dts/mediatek/mt8192-asurada.dtsi     | 959 ++++++++++++++++++
>>>>>   5 files changed, 1083 insertions(+)
>>>>>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
>>>>>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
>>>>>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
>>>>>
>>>>> --
>>>>> 2.36.1
>>>>>


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Re: [PATCH v4 00/19] Introduce support for MediaTek MT8192 Google Chromebooks

[Matthias Brugger]

On 29/06/2022 17:59, Nícolas F. R. A. Prado wrote:
> 
> This series introduces Devicetrees for the MT8192-based Asurada platform
> as well as Asurada Spherion and Asurada Hayato boards.
> 
> Support for the boards is added to the extent that is currently enabled
> in the mt8192.dtsi, and using only properties already merged in the
> dt-bindings, as to not add any dependencies to this series.
> 
> This series was peer-reviewed internally before submission.
> 

Whole series applied. Thanks!

> Series tested on next-20220629.
> 
> v3: https://lore.kernel.org/all/20220512205602.158273-1-nfraprado@collabora.com/
> v2: https://lore.kernel.org/all/20220505194550.3094656-1-nfraprado@collabora.com/
> v1: https://lore.kernel.org/all/20220316151327.564214-1-nfraprado@collabora.com/
> 
> Changes in v4:
> - Added patches 17-19 enabling MMC, SCP and SPI NOR flash
> - Switched mediatek,drive-strength-adv for drive-strength-microamp
> - Switched mediatek,pull-up-adv for bias-pull-up
> - Updated Vgpu minimum voltage to appropriate value
> 
> Changes in v3:
> - Renamed regulator nodes to be generic
> - Fixed keyboard layout for Hayato
> 
> Changes in v2:
> - Added patches 1-2 for Mediatek board dt-bindings
> - Added patches 13-16 enabling hardware for Asurada that has since been
>    enabled on mt8192.dtsi
> 
> Nícolas F. R. A. Prado (19):
>    dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-spherion
>    dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato
>    arm64: dts: mediatek: Introduce MT8192-based Asurada board family
>    arm64: dts: mediatek: asurada: Document GPIO names
>    arm64: dts: mediatek: asurada: Add system-wide power supplies
>    arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses
>    arm64: dts: mediatek: asurada: Add ChromeOS EC
>    arm64: dts: mediatek: asurada: Add keyboard mapping for the top row
>    arm64: dts: mediatek: asurada: Add Cr50 TPM
>    arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad
>    arm64: dts: mediatek: asurada: Add I2C touchscreen
>    arm64: dts: mediatek: spherion: Add keyboard backlight
>    arm64: dts: mediatek: asurada: Enable XHCI
>    arm64: dts: mediatek: asurada: Enable PCIe and add WiFi
>    arm64: dts: mediatek: asurada: Add MT6359 PMIC
>    arm64: dts: mediatek: asurada: Add SPMI regulators
>    arm64: dts: mediatek: asurada: Enable MMC
>    arm64: dts: mediatek: asurada: Enable SCP
>    arm64: dts: mediatek: asurada: Add SPI NOR flash memory
> 
>   .../devicetree/bindings/arm/mediatek.yaml     |  13 +
>   arch/arm64/boot/dts/mediatek/Makefile         |   2 +
>   .../dts/mediatek/mt8192-asurada-hayato-r1.dts |  47 +
>   .../mediatek/mt8192-asurada-spherion-r0.dts   |  62 ++
>   .../boot/dts/mediatek/mt8192-asurada.dtsi     | 959 ++++++++++++++++++
>   5 files changed, 1083 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> 

Re: [PATCH v4 00/19] Introduce support for MediaTek MT8192 Google Chromebooks

[Matthias Brugger]

On 29/06/2022 17:59, Nícolas F. R. A. Prado wrote:
> 
> This series introduces Devicetrees for the MT8192-based Asurada platform
> as well as Asurada Spherion and Asurada Hayato boards.
> 
> Support for the boards is added to the extent that is currently enabled
> in the mt8192.dtsi, and using only properties already merged in the
> dt-bindings, as to not add any dependencies to this series.
> 
> This series was peer-reviewed internally before submission.
> 

Whole series applied. Thanks!

> Series tested on next-20220629.
> 
> v3: https://lore.kernel.org/all/20220512205602.158273-1-nfraprado@collabora.com/
> v2: https://lore.kernel.org/all/20220505194550.3094656-1-nfraprado@collabora.com/
> v1: https://lore.kernel.org/all/20220316151327.564214-1-nfraprado@collabora.com/
> 
> Changes in v4:
> - Added patches 17-19 enabling MMC, SCP and SPI NOR flash
> - Switched mediatek,drive-strength-adv for drive-strength-microamp
> - Switched mediatek,pull-up-adv for bias-pull-up
> - Updated Vgpu minimum voltage to appropriate value
> 
> Changes in v3:
> - Renamed regulator nodes to be generic
> - Fixed keyboard layout for Hayato
> 
> Changes in v2:
> - Added patches 1-2 for Mediatek board dt-bindings
> - Added patches 13-16 enabling hardware for Asurada that has since been
>    enabled on mt8192.dtsi
> 
> Nícolas F. R. A. Prado (19):
>    dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-spherion
>    dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato
>    arm64: dts: mediatek: Introduce MT8192-based Asurada board family
>    arm64: dts: mediatek: asurada: Document GPIO names
>    arm64: dts: mediatek: asurada: Add system-wide power supplies
>    arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses
>    arm64: dts: mediatek: asurada: Add ChromeOS EC
>    arm64: dts: mediatek: asurada: Add keyboard mapping for the top row
>    arm64: dts: mediatek: asurada: Add Cr50 TPM
>    arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad
>    arm64: dts: mediatek: asurada: Add I2C touchscreen
>    arm64: dts: mediatek: spherion: Add keyboard backlight
>    arm64: dts: mediatek: asurada: Enable XHCI
>    arm64: dts: mediatek: asurada: Enable PCIe and add WiFi
>    arm64: dts: mediatek: asurada: Add MT6359 PMIC
>    arm64: dts: mediatek: asurada: Add SPMI regulators
>    arm64: dts: mediatek: asurada: Enable MMC
>    arm64: dts: mediatek: asurada: Enable SCP
>    arm64: dts: mediatek: asurada: Add SPI NOR flash memory
> 
>   .../devicetree/bindings/arm/mediatek.yaml     |  13 +
>   arch/arm64/boot/dts/mediatek/Makefile         |   2 +
>   .../dts/mediatek/mt8192-asurada-hayato-r1.dts |  47 +
>   .../mediatek/mt8192-asurada-spherion-r0.dts   |  62 ++
>   .../boot/dts/mediatek/mt8192-asurada.dtsi     | 959 ++++++++++++++++++
>   5 files changed, 1083 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts
>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts
>   create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
> 

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