* [Intel-gfx] [PATCH v3 00/13] drm/i915/dsi: enable DSC
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
3rd try at enabling DSC on ICL+ DSI. Something very close to this was
tested to work by Vandita.
BR,
Jani.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Jani Nikula (13):
drm/i915/bios: pass devdata to parse_ddi_port
drm/i915/bios: parse compression parameters block
drm/i915/bios: add support for querying DSC details for encoder
drm/i915/dsc: move DP specific compute params to intel_dp.c
drm/i915/dsc: move slice height calculation to encoder
drm/i915/dsc: add support for computing and writing PPS for DSI
encoders
drm/i915/dsi: set pipe_bpp on ICL configure config
drm/i915/dsi: abstract afe_clk calculation
drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
drm/i915/dsi: take compression into account in afe_clk()
drm/i915/dsi: use compressed pixel format with DSC
drm/i915/dsi: account for DSC in horizontal timings
drm/i915/dsi: add support for DSC
drivers/gpu/drm/i915/display/icl_dsi.c | 184 ++++++++++++++----
drivers/gpu/drm/i915/display/intel_bios.c | 167 +++++++++++++++-
drivers/gpu/drm/i915/display/intel_bios.h | 5 +
drivers/gpu/drm/i915/display/intel_dp.c | 59 +++++-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 84 +++-----
6 files changed, 393 insertions(+), 108 deletions(-)
--
2.20.1
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^ permalink raw reply [flat|nested] 56+ messages in thread* [PATCH v3 01/13] drm/i915/bios: pass devdata to parse_ddi_port
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Allow accessing the parent structure later on. Drop const for allowing
future modification as well.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index f6a9a5ccb556..127933f12454 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1525,9 +1525,10 @@ static enum port dvo_port_to_port(u8 dvo_port)
}
static void parse_ddi_port(struct drm_i915_private *dev_priv,
- const struct child_device_config *child,
+ struct display_device_data *devdata,
u8 bdb_version)
{
+ const struct child_device_config *child = &devdata->child;
struct ddi_vbt_port_info *info;
bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
enum port port;
@@ -1679,7 +1680,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv,
static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
{
- const struct display_device_data *devdata;
+ struct display_device_data *devdata;
if (!HAS_DDI(dev_priv) && !IS_CHERRYVIEW(dev_priv))
return;
@@ -1688,7 +1689,7 @@ static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
return;
list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node)
- parse_ddi_port(dev_priv, &devdata->child, bdb_version);
+ parse_ddi_port(dev_priv, devdata, bdb_version);
}
static void
--
2.20.1
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^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH v3 01/13] drm/i915/bios: pass devdata to parse_ddi_port
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Allow accessing the parent structure later on. Drop const for allowing
future modification as well.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index f6a9a5ccb556..127933f12454 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1525,9 +1525,10 @@ static enum port dvo_port_to_port(u8 dvo_port)
}
static void parse_ddi_port(struct drm_i915_private *dev_priv,
- const struct child_device_config *child,
+ struct display_device_data *devdata,
u8 bdb_version)
{
+ const struct child_device_config *child = &devdata->child;
struct ddi_vbt_port_info *info;
bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
enum port port;
@@ -1679,7 +1680,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv,
static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
{
- const struct display_device_data *devdata;
+ struct display_device_data *devdata;
if (!HAS_DDI(dev_priv) && !IS_CHERRYVIEW(dev_priv))
return;
@@ -1688,7 +1689,7 @@ static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
return;
list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node)
- parse_ddi_port(dev_priv, &devdata->child, bdb_version);
+ parse_ddi_port(dev_priv, devdata, bdb_version);
}
static void
--
2.20.1
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^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH v3 01/13] drm/i915/bios: pass devdata to parse_ddi_port
2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula
(?)
@ 2019-12-04 7:52 ` Kulkarni, Vandita
-1 siblings, 0 replies; 56+ messages in thread
From: Kulkarni, Vandita @ 2019-12-04 7:52 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Tuesday, November 26, 2019 7:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: [PATCH v3 01/13] drm/i915/bios: pass devdata to parse_ddi_port
>
> Allow accessing the parent structure later on. Drop const for allowing future
> modification as well.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Thanks,
Vandita
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index f6a9a5ccb556..127933f12454 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1525,9 +1525,10 @@ static enum port dvo_port_to_port(u8 dvo_port)
> }
>
> static void parse_ddi_port(struct drm_i915_private *dev_priv,
> - const struct child_device_config *child,
> + struct display_device_data *devdata,
> u8 bdb_version)
> {
> + const struct child_device_config *child = &devdata->child;
> struct ddi_vbt_port_info *info;
> bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
> enum port port;
> @@ -1679,7 +1680,7 @@ static void parse_ddi_port(struct drm_i915_private
> *dev_priv,
>
> static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8
> bdb_version) {
> - const struct display_device_data *devdata;
> + struct display_device_data *devdata;
>
> if (!HAS_DDI(dev_priv) && !IS_CHERRYVIEW(dev_priv))
> return;
> @@ -1688,7 +1689,7 @@ static void parse_ddi_ports(struct
> drm_i915_private *dev_priv, u8 bdb_version)
> return;
>
> list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node)
> - parse_ddi_port(dev_priv, &devdata->child, bdb_version);
> + parse_ddi_port(dev_priv, devdata, bdb_version);
> }
>
> static void
> --
> 2.20.1
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^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v3 02/13] drm/i915/bios: parse compression parameters block
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Check for child devices that specify compression, and store the device
specific compression parameters in the display device data struct for
later use. Warn if compression is requested but not available.
Use fairly rigid checks for compression data for starters. These can be
made more dynamic later.
Log about DSC presence in DDI port parse, though this is not universal
across platforms or port types (DSI).
v2: amended debug logging
Bspec: 29885
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 61 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 +-
2 files changed, 60 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 127933f12454..9ac6c657a05e 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -61,6 +61,7 @@
/* Wrapper for VBT child device config */
struct display_device_data {
struct child_device_config child;
+ struct dsc_compression_parameters_entry *dsc;
struct list_head node;
};
@@ -1337,6 +1338,57 @@ parse_mipi_sequence(struct drm_i915_private *dev_priv,
memset(dev_priv->vbt.dsi.sequence, 0, sizeof(dev_priv->vbt.dsi.sequence));
}
+static void
+parse_compression_parameters(struct drm_i915_private *i915,
+ const struct bdb_header *bdb)
+{
+ const struct bdb_compression_parameters *params;
+ struct display_device_data *devdata;
+ const struct child_device_config *child;
+ u16 block_size;
+ int index;
+
+ if (bdb->version < 198)
+ return;
+
+ params = find_section(bdb, BDB_COMPRESSION_PARAMETERS);
+ if (params) {
+ /* Sanity checks */
+ if (params->entry_size != sizeof(params->data[0])) {
+ DRM_DEBUG_KMS("VBT: unsupported compression param entry size\n");
+ return;
+ }
+
+ block_size = get_blocksize(params);
+ if (block_size < sizeof(*params)) {
+ DRM_DEBUG_KMS("VBT: expected 16 compression param entries\n");
+ return;
+ }
+ }
+
+ list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+ child = &devdata->child;
+
+ if (!child->compression_enable)
+ continue;
+
+ if (!params) {
+ DRM_DEBUG_KMS("VBT: compression params not available\n");
+ continue;
+ }
+
+ if (child->compression_method_cps) {
+ DRM_DEBUG_KMS("VBT: CPS compression not supported\n");
+ continue;
+ }
+
+ index = child->compression_structure_index;
+
+ devdata->dsc = kmemdup(¶ms->data[index],
+ sizeof(*devdata->dsc), GFP_KERNEL);
+ }
+}
+
static u8 translate_iboost(u8 val)
{
static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */
@@ -1569,10 +1621,11 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv,
if (bdb_version >= 209)
info->supports_tbt = child->tbt;
- DRM_DEBUG_KMS("Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d\n",
+ DRM_DEBUG_KMS("Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n",
port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp,
HAS_LSPCON(dev_priv) && child->lspcon,
- info->supports_typec_usb, info->supports_tbt);
+ info->supports_typec_usb, info->supports_tbt,
+ devdata->dsc != NULL);
if (is_edp && is_dvi)
DRM_DEBUG_KMS("Internal DP port %c is TMDS compatible\n",
@@ -1979,6 +2032,9 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
parse_mipi_config(dev_priv, bdb);
parse_mipi_sequence(dev_priv, bdb);
+ /* Depends on child device list */
+ parse_compression_parameters(dev_priv, bdb);
+
/* Further processing on pre-parsed data */
parse_sdvo_device_mapping(dev_priv, bdb->version);
parse_ddi_ports(dev_priv, bdb->version);
@@ -2003,6 +2059,7 @@ void intel_bios_driver_remove(struct drm_i915_private *dev_priv)
list_for_each_entry_safe(devdata, n, &dev_priv->vbt.display_devices, node) {
list_del(&devdata->node);
+ kfree(devdata->dsc);
kfree(devdata);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index f0338da3a82a..b1ef7f00eb11 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -369,7 +369,7 @@ struct child_device_config {
u16 dtd_buf_ptr; /* 161 */
u8 edidless_efp:1; /* 161 */
u8 compression_enable:1; /* 198 */
- u8 compression_method:1; /* 198 */
+ u8 compression_method_cps:1; /* 198 */
u8 ganged_edp:1; /* 202 */
u8 reserved0:4;
u8 compression_structure_index:4; /* 198 */
--
2.20.1
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^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH v3 02/13] drm/i915/bios: parse compression parameters block
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Check for child devices that specify compression, and store the device
specific compression parameters in the display device data struct for
later use. Warn if compression is requested but not available.
Use fairly rigid checks for compression data for starters. These can be
made more dynamic later.
Log about DSC presence in DDI port parse, though this is not universal
across platforms or port types (DSI).
v2: amended debug logging
Bspec: 29885
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 61 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 +-
2 files changed, 60 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 127933f12454..9ac6c657a05e 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -61,6 +61,7 @@
/* Wrapper for VBT child device config */
struct display_device_data {
struct child_device_config child;
+ struct dsc_compression_parameters_entry *dsc;
struct list_head node;
};
@@ -1337,6 +1338,57 @@ parse_mipi_sequence(struct drm_i915_private *dev_priv,
memset(dev_priv->vbt.dsi.sequence, 0, sizeof(dev_priv->vbt.dsi.sequence));
}
+static void
+parse_compression_parameters(struct drm_i915_private *i915,
+ const struct bdb_header *bdb)
+{
+ const struct bdb_compression_parameters *params;
+ struct display_device_data *devdata;
+ const struct child_device_config *child;
+ u16 block_size;
+ int index;
+
+ if (bdb->version < 198)
+ return;
+
+ params = find_section(bdb, BDB_COMPRESSION_PARAMETERS);
+ if (params) {
+ /* Sanity checks */
+ if (params->entry_size != sizeof(params->data[0])) {
+ DRM_DEBUG_KMS("VBT: unsupported compression param entry size\n");
+ return;
+ }
+
+ block_size = get_blocksize(params);
+ if (block_size < sizeof(*params)) {
+ DRM_DEBUG_KMS("VBT: expected 16 compression param entries\n");
+ return;
+ }
+ }
+
+ list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+ child = &devdata->child;
+
+ if (!child->compression_enable)
+ continue;
+
+ if (!params) {
+ DRM_DEBUG_KMS("VBT: compression params not available\n");
+ continue;
+ }
+
+ if (child->compression_method_cps) {
+ DRM_DEBUG_KMS("VBT: CPS compression not supported\n");
+ continue;
+ }
+
+ index = child->compression_structure_index;
+
+ devdata->dsc = kmemdup(¶ms->data[index],
+ sizeof(*devdata->dsc), GFP_KERNEL);
+ }
+}
+
static u8 translate_iboost(u8 val)
{
static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */
@@ -1569,10 +1621,11 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv,
if (bdb_version >= 209)
info->supports_tbt = child->tbt;
- DRM_DEBUG_KMS("Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d\n",
+ DRM_DEBUG_KMS("Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n",
port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp,
HAS_LSPCON(dev_priv) && child->lspcon,
- info->supports_typec_usb, info->supports_tbt);
+ info->supports_typec_usb, info->supports_tbt,
+ devdata->dsc != NULL);
if (is_edp && is_dvi)
DRM_DEBUG_KMS("Internal DP port %c is TMDS compatible\n",
@@ -1979,6 +2032,9 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
parse_mipi_config(dev_priv, bdb);
parse_mipi_sequence(dev_priv, bdb);
+ /* Depends on child device list */
+ parse_compression_parameters(dev_priv, bdb);
+
/* Further processing on pre-parsed data */
parse_sdvo_device_mapping(dev_priv, bdb->version);
parse_ddi_ports(dev_priv, bdb->version);
@@ -2003,6 +2059,7 @@ void intel_bios_driver_remove(struct drm_i915_private *dev_priv)
list_for_each_entry_safe(devdata, n, &dev_priv->vbt.display_devices, node) {
list_del(&devdata->node);
+ kfree(devdata->dsc);
kfree(devdata);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index f0338da3a82a..b1ef7f00eb11 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -369,7 +369,7 @@ struct child_device_config {
u16 dtd_buf_ptr; /* 161 */
u8 edidless_efp:1; /* 161 */
u8 compression_enable:1; /* 198 */
- u8 compression_method:1; /* 198 */
+ u8 compression_method_cps:1; /* 198 */
u8 ganged_edp:1; /* 202 */
u8 reserved0:4;
u8 compression_structure_index:4; /* 198 */
--
2.20.1
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^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH v3 02/13] drm/i915/bios: parse compression parameters block
2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula
(?)
@ 2019-12-04 8:07 ` Kulkarni, Vandita
-1 siblings, 0 replies; 56+ messages in thread
From: Kulkarni, Vandita @ 2019-12-04 8:07 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Tuesday, November 26, 2019 7:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: [PATCH v3 02/13] drm/i915/bios: parse compression parameters
> block
>
> Check for child devices that specify compression, and store the device
> specific compression parameters in the display device data struct for later
> use. Warn if compression is requested but not available.
>
> Use fairly rigid checks for compression data for starters. These can be made
> more dynamic later.
>
> Log about DSC presence in DDI port parse, though this is not universal across
> platforms or port types (DSI).
>
> v2: amended debug logging
>
> Bspec: 29885
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Thanks,
Vandita
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 61 ++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 +-
> 2 files changed, 60 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 127933f12454..9ac6c657a05e 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -61,6 +61,7 @@
> /* Wrapper for VBT child device config */ struct display_device_data {
> struct child_device_config child;
> + struct dsc_compression_parameters_entry *dsc;
> struct list_head node;
> };
>
> @@ -1337,6 +1338,57 @@ parse_mipi_sequence(struct drm_i915_private
> *dev_priv,
> memset(dev_priv->vbt.dsi.sequence, 0, sizeof(dev_priv-
> >vbt.dsi.sequence));
> }
>
> +static void
> +parse_compression_parameters(struct drm_i915_private *i915,
> + const struct bdb_header *bdb)
> +{
> + const struct bdb_compression_parameters *params;
> + struct display_device_data *devdata;
> + const struct child_device_config *child;
> + u16 block_size;
> + int index;
> +
> + if (bdb->version < 198)
> + return;
> +
> + params = find_section(bdb, BDB_COMPRESSION_PARAMETERS);
> + if (params) {
> + /* Sanity checks */
> + if (params->entry_size != sizeof(params->data[0])) {
> + DRM_DEBUG_KMS("VBT: unsupported compression
> param entry size\n");
> + return;
> + }
> +
> + block_size = get_blocksize(params);
> + if (block_size < sizeof(*params)) {
> + DRM_DEBUG_KMS("VBT: expected 16 compression
> param entries\n");
> + return;
> + }
> + }
> +
> + list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
> + child = &devdata->child;
> +
> + if (!child->compression_enable)
> + continue;
> +
> + if (!params) {
> + DRM_DEBUG_KMS("VBT: compression params not
> available\n");
> + continue;
> + }
> +
> + if (child->compression_method_cps) {
> + DRM_DEBUG_KMS("VBT: CPS compression not
> supported\n");
> + continue;
> + }
> +
> + index = child->compression_structure_index;
> +
> + devdata->dsc = kmemdup(¶ms->data[index],
> + sizeof(*devdata->dsc), GFP_KERNEL);
> + }
> +}
> +
> static u8 translate_iboost(u8 val)
> {
> static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */ @@ -
> 1569,10 +1621,11 @@ static void parse_ddi_port(struct drm_i915_private
> *dev_priv,
> if (bdb_version >= 209)
> info->supports_tbt = child->tbt;
>
> - DRM_DEBUG_KMS("Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d
> eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d\n",
> + DRM_DEBUG_KMS("Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d
> eDP:%d
> +LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n",
> port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp,
> HAS_LSPCON(dev_priv) && child->lspcon,
> - info->supports_typec_usb, info->supports_tbt);
> + info->supports_typec_usb, info->supports_tbt,
> + devdata->dsc != NULL);
>
> if (is_edp && is_dvi)
> DRM_DEBUG_KMS("Internal DP port %c is TMDS
> compatible\n", @@ -1979,6 +2032,9 @@ void intel_bios_init(struct
> drm_i915_private *dev_priv)
> parse_mipi_config(dev_priv, bdb);
> parse_mipi_sequence(dev_priv, bdb);
>
> + /* Depends on child device list */
> + parse_compression_parameters(dev_priv, bdb);
> +
> /* Further processing on pre-parsed data */
> parse_sdvo_device_mapping(dev_priv, bdb->version);
> parse_ddi_ports(dev_priv, bdb->version); @@ -2003,6 +2059,7 @@
> void intel_bios_driver_remove(struct drm_i915_private *dev_priv)
>
> list_for_each_entry_safe(devdata, n, &dev_priv->vbt.display_devices,
> node) {
> list_del(&devdata->node);
> + kfree(devdata->dsc);
> kfree(devdata);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index f0338da3a82a..b1ef7f00eb11 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -369,7 +369,7 @@ struct child_device_config {
> u16 dtd_buf_ptr; /* 161 */
> u8 edidless_efp:1; /* 161 */
> u8 compression_enable:1; /* 198 */
> - u8 compression_method:1; /* 198 */
> + u8 compression_method_cps:1; /*
> 198 */
> u8 ganged_edp:1; /* 202 */
> u8 reserved0:4;
> u8 compression_structure_index:4; /* 198 */
> --
> 2.20.1
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^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v3 03/13] drm/i915/bios: add support for querying DSC details for encoder
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Add function for retrieving the DSC data for an encoder.
Initially, this is DSI specific, as DP does not use VBT settings for DSC
at all. It's also not very pretty.
In the future we might have a pointer from encoder to the child device,
which would make the child device list query here so much more sensible.
v3:
- use crtc_state instead of pipe_config
- return true by default from intel_bios_get_dsc_params()
- expand the comment about rc_buffer_block_size and rc_buffer_size
v2:
- make more robust, debug log errors better
Bspec: 29885
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 99 +++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_bios.h | 5 ++
2 files changed, 104 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 9ac6c657a05e..ef0c8fb28ed6 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -29,6 +29,7 @@
#include <drm/i915_drm.h>
#include "display/intel_display.h"
+#include "display/intel_display_types.h"
#include "display/intel_gmbus.h"
#include "i915_drv.h"
@@ -2337,6 +2338,104 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
return false;
}
+static void fill_dsc(struct intel_crtc_state *crtc_state,
+ struct dsc_compression_parameters_entry *dsc,
+ int dsc_max_bpc)
+{
+ struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+ int bpc = 8;
+
+ vdsc_cfg->dsc_version_major = dsc->version_major;
+ vdsc_cfg->dsc_version_minor = dsc->version_minor;
+
+ if (dsc->support_12bpc && dsc_max_bpc >= 12)
+ bpc = 12;
+ else if (dsc->support_10bpc && dsc_max_bpc >= 10)
+ bpc = 10;
+ else if (dsc->support_8bpc && dsc_max_bpc >= 8)
+ bpc = 8;
+ else
+ DRM_DEBUG_KMS("VBT: Unsupported BPC %d for DCS\n",
+ dsc_max_bpc);
+
+ crtc_state->pipe_bpp = bpc * 3;
+
+ crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
+ VBT_DSC_MAX_BPP(dsc->max_bpp));
+
+ /*
+ * FIXME: This is ugly, and slice count should take DSC engine
+ * throughput etc. into account.
+ *
+ * Also, per spec DSI supports 1, 2, 3 or 4 horizontal slices.
+ */
+ if (dsc->slices_per_line & BIT(2)) {
+ crtc_state->dsc.slice_count = 4;
+ } else if (dsc->slices_per_line & BIT(1)) {
+ crtc_state->dsc.slice_count = 2;
+ } else {
+ /* FIXME */
+ if (!(dsc->slices_per_line & BIT(0)))
+ DRM_DEBUG_KMS("VBT: Unsupported DSC slice count for DSI\n");
+
+ crtc_state->dsc.slice_count = 1;
+ }
+
+ if (crtc_state->hw.adjusted_mode.crtc_hdisplay %
+ crtc_state->dsc.slice_count != 0)
+ DRM_DEBUG_KMS("VBT: DSC hdisplay %d not divisible by slice count %d\n",
+ crtc_state->hw.adjusted_mode.crtc_hdisplay,
+ crtc_state->dsc.slice_count);
+
+ /*
+ * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the
+ * implementation specific physical rate buffer size. Currently we use
+ * the required rate buffer model size calculated in
+ * drm_dsc_compute_rc_parameters() according to VESA DSC Annex E.
+ *
+ * The VBT rc_buffer_block_size and rc_buffer_size definitions
+ * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC
+ * implementation should also use the DPCD (or perhaps VBT for eDP)
+ * provided value for the buffer size.
+ */
+
+ /* FIXME: DSI spec says bpc + 1 for this one */
+ vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);
+
+ vdsc_cfg->block_pred_enable = dsc->block_prediction_enable;
+
+ vdsc_cfg->slice_height = dsc->slice_height;
+}
+
+/* FIXME: initially DSI specific */
+bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ int dsc_max_bpc)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct display_device_data *devdata;
+ const struct child_device_config *child;
+
+ list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+ child = &devdata->child;
+
+ if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))
+ continue;
+
+ if (child->dvo_port - DVO_PORT_MIPIA == encoder->port) {
+ if (!devdata->dsc)
+ return false;
+
+ if (crtc_state)
+ fill_dsc(crtc_state, devdata->dsc, dsc_max_bpc);
+
+ return true;
+ }
+ }
+
+ return false;
+}
+
/**
* intel_bios_is_port_hpd_inverted - is HPD inverted for %port
* @i915: i915 device instance
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index 98f064828a57..d6a0c29d37ac 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -35,6 +35,8 @@
#include <drm/i915_drm.h>
struct drm_i915_private;
+struct intel_crtc_state;
+struct intel_encoder;
enum port;
enum intel_backlight_type {
@@ -242,5 +244,8 @@ bool intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915,
bool intel_bios_is_lspcon_present(const struct drm_i915_private *i915,
enum port port);
enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, enum port port);
+bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ int dsc_max_bpc);
#endif /* _INTEL_BIOS_H_ */
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH v3 03/13] drm/i915/bios: add support for querying DSC details for encoder
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Add function for retrieving the DSC data for an encoder.
Initially, this is DSI specific, as DP does not use VBT settings for DSC
at all. It's also not very pretty.
In the future we might have a pointer from encoder to the child device,
which would make the child device list query here so much more sensible.
v3:
- use crtc_state instead of pipe_config
- return true by default from intel_bios_get_dsc_params()
- expand the comment about rc_buffer_block_size and rc_buffer_size
v2:
- make more robust, debug log errors better
Bspec: 29885
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 99 +++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_bios.h | 5 ++
2 files changed, 104 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 9ac6c657a05e..ef0c8fb28ed6 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -29,6 +29,7 @@
#include <drm/i915_drm.h>
#include "display/intel_display.h"
+#include "display/intel_display_types.h"
#include "display/intel_gmbus.h"
#include "i915_drv.h"
@@ -2337,6 +2338,104 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
return false;
}
+static void fill_dsc(struct intel_crtc_state *crtc_state,
+ struct dsc_compression_parameters_entry *dsc,
+ int dsc_max_bpc)
+{
+ struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+ int bpc = 8;
+
+ vdsc_cfg->dsc_version_major = dsc->version_major;
+ vdsc_cfg->dsc_version_minor = dsc->version_minor;
+
+ if (dsc->support_12bpc && dsc_max_bpc >= 12)
+ bpc = 12;
+ else if (dsc->support_10bpc && dsc_max_bpc >= 10)
+ bpc = 10;
+ else if (dsc->support_8bpc && dsc_max_bpc >= 8)
+ bpc = 8;
+ else
+ DRM_DEBUG_KMS("VBT: Unsupported BPC %d for DCS\n",
+ dsc_max_bpc);
+
+ crtc_state->pipe_bpp = bpc * 3;
+
+ crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
+ VBT_DSC_MAX_BPP(dsc->max_bpp));
+
+ /*
+ * FIXME: This is ugly, and slice count should take DSC engine
+ * throughput etc. into account.
+ *
+ * Also, per spec DSI supports 1, 2, 3 or 4 horizontal slices.
+ */
+ if (dsc->slices_per_line & BIT(2)) {
+ crtc_state->dsc.slice_count = 4;
+ } else if (dsc->slices_per_line & BIT(1)) {
+ crtc_state->dsc.slice_count = 2;
+ } else {
+ /* FIXME */
+ if (!(dsc->slices_per_line & BIT(0)))
+ DRM_DEBUG_KMS("VBT: Unsupported DSC slice count for DSI\n");
+
+ crtc_state->dsc.slice_count = 1;
+ }
+
+ if (crtc_state->hw.adjusted_mode.crtc_hdisplay %
+ crtc_state->dsc.slice_count != 0)
+ DRM_DEBUG_KMS("VBT: DSC hdisplay %d not divisible by slice count %d\n",
+ crtc_state->hw.adjusted_mode.crtc_hdisplay,
+ crtc_state->dsc.slice_count);
+
+ /*
+ * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the
+ * implementation specific physical rate buffer size. Currently we use
+ * the required rate buffer model size calculated in
+ * drm_dsc_compute_rc_parameters() according to VESA DSC Annex E.
+ *
+ * The VBT rc_buffer_block_size and rc_buffer_size definitions
+ * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC
+ * implementation should also use the DPCD (or perhaps VBT for eDP)
+ * provided value for the buffer size.
+ */
+
+ /* FIXME: DSI spec says bpc + 1 for this one */
+ vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);
+
+ vdsc_cfg->block_pred_enable = dsc->block_prediction_enable;
+
+ vdsc_cfg->slice_height = dsc->slice_height;
+}
+
+/* FIXME: initially DSI specific */
+bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ int dsc_max_bpc)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct display_device_data *devdata;
+ const struct child_device_config *child;
+
+ list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+ child = &devdata->child;
+
+ if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))
+ continue;
+
+ if (child->dvo_port - DVO_PORT_MIPIA == encoder->port) {
+ if (!devdata->dsc)
+ return false;
+
+ if (crtc_state)
+ fill_dsc(crtc_state, devdata->dsc, dsc_max_bpc);
+
+ return true;
+ }
+ }
+
+ return false;
+}
+
/**
* intel_bios_is_port_hpd_inverted - is HPD inverted for %port
* @i915: i915 device instance
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index 98f064828a57..d6a0c29d37ac 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -35,6 +35,8 @@
#include <drm/i915_drm.h>
struct drm_i915_private;
+struct intel_crtc_state;
+struct intel_encoder;
enum port;
enum intel_backlight_type {
@@ -242,5 +244,8 @@ bool intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915,
bool intel_bios_is_lspcon_present(const struct drm_i915_private *i915,
enum port port);
enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, enum port port);
+bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ int dsc_max_bpc);
#endif /* _INTEL_BIOS_H_ */
--
2.20.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH v3 03/13] drm/i915/bios: add support for querying DSC details for encoder
2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula
(?)
@ 2019-12-05 4:42 ` Kulkarni, Vandita
-1 siblings, 0 replies; 56+ messages in thread
From: Kulkarni, Vandita @ 2019-12-05 4:42 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Tuesday, November 26, 2019 7:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: [PATCH v3 03/13] drm/i915/bios: add support for querying DSC
> details for encoder
>
> Add function for retrieving the DSC data for an encoder.
>
> Initially, this is DSI specific, as DP does not use VBT settings for DSC at all. It's
> also not very pretty.
>
> In the future we might have a pointer from encoder to the child device,
> which would make the child device list query here so much more sensible.
>
> v3:
> - use crtc_state instead of pipe_config
> - return true by default from intel_bios_get_dsc_params()
> - expand the comment about rc_buffer_block_size and rc_buffer_size
>
> v2:
> - make more robust, debug log errors better
>
> Bspec: 29885
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Thanks,
Vandita
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 99 +++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_bios.h | 5 ++
> 2 files changed, 104 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 9ac6c657a05e..ef0c8fb28ed6 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -29,6 +29,7 @@
> #include <drm/i915_drm.h>
>
> #include "display/intel_display.h"
> +#include "display/intel_display_types.h"
> #include "display/intel_gmbus.h"
>
> #include "i915_drv.h"
> @@ -2337,6 +2338,104 @@ bool intel_bios_is_dsi_present(struct
> drm_i915_private *dev_priv,
> return false;
> }
>
> +static void fill_dsc(struct intel_crtc_state *crtc_state,
> + struct dsc_compression_parameters_entry *dsc,
> + int dsc_max_bpc)
> +{
> + struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> + int bpc = 8;
> +
> + vdsc_cfg->dsc_version_major = dsc->version_major;
> + vdsc_cfg->dsc_version_minor = dsc->version_minor;
> +
> + if (dsc->support_12bpc && dsc_max_bpc >= 12)
> + bpc = 12;
> + else if (dsc->support_10bpc && dsc_max_bpc >= 10)
> + bpc = 10;
> + else if (dsc->support_8bpc && dsc_max_bpc >= 8)
> + bpc = 8;
> + else
> + DRM_DEBUG_KMS("VBT: Unsupported BPC %d for DCS\n",
> + dsc_max_bpc);
> +
> + crtc_state->pipe_bpp = bpc * 3;
> +
> + crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
> + VBT_DSC_MAX_BPP(dsc-
> >max_bpp));
> +
> + /*
> + * FIXME: This is ugly, and slice count should take DSC engine
> + * throughput etc. into account.
> + *
> + * Also, per spec DSI supports 1, 2, 3 or 4 horizontal slices.
> + */
> + if (dsc->slices_per_line & BIT(2)) {
> + crtc_state->dsc.slice_count = 4;
> + } else if (dsc->slices_per_line & BIT(1)) {
> + crtc_state->dsc.slice_count = 2;
> + } else {
> + /* FIXME */
> + if (!(dsc->slices_per_line & BIT(0)))
> + DRM_DEBUG_KMS("VBT: Unsupported DSC slice
> count for DSI\n");
> +
> + crtc_state->dsc.slice_count = 1;
> + }
> +
> + if (crtc_state->hw.adjusted_mode.crtc_hdisplay %
> + crtc_state->dsc.slice_count != 0)
> + DRM_DEBUG_KMS("VBT: DSC hdisplay %d not divisible by
> slice count %d\n",
> + crtc_state->hw.adjusted_mode.crtc_hdisplay,
> + crtc_state->dsc.slice_count);
> +
> + /*
> + * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the
> + * implementation specific physical rate buffer size. Currently we use
> + * the required rate buffer model size calculated in
> + * drm_dsc_compute_rc_parameters() according to VESA DSC Annex
> E.
> + *
> + * The VBT rc_buffer_block_size and rc_buffer_size definitions
> + * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC
> + * implementation should also use the DPCD (or perhaps VBT for
> eDP)
> + * provided value for the buffer size.
> + */
> +
> + /* FIXME: DSI spec says bpc + 1 for this one */
> + vdsc_cfg->line_buf_depth =
> +VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);
> +
> + vdsc_cfg->block_pred_enable = dsc->block_prediction_enable;
> +
> + vdsc_cfg->slice_height = dsc->slice_height; }
> +
> +/* FIXME: initially DSI specific */
> +bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state,
> + int dsc_max_bpc)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + const struct display_device_data *devdata;
> + const struct child_device_config *child;
> +
> + list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
> + child = &devdata->child;
> +
> + if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))
> + continue;
> +
> + if (child->dvo_port - DVO_PORT_MIPIA == encoder->port) {
> + if (!devdata->dsc)
> + return false;
> +
> + if (crtc_state)
> + fill_dsc(crtc_state, devdata->dsc,
> dsc_max_bpc);
> +
> + return true;
> + }
> + }
> +
> + return false;
> +}
> +
> /**
> * intel_bios_is_port_hpd_inverted - is HPD inverted for %port
> * @i915: i915 device instance
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.h
> b/drivers/gpu/drm/i915/display/intel_bios.h
> index 98f064828a57..d6a0c29d37ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.h
> +++ b/drivers/gpu/drm/i915/display/intel_bios.h
> @@ -35,6 +35,8 @@
> #include <drm/i915_drm.h>
>
> struct drm_i915_private;
> +struct intel_crtc_state;
> +struct intel_encoder;
> enum port;
>
> enum intel_backlight_type {
> @@ -242,5 +244,8 @@ bool intel_bios_is_port_hpd_inverted(const struct
> drm_i915_private *i915, bool intel_bios_is_lspcon_present(const struct
> drm_i915_private *i915,
> enum port port);
> enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
> enum port port);
> +bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state,
> + int dsc_max_bpc);
>
> #endif /* _INTEL_BIOS_H_ */
> --
> 2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v3 04/13] drm/i915/dsc: move DP specific compute params to intel_dp.c
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Turns out future DSI specific parameters aren't workable with the
approach of having the encoder specific functions in intel_vdsc.c. Make
intel_dsc_compute_params() a helper that does the encoder independent
parts, and have encoder code call it. Move intel_dsc_dp_compute_params()
to intel_dp.c as intel_dp_dsc_compute_params().
No functional changes.
v2: Rename pipe_config to crtc_state while at it.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 47 +++++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_vdsc.c | 48 +----------------------
2 files changed, 47 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3123958e2081..506c7d19968b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2046,6 +2046,51 @@ static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
return 0;
}
+#define DSC_SUPPORTED_VERSION_MIN 1
+
+static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+ struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+ u8 line_buf_depth;
+ int ret;
+
+ ret = intel_dsc_compute_params(encoder, crtc_state);
+ if (ret)
+ return ret;
+
+ vdsc_cfg->dsc_version_major =
+ (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
+ DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
+ vdsc_cfg->dsc_version_minor =
+ min(DSC_SUPPORTED_VERSION_MIN,
+ (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
+ DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
+
+ vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
+ DP_DSC_RGB;
+
+ line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
+ if (!line_buf_depth) {
+ DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
+ return -EINVAL;
+ }
+
+ if (vdsc_cfg->dsc_version_minor == 2)
+ vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
+ DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
+ else
+ vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
+ DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
+
+ vdsc_cfg->block_pred_enable =
+ intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
+ DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
+
+ return drm_dsc_compute_rc_parameters(vdsc_cfg);
+}
+
static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -2132,7 +2177,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
}
}
- ret = intel_dsc_compute_params(&dig_port->base, pipe_config);
+ ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
if (ret < 0) {
DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
"Compressed BPP = %d\n",
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index b23ba8d108db..834d665a47d2 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -30,8 +30,6 @@ enum COLUMN_INDEX_BPC {
MAX_COLUMN_INDEX
};
-#define DSC_SUPPORTED_VERSION_MIN 1
-
/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
static const u16 rc_buf_thresh[] = {
896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
@@ -335,45 +333,6 @@ static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
return &rc_parameters[row_index][column_index];
}
-/* Values filled from DSC Sink DPCD */
-static int intel_dsc_dp_compute_params(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config)
-{
- struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
- struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
- u8 line_buf_depth;
-
- vdsc_cfg->dsc_version_major =
- (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
- DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
- vdsc_cfg->dsc_version_minor =
- min(DSC_SUPPORTED_VERSION_MIN,
- (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
- DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
-
- vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
- DP_DSC_RGB;
-
- line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
- if (!line_buf_depth) {
- DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
- return -EINVAL;
- }
-
- if (vdsc_cfg->dsc_version_minor == 2)
- vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
- DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
- else
- vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
- DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
-
- vdsc_cfg->block_pred_enable =
- intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
- DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
-
- return 0;
-}
-
int intel_dsc_compute_params(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -381,7 +340,6 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
const struct rc_parameters *rc_params;
u8 i = 0;
- int ret;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
@@ -470,11 +428,7 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
- ret = intel_dsc_dp_compute_params(encoder, pipe_config);
- if (ret)
- return ret;
-
- return drm_dsc_compute_rc_parameters(vdsc_cfg);
+ return 0;
}
enum intel_display_power_domain
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH v3 04/13] drm/i915/dsc: move DP specific compute params to intel_dp.c
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Turns out future DSI specific parameters aren't workable with the
approach of having the encoder specific functions in intel_vdsc.c. Make
intel_dsc_compute_params() a helper that does the encoder independent
parts, and have encoder code call it. Move intel_dsc_dp_compute_params()
to intel_dp.c as intel_dp_dsc_compute_params().
No functional changes.
v2: Rename pipe_config to crtc_state while at it.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 47 +++++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_vdsc.c | 48 +----------------------
2 files changed, 47 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3123958e2081..506c7d19968b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2046,6 +2046,51 @@ static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
return 0;
}
+#define DSC_SUPPORTED_VERSION_MIN 1
+
+static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+ struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+ u8 line_buf_depth;
+ int ret;
+
+ ret = intel_dsc_compute_params(encoder, crtc_state);
+ if (ret)
+ return ret;
+
+ vdsc_cfg->dsc_version_major =
+ (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
+ DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
+ vdsc_cfg->dsc_version_minor =
+ min(DSC_SUPPORTED_VERSION_MIN,
+ (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
+ DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
+
+ vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
+ DP_DSC_RGB;
+
+ line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
+ if (!line_buf_depth) {
+ DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
+ return -EINVAL;
+ }
+
+ if (vdsc_cfg->dsc_version_minor == 2)
+ vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
+ DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
+ else
+ vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
+ DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
+
+ vdsc_cfg->block_pred_enable =
+ intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
+ DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
+
+ return drm_dsc_compute_rc_parameters(vdsc_cfg);
+}
+
static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -2132,7 +2177,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
}
}
- ret = intel_dsc_compute_params(&dig_port->base, pipe_config);
+ ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
if (ret < 0) {
DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
"Compressed BPP = %d\n",
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index b23ba8d108db..834d665a47d2 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -30,8 +30,6 @@ enum COLUMN_INDEX_BPC {
MAX_COLUMN_INDEX
};
-#define DSC_SUPPORTED_VERSION_MIN 1
-
/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
static const u16 rc_buf_thresh[] = {
896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
@@ -335,45 +333,6 @@ static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
return &rc_parameters[row_index][column_index];
}
-/* Values filled from DSC Sink DPCD */
-static int intel_dsc_dp_compute_params(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config)
-{
- struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
- struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
- u8 line_buf_depth;
-
- vdsc_cfg->dsc_version_major =
- (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
- DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
- vdsc_cfg->dsc_version_minor =
- min(DSC_SUPPORTED_VERSION_MIN,
- (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
- DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
-
- vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
- DP_DSC_RGB;
-
- line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
- if (!line_buf_depth) {
- DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
- return -EINVAL;
- }
-
- if (vdsc_cfg->dsc_version_minor == 2)
- vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
- DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
- else
- vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
- DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
-
- vdsc_cfg->block_pred_enable =
- intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
- DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
-
- return 0;
-}
-
int intel_dsc_compute_params(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -381,7 +340,6 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
const struct rc_parameters *rc_params;
u8 i = 0;
- int ret;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
@@ -470,11 +428,7 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
- ret = intel_dsc_dp_compute_params(encoder, pipe_config);
- if (ret)
- return ret;
-
- return drm_dsc_compute_rc_parameters(vdsc_cfg);
+ return 0;
}
enum intel_display_power_domain
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH v3 04/13] drm/i915/dsc: move DP specific compute params to intel_dp.c
2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula
(?)
@ 2019-12-05 5:07 ` Kulkarni, Vandita
-1 siblings, 0 replies; 56+ messages in thread
From: Kulkarni, Vandita @ 2019-12-05 5:07 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Tuesday, November 26, 2019 7:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Navare, Manasi D
> <manasi.d.navare@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: [PATCH v3 04/13] drm/i915/dsc: move DP specific compute params
> to intel_dp.c
>
> Turns out future DSI specific parameters aren't workable with the approach
> of having the encoder specific functions in intel_vdsc.c. Make
> intel_dsc_compute_params() a helper that does the encoder independent
> parts, and have encoder code call it. Move intel_dsc_dp_compute_params()
> to intel_dp.c as intel_dp_dsc_compute_params().
>
> No functional changes.
>
> v2: Rename pipe_config to crtc_state while at it.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Thanks,
Vandita
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 47 +++++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_vdsc.c | 48 +----------------------
> 2 files changed, 47 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 3123958e2081..506c7d19968b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2046,6 +2046,51 @@ static int intel_dp_dsc_compute_bpp(struct
> intel_dp *intel_dp, u8 dsc_max_bpc)
> return 0;
> }
>
> +#define DSC_SUPPORTED_VERSION_MIN 1
> +
> +static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> + struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> + u8 line_buf_depth;
> + int ret;
> +
> + ret = intel_dsc_compute_params(encoder, crtc_state);
> + if (ret)
> + return ret;
> +
> + vdsc_cfg->dsc_version_major =
> + (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
> + DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
> + vdsc_cfg->dsc_version_minor =
> + min(DSC_SUPPORTED_VERSION_MIN,
> + (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
> + DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
> +
> + vdsc_cfg->convert_rgb = intel_dp-
> >dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
> + DP_DSC_RGB;
> +
> + line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp-
> >dsc_dpcd);
> + if (!line_buf_depth) {
> + DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
> + return -EINVAL;
> + }
> +
> + if (vdsc_cfg->dsc_version_minor == 2)
> + vdsc_cfg->line_buf_depth = (line_buf_depth ==
> DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
> + DSC_1_2_MAX_LINEBUF_DEPTH_VAL :
> line_buf_depth;
> + else
> + vdsc_cfg->line_buf_depth = (line_buf_depth >
> DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
> + DSC_1_1_MAX_LINEBUF_DEPTH_BITS :
> line_buf_depth;
> +
> + vdsc_cfg->block_pred_enable =
> + intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT -
> DP_DSC_SUPPORT] &
> + DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
> +
> + return drm_dsc_compute_rc_parameters(vdsc_cfg);
> +}
> +
> static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *pipe_config,
> struct drm_connector_state *conn_state,
> @@ -2132,7 +2177,7 @@ static int intel_dp_dsc_compute_config(struct
> intel_dp *intel_dp,
> }
> }
>
> - ret = intel_dsc_compute_params(&dig_port->base, pipe_config);
> + ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
> if (ret < 0) {
> DRM_DEBUG_KMS("Cannot compute valid DSC parameters
> for Input Bpp = %d "
> "Compressed BPP = %d\n",
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index b23ba8d108db..834d665a47d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -30,8 +30,6 @@ enum COLUMN_INDEX_BPC {
> MAX_COLUMN_INDEX
> };
>
> -#define DSC_SUPPORTED_VERSION_MIN 1
> -
> /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically
> constant */ static const u16 rc_buf_thresh[] = {
> 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, @@ -
> 335,45 +333,6 @@ static const struct rc_parameters *get_rc_params(u16
> compressed_bpp,
> return &rc_parameters[row_index][column_index];
> }
>
> -/* Values filled from DSC Sink DPCD */
> -static int intel_dsc_dp_compute_params(struct intel_encoder *encoder,
> - struct intel_crtc_state *pipe_config)
> -{
> - struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> - struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
> - u8 line_buf_depth;
> -
> - vdsc_cfg->dsc_version_major =
> - (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
> - DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
> - vdsc_cfg->dsc_version_minor =
> - min(DSC_SUPPORTED_VERSION_MIN,
> - (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
> - DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
> -
> - vdsc_cfg->convert_rgb = intel_dp-
> >dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
> - DP_DSC_RGB;
> -
> - line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp-
> >dsc_dpcd);
> - if (!line_buf_depth) {
> - DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
> - return -EINVAL;
> - }
> -
> - if (vdsc_cfg->dsc_version_minor == 2)
> - vdsc_cfg->line_buf_depth = (line_buf_depth ==
> DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
> - DSC_1_2_MAX_LINEBUF_DEPTH_VAL :
> line_buf_depth;
> - else
> - vdsc_cfg->line_buf_depth = (line_buf_depth >
> DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
> - DSC_1_1_MAX_LINEBUF_DEPTH_BITS :
> line_buf_depth;
> -
> - vdsc_cfg->block_pred_enable =
> - intel_dp-
> >dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
> - DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
> -
> - return 0;
> -}
> -
> int intel_dsc_compute_params(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config) { @@ -381,7
> +340,6 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
> u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
> const struct rc_parameters *rc_params;
> u8 i = 0;
> - int ret;
>
> vdsc_cfg->pic_width = pipe_config-
> >hw.adjusted_mode.crtc_hdisplay;
> vdsc_cfg->pic_height = pipe_config-
> >hw.adjusted_mode.crtc_vdisplay;
> @@ -470,11 +428,7 @@ int intel_dsc_compute_params(struct intel_encoder
> *encoder,
> vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
> (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
>
> - ret = intel_dsc_dp_compute_params(encoder, pipe_config);
> - if (ret)
> - return ret;
> -
> - return drm_dsc_compute_rc_parameters(vdsc_cfg);
> + return 0;
> }
>
> enum intel_display_power_domain
> --
> 2.20.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v3 05/13] drm/i915/dsc: move slice height calculation to encoder
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Turns out this isn't compatible with DSI, where we use the value from
VBT. No functional changes.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 11 -----------
2 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 506c7d19968b..1199391331c2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2060,6 +2060,18 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
if (ret)
return ret;
+ /*
+ * Slice Height of 8 works for all currently available panels. So start
+ * with that if pic_height is an integral multiple of 8. Eventually add
+ * logic to try multiple slice heights.
+ */
+ if (vdsc_cfg->pic_height % 8 == 0)
+ vdsc_cfg->slice_height = 8;
+ else if (vdsc_cfg->pic_height % 4 == 0)
+ vdsc_cfg->slice_height = 4;
+ else
+ vdsc_cfg->slice_height = 2;
+
vdsc_cfg->dsc_version_major =
(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 834d665a47d2..c53024dfb1ec 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -345,17 +345,6 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
pipe_config->dsc.slice_count);
- /*
- * Slice Height of 8 works for all currently available panels. So start
- * with that if pic_height is an integral multiple of 8.
- * Eventually add logic to try multiple slice heights.
- */
- if (vdsc_cfg->pic_height % 8 == 0)
- vdsc_cfg->slice_height = 8;
- else if (vdsc_cfg->pic_height % 4 == 0)
- vdsc_cfg->slice_height = 4;
- else
- vdsc_cfg->slice_height = 2;
/* Gen 11 does not support YCbCr */
vdsc_cfg->simple_422 = false;
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Intel-gfx] [PATCH v3 05/13] drm/i915/dsc: move slice height calculation to encoder
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Turns out this isn't compatible with DSI, where we use the value from
VBT. No functional changes.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 11 -----------
2 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 506c7d19968b..1199391331c2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2060,6 +2060,18 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
if (ret)
return ret;
+ /*
+ * Slice Height of 8 works for all currently available panels. So start
+ * with that if pic_height is an integral multiple of 8. Eventually add
+ * logic to try multiple slice heights.
+ */
+ if (vdsc_cfg->pic_height % 8 == 0)
+ vdsc_cfg->slice_height = 8;
+ else if (vdsc_cfg->pic_height % 4 == 0)
+ vdsc_cfg->slice_height = 4;
+ else
+ vdsc_cfg->slice_height = 2;
+
vdsc_cfg->dsc_version_major =
(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 834d665a47d2..c53024dfb1ec 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -345,17 +345,6 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
pipe_config->dsc.slice_count);
- /*
- * Slice Height of 8 works for all currently available panels. So start
- * with that if pic_height is an integral multiple of 8.
- * Eventually add logic to try multiple slice heights.
- */
- if (vdsc_cfg->pic_height % 8 == 0)
- vdsc_cfg->slice_height = 8;
- else if (vdsc_cfg->pic_height % 4 == 0)
- vdsc_cfg->slice_height = 4;
- else
- vdsc_cfg->slice_height = 2;
/* Gen 11 does not support YCbCr */
vdsc_cfg->simple_422 = false;
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread
* Re: [Intel-gfx] [PATCH v3 05/13] drm/i915/dsc: move slice height calculation to encoder
2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula
(?)
@ 2019-12-05 5:28 ` Kulkarni, Vandita
-1 siblings, 0 replies; 56+ messages in thread
From: Kulkarni, Vandita @ 2019-12-05 5:28 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Tuesday, November 26, 2019 7:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Navare, Manasi D
> <manasi.d.navare@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: [PATCH v3 05/13] drm/i915/dsc: move slice height calculation to
> encoder
>
> Turns out this isn't compatible with DSI, where we use the value from VBT.
> No functional changes.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Thanks,
Vandita
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++++++++
> drivers/gpu/drm/i915/display/intel_vdsc.c | 11 -----------
> 2 files changed, 12 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 506c7d19968b..1199391331c2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2060,6 +2060,18 @@ static int intel_dp_dsc_compute_params(struct
> intel_encoder *encoder,
> if (ret)
> return ret;
>
> + /*
> + * Slice Height of 8 works for all currently available panels. So start
> + * with that if pic_height is an integral multiple of 8. Eventually add
> + * logic to try multiple slice heights.
> + */
> + if (vdsc_cfg->pic_height % 8 == 0)
> + vdsc_cfg->slice_height = 8;
> + else if (vdsc_cfg->pic_height % 4 == 0)
> + vdsc_cfg->slice_height = 4;
> + else
> + vdsc_cfg->slice_height = 2;
> +
> vdsc_cfg->dsc_version_major =
> (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
> DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; diff --git
> a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 834d665a47d2..c53024dfb1ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -345,17 +345,6 @@ int intel_dsc_compute_params(struct intel_encoder
> *encoder,
> vdsc_cfg->pic_height = pipe_config-
> >hw.adjusted_mode.crtc_vdisplay;
> vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
> pipe_config->dsc.slice_count);
> - /*
> - * Slice Height of 8 works for all currently available panels. So start
> - * with that if pic_height is an integral multiple of 8.
> - * Eventually add logic to try multiple slice heights.
> - */
> - if (vdsc_cfg->pic_height % 8 == 0)
> - vdsc_cfg->slice_height = 8;
> - else if (vdsc_cfg->pic_height % 4 == 0)
> - vdsc_cfg->slice_height = 4;
> - else
> - vdsc_cfg->slice_height = 2;
>
> /* Gen 11 does not support YCbCr */
> vdsc_cfg->simple_422 = false;
> --
> 2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v3 06/13] drm/i915/dsc: add support for computing and writing PPS for DSI encoders
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Add DSI specific computation and transmission to display of PPS.
With hopes that this approach will work for both DP and DSI encoders.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 25 ++++++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index c53024dfb1ec..7bd727129a8f 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -10,6 +10,7 @@
#include "i915_drv.h"
#include "intel_display_types.h"
+#include "intel_dsi.h"
#include "intel_vdsc.h"
enum ROW_INDEX_BPP {
@@ -844,6 +845,25 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
}
}
+static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct mipi_dsi_device *dsi;
+ struct drm_dsc_picture_parameter_set pps;
+ enum port port;
+
+ drm_dsc_pps_payload_pack(&pps, vdsc_cfg);
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi = intel_dsi->dsi_hosts[port]->device;
+
+ mipi_dsi_picture_parameter_set(dsi, &pps);
+ mipi_dsi_compression_mode(dsi, true);
+ }
+}
+
static void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -882,7 +902,10 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_dsc_pps_configure(encoder, crtc_state);
- intel_dsc_dp_pps_write(encoder, crtc_state);
+ if (encoder->type == INTEL_OUTPUT_DSI)
+ intel_dsc_dsi_pps_write(encoder, crtc_state);
+ else
+ intel_dsc_dp_pps_write(encoder, crtc_state);
if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
dss_ctl1_reg = DSS_CTL1;
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH v3 06/13] drm/i915/dsc: add support for computing and writing PPS for DSI encoders
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Add DSI specific computation and transmission to display of PPS.
With hopes that this approach will work for both DP and DSI encoders.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 25 ++++++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index c53024dfb1ec..7bd727129a8f 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -10,6 +10,7 @@
#include "i915_drv.h"
#include "intel_display_types.h"
+#include "intel_dsi.h"
#include "intel_vdsc.h"
enum ROW_INDEX_BPP {
@@ -844,6 +845,25 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
}
}
+static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct mipi_dsi_device *dsi;
+ struct drm_dsc_picture_parameter_set pps;
+ enum port port;
+
+ drm_dsc_pps_payload_pack(&pps, vdsc_cfg);
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi = intel_dsi->dsi_hosts[port]->device;
+
+ mipi_dsi_picture_parameter_set(dsi, &pps);
+ mipi_dsi_compression_mode(dsi, true);
+ }
+}
+
static void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -882,7 +902,10 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_dsc_pps_configure(encoder, crtc_state);
- intel_dsc_dp_pps_write(encoder, crtc_state);
+ if (encoder->type == INTEL_OUTPUT_DSI)
+ intel_dsc_dsi_pps_write(encoder, crtc_state);
+ else
+ intel_dsc_dp_pps_write(encoder, crtc_state);
if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
dss_ctl1_reg = DSS_CTL1;
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH v3 06/13] drm/i915/dsc: add support for computing and writing PPS for DSI encoders
2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula
(?)
@ 2019-12-05 5:44 ` Kulkarni, Vandita
2019-12-09 15:43 ` Jani Nikula
-1 siblings, 1 reply; 56+ messages in thread
From: Kulkarni, Vandita @ 2019-12-05 5:44 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Tuesday, November 26, 2019 7:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Navare, Manasi D
> <manasi.d.navare@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: [PATCH v3 06/13] drm/i915/dsc: add support for computing and
> writing PPS for DSI encoders
>
> Add DSI specific computation and transmission to display of PPS.
>
> With hopes that this approach will work for both DP and DSI encoders.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 25 ++++++++++++++++++++++-
> 1 file changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index c53024dfb1ec..7bd727129a8f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -10,6 +10,7 @@
>
> #include "i915_drv.h"
> #include "intel_display_types.h"
> +#include "intel_dsi.h"
> #include "intel_vdsc.h"
>
> enum ROW_INDEX_BPP {
> @@ -844,6 +845,25 @@ static void intel_dsc_pps_configure(struct
> intel_encoder *encoder,
> }
> }
>
> +static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state) {
> + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + struct mipi_dsi_device *dsi;
> + struct drm_dsc_picture_parameter_set pps;
> + enum port port;
> +
> + drm_dsc_pps_payload_pack(&pps, vdsc_cfg);
> +
> + for_each_dsi_port(port, intel_dsi->ports) {
> + dsi = intel_dsi->dsi_hosts[port]->device;
> +
> + mipi_dsi_picture_parameter_set(dsi, &pps);
> + mipi_dsi_compression_mode(dsi, true);
> + }
> +}
> +
> static void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state) {
> @@ -882,7 +902,10 @@ void intel_dsc_enable(struct intel_encoder
> *encoder,
>
Slightly out of scope of this patch, but I see that while configuring PPS9, we are using direct macros and not using anything from
vdsc_cfg->rc_model_size and we have not initialized vdsc_cfg-> rc_edge_factor
> intel_dsc_pps_configure(encoder, crtc_state);
>
Other than that, this patch LGTM.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Thanks,
Vandita
> - intel_dsc_dp_pps_write(encoder, crtc_state);
> + if (encoder->type == INTEL_OUTPUT_DSI)
> + intel_dsc_dsi_pps_write(encoder, crtc_state);
> + else
> + intel_dsc_dp_pps_write(encoder, crtc_state);
>
> if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
> dss_ctl1_reg = DSS_CTL1;
> --
> 2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH v3 06/13] drm/i915/dsc: add support for computing and writing PPS for DSI encoders
2019-12-05 5:44 ` Kulkarni, Vandita
@ 2019-12-09 15:43 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-12-09 15:43 UTC (permalink / raw)
To: Kulkarni, Vandita, intel-gfx
On Thu, 05 Dec 2019, "Kulkarni, Vandita" <vandita.kulkarni@intel.com> wrote:
>> -----Original Message-----
>> From: Jani Nikula <jani.nikula@intel.com>
>> Sent: Tuesday, November 26, 2019 7:13 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; Navare, Manasi D
>> <manasi.d.navare@intel.com>; Kulkarni, Vandita
>> <vandita.kulkarni@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Subject: [PATCH v3 06/13] drm/i915/dsc: add support for computing and
>> writing PPS for DSI encoders
>>
>> Add DSI specific computation and transmission to display of PPS.
>>
>> With hopes that this approach will work for both DP and DSI encoders.
>>
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_vdsc.c | 25 ++++++++++++++++++++++-
>> 1 file changed, 24 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index c53024dfb1ec..7bd727129a8f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -10,6 +10,7 @@
>>
>> #include "i915_drv.h"
>> #include "intel_display_types.h"
>> +#include "intel_dsi.h"
>> #include "intel_vdsc.h"
>>
>> enum ROW_INDEX_BPP {
>> @@ -844,6 +845,25 @@ static void intel_dsc_pps_configure(struct
>> intel_encoder *encoder,
>> }
>> }
>>
>> +static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
>> + const struct intel_crtc_state *crtc_state) {
>> + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> + struct mipi_dsi_device *dsi;
>> + struct drm_dsc_picture_parameter_set pps;
>> + enum port port;
>> +
>> + drm_dsc_pps_payload_pack(&pps, vdsc_cfg);
>> +
>> + for_each_dsi_port(port, intel_dsi->ports) {
>> + dsi = intel_dsi->dsi_hosts[port]->device;
>> +
>> + mipi_dsi_picture_parameter_set(dsi, &pps);
>> + mipi_dsi_compression_mode(dsi, true);
>> + }
>> +}
>> +
>> static void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
>> const struct intel_crtc_state *crtc_state) {
>> @@ -882,7 +902,10 @@ void intel_dsc_enable(struct intel_encoder
>> *encoder,
>>
> Slightly out of scope of this patch, but I see that while configuring PPS9, we are using direct macros and not using anything from
> vdsc_cfg->rc_model_size and we have not initialized vdsc_cfg-> rc_edge_factor
As mentioned on IRC, we'll need to fix this also for DP I think, and
that's indeed slightly out of scope here.
BR,
Jani.
>
>> intel_dsc_pps_configure(encoder, crtc_state);
>>
> Other than that, this patch LGTM.
> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>
> Thanks,
> Vandita
>> - intel_dsc_dp_pps_write(encoder, crtc_state);
>> + if (encoder->type == INTEL_OUTPUT_DSI)
>> + intel_dsc_dsi_pps_write(encoder, crtc_state);
>> + else
>> + intel_dsc_dp_pps_write(encoder, crtc_state);
>>
>> if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
>> dss_ctl1_reg = DSS_CTL1;
>> --
>> 2.20.1
>
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v3 07/13] drm/i915/dsi: set pipe_bpp on ICL configure config
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
The ICL DSI pipe_bpp currently comes from
compute_baseline_pipe_bpp(). Fix it.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index f688207932e0..ef53ed6d3ecf 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1286,6 +1286,11 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
else
pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
+ if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
+ pipe_config->pipe_bpp = 24;
+ else
+ pipe_config->pipe_bpp = 18;
+
pipe_config->clock_set = true;
pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [Intel-gfx] [PATCH v3 07/13] drm/i915/dsi: set pipe_bpp on ICL configure config
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
The ICL DSI pipe_bpp currently comes from
compute_baseline_pipe_bpp(). Fix it.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index f688207932e0..ef53ed6d3ecf 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1286,6 +1286,11 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
else
pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
+ if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
+ pipe_config->pipe_bpp = 24;
+ else
+ pipe_config->pipe_bpp = 18;
+
pipe_config->clock_set = true;
pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread
* Re: [Intel-gfx] [PATCH v3 07/13] drm/i915/dsi: set pipe_bpp on ICL configure config
2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula
(?)
@ 2019-12-05 10:15 ` Kulkarni, Vandita
2019-12-09 15:46 ` Jani Nikula
-1 siblings, 1 reply; 56+ messages in thread
From: Kulkarni, Vandita @ 2019-12-05 10:15 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Tuesday, November 26, 2019 7:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: [PATCH v3 07/13] drm/i915/dsi: set pipe_bpp on ICL configure config
>
> The ICL DSI pipe_bpp currently comes from compute_baseline_pipe_bpp().
> Fix it.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index f688207932e0..ef53ed6d3ecf 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1286,6 +1286,11 @@ static int gen11_dsi_compute_config(struct
> intel_encoder *encoder,
> else
> pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
>
Can we use mipi_dsi_pixel_format_to_bpp?
> + if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
> + pipe_config->pipe_bpp = 24;
> + else
> + pipe_config->pipe_bpp = 18;
> +
Otherwise LGTM.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Thanks,
Vandita
> pipe_config->clock_set = true;
> pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
>
> --
> 2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [Intel-gfx] [PATCH v3 07/13] drm/i915/dsi: set pipe_bpp on ICL configure config
2019-12-05 10:15 ` Kulkarni, Vandita
@ 2019-12-09 15:46 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-12-09 15:46 UTC (permalink / raw)
To: Kulkarni, Vandita, intel-gfx
On Thu, 05 Dec 2019, "Kulkarni, Vandita" <vandita.kulkarni@intel.com> wrote:
>> -----Original Message-----
>> From: Jani Nikula <jani.nikula@intel.com>
>> Sent: Tuesday, November 26, 2019 7:13 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; Kulkarni, Vandita
>> <vandita.kulkarni@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Subject: [PATCH v3 07/13] drm/i915/dsi: set pipe_bpp on ICL configure config
>>
>> The ICL DSI pipe_bpp currently comes from compute_baseline_pipe_bpp().
>> Fix it.
>>
>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/icl_dsi.c | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
>> b/drivers/gpu/drm/i915/display/icl_dsi.c
>> index f688207932e0..ef53ed6d3ecf 100644
>> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> @@ -1286,6 +1286,11 @@ static int gen11_dsi_compute_config(struct
>> intel_encoder *encoder,
>> else
>> pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
>>
>
> Can we use mipi_dsi_pixel_format_to_bpp?
No, this is for the pipe which is different from what goes on the DSI.
BR,
Jani.
>
>> + if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
>> + pipe_config->pipe_bpp = 24;
>> + else
>> + pipe_config->pipe_bpp = 18;
>> +
> Otherwise LGTM.
> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>
> Thanks,
> Vandita
>> pipe_config->clock_set = true;
>> pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
>>
>> --
>> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v3 08/13] drm/i915/dsi: abstract afe_clk calculation
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
We'll make more use of it in the future.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index ef53ed6d3ecf..de3743233dcb 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -301,18 +301,26 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
I915_WRITE(DSS_CTL1, dss_ctl1);
}
+/* aka DSI 8X clock */
+static int afe_clk(struct intel_encoder *encoder)
+{
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ int bpp;
+
+ bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+
+ return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
+}
+
static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
enum port port;
- u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
- u32 afe_clk_khz; /* 8X Clock */
+ int afe_clk_khz;
u32 esc_clk_div_m;
- afe_clk_khz = DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp,
- intel_dsi->lane_count);
-
+ afe_clk_khz = afe_clk(encoder);
esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
for_each_dsi_port(port, intel_dsi->ports) {
--
2.20.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH v3 08/13] drm/i915/dsi: abstract afe_clk calculation
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
We'll make more use of it in the future.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index ef53ed6d3ecf..de3743233dcb 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -301,18 +301,26 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
I915_WRITE(DSS_CTL1, dss_ctl1);
}
+/* aka DSI 8X clock */
+static int afe_clk(struct intel_encoder *encoder)
+{
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ int bpp;
+
+ bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+
+ return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
+}
+
static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
enum port port;
- u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
- u32 afe_clk_khz; /* 8X Clock */
+ int afe_clk_khz;
u32 esc_clk_div_m;
- afe_clk_khz = DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp,
- intel_dsi->lane_count);
-
+ afe_clk_khz = afe_clk(encoder);
esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
for_each_dsi_port(port, intel_dsi->ports) {
--
2.20.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH v3 08/13] drm/i915/dsi: abstract afe_clk calculation
2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula
(?)
@ 2019-12-05 8:25 ` Kulkarni, Vandita
-1 siblings, 0 replies; 56+ messages in thread
From: Kulkarni, Vandita @ 2019-12-05 8:25 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Tuesday, November 26, 2019 7:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: [PATCH v3 08/13] drm/i915/dsi: abstract afe_clk calculation
>
> We'll make more use of it in the future.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Thanks,
Vandita
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 18 +++++++++++++-----
> 1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index ef53ed6d3ecf..de3743233dcb 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -301,18 +301,26 @@ static void configure_dual_link_mode(struct
> intel_encoder *encoder,
> I915_WRITE(DSS_CTL1, dss_ctl1);
> }
>
> +/* aka DSI 8X clock */
> +static int afe_clk(struct intel_encoder *encoder) {
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + int bpp;
> +
> + bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
> +
> + return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp,
> +intel_dsi->lane_count); }
> +
> static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder) {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> enum port port;
> - u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
> - u32 afe_clk_khz; /* 8X Clock */
> + int afe_clk_khz;
> u32 esc_clk_div_m;
>
> - afe_clk_khz = DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp,
> - intel_dsi->lane_count);
> -
> + afe_clk_khz = afe_clk(encoder);
> esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
>
> for_each_dsi_port(port, intel_dsi->ports) {
> --
> 2.20.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v3 09/13] drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
We'll be expanding afe_clk() to take DSC into account. Switch to using
it where DSC matters. Which is really everywhere that
intel_dsi_bitrate() is currently used in ICL DSI code.
The functional difference is that we round the result closest instead of
down.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index de3743233dcb..d576f29cef75 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -539,7 +539,7 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
* leave all fields at HW default values.
*/
if (IS_GEN(dev_priv, 11)) {
- if (intel_dsi_bitrate(intel_dsi) <= 800000) {
+ if (afe_clk(encoder) <= 800000) {
for_each_dsi_port(port, intel_dsi->ports) {
tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
tmp &= ~TA_SURE_MASK;
@@ -649,7 +649,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
tmp |= EOTP_DISABLED;
/* enable link calibration if freq > 1.5Gbps */
- if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
+ if (afe_clk(encoder) >= 1500 * 1000) {
tmp &= ~LINK_CALIBRATION_MASK;
tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
}
@@ -930,7 +930,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
* TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
* ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
*/
- divisor = intel_dsi_tlpx_ns(intel_dsi) * intel_dsi_bitrate(intel_dsi) * 1000;
+ divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder) * 1000;
mul = 8 * 1000000;
hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
divisor);
@@ -1300,7 +1300,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
pipe_config->pipe_bpp = 18;
pipe_config->clock_set = true;
- pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
+ pipe_config->port_clock = afe_clk(encoder) / 5;
return 0;
}
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH v3 09/13] drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
We'll be expanding afe_clk() to take DSC into account. Switch to using
it where DSC matters. Which is really everywhere that
intel_dsi_bitrate() is currently used in ICL DSI code.
The functional difference is that we round the result closest instead of
down.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index de3743233dcb..d576f29cef75 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -539,7 +539,7 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
* leave all fields at HW default values.
*/
if (IS_GEN(dev_priv, 11)) {
- if (intel_dsi_bitrate(intel_dsi) <= 800000) {
+ if (afe_clk(encoder) <= 800000) {
for_each_dsi_port(port, intel_dsi->ports) {
tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
tmp &= ~TA_SURE_MASK;
@@ -649,7 +649,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
tmp |= EOTP_DISABLED;
/* enable link calibration if freq > 1.5Gbps */
- if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
+ if (afe_clk(encoder) >= 1500 * 1000) {
tmp &= ~LINK_CALIBRATION_MASK;
tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
}
@@ -930,7 +930,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
* TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
* ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
*/
- divisor = intel_dsi_tlpx_ns(intel_dsi) * intel_dsi_bitrate(intel_dsi) * 1000;
+ divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder) * 1000;
mul = 8 * 1000000;
hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
divisor);
@@ -1300,7 +1300,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
pipe_config->pipe_bpp = 18;
pipe_config->clock_set = true;
- pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
+ pipe_config->port_clock = afe_clk(encoder) / 5;
return 0;
}
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH v3 09/13] drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula
(?)
@ 2019-12-05 13:06 ` Kulkarni, Vandita
-1 siblings, 0 replies; 56+ messages in thread
From: Kulkarni, Vandita @ 2019-12-05 13:06 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Tuesday, November 26, 2019 7:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: [PATCH v3 09/13] drm/i915/dsi: use afe_clk() instead of
> intel_dsi_bitrate()
>
> We'll be expanding afe_clk() to take DSC into account. Switch to using it
> where DSC matters. Which is really everywhere that
> intel_dsi_bitrate() is currently used in ICL DSI code.
>
> The functional difference is that we round the result closest instead of
> down.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Regards,
Vandita
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index de3743233dcb..d576f29cef75 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -539,7 +539,7 @@ static void gen11_dsi_setup_dphy_timings(struct
> intel_encoder *encoder)
> * leave all fields at HW default values.
> */
> if (IS_GEN(dev_priv, 11)) {
> - if (intel_dsi_bitrate(intel_dsi) <= 800000) {
> + if (afe_clk(encoder) <= 800000) {
> for_each_dsi_port(port, intel_dsi->ports) {
> tmp =
> I915_READ(DPHY_TA_TIMING_PARAM(port));
> tmp &= ~TA_SURE_MASK;
> @@ -649,7 +649,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder
> *encoder,
> tmp |= EOTP_DISABLED;
>
> /* enable link calibration if freq > 1.5Gbps */
> - if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
> + if (afe_clk(encoder) >= 1500 * 1000) {
> tmp &= ~LINK_CALIBRATION_MASK;
> tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
> }
> @@ -930,7 +930,7 @@ static void gen11_dsi_setup_timeouts(struct
> intel_encoder *encoder)
> * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
> * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
> */
> - divisor = intel_dsi_tlpx_ns(intel_dsi) * intel_dsi_bitrate(intel_dsi) *
> 1000;
> + divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder) * 1000;
> mul = 8 * 1000000;
> hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
> divisor);
> @@ -1300,7 +1300,7 @@ static int gen11_dsi_compute_config(struct
> intel_encoder *encoder,
> pipe_config->pipe_bpp = 18;
>
> pipe_config->clock_set = true;
> - pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
> + pipe_config->port_clock = afe_clk(encoder) / 5;
>
> return 0;
> }
> --
> 2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v3 10/13] drm/i915/dsi: take compression into account in afe_clk()
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Pass crtc_state to afe_clk() to be able to take compression into account
in the computation. Once we enable compression, that is.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 40 +++++++++++++++-----------
1 file changed, 24 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index d576f29cef75..5149a28a874b 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -302,17 +302,22 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
}
/* aka DSI 8X clock */
-static int afe_clk(struct intel_encoder *encoder)
+static int afe_clk(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
int bpp;
- bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+ if (crtc_state->dsc.compression_enable)
+ bpp = crtc_state->dsc.compressed_bpp;
+ else
+ bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
}
-static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
+static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -320,7 +325,7 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
int afe_clk_khz;
u32 esc_clk_div_m;
- afe_clk_khz = afe_clk(encoder);
+ afe_clk_khz = afe_clk(encoder, crtc_state);
esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
for_each_dsi_port(port, intel_dsi->ports) {
@@ -498,7 +503,9 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
}
}
-static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
+static void
+gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -539,7 +546,7 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
* leave all fields at HW default values.
*/
if (IS_GEN(dev_priv, 11)) {
- if (afe_clk(encoder) <= 800000) {
+ if (afe_clk(encoder, crtc_state) <= 800000) {
for_each_dsi_port(port, intel_dsi->ports) {
tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
tmp &= ~TA_SURE_MASK;
@@ -649,7 +656,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
tmp |= EOTP_DISABLED;
/* enable link calibration if freq > 1.5Gbps */
- if (afe_clk(encoder) >= 1500 * 1000) {
+ if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
tmp &= ~LINK_CALIBRATION_MASK;
tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
}
@@ -915,7 +922,8 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
}
}
-static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
+static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -930,7 +938,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
* TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
* ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
*/
- divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder) * 1000;
+ divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000;
mul = 8 * 1000000;
hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
divisor);
@@ -966,7 +974,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
static void
gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
- const struct intel_crtc_state *pipe_config)
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -983,13 +991,13 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
gen11_dsi_enable_ddi_buffer(encoder);
/* setup D-PHY timings */
- gen11_dsi_setup_dphy_timings(encoder);
+ gen11_dsi_setup_dphy_timings(encoder, crtc_state);
/* step 4h: setup DSI protocol timeouts */
- gen11_dsi_setup_timeouts(encoder);
+ gen11_dsi_setup_timeouts(encoder, crtc_state);
/* Step (4h, 4i, 4j, 4k): Configure transcoder */
- gen11_dsi_configure_transcoder(encoder, pipe_config);
+ gen11_dsi_configure_transcoder(encoder, crtc_state);
/* Step 4l: Gate DDI clocks */
if (IS_GEN(dev_priv, 11))
@@ -1036,14 +1044,14 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
}
static void gen11_dsi_pre_pll_enable(struct intel_encoder *encoder,
- const struct intel_crtc_state *pipe_config,
+ const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
/* step2: enable IO power */
gen11_dsi_enable_io_power(encoder);
/* step3: enable DSI PLL */
- gen11_dsi_program_esc_clk_div(encoder);
+ gen11_dsi_program_esc_clk_div(encoder, crtc_state);
}
static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
@@ -1300,7 +1308,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
pipe_config->pipe_bpp = 18;
pipe_config->clock_set = true;
- pipe_config->port_clock = afe_clk(encoder) / 5;
+ pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
return 0;
}
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH v3 10/13] drm/i915/dsi: take compression into account in afe_clk()
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Pass crtc_state to afe_clk() to be able to take compression into account
in the computation. Once we enable compression, that is.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 40 +++++++++++++++-----------
1 file changed, 24 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index d576f29cef75..5149a28a874b 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -302,17 +302,22 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
}
/* aka DSI 8X clock */
-static int afe_clk(struct intel_encoder *encoder)
+static int afe_clk(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
int bpp;
- bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+ if (crtc_state->dsc.compression_enable)
+ bpp = crtc_state->dsc.compressed_bpp;
+ else
+ bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
}
-static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
+static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -320,7 +325,7 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
int afe_clk_khz;
u32 esc_clk_div_m;
- afe_clk_khz = afe_clk(encoder);
+ afe_clk_khz = afe_clk(encoder, crtc_state);
esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
for_each_dsi_port(port, intel_dsi->ports) {
@@ -498,7 +503,9 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
}
}
-static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
+static void
+gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -539,7 +546,7 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
* leave all fields at HW default values.
*/
if (IS_GEN(dev_priv, 11)) {
- if (afe_clk(encoder) <= 800000) {
+ if (afe_clk(encoder, crtc_state) <= 800000) {
for_each_dsi_port(port, intel_dsi->ports) {
tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
tmp &= ~TA_SURE_MASK;
@@ -649,7 +656,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
tmp |= EOTP_DISABLED;
/* enable link calibration if freq > 1.5Gbps */
- if (afe_clk(encoder) >= 1500 * 1000) {
+ if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
tmp &= ~LINK_CALIBRATION_MASK;
tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
}
@@ -915,7 +922,8 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
}
}
-static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
+static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -930,7 +938,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
* TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
* ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
*/
- divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder) * 1000;
+ divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000;
mul = 8 * 1000000;
hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
divisor);
@@ -966,7 +974,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
static void
gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
- const struct intel_crtc_state *pipe_config)
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -983,13 +991,13 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
gen11_dsi_enable_ddi_buffer(encoder);
/* setup D-PHY timings */
- gen11_dsi_setup_dphy_timings(encoder);
+ gen11_dsi_setup_dphy_timings(encoder, crtc_state);
/* step 4h: setup DSI protocol timeouts */
- gen11_dsi_setup_timeouts(encoder);
+ gen11_dsi_setup_timeouts(encoder, crtc_state);
/* Step (4h, 4i, 4j, 4k): Configure transcoder */
- gen11_dsi_configure_transcoder(encoder, pipe_config);
+ gen11_dsi_configure_transcoder(encoder, crtc_state);
/* Step 4l: Gate DDI clocks */
if (IS_GEN(dev_priv, 11))
@@ -1036,14 +1044,14 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
}
static void gen11_dsi_pre_pll_enable(struct intel_encoder *encoder,
- const struct intel_crtc_state *pipe_config,
+ const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
/* step2: enable IO power */
gen11_dsi_enable_io_power(encoder);
/* step3: enable DSI PLL */
- gen11_dsi_program_esc_clk_div(encoder);
+ gen11_dsi_program_esc_clk_div(encoder, crtc_state);
}
static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
@@ -1300,7 +1308,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
pipe_config->pipe_bpp = 18;
pipe_config->clock_set = true;
- pipe_config->port_clock = afe_clk(encoder) / 5;
+ pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
return 0;
}
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH v3 10/13] drm/i915/dsi: take compression into account in afe_clk()
2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula
(?)
@ 2019-12-05 14:36 ` Kulkarni, Vandita
-1 siblings, 0 replies; 56+ messages in thread
From: Kulkarni, Vandita @ 2019-12-05 14:36 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Tuesday, November 26, 2019 7:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: [PATCH v3 10/13] drm/i915/dsi: take compression into account in
> afe_clk()
>
> Pass crtc_state to afe_clk() to be able to take compression into account in
> the computation. Once we enable compression, that is.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Regards,
Vandita
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 40 +++++++++++++++-----------
> 1 file changed, 24 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index d576f29cef75..5149a28a874b 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -302,17 +302,22 @@ static void configure_dual_link_mode(struct
> intel_encoder *encoder, }
>
> /* aka DSI 8X clock */
> -static int afe_clk(struct intel_encoder *encoder)
> +static int afe_clk(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> {
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> int bpp;
>
> - bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
> + if (crtc_state->dsc.compression_enable)
> + bpp = crtc_state->dsc.compressed_bpp;
> + else
> + bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> >pixel_format);
>
> return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi-
> >lane_count); }
>
> -static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
> +static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
> + const struct intel_crtc_state
> *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@ -
> 320,7 +325,7 @@ static void gen11_dsi_program_esc_clk_div(struct
> intel_encoder *encoder)
> int afe_clk_khz;
> u32 esc_clk_div_m;
>
> - afe_clk_khz = afe_clk(encoder);
> + afe_clk_khz = afe_clk(encoder, crtc_state);
> esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
>
> for_each_dsi_port(port, intel_dsi->ports) { @@ -498,7 +503,9 @@
> static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
> }
> }
>
> -static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
> +static void
> +gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@ -
> 539,7 +546,7 @@ static void gen11_dsi_setup_dphy_timings(struct
> intel_encoder *encoder)
> * leave all fields at HW default values.
> */
> if (IS_GEN(dev_priv, 11)) {
> - if (afe_clk(encoder) <= 800000) {
> + if (afe_clk(encoder, crtc_state) <= 800000) {
> for_each_dsi_port(port, intel_dsi->ports) {
> tmp =
> I915_READ(DPHY_TA_TIMING_PARAM(port));
> tmp &= ~TA_SURE_MASK;
> @@ -649,7 +656,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder
> *encoder,
> tmp |= EOTP_DISABLED;
>
> /* enable link calibration if freq > 1.5Gbps */
> - if (afe_clk(encoder) >= 1500 * 1000) {
> + if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
> tmp &= ~LINK_CALIBRATION_MASK;
> tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
> }
> @@ -915,7 +922,8 @@ static void gen11_dsi_enable_transcoder(struct
> intel_encoder *encoder)
> }
> }
>
> -static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
> +static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@ -
> 930,7 +938,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder
> *encoder)
> * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
> * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
> */
> - divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder) * 1000;
> + divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state)
> +* 1000;
> mul = 8 * 1000000;
> hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
> divisor);
> @@ -966,7 +974,7 @@ static void gen11_dsi_setup_timeouts(struct
> intel_encoder *encoder)
>
> static void
> gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> - const struct intel_crtc_state *pipe_config)
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> @@ -983,13 +991,13 @@ gen11_dsi_enable_port_and_phy(struct
> intel_encoder *encoder,
> gen11_dsi_enable_ddi_buffer(encoder);
>
> /* setup D-PHY timings */
> - gen11_dsi_setup_dphy_timings(encoder);
> + gen11_dsi_setup_dphy_timings(encoder, crtc_state);
>
> /* step 4h: setup DSI protocol timeouts */
> - gen11_dsi_setup_timeouts(encoder);
> + gen11_dsi_setup_timeouts(encoder, crtc_state);
>
> /* Step (4h, 4i, 4j, 4k): Configure transcoder */
> - gen11_dsi_configure_transcoder(encoder, pipe_config);
> + gen11_dsi_configure_transcoder(encoder, crtc_state);
>
> /* Step 4l: Gate DDI clocks */
> if (IS_GEN(dev_priv, 11))
> @@ -1036,14 +1044,14 @@ static void gen11_dsi_powerup_panel(struct
> intel_encoder *encoder) }
>
> static void gen11_dsi_pre_pll_enable(struct intel_encoder *encoder,
> - const struct intel_crtc_state *pipe_config,
> + const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state
> *conn_state) {
> /* step2: enable IO power */
> gen11_dsi_enable_io_power(encoder);
>
> /* step3: enable DSI PLL */
> - gen11_dsi_program_esc_clk_div(encoder);
> + gen11_dsi_program_esc_clk_div(encoder, crtc_state);
> }
>
> static void gen11_dsi_pre_enable(struct intel_encoder *encoder, @@ -
> 1300,7 +1308,7 @@ static int gen11_dsi_compute_config(struct
> intel_encoder *encoder,
> pipe_config->pipe_bpp = 18;
>
> pipe_config->clock_set = true;
> - pipe_config->port_clock = afe_clk(encoder) / 5;
> + pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
>
> return 0;
> }
> --
> 2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v3 11/13] drm/i915/dsi: use compressed pixel format with DSC
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
When compression is enabled, configure the DSI transcoder to use
compressed format.
Suggested-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 36 ++++++++++++++------------
1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 5149a28a874b..460759913708 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -682,22 +682,26 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
/* select pixel format */
tmp &= ~PIX_FMT_MASK;
- switch (intel_dsi->pixel_format) {
- default:
- MISSING_CASE(intel_dsi->pixel_format);
- /* fallthrough */
- case MIPI_DSI_FMT_RGB565:
- tmp |= PIX_FMT_RGB565;
- break;
- case MIPI_DSI_FMT_RGB666_PACKED:
- tmp |= PIX_FMT_RGB666_PACKED;
- break;
- case MIPI_DSI_FMT_RGB666:
- tmp |= PIX_FMT_RGB666_LOOSE;
- break;
- case MIPI_DSI_FMT_RGB888:
- tmp |= PIX_FMT_RGB888;
- break;
+ if (pipe_config->dsc.compression_enable) {
+ tmp |= PIX_FMT_COMPRESSED;
+ } else {
+ switch (intel_dsi->pixel_format) {
+ default:
+ MISSING_CASE(intel_dsi->pixel_format);
+ /* fallthrough */
+ case MIPI_DSI_FMT_RGB565:
+ tmp |= PIX_FMT_RGB565;
+ break;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ tmp |= PIX_FMT_RGB666_PACKED;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ tmp |= PIX_FMT_RGB666_LOOSE;
+ break;
+ case MIPI_DSI_FMT_RGB888:
+ tmp |= PIX_FMT_RGB888;
+ break;
+ }
}
if (INTEL_GEN(dev_priv) >= 12) {
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH v3 11/13] drm/i915/dsi: use compressed pixel format with DSC
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
When compression is enabled, configure the DSI transcoder to use
compressed format.
Suggested-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 36 ++++++++++++++------------
1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 5149a28a874b..460759913708 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -682,22 +682,26 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
/* select pixel format */
tmp &= ~PIX_FMT_MASK;
- switch (intel_dsi->pixel_format) {
- default:
- MISSING_CASE(intel_dsi->pixel_format);
- /* fallthrough */
- case MIPI_DSI_FMT_RGB565:
- tmp |= PIX_FMT_RGB565;
- break;
- case MIPI_DSI_FMT_RGB666_PACKED:
- tmp |= PIX_FMT_RGB666_PACKED;
- break;
- case MIPI_DSI_FMT_RGB666:
- tmp |= PIX_FMT_RGB666_LOOSE;
- break;
- case MIPI_DSI_FMT_RGB888:
- tmp |= PIX_FMT_RGB888;
- break;
+ if (pipe_config->dsc.compression_enable) {
+ tmp |= PIX_FMT_COMPRESSED;
+ } else {
+ switch (intel_dsi->pixel_format) {
+ default:
+ MISSING_CASE(intel_dsi->pixel_format);
+ /* fallthrough */
+ case MIPI_DSI_FMT_RGB565:
+ tmp |= PIX_FMT_RGB565;
+ break;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ tmp |= PIX_FMT_RGB666_PACKED;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ tmp |= PIX_FMT_RGB666_LOOSE;
+ break;
+ case MIPI_DSI_FMT_RGB888:
+ tmp |= PIX_FMT_RGB888;
+ break;
+ }
}
if (INTEL_GEN(dev_priv) >= 12) {
--
2.20.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH v3 11/13] drm/i915/dsi: use compressed pixel format with DSC
2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula
(?)
@ 2019-12-05 14:44 ` Kulkarni, Vandita
-1 siblings, 0 replies; 56+ messages in thread
From: Kulkarni, Vandita @ 2019-12-05 14:44 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Tuesday, November 26, 2019 7:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: [PATCH v3 11/13] drm/i915/dsi: use compressed pixel format with
> DSC
>
> When compression is enabled, configure the DSI transcoder to use
> compressed format.
>
> Suggested-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Regards,
Vandita
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 36 ++++++++++++++------------
> 1 file changed, 20 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 5149a28a874b..460759913708 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -682,22 +682,26 @@ gen11_dsi_configure_transcoder(struct
> intel_encoder *encoder,
>
> /* select pixel format */
> tmp &= ~PIX_FMT_MASK;
> - switch (intel_dsi->pixel_format) {
> - default:
> - MISSING_CASE(intel_dsi->pixel_format);
> - /* fallthrough */
> - case MIPI_DSI_FMT_RGB565:
> - tmp |= PIX_FMT_RGB565;
> - break;
> - case MIPI_DSI_FMT_RGB666_PACKED:
> - tmp |= PIX_FMT_RGB666_PACKED;
> - break;
> - case MIPI_DSI_FMT_RGB666:
> - tmp |= PIX_FMT_RGB666_LOOSE;
> - break;
> - case MIPI_DSI_FMT_RGB888:
> - tmp |= PIX_FMT_RGB888;
> - break;
> + if (pipe_config->dsc.compression_enable) {
> + tmp |= PIX_FMT_COMPRESSED;
> + } else {
> + switch (intel_dsi->pixel_format) {
> + default:
> + MISSING_CASE(intel_dsi->pixel_format);
> + /* fallthrough */
> + case MIPI_DSI_FMT_RGB565:
> + tmp |= PIX_FMT_RGB565;
> + break;
> + case MIPI_DSI_FMT_RGB666_PACKED:
> + tmp |= PIX_FMT_RGB666_PACKED;
> + break;
> + case MIPI_DSI_FMT_RGB666:
> + tmp |= PIX_FMT_RGB666_LOOSE;
> + break;
> + case MIPI_DSI_FMT_RGB888:
> + tmp |= PIX_FMT_RGB888;
> + break;
> + }
> }
>
> if (INTEL_GEN(dev_priv) >= 12) {
> --
> 2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v3 12/13] drm/i915/dsi: account for DSC in horizontal timings
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
When DSC is enabled, we need to adjust the horizontal timings to account
for the compressed (and therefore reduced) link speed.
The compressed frequency ratio simplifies down to the ratio between
compressed and non-compressed bpp.
Bspec: 49263
Suggested-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 24 +++++++++++++++++++-----
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 460759913708..caa477c4b1af 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -785,12 +785,12 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
static void
gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
- const struct intel_crtc_state *pipe_config)
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
const struct drm_display_mode *adjusted_mode =
- &pipe_config->hw.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
enum port port;
enum transcoder dsi_trans;
/* horizontal timings */
@@ -798,11 +798,25 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
u16 hback_porch;
/* vertical timings */
u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
+ int mul = 1, div = 1;
+
+ /*
+ * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
+ * for slower link speed if DSC is enabled.
+ *
+ * The compression frequency ratio is the ratio between compressed and
+ * non-compressed link speeds, and simplifies down to the ratio between
+ * compressed and non-compressed bpp.
+ */
+ if (crtc_state->dsc.compression_enable) {
+ mul = crtc_state->dsc.compressed_bpp;
+ div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+ }
hactive = adjusted_mode->crtc_hdisplay;
- htotal = adjusted_mode->crtc_htotal;
- hsync_start = adjusted_mode->crtc_hsync_start;
- hsync_end = adjusted_mode->crtc_hsync_end;
+ htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
+ hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
+ hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
hsync_size = hsync_end - hsync_start;
hback_porch = (adjusted_mode->crtc_htotal -
adjusted_mode->crtc_hsync_end);
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH v3 12/13] drm/i915/dsi: account for DSC in horizontal timings
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
When DSC is enabled, we need to adjust the horizontal timings to account
for the compressed (and therefore reduced) link speed.
The compressed frequency ratio simplifies down to the ratio between
compressed and non-compressed bpp.
Bspec: 49263
Suggested-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 24 +++++++++++++++++++-----
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 460759913708..caa477c4b1af 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -785,12 +785,12 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
static void
gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
- const struct intel_crtc_state *pipe_config)
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
const struct drm_display_mode *adjusted_mode =
- &pipe_config->hw.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
enum port port;
enum transcoder dsi_trans;
/* horizontal timings */
@@ -798,11 +798,25 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
u16 hback_porch;
/* vertical timings */
u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
+ int mul = 1, div = 1;
+
+ /*
+ * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
+ * for slower link speed if DSC is enabled.
+ *
+ * The compression frequency ratio is the ratio between compressed and
+ * non-compressed link speeds, and simplifies down to the ratio between
+ * compressed and non-compressed bpp.
+ */
+ if (crtc_state->dsc.compression_enable) {
+ mul = crtc_state->dsc.compressed_bpp;
+ div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+ }
hactive = adjusted_mode->crtc_hdisplay;
- htotal = adjusted_mode->crtc_htotal;
- hsync_start = adjusted_mode->crtc_hsync_start;
- hsync_end = adjusted_mode->crtc_hsync_end;
+ htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
+ hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
+ hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
hsync_size = hsync_end - hsync_start;
hback_porch = (adjusted_mode->crtc_htotal -
adjusted_mode->crtc_hsync_end);
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH v3 12/13] drm/i915/dsi: account for DSC in horizontal timings
2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula
(?)
@ 2019-12-05 14:52 ` Kulkarni, Vandita
-1 siblings, 0 replies; 56+ messages in thread
From: Kulkarni, Vandita @ 2019-12-05 14:52 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Tuesday, November 26, 2019 7:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: [PATCH v3 12/13] drm/i915/dsi: account for DSC in horizontal
> timings
>
> When DSC is enabled, we need to adjust the horizontal timings to account
> for the compressed (and therefore reduced) link speed.
>
> The compressed frequency ratio simplifies down to the ratio between
> compressed and non-compressed bpp.
>
> Bspec: 49263
> Suggested-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Can be considered out of this patch, but gen11_dsi_get_timings would need corresponding
Changes to avoid state mismatch wrt horizontal timings.
Other than that, this patch looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Thanks,
Vandita
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 24 +++++++++++++++++++-----
> 1 file changed, 19 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 460759913708..caa477c4b1af 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -785,12 +785,12 @@ gen11_dsi_configure_transcoder(struct
> intel_encoder *encoder,
>
> static void
> gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> - const struct intel_crtc_state *pipe_config)
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> const struct drm_display_mode *adjusted_mode =
> - &pipe_config->hw.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> enum port port;
> enum transcoder dsi_trans;
> /* horizontal timings */
> @@ -798,11 +798,25 @@ gen11_dsi_set_transcoder_timings(struct
> intel_encoder *encoder,
> u16 hback_porch;
> /* vertical timings */
> u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
> + int mul = 1, div = 1;
> +
> + /*
> + * Adjust horizontal timings (htotal, hsync_start, hsync_end) to
> account
> + * for slower link speed if DSC is enabled.
> + *
> + * The compression frequency ratio is the ratio between compressed
> and
> + * non-compressed link speeds, and simplifies down to the ratio
> between
> + * compressed and non-compressed bpp.
> + */
> + if (crtc_state->dsc.compression_enable) {
> + mul = crtc_state->dsc.compressed_bpp;
> + div = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> >pixel_format);
> + }
>
> hactive = adjusted_mode->crtc_hdisplay;
> - htotal = adjusted_mode->crtc_htotal;
> - hsync_start = adjusted_mode->crtc_hsync_start;
> - hsync_end = adjusted_mode->crtc_hsync_end;
> + htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
> + hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start *
> mul, div);
> + hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end *
> mul, div);
> hsync_size = hsync_end - hsync_start;
> hback_porch = (adjusted_mode->crtc_htotal -
> adjusted_mode->crtc_hsync_end);
> --
> 2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v3 13/13] drm/i915/dsi: add support for DSC
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Enable DSC for DSI, if specified in VBT.
This still lacks DSC aware get config implementation, and therefore
state checker will fail. Also mode valid is not there yet.
v4:
- convert_rgb = true (Vandita)
- ignore max cdclock check (Vandita)
- rename pipe_config to crtc_state
v3:
- take compressed bpp into account
v2:
- Nuke conn_state->max_requested_bpc, it's not used on DSI
Bspec: 49263
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 67 ++++++++++++++++++++++++--
1 file changed, 64 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index caa477c4b1af..e142ac64f680 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -34,6 +34,7 @@
#include "intel_ddi.h"
#include "intel_dsi.h"
#include "intel_panel.h"
+#include "intel_vdsc.h"
static inline int header_credits_available(struct drm_i915_private *dev_priv,
enum transcoder dsi_trans)
@@ -1087,6 +1088,8 @@ static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
/* step5: program and powerup panel */
gen11_dsi_powerup_panel(encoder);
+ intel_dsc_enable(encoder, pipe_config);
+
/* step6c: configure transcoder timings */
gen11_dsi_set_transcoder_timings(encoder, pipe_config);
@@ -1248,6 +1251,13 @@ static void gen11_dsi_disable(struct intel_encoder *encoder,
gen11_dsi_disable_io_power(encoder);
}
+static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ /* FIXME: DSC? */
+ return intel_dsi_mode_valid(connector, mode);
+}
+
static void gen11_dsi_get_timings(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -1295,6 +1305,48 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
}
+static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+ int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10;
+ bool use_dsc;
+ int ret;
+
+ use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc);
+ if (!use_dsc)
+ return 0;
+
+ if (crtc_state->pipe_bpp < 8 * 3)
+ return -EINVAL;
+
+ /* FIXME: split only when necessary */
+ if (crtc_state->dsc.slice_count > 1)
+ crtc_state->dsc.dsc_split = true;
+
+ vdsc_cfg->convert_rgb = true;
+
+ ret = intel_dsc_compute_params(encoder, crtc_state);
+ if (ret)
+ return ret;
+
+ /* DSI specific sanity checks on the common code */
+ WARN_ON(vdsc_cfg->vbr_enable);
+ WARN_ON(vdsc_cfg->simple_422);
+ WARN_ON(vdsc_cfg->pic_width % vdsc_cfg->slice_width);
+ WARN_ON(vdsc_cfg->slice_height < 8);
+ WARN_ON(vdsc_cfg->pic_height % vdsc_cfg->slice_height);
+
+ ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
+ if (ret)
+ return ret;
+
+ crtc_state->dsc.compression_enable = true;
+
+ return 0;
+}
+
static int gen11_dsi_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
@@ -1326,6 +1378,10 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
pipe_config->pipe_bpp = 18;
pipe_config->clock_set = true;
+
+ if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
+ DRM_DEBUG_KMS("Attempting to use DSC failed\n");
+
pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
return 0;
@@ -1334,8 +1390,13 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
- get_dsi_io_power_domains(to_i915(encoder->base.dev),
- enc_to_intel_dsi(&encoder->base));
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ get_dsi_io_power_domains(i915, enc_to_intel_dsi(&encoder->base));
+
+ if (crtc_state->dsc.compression_enable)
+ intel_display_power_get(i915,
+ intel_dsc_power_domain(crtc_state));
}
static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
@@ -1405,7 +1466,7 @@ static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
.get_modes = intel_dsi_get_modes,
- .mode_valid = intel_dsi_mode_valid,
+ .mode_valid = gen11_dsi_mode_valid,
.atomic_check = intel_digital_connector_atomic_check,
};
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* [Intel-gfx] [PATCH v3 13/13] drm/i915/dsi: add support for DSC
@ 2019-11-26 13:42 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-11-26 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Enable DSC for DSI, if specified in VBT.
This still lacks DSC aware get config implementation, and therefore
state checker will fail. Also mode valid is not there yet.
v4:
- convert_rgb = true (Vandita)
- ignore max cdclock check (Vandita)
- rename pipe_config to crtc_state
v3:
- take compressed bpp into account
v2:
- Nuke conn_state->max_requested_bpc, it's not used on DSI
Bspec: 49263
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 67 ++++++++++++++++++++++++--
1 file changed, 64 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index caa477c4b1af..e142ac64f680 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -34,6 +34,7 @@
#include "intel_ddi.h"
#include "intel_dsi.h"
#include "intel_panel.h"
+#include "intel_vdsc.h"
static inline int header_credits_available(struct drm_i915_private *dev_priv,
enum transcoder dsi_trans)
@@ -1087,6 +1088,8 @@ static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
/* step5: program and powerup panel */
gen11_dsi_powerup_panel(encoder);
+ intel_dsc_enable(encoder, pipe_config);
+
/* step6c: configure transcoder timings */
gen11_dsi_set_transcoder_timings(encoder, pipe_config);
@@ -1248,6 +1251,13 @@ static void gen11_dsi_disable(struct intel_encoder *encoder,
gen11_dsi_disable_io_power(encoder);
}
+static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ /* FIXME: DSC? */
+ return intel_dsi_mode_valid(connector, mode);
+}
+
static void gen11_dsi_get_timings(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -1295,6 +1305,48 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
}
+static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+ int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10;
+ bool use_dsc;
+ int ret;
+
+ use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc);
+ if (!use_dsc)
+ return 0;
+
+ if (crtc_state->pipe_bpp < 8 * 3)
+ return -EINVAL;
+
+ /* FIXME: split only when necessary */
+ if (crtc_state->dsc.slice_count > 1)
+ crtc_state->dsc.dsc_split = true;
+
+ vdsc_cfg->convert_rgb = true;
+
+ ret = intel_dsc_compute_params(encoder, crtc_state);
+ if (ret)
+ return ret;
+
+ /* DSI specific sanity checks on the common code */
+ WARN_ON(vdsc_cfg->vbr_enable);
+ WARN_ON(vdsc_cfg->simple_422);
+ WARN_ON(vdsc_cfg->pic_width % vdsc_cfg->slice_width);
+ WARN_ON(vdsc_cfg->slice_height < 8);
+ WARN_ON(vdsc_cfg->pic_height % vdsc_cfg->slice_height);
+
+ ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
+ if (ret)
+ return ret;
+
+ crtc_state->dsc.compression_enable = true;
+
+ return 0;
+}
+
static int gen11_dsi_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
@@ -1326,6 +1378,10 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
pipe_config->pipe_bpp = 18;
pipe_config->clock_set = true;
+
+ if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
+ DRM_DEBUG_KMS("Attempting to use DSC failed\n");
+
pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
return 0;
@@ -1334,8 +1390,13 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
- get_dsi_io_power_domains(to_i915(encoder->base.dev),
- enc_to_intel_dsi(&encoder->base));
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ get_dsi_io_power_domains(i915, enc_to_intel_dsi(&encoder->base));
+
+ if (crtc_state->dsc.compression_enable)
+ intel_display_power_get(i915,
+ intel_dsc_power_domain(crtc_state));
}
static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
@@ -1405,7 +1466,7 @@ static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
.get_modes = intel_dsi_get_modes,
- .mode_valid = intel_dsi_mode_valid,
+ .mode_valid = gen11_dsi_mode_valid,
.atomic_check = intel_digital_connector_atomic_check,
};
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH v3 13/13] drm/i915/dsi: add support for DSC
2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula
(?)
@ 2019-12-05 6:14 ` Kulkarni, Vandita
2019-12-09 16:02 ` Jani Nikula
-1 siblings, 1 reply; 56+ messages in thread
From: Kulkarni, Vandita @ 2019-12-05 6:14 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Tuesday, November 26, 2019 7:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: [PATCH v3 13/13] drm/i915/dsi: add support for DSC
>
> Enable DSC for DSI, if specified in VBT.
>
> This still lacks DSC aware get config implementation, and therefore state
> checker will fail. Also mode valid is not there yet.
>
> v4:
> - convert_rgb = true (Vandita)
> - ignore max cdclock check (Vandita)
> - rename pipe_config to crtc_state
>
> v3:
> - take compressed bpp into account
>
> v2:
> - Nuke conn_state->max_requested_bpc, it's not used on DSI
>
> Bspec: 49263
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 67 ++++++++++++++++++++++++--
> 1 file changed, 64 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index caa477c4b1af..e142ac64f680 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -34,6 +34,7 @@
> #include "intel_ddi.h"
> #include "intel_dsi.h"
> #include "intel_panel.h"
> +#include "intel_vdsc.h"
>
> static inline int header_credits_available(struct drm_i915_private *dev_priv,
> enum transcoder dsi_trans)
> @@ -1087,6 +1088,8 @@ static void gen11_dsi_pre_enable(struct
> intel_encoder *encoder,
> /* step5: program and powerup panel */
> gen11_dsi_powerup_panel(encoder);
>
> + intel_dsc_enable(encoder, pipe_config);
> +
> /* step6c: configure transcoder timings */
> gen11_dsi_set_transcoder_timings(encoder, pipe_config);
>
> @@ -1248,6 +1251,13 @@ static void gen11_dsi_disable(struct
> intel_encoder *encoder,
> gen11_dsi_disable_io_power(encoder);
> }
>
> +static enum drm_mode_status gen11_dsi_mode_valid(struct
> drm_connector *connector,
> + struct drm_display_mode
> *mode)
> +{
> + /* FIXME: DSC? */
> + return intel_dsi_mode_valid(connector, mode); }
> +
> static void gen11_dsi_get_timings(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config) { @@ -
> 1295,6 +1305,48 @@ static void gen11_dsi_get_config(struct intel_encoder
> *encoder,
> pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); }
>
> +static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state) {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> + int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10;
> + bool use_dsc;
> + int ret;
> +
> + use_dsc = intel_bios_get_dsc_params(encoder, crtc_state,
> dsc_max_bpc);
> + if (!use_dsc)
> + return 0;
> +
> + if (crtc_state->pipe_bpp < 8 * 3)
> + return -EINVAL;
> +
> + /* FIXME: split only when necessary */
> + if (crtc_state->dsc.slice_count > 1)
> + crtc_state->dsc.dsc_split = true;
> +
> + vdsc_cfg->convert_rgb = true;
> +
Is there a chance this might fail and pipe_config->bpp might remain changed as per what happens in intel_bios_get_dsc_params?
> + ret = intel_dsc_compute_params(encoder, crtc_state);
> + if (ret)
> + return ret;
> +
> + /* DSI specific sanity checks on the common code */
> + WARN_ON(vdsc_cfg->vbr_enable);
> + WARN_ON(vdsc_cfg->simple_422);
> + WARN_ON(vdsc_cfg->pic_width % vdsc_cfg->slice_width);
> + WARN_ON(vdsc_cfg->slice_height < 8);
> + WARN_ON(vdsc_cfg->pic_height % vdsc_cfg->slice_height);
> +
> + ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
> + if (ret)
> + return ret;
> +
> + crtc_state->dsc.compression_enable = true;
> +
> + return 0;
> +}
> +
> static int gen11_dsi_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> struct drm_connector_state *conn_state)
> @@ -1326,6 +1378,10 @@ static int gen11_dsi_compute_config(struct
> intel_encoder *encoder,
> pipe_config->pipe_bpp = 18;
>
> pipe_config->clock_set = true;
> +
> + if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
> + DRM_DEBUG_KMS("Attempting to use DSC failed\n");
> +
> pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
>
> return 0;
> @@ -1334,8 +1390,13 @@ static int gen11_dsi_compute_config(struct
> intel_encoder *encoder, static void gen11_dsi_get_power_domains(struct
> intel_encoder *encoder,
> struct intel_crtc_state *crtc_state) {
> - get_dsi_io_power_domains(to_i915(encoder->base.dev),
> - enc_to_intel_dsi(&encoder->base));
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +
> + get_dsi_io_power_domains(i915, enc_to_intel_dsi(&encoder-
> >base));
> +
> + if (crtc_state->dsc.compression_enable)
> + intel_display_power_get(i915,
> +
> intel_dsc_power_domain(crtc_state));
> }
>
> static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, @@ -
> 1405,7 +1466,7 @@ static const struct drm_connector_funcs
> gen11_dsi_connector_funcs = {
>
> static const struct drm_connector_helper_funcs
> gen11_dsi_connector_helper_funcs = {
> .get_modes = intel_dsi_get_modes,
> - .mode_valid = intel_dsi_mode_valid,
> + .mode_valid = gen11_dsi_mode_valid,
> .atomic_check = intel_digital_connector_atomic_check,
> };
>
> --
> 2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [Intel-gfx] [PATCH v3 13/13] drm/i915/dsi: add support for DSC
2019-12-05 6:14 ` Kulkarni, Vandita
@ 2019-12-09 16:02 ` Jani Nikula
0 siblings, 0 replies; 56+ messages in thread
From: Jani Nikula @ 2019-12-09 16:02 UTC (permalink / raw)
To: Kulkarni, Vandita, intel-gfx
On Thu, 05 Dec 2019, "Kulkarni, Vandita" <vandita.kulkarni@intel.com> wrote:
>> -----Original Message-----
>> From: Jani Nikula <jani.nikula@intel.com>
>> Sent: Tuesday, November 26, 2019 7:13 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; Kulkarni, Vandita
>> <vandita.kulkarni@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Subject: [PATCH v3 13/13] drm/i915/dsi: add support for DSC
>>
>> Enable DSC for DSI, if specified in VBT.
>>
>> This still lacks DSC aware get config implementation, and therefore state
>> checker will fail. Also mode valid is not there yet.
>>
>> v4:
>> - convert_rgb = true (Vandita)
>> - ignore max cdclock check (Vandita)
>> - rename pipe_config to crtc_state
>>
>> v3:
>> - take compressed bpp into account
>>
>> v2:
>> - Nuke conn_state->max_requested_bpc, it's not used on DSI
>>
>> Bspec: 49263
>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/icl_dsi.c | 67 ++++++++++++++++++++++++--
>> 1 file changed, 64 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
>> b/drivers/gpu/drm/i915/display/icl_dsi.c
>> index caa477c4b1af..e142ac64f680 100644
>> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> @@ -34,6 +34,7 @@
>> #include "intel_ddi.h"
>> #include "intel_dsi.h"
>> #include "intel_panel.h"
>> +#include "intel_vdsc.h"
>>
>> static inline int header_credits_available(struct drm_i915_private *dev_priv,
>> enum transcoder dsi_trans)
>> @@ -1087,6 +1088,8 @@ static void gen11_dsi_pre_enable(struct
>> intel_encoder *encoder,
>> /* step5: program and powerup panel */
>> gen11_dsi_powerup_panel(encoder);
>>
>> + intel_dsc_enable(encoder, pipe_config);
>> +
>> /* step6c: configure transcoder timings */
>> gen11_dsi_set_transcoder_timings(encoder, pipe_config);
>>
>> @@ -1248,6 +1251,13 @@ static void gen11_dsi_disable(struct
>> intel_encoder *encoder,
>> gen11_dsi_disable_io_power(encoder);
>> }
>>
>> +static enum drm_mode_status gen11_dsi_mode_valid(struct
>> drm_connector *connector,
>> + struct drm_display_mode
>> *mode)
>> +{
>> + /* FIXME: DSC? */
>> + return intel_dsi_mode_valid(connector, mode); }
>> +
>> static void gen11_dsi_get_timings(struct intel_encoder *encoder,
>> struct intel_crtc_state *pipe_config) { @@ -
>> 1295,6 +1305,48 @@ static void gen11_dsi_get_config(struct intel_encoder
>> *encoder,
>> pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); }
>>
>> +static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
>> + struct intel_crtc_state *crtc_state) {
>> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> + struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>> + int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10;
>> + bool use_dsc;
>> + int ret;
>> +
>> + use_dsc = intel_bios_get_dsc_params(encoder, crtc_state,
>> dsc_max_bpc);
>> + if (!use_dsc)
>> + return 0;
>> +
>> + if (crtc_state->pipe_bpp < 8 * 3)
>> + return -EINVAL;
>> +
>> + /* FIXME: split only when necessary */
>> + if (crtc_state->dsc.slice_count > 1)
>> + crtc_state->dsc.dsc_split = true;
>> +
>> + vdsc_cfg->convert_rgb = true;
>> +
>
> Is there a chance this might fail and pipe_config->bpp might remain
> changed as per what happens in intel_bios_get_dsc_params?
In theory, yes, but I'm doubtful we'll be able to get anything on screen
if VBT says DSC is required and it fails somehow.
BR,
Jani.
>
>> + ret = intel_dsc_compute_params(encoder, crtc_state);
>> + if (ret)
>> + return ret;
>> +
>> + /* DSI specific sanity checks on the common code */
>> + WARN_ON(vdsc_cfg->vbr_enable);
>> + WARN_ON(vdsc_cfg->simple_422);
>> + WARN_ON(vdsc_cfg->pic_width % vdsc_cfg->slice_width);
>> + WARN_ON(vdsc_cfg->slice_height < 8);
>> + WARN_ON(vdsc_cfg->pic_height % vdsc_cfg->slice_height);
>> +
>> + ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
>> + if (ret)
>> + return ret;
>> +
>> + crtc_state->dsc.compression_enable = true;
>> +
>> + return 0;
>> +}
>> +
>> static int gen11_dsi_compute_config(struct intel_encoder *encoder,
>> struct intel_crtc_state *pipe_config,
>> struct drm_connector_state *conn_state)
>> @@ -1326,6 +1378,10 @@ static int gen11_dsi_compute_config(struct
>> intel_encoder *encoder,
>> pipe_config->pipe_bpp = 18;
>>
>> pipe_config->clock_set = true;
>> +
>> + if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
>> + DRM_DEBUG_KMS("Attempting to use DSC failed\n");
>> +
>> pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
>>
>> return 0;
>> @@ -1334,8 +1390,13 @@ static int gen11_dsi_compute_config(struct
>> intel_encoder *encoder, static void gen11_dsi_get_power_domains(struct
>> intel_encoder *encoder,
>> struct intel_crtc_state *crtc_state) {
>> - get_dsi_io_power_domains(to_i915(encoder->base.dev),
>> - enc_to_intel_dsi(&encoder->base));
>> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> +
>> + get_dsi_io_power_domains(i915, enc_to_intel_dsi(&encoder-
>> >base));
>> +
>> + if (crtc_state->dsc.compression_enable)
>> + intel_display_power_get(i915,
>> +
>> intel_dsc_power_domain(crtc_state));
>> }
>>
>> static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, @@ -
>> 1405,7 +1466,7 @@ static const struct drm_connector_funcs
>> gen11_dsi_connector_funcs = {
>>
>> static const struct drm_connector_helper_funcs
>> gen11_dsi_connector_helper_funcs = {
>> .get_modes = intel_dsi_get_modes,
>> - .mode_valid = intel_dsi_mode_valid,
>> + .mode_valid = gen11_dsi_mode_valid,
>> .atomic_check = intel_digital_connector_atomic_check,
>> };
>>
>> --
>> 2.20.1
>
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: enable DSC (rev3)
@ 2019-11-26 18:22 ` Patchwork
0 siblings, 0 replies; 56+ messages in thread
From: Patchwork @ 2019-11-26 18:22 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dsi: enable DSC (rev3)
URL : https://patchwork.freedesktop.org/series/69540/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4bb56f2cb8ef drm/i915/bios: pass devdata to parse_ddi_port
a8b033ae3755 drm/i915/bios: parse compression parameters block
-:106: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "devdata->dsc"
#106: FILE: drivers/gpu/drm/i915/display/intel_bios.c:1628:
+ devdata->dsc != NULL);
total: 0 errors, 0 warnings, 1 checks, 101 lines checked
25a856d626a8 drm/i915/bios: add support for querying DSC details for encoder
72b5f77fdaee drm/i915/dsc: move DP specific compute params to intel_dp.c
42216940dadf drm/i915/dsc: move slice height calculation to encoder
546db86ab719 drm/i915/dsc: add support for computing and writing PPS for DSI encoders
ff00c236d4f0 drm/i915/dsi: set pipe_bpp on ICL configure config
0dbb4c5c1944 drm/i915/dsi: abstract afe_clk calculation
9200aaeb1c25 drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
096a57a803a5 drm/i915/dsi: take compression into account in afe_clk()
a22f9efe184b drm/i915/dsi: use compressed pixel format with DSC
39b94660b782 drm/i915/dsi: account for DSC in horizontal timings
f7df132f1037 drm/i915/dsi: add support for DSC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: enable DSC (rev3)
@ 2019-11-26 18:22 ` Patchwork
0 siblings, 0 replies; 56+ messages in thread
From: Patchwork @ 2019-11-26 18:22 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dsi: enable DSC (rev3)
URL : https://patchwork.freedesktop.org/series/69540/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4bb56f2cb8ef drm/i915/bios: pass devdata to parse_ddi_port
a8b033ae3755 drm/i915/bios: parse compression parameters block
-:106: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "devdata->dsc"
#106: FILE: drivers/gpu/drm/i915/display/intel_bios.c:1628:
+ devdata->dsc != NULL);
total: 0 errors, 0 warnings, 1 checks, 101 lines checked
25a856d626a8 drm/i915/bios: add support for querying DSC details for encoder
72b5f77fdaee drm/i915/dsc: move DP specific compute params to intel_dp.c
42216940dadf drm/i915/dsc: move slice height calculation to encoder
546db86ab719 drm/i915/dsc: add support for computing and writing PPS for DSI encoders
ff00c236d4f0 drm/i915/dsi: set pipe_bpp on ICL configure config
0dbb4c5c1944 drm/i915/dsi: abstract afe_clk calculation
9200aaeb1c25 drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
096a57a803a5 drm/i915/dsi: take compression into account in afe_clk()
a22f9efe184b drm/i915/dsi: use compressed pixel format with DSC
39b94660b782 drm/i915/dsi: account for DSC in horizontal timings
f7df132f1037 drm/i915/dsi: add support for DSC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/dsi: enable DSC (rev3)
@ 2019-11-26 18:52 ` Patchwork
0 siblings, 0 replies; 56+ messages in thread
From: Patchwork @ 2019-11-26 18:52 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dsi: enable DSC (rev3)
URL : https://patchwork.freedesktop.org/series/69540/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7426 -> Patchwork_15439
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15439 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15439, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15439/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15439:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_gem_contexts:
- fi-skl-6770hq: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-skl-6770hq/igt@i915_selftest@live_gem_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15439/fi-skl-6770hq/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_gt_heartbeat:
- fi-kbl-soraka: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-kbl-soraka/igt@i915_selftest@live_gt_heartbeat.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15439/fi-kbl-soraka/igt@i915_selftest@live_gt_heartbeat.html
Known issues
------------
Here are the changes found in Patchwork_15439 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-guc: [PASS][5] -> [INCOMPLETE][6] ([fdo#106070] / [fdo#111700])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15439/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
#### Possible fixes ####
* igt@i915_selftest@live_gem_contexts:
- fi-skl-lmem: [DMESG-FAIL][7] -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15439/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
#### Warnings ####
* igt@kms_busy@basic-flip-pipe-a:
- fi-kbl-x1275: [DMESG-WARN][9] ([fdo#103558] / [fdo#105602] / [fdo#105763]) -> [DMESG-WARN][10] ([fdo#103558] / [fdo#105602]) +7 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-a.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15439/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-a.html
* igt@kms_flip@basic-flip-vs-modeset:
- fi-kbl-x1275: [DMESG-WARN][11] ([fdo#103558] / [fdo#105602]) -> [DMESG-WARN][12] ([fdo#103558] / [fdo#105602] / [fdo#105763]) +7 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15439/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070
[fdo#111700]: https://bugs.freedesktop.org/show_bug.cgi?id=111700
Participating hosts (49 -> 44)
------------------------------
Additional (1): fi-whl-u
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7426 -> Patchwork_15439
CI-20190529: 20190529
CI_DRM_7426: b204d72d3485a148456e2077683974739b675b21 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5310: d1ea62b3f759f10ff6860561ba82e5c4902511d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15439: f7df132f1037fb81739a404b11aa9c76aa3736d3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f7df132f1037 drm/i915/dsi: add support for DSC
39b94660b782 drm/i915/dsi: account for DSC in horizontal timings
a22f9efe184b drm/i915/dsi: use compressed pixel format with DSC
096a57a803a5 drm/i915/dsi: take compression into account in afe_clk()
9200aaeb1c25 drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
0dbb4c5c1944 drm/i915/dsi: abstract afe_clk calculation
ff00c236d4f0 drm/i915/dsi: set pipe_bpp on ICL configure config
546db86ab719 drm/i915/dsc: add support for computing and writing PPS for DSI encoders
42216940dadf drm/i915/dsc: move slice height calculation to encoder
72b5f77fdaee drm/i915/dsc: move DP specific compute params to intel_dp.c
25a856d626a8 drm/i915/bios: add support for querying DSC details for encoder
a8b033ae3755 drm/i915/bios: parse compression parameters block
4bb56f2cb8ef drm/i915/bios: pass devdata to parse_ddi_port
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15439/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: enable DSC (rev4)
@ 2019-11-27 14:07 ` Patchwork
0 siblings, 0 replies; 56+ messages in thread
From: Patchwork @ 2019-11-27 14:07 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dsi: enable DSC (rev4)
URL : https://patchwork.freedesktop.org/series/69540/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5531079c698e drm/i915/bios: pass devdata to parse_ddi_port
94a64f506df8 drm/i915/bios: parse compression parameters block
-:106: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "devdata->dsc"
#106: FILE: drivers/gpu/drm/i915/display/intel_bios.c:1628:
+ devdata->dsc != NULL);
total: 0 errors, 0 warnings, 1 checks, 101 lines checked
64b22756d726 drm/i915/bios: add support for querying DSC details for encoder
b957c9c66c49 drm/i915/dsc: move DP specific compute params to intel_dp.c
c389c5517ef9 drm/i915/dsc: move slice height calculation to encoder
a5f249d32752 drm/i915/dsc: add support for computing and writing PPS for DSI encoders
dd6deac9a4e4 drm/i915/dsi: set pipe_bpp on ICL configure config
cf3b9762ec5d drm/i915/dsi: abstract afe_clk calculation
a789653d1efd drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
3ce31b856fb6 drm/i915/dsi: take compression into account in afe_clk()
dbe5aa70e1c4 drm/i915/dsi: use compressed pixel format with DSC
2957e1adf1d1 drm/i915/dsi: account for DSC in horizontal timings
8006c1152138 drm/i915/dsi: add support for DSC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: enable DSC (rev4)
@ 2019-11-27 14:07 ` Patchwork
0 siblings, 0 replies; 56+ messages in thread
From: Patchwork @ 2019-11-27 14:07 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dsi: enable DSC (rev4)
URL : https://patchwork.freedesktop.org/series/69540/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5531079c698e drm/i915/bios: pass devdata to parse_ddi_port
94a64f506df8 drm/i915/bios: parse compression parameters block
-:106: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "devdata->dsc"
#106: FILE: drivers/gpu/drm/i915/display/intel_bios.c:1628:
+ devdata->dsc != NULL);
total: 0 errors, 0 warnings, 1 checks, 101 lines checked
64b22756d726 drm/i915/bios: add support for querying DSC details for encoder
b957c9c66c49 drm/i915/dsc: move DP specific compute params to intel_dp.c
c389c5517ef9 drm/i915/dsc: move slice height calculation to encoder
a5f249d32752 drm/i915/dsc: add support for computing and writing PPS for DSI encoders
dd6deac9a4e4 drm/i915/dsi: set pipe_bpp on ICL configure config
cf3b9762ec5d drm/i915/dsi: abstract afe_clk calculation
a789653d1efd drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
3ce31b856fb6 drm/i915/dsi: take compression into account in afe_clk()
dbe5aa70e1c4 drm/i915/dsi: use compressed pixel format with DSC
2957e1adf1d1 drm/i915/dsi: account for DSC in horizontal timings
8006c1152138 drm/i915/dsi: add support for DSC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/dsi: enable DSC (rev4)
@ 2019-11-27 14:30 ` Patchwork
0 siblings, 0 replies; 56+ messages in thread
From: Patchwork @ 2019-11-27 14:30 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dsi: enable DSC (rev4)
URL : https://patchwork.freedesktop.org/series/69540/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7431 -> Patchwork_15462
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/index.html
Known issues
------------
Here are the changes found in Patchwork_15462 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload-with-fault-injection:
- fi-icl-y: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/fi-icl-y/igt@i915_module_load@reload-with-fault-injection.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/fi-icl-y/igt@i915_module_load@reload-with-fault-injection.html
- fi-icl-u3: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/fi-icl-u3/igt@i915_module_load@reload-with-fault-injection.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/fi-icl-u3/igt@i915_module_load@reload-with-fault-injection.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- {fi-tgl-u}: [INCOMPLETE][5] ([fdo#111735]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/fi-tgl-u/igt@gem_ctx_create@basic-files.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/fi-tgl-u/igt@gem_ctx_create@basic-files.html
#### Warnings ####
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][7] ([fdo#103558] / [fdo#105602]) -> [DMESG-WARN][8] ([fdo#103558] / [fdo#105602] / [fdo#105763]) +4 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][9] ([fdo#103558] / [fdo#105602] / [fdo#105763]) -> [DMESG-WARN][10] ([fdo#103558] / [fdo#105602]) +6 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
Participating hosts (52 -> 45)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7431 -> Patchwork_15462
CI-20190529: 20190529
CI_DRM_7431: 1e2339ed90d558c4bb1d154b0ea2a51e11da8196 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5310: d1ea62b3f759f10ff6860561ba82e5c4902511d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15462: 8006c1152138b3351636d5a59ba698b8922dcd4e @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8006c1152138 drm/i915/dsi: add support for DSC
2957e1adf1d1 drm/i915/dsi: account for DSC in horizontal timings
dbe5aa70e1c4 drm/i915/dsi: use compressed pixel format with DSC
3ce31b856fb6 drm/i915/dsi: take compression into account in afe_clk()
a789653d1efd drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
cf3b9762ec5d drm/i915/dsi: abstract afe_clk calculation
dd6deac9a4e4 drm/i915/dsi: set pipe_bpp on ICL configure config
a5f249d32752 drm/i915/dsc: add support for computing and writing PPS for DSI encoders
c389c5517ef9 drm/i915/dsc: move slice height calculation to encoder
b957c9c66c49 drm/i915/dsc: move DP specific compute params to intel_dp.c
64b22756d726 drm/i915/bios: add support for querying DSC details for encoder
94a64f506df8 drm/i915/bios: parse compression parameters block
5531079c698e drm/i915/bios: pass devdata to parse_ddi_port
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* ✗ Fi.CI.IGT: failure for drm/i915/dsi: enable DSC (rev4)
@ 2019-11-28 14:21 ` Patchwork
0 siblings, 0 replies; 56+ messages in thread
From: Patchwork @ 2019-11-28 14:21 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dsi: enable DSC (rev4)
URL : https://patchwork.freedesktop.org/series/69540/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7431_full -> Patchwork_15462_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15462_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15462_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15462_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
- shard-skl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-skl3/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-skl3/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
Known issues
------------
Here are the changes found in Patchwork_15462_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@vcs1-s3:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-iclb2/igt@gem_ctx_isolation@vcs1-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-iclb5/igt@gem_ctx_isolation@vcs1-s3.html
* igt@gem_ctx_shared@q-smoketest-bsd:
- shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([fdo# 111852 ])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-tglb5/igt@gem_ctx_shared@q-smoketest-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-tglb6/igt@gem_ctx_shared@q-smoketest-bsd.html
* igt@gem_eio@kms:
- shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([fdo#105345])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-kbl7/igt@gem_eio@kms.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-kbl2/igt@gem_eio@kms.html
* igt@gem_exec_parallel@vcs0:
- shard-tglb: [PASS][9] -> [INCOMPLETE][10] ([fdo#111593])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-tglb8/igt@gem_exec_parallel@vcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-tglb4/igt@gem_exec_parallel@vcs0.html
* igt@gem_exec_schedule@preempt-self-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-iclb7/igt@gem_exec_schedule@preempt-self-bsd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-iclb1/igt@gem_exec_schedule@preempt-self-bsd.html
* igt@gem_exec_schedule@smoketest-bsd1:
- shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([fdo#111855])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-tglb9/igt@gem_exec_schedule@smoketest-bsd1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-tglb9/igt@gem_exec_schedule@smoketest-bsd1.html
* igt@gem_exec_schedule@smoketest-bsd2:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109276]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-iclb4/igt@gem_exec_schedule@smoketest-bsd2.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-iclb5/igt@gem_exec_schedule@smoketest-bsd2.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [PASS][17] -> [FAIL][18] ([fdo#112392])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-glk5/igt@gem_ppgtt@flink-and-close-vma-leak.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-glk5/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_userptr_blits@sync-unmap:
- shard-snb: [PASS][19] -> [DMESG-WARN][20] ([fdo#111870])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-snb1/igt@gem_userptr_blits@sync-unmap.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-snb5/igt@gem_userptr_blits@sync-unmap.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-hsw: [PASS][21] -> [DMESG-WARN][22] ([fdo#111870])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-hsw8/igt@gem_userptr_blits@sync-unmap-after-close.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-hsw7/igt@gem_userptr_blits@sync-unmap-after-close.html
* igt@i915_pm_backlight@fade_with_suspend:
- shard-tglb: [PASS][23] -> [INCOMPLETE][24] ([fdo#111832] / [fdo#111850]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-tglb9/igt@i915_pm_backlight@fade_with_suspend.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-tglb7/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_pm_dc@dc5-dpms:
- shard-iclb: [PASS][25] -> [FAIL][26] ([fdo#111795 ])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-iclb6/igt@i915_pm_dc@dc5-dpms.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html
* igt@i915_pm_rpm@system-suspend:
- shard-kbl: [PASS][27] -> [INCOMPLETE][28] ([fdo#103665] / [fdo#107807])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-kbl4/igt@i915_pm_rpm@system-suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-kbl2/igt@i915_pm_rpm@system-suspend.html
* igt@i915_suspend@forcewake:
- shard-apl: [PASS][29] -> [DMESG-WARN][30] ([fdo#108566])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-apl7/igt@i915_suspend@forcewake.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-apl6/igt@i915_suspend@forcewake.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-0:
- shard-skl: [PASS][31] -> [DMESG-WARN][32] ([fdo#106107])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-skl5/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-skl4/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [PASS][33] -> [FAIL][34] ([fdo#105767])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-hsw5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic:
- shard-hsw: [PASS][35] -> [FAIL][36] ([fdo#103355])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-hsw2/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic:
- shard-hsw: [PASS][37] -> [INCOMPLETE][38] ([fdo#103540])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-hsw6/igt@kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-hsw7/igt@kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][39] -> [FAIL][40] ([fdo#105363])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-tglb: [PASS][41] -> [FAIL][42] ([fdo#103167])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-iclb: [PASS][43] -> [INCOMPLETE][44] ([fdo#106978] / [fdo#107713])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
- shard-skl: [PASS][45] -> [INCOMPLETE][46] ([fdo#106978]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_plane@pixel-format-pipe-a-planes:
- shard-kbl: [PASS][47] -> [INCOMPLETE][48] ([fdo#103665]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-kbl7/igt@kms_plane@pixel-format-pipe-a-planes.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-kbl2/igt@kms_plane@pixel-format-pipe-a-planes.html
* igt@kms_plane@pixel-format-pipe-b-planes:
- shard-skl: [PASS][49] -> [INCOMPLETE][50] ([fdo#112391])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-skl9/igt@kms_plane@pixel-format-pipe-b-planes.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-skl9/igt@kms_plane@pixel-format-pipe-b-planes.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][51] -> [FAIL][52] ([fdo#99912])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-apl3/igt@kms_setmode@basic.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-apl7/igt@kms_setmode@basic.html
* igt@perf_pmu@semaphore-wait-vcs1:
- shard-iclb: [PASS][53] -> [SKIP][54] ([fdo#112080]) +2 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-iclb4/igt@perf_pmu@semaphore-wait-vcs1.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-iclb5/igt@perf_pmu@semaphore-wait-vcs1.html
#### Possible fixes ####
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [SKIP][55] ([fdo#110841]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-iclb5/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_ctx_switch@legacy-default:
- shard-hsw: [INCOMPLETE][57] ([fdo#103540]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-hsw7/igt@gem_ctx_switch@legacy-default.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-hsw1/igt@gem_ctx_switch@legacy-default.html
* igt@gem_exec_create@forked:
- shard-tglb: [INCOMPLETE][59] ([fdo#108838] / [fdo#111747]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-tglb6/igt@gem_exec_create@forked.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-tglb1/igt@gem_exec_create@forked.html
* igt@gem_exec_reloc@basic-wc-cpu-active:
- shard-skl: [DMESG-WARN][61] ([fdo#106107]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-skl9/igt@gem_exec_reloc@basic-wc-cpu-active.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-skl4/igt@gem_exec_reloc@basic-wc-cpu-active.html
* igt@gem_exec_schedule@preempt-queue-chain-bsd:
- shard-iclb: [SKIP][63] ([fdo#112146]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-iclb2/igt@gem_exec_schedule@preempt-queue-chain-bsd.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-iclb5/igt@gem_exec_schedule@preempt-queue-chain-bsd.html
* igt@gem_exec_schedule@reorder-wide-bsd1:
- shard-iclb: [SKIP][65] ([fdo#109276]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-iclb7/igt@gem_exec_schedule@reorder-wide-bsd1.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-iclb1/igt@gem_exec_schedule@reorder-wide-bsd1.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-kbl: [FAIL][67] ([fdo#112037]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-kbl1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-kbl7/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-kbl: [FAIL][69] ([fdo#112392]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-kbl2/igt@gem_ppgtt@flink-and-close-vma-leak.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-kbl1/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-snb: [DMESG-WARN][71] ([fdo#111870]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
- shard-hsw: [DMESG-WARN][73] ([fdo#111870]) -> [PASS][74] +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_wait@await-vcs1:
- shard-iclb: [SKIP][75] ([fdo#112080]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-iclb7/igt@gem_wait@await-vcs1.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-iclb1/igt@gem_wait@await-vcs1.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][77] ([fdo#108566]) -> [PASS][78] +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-apl4/igt@i915_suspend@sysfs-reader.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-apl7/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-tglb: [INCOMPLETE][79] ([fdo#111850]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled:
- shard-kbl: [INCOMPLETE][81] ([fdo#103665]) -> [PASS][82] +2 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-kbl3/igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-kbl7/igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-tglb: [INCOMPLETE][83] ([fdo#111747] / [fdo#111832] / [fdo#111850]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-tglb7/igt@kms_fbcon_fbt@fbc-suspend.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-tglb6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-apl: [FAIL][85] ([fdo#105363]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-apl2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-apl4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-snb: [INCOMPLETE][87] ([fdo#105411]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-snb1/igt@kms_flip@flip-vs-suspend-interruptible.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-snb6/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
- shard-tglb: [FAIL][89] ([fdo#103167]) -> [PASS][90] +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
- shard-kbl: [INCOMPLETE][91] ([fdo#103665] / [fdo#112356]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-iclb: [INCOMPLETE][93] ([fdo#107713]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_lease@lease_unleased_connector:
- shard-snb: [SKIP][95] ([fdo#109271]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-snb2/igt@kms_lease@lease_unleased_connector.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-snb1/igt@kms_lease@lease_unleased_connector.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-tglb: [INCOMPLETE][97] ([fdo#111832] / [fdo#111850]) -> [PASS][98] +2 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-tglb7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-tglb4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][99] ([fdo#108566]) -> [PASS][100] +8 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
#### Warnings ####
* igt@gem_eio@kms:
- shard-snb: [INCOMPLETE][101] ([fdo#105411]) -> [DMESG-WARN][102] ([fdo# 112000 ] / [fdo#111781])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-snb6/igt@gem_eio@kms.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-snb7/igt@gem_eio@kms.html
* igt@gem_exec_schedule@deep-render:
- shard-tglb: [INCOMPLETE][103] ([fdo#111671]) -> [FAIL][104] ([fdo#111646])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-tglb7/igt@gem_exec_schedule@deep-render.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-tglb2/igt@gem_exec_schedule@deep-render.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-snb: [DMESG-WARN][105] ([fdo#110789] / [fdo#111870]) -> [DMESG-WARN][106] ([fdo#111870])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7431/shard-snb6/igt@gem_userptr_blits@sync-unmap-after-close.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/shard-snb2/igt@gem_userptr_blits@sync-unmap-after-close.html
[fdo# 111852 ]: https://bugs.freedesktop.org/show_bug.cgi?id= 111852
[fdo# 112000 ]: https://bugs.freedesktop.org/show_bug.cgi?id= 112000
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#105345]: https://bugs.freedesktop.org/show_bug.cgi?id=105345
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108838]: https://bugs.freedesktop.org/show_bug.cgi?id=108838
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[fdo#111646]: https://bugs.freedesktop.org/show_bug.cgi?id=111646
[fdo#111671]: https://bugs.freedesktop.org/show_bug.cgi?id=111671
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#111781]: https://bugs.freedesktop.org/show_bug.cgi?id=111781
[fdo#111795 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111795
[fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
[fdo#111855]: https://bugs.freedesktop.org/show_bug.cgi?id=111855
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#112037]: https://bugs.freedesktop.org/show_bug.cgi?id=112037
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[fdo#112356]: https://bugs.freedesktop.org/show_bug.cgi?id=112356
[fdo#112391]: https://bugs.freedesktop.org/show_bug.cgi?id=112391
[fdo#112392]: https://bugs.freedesktop.org/show_bug.cgi?id=112392
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7431 -> Patchwork_15462
CI-20190529: 20190529
CI_DRM_7431: 1e2339ed90d558c4bb1d154b0ea2a51e11da8196 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5310: d1ea62b3f759f10ff6860561ba82e5c4902511d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15462: 8006c1152138b3351636d5a59ba698b8922dcd4e @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15462/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: enable DSC (rev5)
2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula
` (18 preceding siblings ...)
(?)
@ 2019-12-05 15:24 ` Patchwork
-1 siblings, 0 replies; 56+ messages in thread
From: Patchwork @ 2019-12-05 15:24 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dsi: enable DSC (rev5)
URL : https://patchwork.freedesktop.org/series/69540/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d1eac96f3ca9 drm/i915/bios: pass devdata to parse_ddi_port
7bbf115b2fe1 drm/i915/bios: parse compression parameters block
-:107: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "devdata->dsc"
#107: FILE: drivers/gpu/drm/i915/display/intel_bios.c:1657:
+ devdata->dsc != NULL);
total: 0 errors, 0 warnings, 1 checks, 101 lines checked
df83ffb4fe22 drm/i915/bios: add support for querying DSC details for encoder
121299cced8c drm/i915/dsc: move DP specific compute params to intel_dp.c
59ce59912b93 drm/i915/dsc: move slice height calculation to encoder
43d897f1d016 drm/i915/dsc: add support for computing and writing PPS for DSI encoders
23a2e041cf02 drm/i915/dsi: set pipe_bpp on ICL configure config
bc6b5ae33239 drm/i915/dsi: abstract afe_clk calculation
7460bcfe7cab drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
05891ad7d716 drm/i915/dsi: take compression into account in afe_clk()
fea7c7f0cfdd drm/i915/dsi: use compressed pixel format with DSC
871e85117950 drm/i915/dsi: account for DSC in horizontal timings
10d79292fa34 drm/i915/dsi: add support for DSC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 56+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsi: enable DSC (rev5)
2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula
` (19 preceding siblings ...)
(?)
@ 2019-12-05 16:20 ` Patchwork
-1 siblings, 0 replies; 56+ messages in thread
From: Patchwork @ 2019-12-05 16:20 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dsi: enable DSC (rev5)
URL : https://patchwork.freedesktop.org/series/69540/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7490 -> Patchwork_15605
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15605 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15605, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15605/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15605:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_workarounds:
- fi-icl-dsi: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7490/fi-icl-dsi/igt@i915_selftest@live_workarounds.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15605/fi-icl-dsi/igt@i915_selftest@live_workarounds.html
Known issues
------------
Here are the changes found in Patchwork_15605 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s0:
- fi-cml-u2: [PASS][3] -> [INCOMPLETE][4] ([i915#283])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7490/fi-cml-u2/igt@gem_exec_suspend@basic-s0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15605/fi-cml-u2/igt@gem_exec_suspend@basic-s0.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770r: [PASS][5] -> [DMESG-FAIL][6] ([i915#563])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7490/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15605/fi-hsw-4770r/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-byt-j1900: [PASS][7] -> [INCOMPLETE][8] ([i915#45])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7490/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15605/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
- fi-byt-n2820: [PASS][9] -> [DMESG-FAIL][10] ([i915#722])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7490/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15605/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][11] -> [FAIL][12] ([fdo#111096] / [i915#323])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7490/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15605/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_exec_gttfill@basic:
- {fi-tgl-guc}: [INCOMPLETE][13] ([fdo#111593]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7490/fi-tgl-guc/igt@gem_exec_gttfill@basic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15605/fi-tgl-guc/igt@gem_exec_gttfill@basic.html
* igt@gem_exec_parallel@basic:
- {fi-tgl-u}: [INCOMPLETE][15] ([i915#476]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7490/fi-tgl-u/igt@gem_exec_parallel@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15605/fi-tgl-u/igt@gem_exec_parallel@basic.html
* igt@i915_selftest@live_gem_contexts:
- fi-hsw-peppy: [INCOMPLETE][17] ([i915#694]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7490/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15605/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +9 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7490/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15605/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
* igt@kms_busy@basic-flip-pipe-b:
- fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7490/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-b.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15605/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476
[i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (53 -> 47)
------------------------------
Additional (1): fi-gdg-551
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7490 -> Patchwork_15605
CI-20190529: 20190529
CI_DRM_7490: 803ecbbe6117e981cb05e507a753711068a1e1d4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5333: e08522bb09ff1b9720359b3867da7e4aca0bd5f1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15605: 10d79292fa34b09c9c3364af30faa67b07d61dea @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
10d79292fa34 drm/i915/dsi: add support for DSC
871e85117950 drm/i915/dsi: account for DSC in horizontal timings
fea7c7f0cfdd drm/i915/dsi: use compressed pixel format with DSC
05891ad7d716 drm/i915/dsi: take compression into account in afe_clk()
7460bcfe7cab drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
bc6b5ae33239 drm/i915/dsi: abstract afe_clk calculation
23a2e041cf02 drm/i915/dsi: set pipe_bpp on ICL configure config
43d897f1d016 drm/i915/dsc: add support for computing and writing PPS for DSI encoders
59ce59912b93 drm/i915/dsc: move slice height calculation to encoder
121299cced8c drm/i915/dsc: move DP specific compute params to intel_dp.c
df83ffb4fe22 drm/i915/bios: add support for querying DSC details for encoder
7bbf115b2fe1 drm/i915/bios: parse compression parameters block
d1eac96f3ca9 drm/i915/bios: pass devdata to parse_ddi_port
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15605/index.html
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