* [PATCH 0/7] xen/arm: TLB flush helpers rework
@ 2019-04-17 17:58 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-17 17:58 UTC (permalink / raw)
To: xen-devel; +Cc: Oleksandr_Tyshchenko, Julien Grall, sstabellini, Andrii_Anisov
Hi all,
I spent the last few months looking at Xen boot and memory management to make
it simpler, more efficient and also more compliant in respect of the Arm Arm.
The full rework is quite consequence (already 150 patches and I haven't yet
finished!), so I am planning to send in smaller part over the next few weeks.
In this first part, I focus on reworking how we flush the TLBs in Xen.
Cheers,
Julien Grall (7):
xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place
xen/arm: Remove flush_xen_text_tlb_local()
xen/arm: tlbflush: Clarify the TLB helpers name
xen/arm: page: Clarify the Xen TLBs helpers name
xen/arm: Gather all TLB flush helpers in tlbflush.h
xen/arm: tlbflush: Rework TLB helpers
xen/arm: mm: Flush the TLBs even if a mapping failed in
create_xen_entries
xen/arch/arm/mm.c | 69 ++++++++++++++++++++++-----------
xen/arch/arm/p2m.c | 6 +--
xen/arch/arm/smp.c | 2 +-
xen/arch/arm/traps.c | 2 +-
xen/include/asm-arm/arm32/flushtlb.h | 71 +++++++++++++++++++---------------
xen/include/asm-arm/arm32/page.h | 48 ++++-------------------
xen/include/asm-arm/arm64/flushtlb.h | 75 ++++++++++++++++++++----------------
xen/include/asm-arm/arm64/page.h | 49 +++--------------------
xen/include/asm-arm/flushtlb.h | 38 ++++++++++++++++++
xen/include/asm-arm/page.h | 38 ------------------
10 files changed, 184 insertions(+), 214 deletions(-)
--
2.11.0
_______________________________________________
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https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Xen-devel] [PATCH 0/7] xen/arm: TLB flush helpers rework
@ 2019-04-17 17:58 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-17 17:58 UTC (permalink / raw)
To: xen-devel; +Cc: Oleksandr_Tyshchenko, Julien Grall, sstabellini, Andrii_Anisov
Hi all,
I spent the last few months looking at Xen boot and memory management to make
it simpler, more efficient and also more compliant in respect of the Arm Arm.
The full rework is quite consequence (already 150 patches and I haven't yet
finished!), so I am planning to send in smaller part over the next few weeks.
In this first part, I focus on reworking how we flush the TLBs in Xen.
Cheers,
Julien Grall (7):
xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place
xen/arm: Remove flush_xen_text_tlb_local()
xen/arm: tlbflush: Clarify the TLB helpers name
xen/arm: page: Clarify the Xen TLBs helpers name
xen/arm: Gather all TLB flush helpers in tlbflush.h
xen/arm: tlbflush: Rework TLB helpers
xen/arm: mm: Flush the TLBs even if a mapping failed in
create_xen_entries
xen/arch/arm/mm.c | 69 ++++++++++++++++++++++-----------
xen/arch/arm/p2m.c | 6 +--
xen/arch/arm/smp.c | 2 +-
xen/arch/arm/traps.c | 2 +-
xen/include/asm-arm/arm32/flushtlb.h | 71 +++++++++++++++++++---------------
xen/include/asm-arm/arm32/page.h | 48 ++++-------------------
xen/include/asm-arm/arm64/flushtlb.h | 75 ++++++++++++++++++++----------------
xen/include/asm-arm/arm64/page.h | 49 +++--------------------
xen/include/asm-arm/flushtlb.h | 38 ++++++++++++++++++
xen/include/asm-arm/page.h | 38 ------------------
10 files changed, 184 insertions(+), 214 deletions(-)
--
2.11.0
_______________________________________________
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Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 1/7] xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place
@ 2019-04-17 17:58 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-17 17:58 UTC (permalink / raw)
To: xen-devel; +Cc: Oleksandr_Tyshchenko, Julien Grall, sstabellini, Andrii_Anisov
The logic to set SCTLR_EL2.WXN is the same for the boot CPU and
non-boot CPU. So introduce a function to set the bit and clear TBLs.
This new function will help us to document and update the logic in a
single place.
Signed-off-by: Julien Grall <julien.grall@arm.com>
---
xen/arch/arm/mm.c | 22 +++++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
index 01ae2cccc0..93ad118183 100644
--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -601,6 +601,19 @@ void __init remove_early_mappings(void)
flush_xen_data_tlb_range_va(BOOT_FDT_VIRT_START, BOOT_FDT_SLOT_SIZE);
}
+/*
+ * After boot, Xen page-tables should not contain mapping that are both
+ * Writable and eXecutables.
+ *
+ * This should be called on each CPU to enforce the policy.
+ */
+static void xen_pt_enforce_wnx(void)
+{
+ WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
+ /* Flush everything after setting WXN bit. */
+ flush_xen_text_tlb_local();
+}
+
extern void switch_ttbr(uint64_t ttbr);
/* Clear a translation table and clean & invalidate the cache */
@@ -702,10 +715,7 @@ void __init setup_pagetables(unsigned long boot_phys_offset)
clear_table(boot_second);
clear_table(boot_third);
- /* From now on, no mapping may be both writable and executable. */
- WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
- /* Flush everything after setting WXN bit. */
- flush_xen_text_tlb_local();
+ xen_pt_enforce_wnx();
#ifdef CONFIG_ARM_32
per_cpu(xen_pgtable, 0) = cpu0_pgtable;
@@ -777,9 +787,7 @@ int init_secondary_pagetables(int cpu)
/* MMU setup for secondary CPUS (which already have paging enabled) */
void mmu_init_secondary_cpu(void)
{
- /* From now on, no mapping may be both writable and executable. */
- WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
- flush_xen_text_tlb_local();
+ xen_pt_enforce_wnx();
}
#ifdef CONFIG_ARM_32
--
2.11.0
_______________________________________________
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https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Xen-devel] [PATCH 1/7] xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place
@ 2019-04-17 17:58 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-17 17:58 UTC (permalink / raw)
To: xen-devel; +Cc: Oleksandr_Tyshchenko, Julien Grall, sstabellini, Andrii_Anisov
The logic to set SCTLR_EL2.WXN is the same for the boot CPU and
non-boot CPU. So introduce a function to set the bit and clear TBLs.
This new function will help us to document and update the logic in a
single place.
Signed-off-by: Julien Grall <julien.grall@arm.com>
---
xen/arch/arm/mm.c | 22 +++++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
index 01ae2cccc0..93ad118183 100644
--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -601,6 +601,19 @@ void __init remove_early_mappings(void)
flush_xen_data_tlb_range_va(BOOT_FDT_VIRT_START, BOOT_FDT_SLOT_SIZE);
}
+/*
+ * After boot, Xen page-tables should not contain mapping that are both
+ * Writable and eXecutables.
+ *
+ * This should be called on each CPU to enforce the policy.
+ */
+static void xen_pt_enforce_wnx(void)
+{
+ WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
+ /* Flush everything after setting WXN bit. */
+ flush_xen_text_tlb_local();
+}
+
extern void switch_ttbr(uint64_t ttbr);
/* Clear a translation table and clean & invalidate the cache */
@@ -702,10 +715,7 @@ void __init setup_pagetables(unsigned long boot_phys_offset)
clear_table(boot_second);
clear_table(boot_third);
- /* From now on, no mapping may be both writable and executable. */
- WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
- /* Flush everything after setting WXN bit. */
- flush_xen_text_tlb_local();
+ xen_pt_enforce_wnx();
#ifdef CONFIG_ARM_32
per_cpu(xen_pgtable, 0) = cpu0_pgtable;
@@ -777,9 +787,7 @@ int init_secondary_pagetables(int cpu)
/* MMU setup for secondary CPUS (which already have paging enabled) */
void mmu_init_secondary_cpu(void)
{
- /* From now on, no mapping may be both writable and executable. */
- WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
- flush_xen_text_tlb_local();
+ xen_pt_enforce_wnx();
}
#ifdef CONFIG_ARM_32
--
2.11.0
_______________________________________________
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Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 2/7] xen/arm: Remove flush_xen_text_tlb_local()
@ 2019-04-17 17:58 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-17 17:58 UTC (permalink / raw)
To: xen-devel; +Cc: Oleksandr_Tyshchenko, Julien Grall, sstabellini, Andrii_Anisov
The function flush_xen_text_tlb_local() has been misused and will result
to invalidate the instruction cache more than necessary.
For instance, there are no need to invalidate the instruction cache if
we are setting SCTLR_EL2.WXN.
There are effectively only one caller (i.e free_init_memory() would
who need to invalidate the instruction cache.
So rather than keeping around the function flush_xen_text_tlb_local()
around, replace it with call to flush_xen_tlb_local() and explicitely
flush the cache when necessary.
Signed-off-by: Julien Grall <julien.grall@arm.com>
---
xen/arch/arm/mm.c | 17 ++++++++++++++---
xen/include/asm-arm/arm32/page.h | 23 +++++++++--------------
xen/include/asm-arm/arm64/page.h | 21 +++++----------------
3 files changed, 28 insertions(+), 33 deletions(-)
diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
index 93ad118183..dfbe39c70a 100644
--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -610,8 +610,12 @@ void __init remove_early_mappings(void)
static void xen_pt_enforce_wnx(void)
{
WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
- /* Flush everything after setting WXN bit. */
- flush_xen_text_tlb_local();
+ /*
+ * The TLBs may cache SCTLR_EL2.WXN. So ensure it is synchronized
+ * before flushing the TLBs.
+ */
+ isb();
+ flush_xen_data_tlb_local();
}
extern void switch_ttbr(uint64_t ttbr);
@@ -1123,7 +1127,7 @@ static void set_pte_flags_on_range(const char *p, unsigned long l, enum mg mg)
}
write_pte(xen_xenmap + i, pte);
}
- flush_xen_text_tlb_local();
+ flush_xen_data_tlb_local();
}
/* Release all __init and __initdata ranges to be reused */
@@ -1136,6 +1140,13 @@ void free_init_memory(void)
uint32_t *p;
set_pte_flags_on_range(__init_begin, len, mg_rw);
+
+ /*
+ * From now on, init will not be used for execution anymore,
+ * so nuke the instruction cache to remove entries related to init.
+ */
+ invalidate_icache_local();
+
#ifdef CONFIG_ARM_32
/* udf instruction i.e (see A8.8.247 in ARM DDI 0406C.c) */
insn = 0xe7f000f0;
diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h
index ea4b312c70..40a77daa9d 100644
--- a/xen/include/asm-arm/arm32/page.h
+++ b/xen/include/asm-arm/arm32/page.h
@@ -46,24 +46,19 @@ static inline void invalidate_icache(void)
}
/*
- * Flush all hypervisor mappings from the TLB and branch predictor of
- * the local processor.
- *
- * This is needed after changing Xen code mappings.
- *
- * The caller needs to issue the necessary DSB and D-cache flushes
- * before calling flush_xen_text_tlb.
+ * Invalidate all instruction caches on the local processor to PoU.
+ * We also need to flush the branch predictor for ARMv7 as it may be
+ * architecturally visible to the software (see B2.2.4 in ARM DDI 0406C.b).
*/
-static inline void flush_xen_text_tlb_local(void)
+static inline void invalidate_icache_local(void)
{
asm volatile (
- "isb;" /* Ensure synchronization with previous changes to text */
- CMD_CP32(TLBIALLH) /* Flush hypervisor TLB */
- CMD_CP32(ICIALLU) /* Flush I-cache */
- CMD_CP32(BPIALL) /* Flush branch predictor */
- "dsb;" /* Ensure completion of TLB+BP flush */
- "isb;"
+ CMD_CP32(ICIALLU) /* Flush I-cache. */
+ CMD_CP32(BPIALL) /* Flush branch predictor. */
: : : "memory");
+
+ dsb(nsh); /* Ensure completion of the flush I-cache */
+ isb(); /* Synchronize fetched instruction stream. */
}
/*
diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h
index 23d778154d..6c36d0210f 100644
--- a/xen/include/asm-arm/arm64/page.h
+++ b/xen/include/asm-arm/arm64/page.h
@@ -37,23 +37,12 @@ static inline void invalidate_icache(void)
isb();
}
-/*
- * Flush all hypervisor mappings from the TLB of the local processor.
- *
- * This is needed after changing Xen code mappings.
- *
- * The caller needs to issue the necessary DSB and D-cache flushes
- * before calling flush_xen_text_tlb.
- */
-static inline void flush_xen_text_tlb_local(void)
+/* Invalidate all instruction caches on the local processor to PoU */
+static inline void invalidate_icache_local(void)
{
- asm volatile (
- "isb;" /* Ensure synchronization with previous changes to text */
- "tlbi alle2;" /* Flush hypervisor TLB */
- "ic iallu;" /* Flush I-cache */
- "dsb sy;" /* Ensure completion of TLB flush */
- "isb;"
- : : : "memory");
+ asm volatile ("ic iallu");
+ dsb(nsh); /* Ensure completion of the I-cache flush */
+ isb();
}
/*
--
2.11.0
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^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Xen-devel] [PATCH 2/7] xen/arm: Remove flush_xen_text_tlb_local()
@ 2019-04-17 17:58 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-17 17:58 UTC (permalink / raw)
To: xen-devel; +Cc: Oleksandr_Tyshchenko, Julien Grall, sstabellini, Andrii_Anisov
The function flush_xen_text_tlb_local() has been misused and will result
to invalidate the instruction cache more than necessary.
For instance, there are no need to invalidate the instruction cache if
we are setting SCTLR_EL2.WXN.
There are effectively only one caller (i.e free_init_memory() would
who need to invalidate the instruction cache.
So rather than keeping around the function flush_xen_text_tlb_local()
around, replace it with call to flush_xen_tlb_local() and explicitely
flush the cache when necessary.
Signed-off-by: Julien Grall <julien.grall@arm.com>
---
xen/arch/arm/mm.c | 17 ++++++++++++++---
xen/include/asm-arm/arm32/page.h | 23 +++++++++--------------
xen/include/asm-arm/arm64/page.h | 21 +++++----------------
3 files changed, 28 insertions(+), 33 deletions(-)
diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
index 93ad118183..dfbe39c70a 100644
--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -610,8 +610,12 @@ void __init remove_early_mappings(void)
static void xen_pt_enforce_wnx(void)
{
WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
- /* Flush everything after setting WXN bit. */
- flush_xen_text_tlb_local();
+ /*
+ * The TLBs may cache SCTLR_EL2.WXN. So ensure it is synchronized
+ * before flushing the TLBs.
+ */
+ isb();
+ flush_xen_data_tlb_local();
}
extern void switch_ttbr(uint64_t ttbr);
@@ -1123,7 +1127,7 @@ static void set_pte_flags_on_range(const char *p, unsigned long l, enum mg mg)
}
write_pte(xen_xenmap + i, pte);
}
- flush_xen_text_tlb_local();
+ flush_xen_data_tlb_local();
}
/* Release all __init and __initdata ranges to be reused */
@@ -1136,6 +1140,13 @@ void free_init_memory(void)
uint32_t *p;
set_pte_flags_on_range(__init_begin, len, mg_rw);
+
+ /*
+ * From now on, init will not be used for execution anymore,
+ * so nuke the instruction cache to remove entries related to init.
+ */
+ invalidate_icache_local();
+
#ifdef CONFIG_ARM_32
/* udf instruction i.e (see A8.8.247 in ARM DDI 0406C.c) */
insn = 0xe7f000f0;
diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h
index ea4b312c70..40a77daa9d 100644
--- a/xen/include/asm-arm/arm32/page.h
+++ b/xen/include/asm-arm/arm32/page.h
@@ -46,24 +46,19 @@ static inline void invalidate_icache(void)
}
/*
- * Flush all hypervisor mappings from the TLB and branch predictor of
- * the local processor.
- *
- * This is needed after changing Xen code mappings.
- *
- * The caller needs to issue the necessary DSB and D-cache flushes
- * before calling flush_xen_text_tlb.
+ * Invalidate all instruction caches on the local processor to PoU.
+ * We also need to flush the branch predictor for ARMv7 as it may be
+ * architecturally visible to the software (see B2.2.4 in ARM DDI 0406C.b).
*/
-static inline void flush_xen_text_tlb_local(void)
+static inline void invalidate_icache_local(void)
{
asm volatile (
- "isb;" /* Ensure synchronization with previous changes to text */
- CMD_CP32(TLBIALLH) /* Flush hypervisor TLB */
- CMD_CP32(ICIALLU) /* Flush I-cache */
- CMD_CP32(BPIALL) /* Flush branch predictor */
- "dsb;" /* Ensure completion of TLB+BP flush */
- "isb;"
+ CMD_CP32(ICIALLU) /* Flush I-cache. */
+ CMD_CP32(BPIALL) /* Flush branch predictor. */
: : : "memory");
+
+ dsb(nsh); /* Ensure completion of the flush I-cache */
+ isb(); /* Synchronize fetched instruction stream. */
}
/*
diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h
index 23d778154d..6c36d0210f 100644
--- a/xen/include/asm-arm/arm64/page.h
+++ b/xen/include/asm-arm/arm64/page.h
@@ -37,23 +37,12 @@ static inline void invalidate_icache(void)
isb();
}
-/*
- * Flush all hypervisor mappings from the TLB of the local processor.
- *
- * This is needed after changing Xen code mappings.
- *
- * The caller needs to issue the necessary DSB and D-cache flushes
- * before calling flush_xen_text_tlb.
- */
-static inline void flush_xen_text_tlb_local(void)
+/* Invalidate all instruction caches on the local processor to PoU */
+static inline void invalidate_icache_local(void)
{
- asm volatile (
- "isb;" /* Ensure synchronization with previous changes to text */
- "tlbi alle2;" /* Flush hypervisor TLB */
- "ic iallu;" /* Flush I-cache */
- "dsb sy;" /* Ensure completion of TLB flush */
- "isb;"
- : : : "memory");
+ asm volatile ("ic iallu");
+ dsb(nsh); /* Ensure completion of the I-cache flush */
+ isb();
}
/*
--
2.11.0
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^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 3/7] xen/arm: tlbflush: Clarify the TLB helpers name
@ 2019-04-17 17:58 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-17 17:58 UTC (permalink / raw)
To: xen-devel; +Cc: Oleksandr_Tyshchenko, Julien Grall, sstabellini, Andrii_Anisov
TLB helpers in the headers tlbflush.h are currently quite confusing to
use the name may lead to think they are dealing with hypervisors TLBs
while they actually deal with guest TLBs.
Rename them to make it clearer that we are dealing with guest TLBs.
Signed-off-by: Julien Grall <julien.grall@arm.com>
---
xen/arch/arm/p2m.c | 6 +++---
xen/arch/arm/smp.c | 2 +-
xen/arch/arm/traps.c | 2 +-
xen/include/asm-arm/arm32/flushtlb.h | 8 ++++----
xen/include/asm-arm/arm64/flushtlb.h | 8 ++++----
5 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c
index c38bd7e16e..92c2413f20 100644
--- a/xen/arch/arm/p2m.c
+++ b/xen/arch/arm/p2m.c
@@ -151,7 +151,7 @@ void p2m_restore_state(struct vcpu *n)
* when running multiple vCPU of the same domain on a single pCPU.
*/
if ( *last_vcpu_ran != INVALID_VCPU_ID && *last_vcpu_ran != n->vcpu_id )
- flush_tlb_local();
+ flush_guest_tlb_local();
*last_vcpu_ran = n->vcpu_id;
}
@@ -196,7 +196,7 @@ static void p2m_force_tlb_flush_sync(struct p2m_domain *p2m)
isb();
}
- flush_tlb();
+ flush_guest_tlb();
if ( ovttbr != READ_SYSREG64(VTTBR_EL2) )
{
@@ -1969,7 +1969,7 @@ static void setup_virt_paging_one(void *data)
WRITE_SYSREG(READ_SYSREG(HCR_EL2) | HCR_VM, HCR_EL2);
isb();
- flush_tlb_all_local();
+ flush_all_guests_tlb_local();
}
}
diff --git a/xen/arch/arm/smp.c b/xen/arch/arm/smp.c
index 62f57f0ba2..ce1fcc8ef9 100644
--- a/xen/arch/arm/smp.c
+++ b/xen/arch/arm/smp.c
@@ -8,7 +8,7 @@
void flush_tlb_mask(const cpumask_t *mask)
{
/* No need to IPI other processors on ARM, the processor takes care of it. */
- flush_tlb_all();
+ flush_all_guests_tlb();
}
void smp_send_event_check_mask(const cpumask_t *mask)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index d8b9a8a0f0..1aba970415 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -1924,7 +1924,7 @@ static void do_trap_stage2_abort_guest(struct cpu_user_regs *regs,
* still be inaccurate.
*/
if ( !is_data )
- flush_tlb_local();
+ flush_guest_tlb_local();
rc = gva_to_ipa(gva, &gpa, GV2M_READ);
/*
diff --git a/xen/include/asm-arm/arm32/flushtlb.h b/xen/include/asm-arm/arm32/flushtlb.h
index bbcc82f490..22e100eccf 100644
--- a/xen/include/asm-arm/arm32/flushtlb.h
+++ b/xen/include/asm-arm/arm32/flushtlb.h
@@ -2,7 +2,7 @@
#define __ASM_ARM_ARM32_FLUSHTLB_H__
/* Flush local TLBs, current VMID only */
-static inline void flush_tlb_local(void)
+static inline void flush_guest_tlb_local(void)
{
dsb(sy);
@@ -13,7 +13,7 @@ static inline void flush_tlb_local(void)
}
/* Flush inner shareable TLBs, current VMID only */
-static inline void flush_tlb(void)
+static inline void flush_guest_tlb(void)
{
dsb(sy);
@@ -24,7 +24,7 @@ static inline void flush_tlb(void)
}
/* Flush local TLBs, all VMIDs, non-hypervisor mode */
-static inline void flush_tlb_all_local(void)
+static inline void flush_all_guests_tlb_local(void)
{
dsb(sy);
@@ -35,7 +35,7 @@ static inline void flush_tlb_all_local(void)
}
/* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */
-static inline void flush_tlb_all(void)
+static inline void flush_all_guests_tlb(void)
{
dsb(sy);
diff --git a/xen/include/asm-arm/arm64/flushtlb.h b/xen/include/asm-arm/arm64/flushtlb.h
index 942f2d3992..adbbd5c522 100644
--- a/xen/include/asm-arm/arm64/flushtlb.h
+++ b/xen/include/asm-arm/arm64/flushtlb.h
@@ -2,7 +2,7 @@
#define __ASM_ARM_ARM64_FLUSHTLB_H__
/* Flush local TLBs, current VMID only */
-static inline void flush_tlb_local(void)
+static inline void flush_guest_tlb_local(void)
{
asm volatile(
"dsb sy;"
@@ -13,7 +13,7 @@ static inline void flush_tlb_local(void)
}
/* Flush innershareable TLBs, current VMID only */
-static inline void flush_tlb(void)
+static inline void flush_guest_tlb(void)
{
asm volatile(
"dsb sy;"
@@ -24,7 +24,7 @@ static inline void flush_tlb(void)
}
/* Flush local TLBs, all VMIDs, non-hypervisor mode */
-static inline void flush_tlb_all_local(void)
+static inline void flush_all_guests_tlb_local(void)
{
asm volatile(
"dsb sy;"
@@ -35,7 +35,7 @@ static inline void flush_tlb_all_local(void)
}
/* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */
-static inline void flush_tlb_all(void)
+static inline void flush_all_guests_tlb(void)
{
asm volatile(
"dsb sy;"
--
2.11.0
_______________________________________________
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Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Xen-devel] [PATCH 3/7] xen/arm: tlbflush: Clarify the TLB helpers name
@ 2019-04-17 17:58 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-17 17:58 UTC (permalink / raw)
To: xen-devel; +Cc: Oleksandr_Tyshchenko, Julien Grall, sstabellini, Andrii_Anisov
TLB helpers in the headers tlbflush.h are currently quite confusing to
use the name may lead to think they are dealing with hypervisors TLBs
while they actually deal with guest TLBs.
Rename them to make it clearer that we are dealing with guest TLBs.
Signed-off-by: Julien Grall <julien.grall@arm.com>
---
xen/arch/arm/p2m.c | 6 +++---
xen/arch/arm/smp.c | 2 +-
xen/arch/arm/traps.c | 2 +-
xen/include/asm-arm/arm32/flushtlb.h | 8 ++++----
xen/include/asm-arm/arm64/flushtlb.h | 8 ++++----
5 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c
index c38bd7e16e..92c2413f20 100644
--- a/xen/arch/arm/p2m.c
+++ b/xen/arch/arm/p2m.c
@@ -151,7 +151,7 @@ void p2m_restore_state(struct vcpu *n)
* when running multiple vCPU of the same domain on a single pCPU.
*/
if ( *last_vcpu_ran != INVALID_VCPU_ID && *last_vcpu_ran != n->vcpu_id )
- flush_tlb_local();
+ flush_guest_tlb_local();
*last_vcpu_ran = n->vcpu_id;
}
@@ -196,7 +196,7 @@ static void p2m_force_tlb_flush_sync(struct p2m_domain *p2m)
isb();
}
- flush_tlb();
+ flush_guest_tlb();
if ( ovttbr != READ_SYSREG64(VTTBR_EL2) )
{
@@ -1969,7 +1969,7 @@ static void setup_virt_paging_one(void *data)
WRITE_SYSREG(READ_SYSREG(HCR_EL2) | HCR_VM, HCR_EL2);
isb();
- flush_tlb_all_local();
+ flush_all_guests_tlb_local();
}
}
diff --git a/xen/arch/arm/smp.c b/xen/arch/arm/smp.c
index 62f57f0ba2..ce1fcc8ef9 100644
--- a/xen/arch/arm/smp.c
+++ b/xen/arch/arm/smp.c
@@ -8,7 +8,7 @@
void flush_tlb_mask(const cpumask_t *mask)
{
/* No need to IPI other processors on ARM, the processor takes care of it. */
- flush_tlb_all();
+ flush_all_guests_tlb();
}
void smp_send_event_check_mask(const cpumask_t *mask)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index d8b9a8a0f0..1aba970415 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -1924,7 +1924,7 @@ static void do_trap_stage2_abort_guest(struct cpu_user_regs *regs,
* still be inaccurate.
*/
if ( !is_data )
- flush_tlb_local();
+ flush_guest_tlb_local();
rc = gva_to_ipa(gva, &gpa, GV2M_READ);
/*
diff --git a/xen/include/asm-arm/arm32/flushtlb.h b/xen/include/asm-arm/arm32/flushtlb.h
index bbcc82f490..22e100eccf 100644
--- a/xen/include/asm-arm/arm32/flushtlb.h
+++ b/xen/include/asm-arm/arm32/flushtlb.h
@@ -2,7 +2,7 @@
#define __ASM_ARM_ARM32_FLUSHTLB_H__
/* Flush local TLBs, current VMID only */
-static inline void flush_tlb_local(void)
+static inline void flush_guest_tlb_local(void)
{
dsb(sy);
@@ -13,7 +13,7 @@ static inline void flush_tlb_local(void)
}
/* Flush inner shareable TLBs, current VMID only */
-static inline void flush_tlb(void)
+static inline void flush_guest_tlb(void)
{
dsb(sy);
@@ -24,7 +24,7 @@ static inline void flush_tlb(void)
}
/* Flush local TLBs, all VMIDs, non-hypervisor mode */
-static inline void flush_tlb_all_local(void)
+static inline void flush_all_guests_tlb_local(void)
{
dsb(sy);
@@ -35,7 +35,7 @@ static inline void flush_tlb_all_local(void)
}
/* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */
-static inline void flush_tlb_all(void)
+static inline void flush_all_guests_tlb(void)
{
dsb(sy);
diff --git a/xen/include/asm-arm/arm64/flushtlb.h b/xen/include/asm-arm/arm64/flushtlb.h
index 942f2d3992..adbbd5c522 100644
--- a/xen/include/asm-arm/arm64/flushtlb.h
+++ b/xen/include/asm-arm/arm64/flushtlb.h
@@ -2,7 +2,7 @@
#define __ASM_ARM_ARM64_FLUSHTLB_H__
/* Flush local TLBs, current VMID only */
-static inline void flush_tlb_local(void)
+static inline void flush_guest_tlb_local(void)
{
asm volatile(
"dsb sy;"
@@ -13,7 +13,7 @@ static inline void flush_tlb_local(void)
}
/* Flush innershareable TLBs, current VMID only */
-static inline void flush_tlb(void)
+static inline void flush_guest_tlb(void)
{
asm volatile(
"dsb sy;"
@@ -24,7 +24,7 @@ static inline void flush_tlb(void)
}
/* Flush local TLBs, all VMIDs, non-hypervisor mode */
-static inline void flush_tlb_all_local(void)
+static inline void flush_all_guests_tlb_local(void)
{
asm volatile(
"dsb sy;"
@@ -35,7 +35,7 @@ static inline void flush_tlb_all_local(void)
}
/* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */
-static inline void flush_tlb_all(void)
+static inline void flush_all_guests_tlb(void)
{
asm volatile(
"dsb sy;"
--
2.11.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 4/7] xen/arm: page: Clarify the Xen TLBs helpers name
@ 2019-04-17 17:58 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-17 17:58 UTC (permalink / raw)
To: xen-devel; +Cc: Oleksandr_Tyshchenko, Julien Grall, sstabellini, Andrii_Anisov
Now that we dropped flush_xen_text_tlb_local(), we have only one set of
helpers acting on Xen TLBs. There naming are quite confusing because the
TLB instructions used will act on both Data and Instruction TLBs.
Take the opportunity to rework the documentation that can be confusing
to read as they don't match the implementation.
Lastly, switch from unsigned lont to vaddr_t as the function technically
deal with virtual address.
Signed-off-by: Julien Grall <julien.grall@arm.com>
---
xen/arch/arm/mm.c | 18 +++++++++---------
xen/include/asm-arm/arm32/page.h | 15 +++++----------
xen/include/asm-arm/arm64/page.h | 15 +++++----------
xen/include/asm-arm/page.h | 28 ++++++++++++++--------------
4 files changed, 33 insertions(+), 43 deletions(-)
diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
index dfbe39c70a..8ee828d445 100644
--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -335,7 +335,7 @@ void set_fixmap(unsigned map, mfn_t mfn, unsigned int flags)
pte.pt.table = 1; /* 4k mappings always have this bit set */
pte.pt.xn = 1;
write_pte(xen_fixmap + third_table_offset(FIXMAP_ADDR(map)), pte);
- flush_xen_data_tlb_range_va(FIXMAP_ADDR(map), PAGE_SIZE);
+ flush_xen_tlb_range_va(FIXMAP_ADDR(map), PAGE_SIZE);
}
/* Remove a mapping from a fixmap entry */
@@ -343,7 +343,7 @@ void clear_fixmap(unsigned map)
{
lpae_t pte = {0};
write_pte(xen_fixmap + third_table_offset(FIXMAP_ADDR(map)), pte);
- flush_xen_data_tlb_range_va(FIXMAP_ADDR(map), PAGE_SIZE);
+ flush_xen_tlb_range_va(FIXMAP_ADDR(map), PAGE_SIZE);
}
/* Create Xen's mappings of memory.
@@ -377,7 +377,7 @@ static void __init create_mappings(lpae_t *second,
write_pte(p + i, pte);
pte.pt.base += 1 << LPAE_SHIFT;
}
- flush_xen_data_tlb_local();
+ flush_xen_tlb_local();
}
#ifdef CONFIG_DOMAIN_PAGE
@@ -455,7 +455,7 @@ void *map_domain_page(mfn_t mfn)
* We may not have flushed this specific subpage at map time,
* since we only flush the 4k page not the superpage
*/
- flush_xen_data_tlb_range_va_local(va, PAGE_SIZE);
+ flush_xen_tlb_range_va_local(va, PAGE_SIZE);
return (void *)va;
}
@@ -598,7 +598,7 @@ void __init remove_early_mappings(void)
write_pte(xen_second + second_table_offset(BOOT_FDT_VIRT_START), pte);
write_pte(xen_second + second_table_offset(BOOT_FDT_VIRT_START + SZ_2M),
pte);
- flush_xen_data_tlb_range_va(BOOT_FDT_VIRT_START, BOOT_FDT_SLOT_SIZE);
+ flush_xen_tlb_range_va(BOOT_FDT_VIRT_START, BOOT_FDT_SLOT_SIZE);
}
/*
@@ -615,7 +615,7 @@ static void xen_pt_enforce_wnx(void)
* before flushing the TLBs.
*/
isb();
- flush_xen_data_tlb_local();
+ flush_xen_tlb_local();
}
extern void switch_ttbr(uint64_t ttbr);
@@ -879,7 +879,7 @@ void __init setup_xenheap_mappings(unsigned long base_mfn,
vaddr += FIRST_SIZE;
}
- flush_xen_data_tlb_local();
+ flush_xen_tlb_local();
}
#endif
@@ -1052,7 +1052,7 @@ static int create_xen_entries(enum xenmap_operation op,
BUG();
}
}
- flush_xen_data_tlb_range_va(virt, PAGE_SIZE * nr_mfns);
+ flush_xen_tlb_range_va(virt, PAGE_SIZE * nr_mfns);
rc = 0;
@@ -1127,7 +1127,7 @@ static void set_pte_flags_on_range(const char *p, unsigned long l, enum mg mg)
}
write_pte(xen_xenmap + i, pte);
}
- flush_xen_data_tlb_local();
+ flush_xen_tlb_local();
}
/* Release all __init and __initdata ranges to be reused */
diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h
index 40a77daa9d..0b41b9214b 100644
--- a/xen/include/asm-arm/arm32/page.h
+++ b/xen/include/asm-arm/arm32/page.h
@@ -61,12 +61,8 @@ static inline void invalidate_icache_local(void)
isb(); /* Synchronize fetched instruction stream. */
}
-/*
- * Flush all hypervisor mappings from the data TLB of the local
- * processor. This is not sufficient when changing code mappings or
- * for self modifying code.
- */
-static inline void flush_xen_data_tlb_local(void)
+/* Flush all hypervisor mappings from the TLB of the local processor. */
+static inline void flush_xen_tlb_local(void)
{
asm volatile("dsb;" /* Ensure preceding are visible */
CMD_CP32(TLBIALLH)
@@ -76,14 +72,13 @@ static inline void flush_xen_data_tlb_local(void)
}
/* Flush TLB of local processor for address va. */
-static inline void __flush_xen_data_tlb_one_local(vaddr_t va)
+static inline void __flush_xen_tlb_one_local(vaddr_t va)
{
asm volatile(STORE_CP32(0, TLBIMVAH) : : "r" (va) : "memory");
}
-/* Flush TLB of all processors in the inner-shareable domain for
- * address va. */
-static inline void __flush_xen_data_tlb_one(vaddr_t va)
+/* Flush TLB of all processors in the inner-shareable domain for address va. */
+static inline void __flush_xen_tlb_one(vaddr_t va)
{
asm volatile(STORE_CP32(0, TLBIMVAHIS) : : "r" (va) : "memory");
}
diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h
index 6c36d0210f..31d04ecf76 100644
--- a/xen/include/asm-arm/arm64/page.h
+++ b/xen/include/asm-arm/arm64/page.h
@@ -45,12 +45,8 @@ static inline void invalidate_icache_local(void)
isb();
}
-/*
- * Flush all hypervisor mappings from the data TLB of the local
- * processor. This is not sufficient when changing code mappings or
- * for self modifying code.
- */
-static inline void flush_xen_data_tlb_local(void)
+/* Flush all hypervisor mappings from the TLB of the local processor. */
+static inline void flush_xen_tlb_local(void)
{
asm volatile (
"dsb sy;" /* Ensure visibility of PTE writes */
@@ -61,14 +57,13 @@ static inline void flush_xen_data_tlb_local(void)
}
/* Flush TLB of local processor for address va. */
-static inline void __flush_xen_data_tlb_one_local(vaddr_t va)
+static inline void __flush_xen_tlb_one_local(vaddr_t va)
{
asm volatile("tlbi vae2, %0;" : : "r" (va>>PAGE_SHIFT) : "memory");
}
-/* Flush TLB of all processors in the inner-shareable domain for
- * address va. */
-static inline void __flush_xen_data_tlb_one(vaddr_t va)
+/* Flush TLB of all processors in the inner-shareable domain for address va. */
+static inline void __flush_xen_tlb_one(vaddr_t va)
{
asm volatile("tlbi vae2is, %0;" : : "r" (va>>PAGE_SHIFT) : "memory");
}
diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h
index 1a1713ce02..195345e24a 100644
--- a/xen/include/asm-arm/page.h
+++ b/xen/include/asm-arm/page.h
@@ -234,18 +234,18 @@ static inline int clean_and_invalidate_dcache_va_range
} while (0)
/*
- * Flush a range of VA's hypervisor mappings from the data TLB of the
- * local processor. This is not sufficient when changing code mappings
- * or for self modifying code.
+ * Flush a range of VA's hypervisor mappings from the TLB of the local
+ * processor.
*/
-static inline void flush_xen_data_tlb_range_va_local(unsigned long va,
- unsigned long size)
+static inline void flush_xen_tlb_range_va_local(vaddr_t va,
+ unsigned long size)
{
- unsigned long end = va + size;
+ vaddr_t end = va + size;
+
dsb(sy); /* Ensure preceding are visible */
while ( va < end )
{
- __flush_xen_data_tlb_one_local(va);
+ __flush_xen_tlb_one_local(va);
va += PAGE_SIZE;
}
dsb(sy); /* Ensure completion of the TLB flush */
@@ -253,18 +253,18 @@ static inline void flush_xen_data_tlb_range_va_local(unsigned long va,
}
/*
- * Flush a range of VA's hypervisor mappings from the data TLB of all
- * processors in the inner-shareable domain. This is not sufficient
- * when changing code mappings or for self modifying code.
+ * Flush a range of VA's hypervisor mappings from the TLB of all
+ * processors in the inner-shareable domain.
*/
-static inline void flush_xen_data_tlb_range_va(unsigned long va,
- unsigned long size)
+static inline void flush_xen_tlb_range_va(vaddr_t va,
+ unsigned long size)
{
- unsigned long end = va + size;
+ vaddr_t end = va + size;
+
dsb(sy); /* Ensure preceding are visible */
while ( va < end )
{
- __flush_xen_data_tlb_one(va);
+ __flush_xen_tlb_one(va);
va += PAGE_SIZE;
}
dsb(sy); /* Ensure completion of the TLB flush */
--
2.11.0
_______________________________________________
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Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Xen-devel] [PATCH 4/7] xen/arm: page: Clarify the Xen TLBs helpers name
@ 2019-04-17 17:58 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-17 17:58 UTC (permalink / raw)
To: xen-devel; +Cc: Oleksandr_Tyshchenko, Julien Grall, sstabellini, Andrii_Anisov
Now that we dropped flush_xen_text_tlb_local(), we have only one set of
helpers acting on Xen TLBs. There naming are quite confusing because the
TLB instructions used will act on both Data and Instruction TLBs.
Take the opportunity to rework the documentation that can be confusing
to read as they don't match the implementation.
Lastly, switch from unsigned lont to vaddr_t as the function technically
deal with virtual address.
Signed-off-by: Julien Grall <julien.grall@arm.com>
---
xen/arch/arm/mm.c | 18 +++++++++---------
xen/include/asm-arm/arm32/page.h | 15 +++++----------
xen/include/asm-arm/arm64/page.h | 15 +++++----------
xen/include/asm-arm/page.h | 28 ++++++++++++++--------------
4 files changed, 33 insertions(+), 43 deletions(-)
diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
index dfbe39c70a..8ee828d445 100644
--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -335,7 +335,7 @@ void set_fixmap(unsigned map, mfn_t mfn, unsigned int flags)
pte.pt.table = 1; /* 4k mappings always have this bit set */
pte.pt.xn = 1;
write_pte(xen_fixmap + third_table_offset(FIXMAP_ADDR(map)), pte);
- flush_xen_data_tlb_range_va(FIXMAP_ADDR(map), PAGE_SIZE);
+ flush_xen_tlb_range_va(FIXMAP_ADDR(map), PAGE_SIZE);
}
/* Remove a mapping from a fixmap entry */
@@ -343,7 +343,7 @@ void clear_fixmap(unsigned map)
{
lpae_t pte = {0};
write_pte(xen_fixmap + third_table_offset(FIXMAP_ADDR(map)), pte);
- flush_xen_data_tlb_range_va(FIXMAP_ADDR(map), PAGE_SIZE);
+ flush_xen_tlb_range_va(FIXMAP_ADDR(map), PAGE_SIZE);
}
/* Create Xen's mappings of memory.
@@ -377,7 +377,7 @@ static void __init create_mappings(lpae_t *second,
write_pte(p + i, pte);
pte.pt.base += 1 << LPAE_SHIFT;
}
- flush_xen_data_tlb_local();
+ flush_xen_tlb_local();
}
#ifdef CONFIG_DOMAIN_PAGE
@@ -455,7 +455,7 @@ void *map_domain_page(mfn_t mfn)
* We may not have flushed this specific subpage at map time,
* since we only flush the 4k page not the superpage
*/
- flush_xen_data_tlb_range_va_local(va, PAGE_SIZE);
+ flush_xen_tlb_range_va_local(va, PAGE_SIZE);
return (void *)va;
}
@@ -598,7 +598,7 @@ void __init remove_early_mappings(void)
write_pte(xen_second + second_table_offset(BOOT_FDT_VIRT_START), pte);
write_pte(xen_second + second_table_offset(BOOT_FDT_VIRT_START + SZ_2M),
pte);
- flush_xen_data_tlb_range_va(BOOT_FDT_VIRT_START, BOOT_FDT_SLOT_SIZE);
+ flush_xen_tlb_range_va(BOOT_FDT_VIRT_START, BOOT_FDT_SLOT_SIZE);
}
/*
@@ -615,7 +615,7 @@ static void xen_pt_enforce_wnx(void)
* before flushing the TLBs.
*/
isb();
- flush_xen_data_tlb_local();
+ flush_xen_tlb_local();
}
extern void switch_ttbr(uint64_t ttbr);
@@ -879,7 +879,7 @@ void __init setup_xenheap_mappings(unsigned long base_mfn,
vaddr += FIRST_SIZE;
}
- flush_xen_data_tlb_local();
+ flush_xen_tlb_local();
}
#endif
@@ -1052,7 +1052,7 @@ static int create_xen_entries(enum xenmap_operation op,
BUG();
}
}
- flush_xen_data_tlb_range_va(virt, PAGE_SIZE * nr_mfns);
+ flush_xen_tlb_range_va(virt, PAGE_SIZE * nr_mfns);
rc = 0;
@@ -1127,7 +1127,7 @@ static void set_pte_flags_on_range(const char *p, unsigned long l, enum mg mg)
}
write_pte(xen_xenmap + i, pte);
}
- flush_xen_data_tlb_local();
+ flush_xen_tlb_local();
}
/* Release all __init and __initdata ranges to be reused */
diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h
index 40a77daa9d..0b41b9214b 100644
--- a/xen/include/asm-arm/arm32/page.h
+++ b/xen/include/asm-arm/arm32/page.h
@@ -61,12 +61,8 @@ static inline void invalidate_icache_local(void)
isb(); /* Synchronize fetched instruction stream. */
}
-/*
- * Flush all hypervisor mappings from the data TLB of the local
- * processor. This is not sufficient when changing code mappings or
- * for self modifying code.
- */
-static inline void flush_xen_data_tlb_local(void)
+/* Flush all hypervisor mappings from the TLB of the local processor. */
+static inline void flush_xen_tlb_local(void)
{
asm volatile("dsb;" /* Ensure preceding are visible */
CMD_CP32(TLBIALLH)
@@ -76,14 +72,13 @@ static inline void flush_xen_data_tlb_local(void)
}
/* Flush TLB of local processor for address va. */
-static inline void __flush_xen_data_tlb_one_local(vaddr_t va)
+static inline void __flush_xen_tlb_one_local(vaddr_t va)
{
asm volatile(STORE_CP32(0, TLBIMVAH) : : "r" (va) : "memory");
}
-/* Flush TLB of all processors in the inner-shareable domain for
- * address va. */
-static inline void __flush_xen_data_tlb_one(vaddr_t va)
+/* Flush TLB of all processors in the inner-shareable domain for address va. */
+static inline void __flush_xen_tlb_one(vaddr_t va)
{
asm volatile(STORE_CP32(0, TLBIMVAHIS) : : "r" (va) : "memory");
}
diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h
index 6c36d0210f..31d04ecf76 100644
--- a/xen/include/asm-arm/arm64/page.h
+++ b/xen/include/asm-arm/arm64/page.h
@@ -45,12 +45,8 @@ static inline void invalidate_icache_local(void)
isb();
}
-/*
- * Flush all hypervisor mappings from the data TLB of the local
- * processor. This is not sufficient when changing code mappings or
- * for self modifying code.
- */
-static inline void flush_xen_data_tlb_local(void)
+/* Flush all hypervisor mappings from the TLB of the local processor. */
+static inline void flush_xen_tlb_local(void)
{
asm volatile (
"dsb sy;" /* Ensure visibility of PTE writes */
@@ -61,14 +57,13 @@ static inline void flush_xen_data_tlb_local(void)
}
/* Flush TLB of local processor for address va. */
-static inline void __flush_xen_data_tlb_one_local(vaddr_t va)
+static inline void __flush_xen_tlb_one_local(vaddr_t va)
{
asm volatile("tlbi vae2, %0;" : : "r" (va>>PAGE_SHIFT) : "memory");
}
-/* Flush TLB of all processors in the inner-shareable domain for
- * address va. */
-static inline void __flush_xen_data_tlb_one(vaddr_t va)
+/* Flush TLB of all processors in the inner-shareable domain for address va. */
+static inline void __flush_xen_tlb_one(vaddr_t va)
{
asm volatile("tlbi vae2is, %0;" : : "r" (va>>PAGE_SHIFT) : "memory");
}
diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h
index 1a1713ce02..195345e24a 100644
--- a/xen/include/asm-arm/page.h
+++ b/xen/include/asm-arm/page.h
@@ -234,18 +234,18 @@ static inline int clean_and_invalidate_dcache_va_range
} while (0)
/*
- * Flush a range of VA's hypervisor mappings from the data TLB of the
- * local processor. This is not sufficient when changing code mappings
- * or for self modifying code.
+ * Flush a range of VA's hypervisor mappings from the TLB of the local
+ * processor.
*/
-static inline void flush_xen_data_tlb_range_va_local(unsigned long va,
- unsigned long size)
+static inline void flush_xen_tlb_range_va_local(vaddr_t va,
+ unsigned long size)
{
- unsigned long end = va + size;
+ vaddr_t end = va + size;
+
dsb(sy); /* Ensure preceding are visible */
while ( va < end )
{
- __flush_xen_data_tlb_one_local(va);
+ __flush_xen_tlb_one_local(va);
va += PAGE_SIZE;
}
dsb(sy); /* Ensure completion of the TLB flush */
@@ -253,18 +253,18 @@ static inline void flush_xen_data_tlb_range_va_local(unsigned long va,
}
/*
- * Flush a range of VA's hypervisor mappings from the data TLB of all
- * processors in the inner-shareable domain. This is not sufficient
- * when changing code mappings or for self modifying code.
+ * Flush a range of VA's hypervisor mappings from the TLB of all
+ * processors in the inner-shareable domain.
*/
-static inline void flush_xen_data_tlb_range_va(unsigned long va,
- unsigned long size)
+static inline void flush_xen_tlb_range_va(vaddr_t va,
+ unsigned long size)
{
- unsigned long end = va + size;
+ vaddr_t end = va + size;
+
dsb(sy); /* Ensure preceding are visible */
while ( va < end )
{
- __flush_xen_data_tlb_one(va);
+ __flush_xen_tlb_one(va);
va += PAGE_SIZE;
}
dsb(sy); /* Ensure completion of the TLB flush */
--
2.11.0
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Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 5/7] xen/arm: Gather all TLB flush helpers in tlbflush.h
@ 2019-04-17 17:58 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-17 17:58 UTC (permalink / raw)
To: xen-devel; +Cc: Oleksandr_Tyshchenko, Julien Grall, sstabellini, Andrii_Anisov
At the moment, TLB helpers are scattered in 2 headers: page.h (for
Xen TLB helpers) and tlbflush.h (for guest TLB helpers).
This patch is gathering all of them in tlbflush. This will help to
uniformize and update the logic of the helpers in follow-up patches.
Signed-off-by: Julien Grall <julien.grall@arm.com>
---
xen/include/asm-arm/arm32/flushtlb.h | 22 +++++++++++++++++++++
xen/include/asm-arm/arm32/page.h | 22 ---------------------
xen/include/asm-arm/arm64/flushtlb.h | 23 ++++++++++++++++++++++
xen/include/asm-arm/arm64/page.h | 23 ----------------------
xen/include/asm-arm/flushtlb.h | 38 ++++++++++++++++++++++++++++++++++++
xen/include/asm-arm/page.h | 38 ------------------------------------
6 files changed, 83 insertions(+), 83 deletions(-)
diff --git a/xen/include/asm-arm/arm32/flushtlb.h b/xen/include/asm-arm/arm32/flushtlb.h
index 22e100eccf..b629db61cb 100644
--- a/xen/include/asm-arm/arm32/flushtlb.h
+++ b/xen/include/asm-arm/arm32/flushtlb.h
@@ -45,6 +45,28 @@ static inline void flush_all_guests_tlb(void)
isb();
}
+/* Flush all hypervisor mappings from the TLB of the local processor. */
+static inline void flush_xen_tlb_local(void)
+{
+ asm volatile("dsb;" /* Ensure preceding are visible */
+ CMD_CP32(TLBIALLH)
+ "dsb;" /* Ensure completion of the TLB flush */
+ "isb;"
+ : : : "memory");
+}
+
+/* Flush TLB of local processor for address va. */
+static inline void __flush_xen_tlb_one_local(vaddr_t va)
+{
+ asm volatile(STORE_CP32(0, TLBIMVAH) : : "r" (va) : "memory");
+}
+
+/* Flush TLB of all processors in the inner-shareable domain for address va. */
+static inline void __flush_xen_tlb_one(vaddr_t va)
+{
+ asm volatile(STORE_CP32(0, TLBIMVAHIS) : : "r" (va) : "memory");
+}
+
#endif /* __ASM_ARM_ARM32_FLUSHTLB_H__ */
/*
* Local variables:
diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h
index 0b41b9214b..715a9e4fef 100644
--- a/xen/include/asm-arm/arm32/page.h
+++ b/xen/include/asm-arm/arm32/page.h
@@ -61,28 +61,6 @@ static inline void invalidate_icache_local(void)
isb(); /* Synchronize fetched instruction stream. */
}
-/* Flush all hypervisor mappings from the TLB of the local processor. */
-static inline void flush_xen_tlb_local(void)
-{
- asm volatile("dsb;" /* Ensure preceding are visible */
- CMD_CP32(TLBIALLH)
- "dsb;" /* Ensure completion of the TLB flush */
- "isb;"
- : : : "memory");
-}
-
-/* Flush TLB of local processor for address va. */
-static inline void __flush_xen_tlb_one_local(vaddr_t va)
-{
- asm volatile(STORE_CP32(0, TLBIMVAH) : : "r" (va) : "memory");
-}
-
-/* Flush TLB of all processors in the inner-shareable domain for address va. */
-static inline void __flush_xen_tlb_one(vaddr_t va)
-{
- asm volatile(STORE_CP32(0, TLBIMVAHIS) : : "r" (va) : "memory");
-}
-
/* Ask the MMU to translate a VA for us */
static inline uint64_t __va_to_par(vaddr_t va)
{
diff --git a/xen/include/asm-arm/arm64/flushtlb.h b/xen/include/asm-arm/arm64/flushtlb.h
index adbbd5c522..2fed34b2ec 100644
--- a/xen/include/asm-arm/arm64/flushtlb.h
+++ b/xen/include/asm-arm/arm64/flushtlb.h
@@ -45,6 +45,29 @@ static inline void flush_all_guests_tlb(void)
: : : "memory");
}
+/* Flush all hypervisor mappings from the TLB of the local processor. */
+static inline void flush_xen_tlb_local(void)
+{
+ asm volatile (
+ "dsb sy;" /* Ensure visibility of PTE writes */
+ "tlbi alle2;" /* Flush hypervisor TLB */
+ "dsb sy;" /* Ensure completion of TLB flush */
+ "isb;"
+ : : : "memory");
+}
+
+/* Flush TLB of local processor for address va. */
+static inline void __flush_xen_tlb_one_local(vaddr_t va)
+{
+ asm volatile("tlbi vae2, %0;" : : "r" (va>>PAGE_SHIFT) : "memory");
+}
+
+/* Flush TLB of all processors in the inner-shareable domain for address va. */
+static inline void __flush_xen_tlb_one(vaddr_t va)
+{
+ asm volatile("tlbi vae2is, %0;" : : "r" (va>>PAGE_SHIFT) : "memory");
+}
+
#endif /* __ASM_ARM_ARM64_FLUSHTLB_H__ */
/*
* Local variables:
diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h
index 31d04ecf76..0cba266373 100644
--- a/xen/include/asm-arm/arm64/page.h
+++ b/xen/include/asm-arm/arm64/page.h
@@ -45,29 +45,6 @@ static inline void invalidate_icache_local(void)
isb();
}
-/* Flush all hypervisor mappings from the TLB of the local processor. */
-static inline void flush_xen_tlb_local(void)
-{
- asm volatile (
- "dsb sy;" /* Ensure visibility of PTE writes */
- "tlbi alle2;" /* Flush hypervisor TLB */
- "dsb sy;" /* Ensure completion of TLB flush */
- "isb;"
- : : : "memory");
-}
-
-/* Flush TLB of local processor for address va. */
-static inline void __flush_xen_tlb_one_local(vaddr_t va)
-{
- asm volatile("tlbi vae2, %0;" : : "r" (va>>PAGE_SHIFT) : "memory");
-}
-
-/* Flush TLB of all processors in the inner-shareable domain for address va. */
-static inline void __flush_xen_tlb_one(vaddr_t va)
-{
- asm volatile("tlbi vae2is, %0;" : : "r" (va>>PAGE_SHIFT) : "memory");
-}
-
/* Ask the MMU to translate a VA for us */
static inline uint64_t __va_to_par(vaddr_t va)
{
diff --git a/xen/include/asm-arm/flushtlb.h b/xen/include/asm-arm/flushtlb.h
index 83ff9fa8b3..ab1aae5c90 100644
--- a/xen/include/asm-arm/flushtlb.h
+++ b/xen/include/asm-arm/flushtlb.h
@@ -28,6 +28,44 @@ static inline void page_set_tlbflush_timestamp(struct page_info *page)
/* Flush specified CPUs' TLBs */
void flush_tlb_mask(const cpumask_t *mask);
+/*
+ * Flush a range of VA's hypervisor mappings from the TLB of the local
+ * processor.
+ */
+static inline void flush_xen_tlb_range_va_local(vaddr_t va,
+ unsigned long size)
+{
+ vaddr_t end = va + size;
+
+ dsb(sy); /* Ensure preceding are visible */
+ while ( va < end )
+ {
+ __flush_xen_tlb_one_local(va);
+ va += PAGE_SIZE;
+ }
+ dsb(sy); /* Ensure completion of the TLB flush */
+ isb();
+}
+
+/*
+ * Flush a range of VA's hypervisor mappings from the TLB of all
+ * processors in the inner-shareable domain.
+ */
+static inline void flush_xen_tlb_range_va(vaddr_t va,
+ unsigned long size)
+{
+ vaddr_t end = va + size;
+
+ dsb(sy); /* Ensure preceding are visible */
+ while ( va < end )
+ {
+ __flush_xen_tlb_one(va);
+ va += PAGE_SIZE;
+ }
+ dsb(sy); /* Ensure completion of the TLB flush */
+ isb();
+}
+
#endif /* __ASM_ARM_FLUSHTLB_H__ */
/*
* Local variables:
diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h
index 195345e24a..2bcdb0f1a5 100644
--- a/xen/include/asm-arm/page.h
+++ b/xen/include/asm-arm/page.h
@@ -233,44 +233,6 @@ static inline int clean_and_invalidate_dcache_va_range
: : "r" (_p), "m" (*_p)); \
} while (0)
-/*
- * Flush a range of VA's hypervisor mappings from the TLB of the local
- * processor.
- */
-static inline void flush_xen_tlb_range_va_local(vaddr_t va,
- unsigned long size)
-{
- vaddr_t end = va + size;
-
- dsb(sy); /* Ensure preceding are visible */
- while ( va < end )
- {
- __flush_xen_tlb_one_local(va);
- va += PAGE_SIZE;
- }
- dsb(sy); /* Ensure completion of the TLB flush */
- isb();
-}
-
-/*
- * Flush a range of VA's hypervisor mappings from the TLB of all
- * processors in the inner-shareable domain.
- */
-static inline void flush_xen_tlb_range_va(vaddr_t va,
- unsigned long size)
-{
- vaddr_t end = va + size;
-
- dsb(sy); /* Ensure preceding are visible */
- while ( va < end )
- {
- __flush_xen_tlb_one(va);
- va += PAGE_SIZE;
- }
- dsb(sy); /* Ensure completion of the TLB flush */
- isb();
-}
-
/* Flush the dcache for an entire page. */
void flush_page_to_ram(unsigned long mfn, bool sync_icache);
--
2.11.0
_______________________________________________
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Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Xen-devel] [PATCH 5/7] xen/arm: Gather all TLB flush helpers in tlbflush.h
@ 2019-04-17 17:58 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-17 17:58 UTC (permalink / raw)
To: xen-devel; +Cc: Oleksandr_Tyshchenko, Julien Grall, sstabellini, Andrii_Anisov
At the moment, TLB helpers are scattered in 2 headers: page.h (for
Xen TLB helpers) and tlbflush.h (for guest TLB helpers).
This patch is gathering all of them in tlbflush. This will help to
uniformize and update the logic of the helpers in follow-up patches.
Signed-off-by: Julien Grall <julien.grall@arm.com>
---
xen/include/asm-arm/arm32/flushtlb.h | 22 +++++++++++++++++++++
xen/include/asm-arm/arm32/page.h | 22 ---------------------
xen/include/asm-arm/arm64/flushtlb.h | 23 ++++++++++++++++++++++
xen/include/asm-arm/arm64/page.h | 23 ----------------------
xen/include/asm-arm/flushtlb.h | 38 ++++++++++++++++++++++++++++++++++++
xen/include/asm-arm/page.h | 38 ------------------------------------
6 files changed, 83 insertions(+), 83 deletions(-)
diff --git a/xen/include/asm-arm/arm32/flushtlb.h b/xen/include/asm-arm/arm32/flushtlb.h
index 22e100eccf..b629db61cb 100644
--- a/xen/include/asm-arm/arm32/flushtlb.h
+++ b/xen/include/asm-arm/arm32/flushtlb.h
@@ -45,6 +45,28 @@ static inline void flush_all_guests_tlb(void)
isb();
}
+/* Flush all hypervisor mappings from the TLB of the local processor. */
+static inline void flush_xen_tlb_local(void)
+{
+ asm volatile("dsb;" /* Ensure preceding are visible */
+ CMD_CP32(TLBIALLH)
+ "dsb;" /* Ensure completion of the TLB flush */
+ "isb;"
+ : : : "memory");
+}
+
+/* Flush TLB of local processor for address va. */
+static inline void __flush_xen_tlb_one_local(vaddr_t va)
+{
+ asm volatile(STORE_CP32(0, TLBIMVAH) : : "r" (va) : "memory");
+}
+
+/* Flush TLB of all processors in the inner-shareable domain for address va. */
+static inline void __flush_xen_tlb_one(vaddr_t va)
+{
+ asm volatile(STORE_CP32(0, TLBIMVAHIS) : : "r" (va) : "memory");
+}
+
#endif /* __ASM_ARM_ARM32_FLUSHTLB_H__ */
/*
* Local variables:
diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h
index 0b41b9214b..715a9e4fef 100644
--- a/xen/include/asm-arm/arm32/page.h
+++ b/xen/include/asm-arm/arm32/page.h
@@ -61,28 +61,6 @@ static inline void invalidate_icache_local(void)
isb(); /* Synchronize fetched instruction stream. */
}
-/* Flush all hypervisor mappings from the TLB of the local processor. */
-static inline void flush_xen_tlb_local(void)
-{
- asm volatile("dsb;" /* Ensure preceding are visible */
- CMD_CP32(TLBIALLH)
- "dsb;" /* Ensure completion of the TLB flush */
- "isb;"
- : : : "memory");
-}
-
-/* Flush TLB of local processor for address va. */
-static inline void __flush_xen_tlb_one_local(vaddr_t va)
-{
- asm volatile(STORE_CP32(0, TLBIMVAH) : : "r" (va) : "memory");
-}
-
-/* Flush TLB of all processors in the inner-shareable domain for address va. */
-static inline void __flush_xen_tlb_one(vaddr_t va)
-{
- asm volatile(STORE_CP32(0, TLBIMVAHIS) : : "r" (va) : "memory");
-}
-
/* Ask the MMU to translate a VA for us */
static inline uint64_t __va_to_par(vaddr_t va)
{
diff --git a/xen/include/asm-arm/arm64/flushtlb.h b/xen/include/asm-arm/arm64/flushtlb.h
index adbbd5c522..2fed34b2ec 100644
--- a/xen/include/asm-arm/arm64/flushtlb.h
+++ b/xen/include/asm-arm/arm64/flushtlb.h
@@ -45,6 +45,29 @@ static inline void flush_all_guests_tlb(void)
: : : "memory");
}
+/* Flush all hypervisor mappings from the TLB of the local processor. */
+static inline void flush_xen_tlb_local(void)
+{
+ asm volatile (
+ "dsb sy;" /* Ensure visibility of PTE writes */
+ "tlbi alle2;" /* Flush hypervisor TLB */
+ "dsb sy;" /* Ensure completion of TLB flush */
+ "isb;"
+ : : : "memory");
+}
+
+/* Flush TLB of local processor for address va. */
+static inline void __flush_xen_tlb_one_local(vaddr_t va)
+{
+ asm volatile("tlbi vae2, %0;" : : "r" (va>>PAGE_SHIFT) : "memory");
+}
+
+/* Flush TLB of all processors in the inner-shareable domain for address va. */
+static inline void __flush_xen_tlb_one(vaddr_t va)
+{
+ asm volatile("tlbi vae2is, %0;" : : "r" (va>>PAGE_SHIFT) : "memory");
+}
+
#endif /* __ASM_ARM_ARM64_FLUSHTLB_H__ */
/*
* Local variables:
diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h
index 31d04ecf76..0cba266373 100644
--- a/xen/include/asm-arm/arm64/page.h
+++ b/xen/include/asm-arm/arm64/page.h
@@ -45,29 +45,6 @@ static inline void invalidate_icache_local(void)
isb();
}
-/* Flush all hypervisor mappings from the TLB of the local processor. */
-static inline void flush_xen_tlb_local(void)
-{
- asm volatile (
- "dsb sy;" /* Ensure visibility of PTE writes */
- "tlbi alle2;" /* Flush hypervisor TLB */
- "dsb sy;" /* Ensure completion of TLB flush */
- "isb;"
- : : : "memory");
-}
-
-/* Flush TLB of local processor for address va. */
-static inline void __flush_xen_tlb_one_local(vaddr_t va)
-{
- asm volatile("tlbi vae2, %0;" : : "r" (va>>PAGE_SHIFT) : "memory");
-}
-
-/* Flush TLB of all processors in the inner-shareable domain for address va. */
-static inline void __flush_xen_tlb_one(vaddr_t va)
-{
- asm volatile("tlbi vae2is, %0;" : : "r" (va>>PAGE_SHIFT) : "memory");
-}
-
/* Ask the MMU to translate a VA for us */
static inline uint64_t __va_to_par(vaddr_t va)
{
diff --git a/xen/include/asm-arm/flushtlb.h b/xen/include/asm-arm/flushtlb.h
index 83ff9fa8b3..ab1aae5c90 100644
--- a/xen/include/asm-arm/flushtlb.h
+++ b/xen/include/asm-arm/flushtlb.h
@@ -28,6 +28,44 @@ static inline void page_set_tlbflush_timestamp(struct page_info *page)
/* Flush specified CPUs' TLBs */
void flush_tlb_mask(const cpumask_t *mask);
+/*
+ * Flush a range of VA's hypervisor mappings from the TLB of the local
+ * processor.
+ */
+static inline void flush_xen_tlb_range_va_local(vaddr_t va,
+ unsigned long size)
+{
+ vaddr_t end = va + size;
+
+ dsb(sy); /* Ensure preceding are visible */
+ while ( va < end )
+ {
+ __flush_xen_tlb_one_local(va);
+ va += PAGE_SIZE;
+ }
+ dsb(sy); /* Ensure completion of the TLB flush */
+ isb();
+}
+
+/*
+ * Flush a range of VA's hypervisor mappings from the TLB of all
+ * processors in the inner-shareable domain.
+ */
+static inline void flush_xen_tlb_range_va(vaddr_t va,
+ unsigned long size)
+{
+ vaddr_t end = va + size;
+
+ dsb(sy); /* Ensure preceding are visible */
+ while ( va < end )
+ {
+ __flush_xen_tlb_one(va);
+ va += PAGE_SIZE;
+ }
+ dsb(sy); /* Ensure completion of the TLB flush */
+ isb();
+}
+
#endif /* __ASM_ARM_FLUSHTLB_H__ */
/*
* Local variables:
diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h
index 195345e24a..2bcdb0f1a5 100644
--- a/xen/include/asm-arm/page.h
+++ b/xen/include/asm-arm/page.h
@@ -233,44 +233,6 @@ static inline int clean_and_invalidate_dcache_va_range
: : "r" (_p), "m" (*_p)); \
} while (0)
-/*
- * Flush a range of VA's hypervisor mappings from the TLB of the local
- * processor.
- */
-static inline void flush_xen_tlb_range_va_local(vaddr_t va,
- unsigned long size)
-{
- vaddr_t end = va + size;
-
- dsb(sy); /* Ensure preceding are visible */
- while ( va < end )
- {
- __flush_xen_tlb_one_local(va);
- va += PAGE_SIZE;
- }
- dsb(sy); /* Ensure completion of the TLB flush */
- isb();
-}
-
-/*
- * Flush a range of VA's hypervisor mappings from the TLB of all
- * processors in the inner-shareable domain.
- */
-static inline void flush_xen_tlb_range_va(vaddr_t va,
- unsigned long size)
-{
- vaddr_t end = va + size;
-
- dsb(sy); /* Ensure preceding are visible */
- while ( va < end )
- {
- __flush_xen_tlb_one(va);
- va += PAGE_SIZE;
- }
- dsb(sy); /* Ensure completion of the TLB flush */
- isb();
-}
-
/* Flush the dcache for an entire page. */
void flush_page_to_ram(unsigned long mfn, bool sync_icache);
--
2.11.0
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^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 6/7] xen/arm: tlbflush: Rework TLB helpers
@ 2019-04-17 17:58 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-17 17:58 UTC (permalink / raw)
To: xen-devel; +Cc: Oleksandr_Tyshchenko, Julien Grall, sstabellini, Andrii_Anisov
All the TLBs helpers invalidate all the TLB entries are using the same
pattern:
DSB SY
TLBI ...
DSB SY
ISB
This pattern is following pattern recommended by the Arm Arm to ensure
visibility of updates to translation tables (see K10-5610 in ARM DDI
0487.A.k).
We have been a bit too eager in Xen and use system-wide DSBs when this
can be limited to the inner-shareable domain.
Furthermore, the first DSB can be restrict further to only store in the
inner-shareable domain. This is because the DSB is here to ensure
visibility of the update to translation table walks.
Lastly, there are a lack of documentation in most of the TLBs helper.
Rather than trying to update the helpers one by one, this patch
introduce a per-arch macro to generate the TLB helpers. This will be
easier to update the TLBs helper in the future and the documentation.
Signed-off-by: Julien Grall <julien.grall@arm.com>
---
xen/include/asm-arm/arm32/flushtlb.h | 73 ++++++++++++++--------------------
xen/include/asm-arm/arm64/flushtlb.h | 76 +++++++++++++++---------------------
2 files changed, 60 insertions(+), 89 deletions(-)
diff --git a/xen/include/asm-arm/arm32/flushtlb.h b/xen/include/asm-arm/arm32/flushtlb.h
index b629db61cb..9085e65011 100644
--- a/xen/include/asm-arm/arm32/flushtlb.h
+++ b/xen/include/asm-arm/arm32/flushtlb.h
@@ -1,59 +1,44 @@
#ifndef __ASM_ARM_ARM32_FLUSHTLB_H__
#define __ASM_ARM_ARM32_FLUSHTLB_H__
-/* Flush local TLBs, current VMID only */
-static inline void flush_guest_tlb_local(void)
-{
- dsb(sy);
-
- WRITE_CP32((uint32_t) 0, TLBIALL);
-
- dsb(sy);
- isb();
+/*
+ * Every invalidation operation use the following patterns:
+ *
+ * DSB ISHST // Ensure prior page-tables updates have completed
+ * TLBI... // Invalidate the TLB
+ * DSB ISH // Ensure the TLB invalidation has completed
+ * ISB // See explanation below
+ *
+ * For Xen page-tables the ISB will discard any instructions fetched
+ * from the old mappings.
+ *
+ * For the Stage-2 page-tables the ISB ensures the completion of the DSB
+ * (and therefore the TLB invalidation) before continuing. So we know
+ * the TLBs cannot contain an entry for a mapping we may have removed.
+ */
+#define TLB_HELPER(name, tlbop) \
+static inline void name(void) \
+{ \
+ dsb(ishst); \
+ WRITE_CP32(0, tlbop); \
+ dsb(ish); \
+ isb(); \
}
-/* Flush inner shareable TLBs, current VMID only */
-static inline void flush_guest_tlb(void)
-{
- dsb(sy);
-
- WRITE_CP32((uint32_t) 0, TLBIALLIS);
+/* Flush local TLBs, current VMID only */
+TLB_HELPER(flush_guest_tlb_local, TLBIALL);
- dsb(sy);
- isb();
-}
+/* Flush inner shareable TLBs, current VMID only */
+TLB_HELPER(flush_guest_tlb, TLBIALLIS);
/* Flush local TLBs, all VMIDs, non-hypervisor mode */
-static inline void flush_all_guests_tlb_local(void)
-{
- dsb(sy);
-
- WRITE_CP32((uint32_t) 0, TLBIALLNSNH);
-
- dsb(sy);
- isb();
-}
+TLB_HELPER(flush_all_guests_tlb_local, TLBIALLNSNH);
/* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */
-static inline void flush_all_guests_tlb(void)
-{
- dsb(sy);
-
- WRITE_CP32((uint32_t) 0, TLBIALLNSNHIS);
-
- dsb(sy);
- isb();
-}
+TLB_HELPER(flush_all_guests_tlb, TLBIALLNSNHIS);
/* Flush all hypervisor mappings from the TLB of the local processor. */
-static inline void flush_xen_tlb_local(void)
-{
- asm volatile("dsb;" /* Ensure preceding are visible */
- CMD_CP32(TLBIALLH)
- "dsb;" /* Ensure completion of the TLB flush */
- "isb;"
- : : : "memory");
-}
+TLB_HELPER(flush_xen_tlb_local, TLBIALLH);
/* Flush TLB of local processor for address va. */
static inline void __flush_xen_tlb_one_local(vaddr_t va)
diff --git a/xen/include/asm-arm/arm64/flushtlb.h b/xen/include/asm-arm/arm64/flushtlb.h
index 2fed34b2ec..ceec59542e 100644
--- a/xen/include/asm-arm/arm64/flushtlb.h
+++ b/xen/include/asm-arm/arm64/flushtlb.h
@@ -1,60 +1,46 @@
#ifndef __ASM_ARM_ARM64_FLUSHTLB_H__
#define __ASM_ARM_ARM64_FLUSHTLB_H__
-/* Flush local TLBs, current VMID only */
-static inline void flush_guest_tlb_local(void)
-{
- asm volatile(
- "dsb sy;"
- "tlbi vmalls12e1;"
- "dsb sy;"
- "isb;"
- : : : "memory");
+/*
+ * Every invalidation operation use the following patterns:
+ *
+ * DSB ISHST // Ensure prior page-tables updates have completed
+ * TLBI... // Invalidate the TLB
+ * DSB ISH // Ensure the TLB invalidation has completed
+ * ISB // See explanation below
+ *
+ * For Xen page-tables the ISB will discard any instructions fetched
+ * from the old mappings.
+ *
+ * For the Stage-2 page-tables the ISB ensures the completion of the DSB
+ * (and therefore the TLB invalidation) before continuing. So we know
+ * the TLBs cannot contain an entry for a mapping we may have removed.
+ */
+#define TLB_HELPER(name, tlbop) \
+static inline void name(void) \
+{ \
+ asm volatile( \
+ "dsb ishst;" \
+ "tlbi " # tlbop ";" \
+ "dsb ish;" \
+ "isb;" \
+ : : : "memory"); \
}
+/* Flush local TLBs, current VMID only. */
+TLB_HELPER(flush_guest_tlb_local, vmalls12e1);
+
/* Flush innershareable TLBs, current VMID only */
-static inline void flush_guest_tlb(void)
-{
- asm volatile(
- "dsb sy;"
- "tlbi vmalls12e1is;"
- "dsb sy;"
- "isb;"
- : : : "memory");
-}
+TLB_HELPER(flush_guest_tlb, vmalls12e1is);
/* Flush local TLBs, all VMIDs, non-hypervisor mode */
-static inline void flush_all_guests_tlb_local(void)
-{
- asm volatile(
- "dsb sy;"
- "tlbi alle1;"
- "dsb sy;"
- "isb;"
- : : : "memory");
-}
+TLB_HELPER(flush_all_guests_tlb_local, alle1);
/* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */
-static inline void flush_all_guests_tlb(void)
-{
- asm volatile(
- "dsb sy;"
- "tlbi alle1is;"
- "dsb sy;"
- "isb;"
- : : : "memory");
-}
+TLB_HELPER(flush_all_guests_tlb, alle1is);
/* Flush all hypervisor mappings from the TLB of the local processor. */
-static inline void flush_xen_tlb_local(void)
-{
- asm volatile (
- "dsb sy;" /* Ensure visibility of PTE writes */
- "tlbi alle2;" /* Flush hypervisor TLB */
- "dsb sy;" /* Ensure completion of TLB flush */
- "isb;"
- : : : "memory");
-}
+TLB_HELPER(flush_xen_tlb_local, alle2);
/* Flush TLB of local processor for address va. */
static inline void __flush_xen_tlb_one_local(vaddr_t va)
--
2.11.0
_______________________________________________
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Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Xen-devel] [PATCH 6/7] xen/arm: tlbflush: Rework TLB helpers
@ 2019-04-17 17:58 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-17 17:58 UTC (permalink / raw)
To: xen-devel; +Cc: Oleksandr_Tyshchenko, Julien Grall, sstabellini, Andrii_Anisov
All the TLBs helpers invalidate all the TLB entries are using the same
pattern:
DSB SY
TLBI ...
DSB SY
ISB
This pattern is following pattern recommended by the Arm Arm to ensure
visibility of updates to translation tables (see K10-5610 in ARM DDI
0487.A.k).
We have been a bit too eager in Xen and use system-wide DSBs when this
can be limited to the inner-shareable domain.
Furthermore, the first DSB can be restrict further to only store in the
inner-shareable domain. This is because the DSB is here to ensure
visibility of the update to translation table walks.
Lastly, there are a lack of documentation in most of the TLBs helper.
Rather than trying to update the helpers one by one, this patch
introduce a per-arch macro to generate the TLB helpers. This will be
easier to update the TLBs helper in the future and the documentation.
Signed-off-by: Julien Grall <julien.grall@arm.com>
---
xen/include/asm-arm/arm32/flushtlb.h | 73 ++++++++++++++--------------------
xen/include/asm-arm/arm64/flushtlb.h | 76 +++++++++++++++---------------------
2 files changed, 60 insertions(+), 89 deletions(-)
diff --git a/xen/include/asm-arm/arm32/flushtlb.h b/xen/include/asm-arm/arm32/flushtlb.h
index b629db61cb..9085e65011 100644
--- a/xen/include/asm-arm/arm32/flushtlb.h
+++ b/xen/include/asm-arm/arm32/flushtlb.h
@@ -1,59 +1,44 @@
#ifndef __ASM_ARM_ARM32_FLUSHTLB_H__
#define __ASM_ARM_ARM32_FLUSHTLB_H__
-/* Flush local TLBs, current VMID only */
-static inline void flush_guest_tlb_local(void)
-{
- dsb(sy);
-
- WRITE_CP32((uint32_t) 0, TLBIALL);
-
- dsb(sy);
- isb();
+/*
+ * Every invalidation operation use the following patterns:
+ *
+ * DSB ISHST // Ensure prior page-tables updates have completed
+ * TLBI... // Invalidate the TLB
+ * DSB ISH // Ensure the TLB invalidation has completed
+ * ISB // See explanation below
+ *
+ * For Xen page-tables the ISB will discard any instructions fetched
+ * from the old mappings.
+ *
+ * For the Stage-2 page-tables the ISB ensures the completion of the DSB
+ * (and therefore the TLB invalidation) before continuing. So we know
+ * the TLBs cannot contain an entry for a mapping we may have removed.
+ */
+#define TLB_HELPER(name, tlbop) \
+static inline void name(void) \
+{ \
+ dsb(ishst); \
+ WRITE_CP32(0, tlbop); \
+ dsb(ish); \
+ isb(); \
}
-/* Flush inner shareable TLBs, current VMID only */
-static inline void flush_guest_tlb(void)
-{
- dsb(sy);
-
- WRITE_CP32((uint32_t) 0, TLBIALLIS);
+/* Flush local TLBs, current VMID only */
+TLB_HELPER(flush_guest_tlb_local, TLBIALL);
- dsb(sy);
- isb();
-}
+/* Flush inner shareable TLBs, current VMID only */
+TLB_HELPER(flush_guest_tlb, TLBIALLIS);
/* Flush local TLBs, all VMIDs, non-hypervisor mode */
-static inline void flush_all_guests_tlb_local(void)
-{
- dsb(sy);
-
- WRITE_CP32((uint32_t) 0, TLBIALLNSNH);
-
- dsb(sy);
- isb();
-}
+TLB_HELPER(flush_all_guests_tlb_local, TLBIALLNSNH);
/* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */
-static inline void flush_all_guests_tlb(void)
-{
- dsb(sy);
-
- WRITE_CP32((uint32_t) 0, TLBIALLNSNHIS);
-
- dsb(sy);
- isb();
-}
+TLB_HELPER(flush_all_guests_tlb, TLBIALLNSNHIS);
/* Flush all hypervisor mappings from the TLB of the local processor. */
-static inline void flush_xen_tlb_local(void)
-{
- asm volatile("dsb;" /* Ensure preceding are visible */
- CMD_CP32(TLBIALLH)
- "dsb;" /* Ensure completion of the TLB flush */
- "isb;"
- : : : "memory");
-}
+TLB_HELPER(flush_xen_tlb_local, TLBIALLH);
/* Flush TLB of local processor for address va. */
static inline void __flush_xen_tlb_one_local(vaddr_t va)
diff --git a/xen/include/asm-arm/arm64/flushtlb.h b/xen/include/asm-arm/arm64/flushtlb.h
index 2fed34b2ec..ceec59542e 100644
--- a/xen/include/asm-arm/arm64/flushtlb.h
+++ b/xen/include/asm-arm/arm64/flushtlb.h
@@ -1,60 +1,46 @@
#ifndef __ASM_ARM_ARM64_FLUSHTLB_H__
#define __ASM_ARM_ARM64_FLUSHTLB_H__
-/* Flush local TLBs, current VMID only */
-static inline void flush_guest_tlb_local(void)
-{
- asm volatile(
- "dsb sy;"
- "tlbi vmalls12e1;"
- "dsb sy;"
- "isb;"
- : : : "memory");
+/*
+ * Every invalidation operation use the following patterns:
+ *
+ * DSB ISHST // Ensure prior page-tables updates have completed
+ * TLBI... // Invalidate the TLB
+ * DSB ISH // Ensure the TLB invalidation has completed
+ * ISB // See explanation below
+ *
+ * For Xen page-tables the ISB will discard any instructions fetched
+ * from the old mappings.
+ *
+ * For the Stage-2 page-tables the ISB ensures the completion of the DSB
+ * (and therefore the TLB invalidation) before continuing. So we know
+ * the TLBs cannot contain an entry for a mapping we may have removed.
+ */
+#define TLB_HELPER(name, tlbop) \
+static inline void name(void) \
+{ \
+ asm volatile( \
+ "dsb ishst;" \
+ "tlbi " # tlbop ";" \
+ "dsb ish;" \
+ "isb;" \
+ : : : "memory"); \
}
+/* Flush local TLBs, current VMID only. */
+TLB_HELPER(flush_guest_tlb_local, vmalls12e1);
+
/* Flush innershareable TLBs, current VMID only */
-static inline void flush_guest_tlb(void)
-{
- asm volatile(
- "dsb sy;"
- "tlbi vmalls12e1is;"
- "dsb sy;"
- "isb;"
- : : : "memory");
-}
+TLB_HELPER(flush_guest_tlb, vmalls12e1is);
/* Flush local TLBs, all VMIDs, non-hypervisor mode */
-static inline void flush_all_guests_tlb_local(void)
-{
- asm volatile(
- "dsb sy;"
- "tlbi alle1;"
- "dsb sy;"
- "isb;"
- : : : "memory");
-}
+TLB_HELPER(flush_all_guests_tlb_local, alle1);
/* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */
-static inline void flush_all_guests_tlb(void)
-{
- asm volatile(
- "dsb sy;"
- "tlbi alle1is;"
- "dsb sy;"
- "isb;"
- : : : "memory");
-}
+TLB_HELPER(flush_all_guests_tlb, alle1is);
/* Flush all hypervisor mappings from the TLB of the local processor. */
-static inline void flush_xen_tlb_local(void)
-{
- asm volatile (
- "dsb sy;" /* Ensure visibility of PTE writes */
- "tlbi alle2;" /* Flush hypervisor TLB */
- "dsb sy;" /* Ensure completion of TLB flush */
- "isb;"
- : : : "memory");
-}
+TLB_HELPER(flush_xen_tlb_local, alle2);
/* Flush TLB of local processor for address va. */
static inline void __flush_xen_tlb_one_local(vaddr_t va)
--
2.11.0
_______________________________________________
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Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 7/7] xen/arm: mm: Flush the TLBs even if a mapping failed in create_xen_entries
@ 2019-04-17 17:58 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-17 17:58 UTC (permalink / raw)
To: xen-devel; +Cc: Oleksandr_Tyshchenko, Julien Grall, sstabellini, Andrii_Anisov
At the moment, create_xen_entries will only flush the TLBs if the full
range has successfully been updated. This may lead to leave unwanted
entries in the TLBs if we fail to update some entries.
Signed-off-by: Julien Grall <julien.grall@arm.com>
---
xen/arch/arm/mm.c | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
index 8ee828d445..9d584e4cbf 100644
--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -984,7 +984,7 @@ static int create_xen_entries(enum xenmap_operation op,
unsigned long nr_mfns,
unsigned int flags)
{
- int rc;
+ int rc = 0;
unsigned long addr = virt, addr_end = addr + nr_mfns * PAGE_SIZE;
lpae_t pte, *entry;
lpae_t *third = NULL;
@@ -1013,7 +1013,8 @@ static int create_xen_entries(enum xenmap_operation op,
{
printk("%s: trying to replace an existing mapping addr=%lx mfn=%"PRI_mfn"\n",
__func__, addr, mfn_x(mfn));
- return -EINVAL;
+ rc = -EINVAL;
+ goto out;
}
if ( op == RESERVE )
break;
@@ -1030,7 +1031,8 @@ static int create_xen_entries(enum xenmap_operation op,
{
printk("%s: trying to %s a non-existing mapping addr=%lx\n",
__func__, op == REMOVE ? "remove" : "modify", addr);
- return -EINVAL;
+ rc = -EINVAL;
+ goto out;
}
if ( op == REMOVE )
pte.bits = 0;
@@ -1043,7 +1045,8 @@ static int create_xen_entries(enum xenmap_operation op,
{
printk("%s: Incorrect combination for addr=%lx\n",
__func__, addr);
- return -EINVAL;
+ rc = -EINVAL;
+ goto out;
}
}
write_pte(entry, pte);
@@ -1052,11 +1055,14 @@ static int create_xen_entries(enum xenmap_operation op,
BUG();
}
}
+out:
+ /*
+ * Flush the TLBs even in case of failure because we may have
+ * partially modified the PT. This will prevent any unexpected
+ * behavior afterwards.
+ */
flush_xen_tlb_range_va(virt, PAGE_SIZE * nr_mfns);
- rc = 0;
-
-out:
return rc;
}
--
2.11.0
_______________________________________________
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https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Xen-devel] [PATCH 7/7] xen/arm: mm: Flush the TLBs even if a mapping failed in create_xen_entries
@ 2019-04-17 17:58 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-17 17:58 UTC (permalink / raw)
To: xen-devel; +Cc: Oleksandr_Tyshchenko, Julien Grall, sstabellini, Andrii_Anisov
At the moment, create_xen_entries will only flush the TLBs if the full
range has successfully been updated. This may lead to leave unwanted
entries in the TLBs if we fail to update some entries.
Signed-off-by: Julien Grall <julien.grall@arm.com>
---
xen/arch/arm/mm.c | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
index 8ee828d445..9d584e4cbf 100644
--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -984,7 +984,7 @@ static int create_xen_entries(enum xenmap_operation op,
unsigned long nr_mfns,
unsigned int flags)
{
- int rc;
+ int rc = 0;
unsigned long addr = virt, addr_end = addr + nr_mfns * PAGE_SIZE;
lpae_t pte, *entry;
lpae_t *third = NULL;
@@ -1013,7 +1013,8 @@ static int create_xen_entries(enum xenmap_operation op,
{
printk("%s: trying to replace an existing mapping addr=%lx mfn=%"PRI_mfn"\n",
__func__, addr, mfn_x(mfn));
- return -EINVAL;
+ rc = -EINVAL;
+ goto out;
}
if ( op == RESERVE )
break;
@@ -1030,7 +1031,8 @@ static int create_xen_entries(enum xenmap_operation op,
{
printk("%s: trying to %s a non-existing mapping addr=%lx\n",
__func__, op == REMOVE ? "remove" : "modify", addr);
- return -EINVAL;
+ rc = -EINVAL;
+ goto out;
}
if ( op == REMOVE )
pte.bits = 0;
@@ -1043,7 +1045,8 @@ static int create_xen_entries(enum xenmap_operation op,
{
printk("%s: Incorrect combination for addr=%lx\n",
__func__, addr);
- return -EINVAL;
+ rc = -EINVAL;
+ goto out;
}
}
write_pte(entry, pte);
@@ -1052,11 +1055,14 @@ static int create_xen_entries(enum xenmap_operation op,
BUG();
}
}
+out:
+ /*
+ * Flush the TLBs even in case of failure because we may have
+ * partially modified the PT. This will prevent any unexpected
+ * behavior afterwards.
+ */
flush_xen_tlb_range_va(virt, PAGE_SIZE * nr_mfns);
- rc = 0;
-
-out:
return rc;
}
--
2.11.0
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^ permalink raw reply related [flat|nested] 52+ messages in thread
* Re: [PATCH 1/7] xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place
@ 2019-04-25 18:00 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-25 18:00 UTC (permalink / raw)
To: Julien Grall, xen-devel; +Cc: Oleksandr_Tyshchenko, sstabellini, Andrii_Anisov
On 17.04.19 20:58, Julien Grall wrote:
> The logic to set SCTLR_EL2.WXN is the same for the boot CPU and
> non-boot CPU. So introduce a function to set the bit and clear TBLs.
s/TBL/TLB/
>
> This new function will help us to document and update the logic in a
> single place.
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
> ---
> xen/arch/arm/mm.c | 22 +++++++++++++++-------
> 1 file changed, 15 insertions(+), 7 deletions(-)
>
> diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
> index 01ae2cccc0..93ad118183 100644
> --- a/xen/arch/arm/mm.c
> +++ b/xen/arch/arm/mm.c
> @@ -601,6 +601,19 @@ void __init remove_early_mappings(void)
> flush_xen_data_tlb_range_va(BOOT_FDT_VIRT_START, BOOT_FDT_SLOT_SIZE);
> }
>
> +/*
> + * After boot, Xen page-tables should not contain mapping that are both
> + * Writable and eXecutables.
> + *
> + * This should be called on each CPU to enforce the policy.
> + */
> +static void xen_pt_enforce_wnx(void)
Could it be inline?
> +{
> + WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
> + /* Flush everything after setting WXN bit. */
> + flush_xen_text_tlb_local();
> +}
> +
> extern void switch_ttbr(uint64_t ttbr);
>
> /* Clear a translation table and clean & invalidate the cache */
> @@ -702,10 +715,7 @@ void __init setup_pagetables(unsigned long boot_phys_offset)
> clear_table(boot_second);
> clear_table(boot_third);
>
> - /* From now on, no mapping may be both writable and executable. */
> - WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
> - /* Flush everything after setting WXN bit. */
> - flush_xen_text_tlb_local();
> + xen_pt_enforce_wnx();
>
> #ifdef CONFIG_ARM_32
> per_cpu(xen_pgtable, 0) = cpu0_pgtable;
> @@ -777,9 +787,7 @@ int init_secondary_pagetables(int cpu)
> /* MMU setup for secondary CPUS (which already have paging enabled) */
> void mmu_init_secondary_cpu(void)
> {
> - /* From now on, no mapping may be both writable and executable. */
> - WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
> - flush_xen_text_tlb_local();
> + xen_pt_enforce_wnx();
> }
>
> #ifdef CONFIG_ARM_32
>
With minor notes,
Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Xen-devel] [PATCH 1/7] xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place
@ 2019-04-25 18:00 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-25 18:00 UTC (permalink / raw)
To: Julien Grall, xen-devel; +Cc: Oleksandr_Tyshchenko, sstabellini, Andrii_Anisov
On 17.04.19 20:58, Julien Grall wrote:
> The logic to set SCTLR_EL2.WXN is the same for the boot CPU and
> non-boot CPU. So introduce a function to set the bit and clear TBLs.
s/TBL/TLB/
>
> This new function will help us to document and update the logic in a
> single place.
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
> ---
> xen/arch/arm/mm.c | 22 +++++++++++++++-------
> 1 file changed, 15 insertions(+), 7 deletions(-)
>
> diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
> index 01ae2cccc0..93ad118183 100644
> --- a/xen/arch/arm/mm.c
> +++ b/xen/arch/arm/mm.c
> @@ -601,6 +601,19 @@ void __init remove_early_mappings(void)
> flush_xen_data_tlb_range_va(BOOT_FDT_VIRT_START, BOOT_FDT_SLOT_SIZE);
> }
>
> +/*
> + * After boot, Xen page-tables should not contain mapping that are both
> + * Writable and eXecutables.
> + *
> + * This should be called on each CPU to enforce the policy.
> + */
> +static void xen_pt_enforce_wnx(void)
Could it be inline?
> +{
> + WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
> + /* Flush everything after setting WXN bit. */
> + flush_xen_text_tlb_local();
> +}
> +
> extern void switch_ttbr(uint64_t ttbr);
>
> /* Clear a translation table and clean & invalidate the cache */
> @@ -702,10 +715,7 @@ void __init setup_pagetables(unsigned long boot_phys_offset)
> clear_table(boot_second);
> clear_table(boot_third);
>
> - /* From now on, no mapping may be both writable and executable. */
> - WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
> - /* Flush everything after setting WXN bit. */
> - flush_xen_text_tlb_local();
> + xen_pt_enforce_wnx();
>
> #ifdef CONFIG_ARM_32
> per_cpu(xen_pgtable, 0) = cpu0_pgtable;
> @@ -777,9 +787,7 @@ int init_secondary_pagetables(int cpu)
> /* MMU setup for secondary CPUS (which already have paging enabled) */
> void mmu_init_secondary_cpu(void)
> {
> - /* From now on, no mapping may be both writable and executable. */
> - WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
> - flush_xen_text_tlb_local();
> + xen_pt_enforce_wnx();
> }
>
> #ifdef CONFIG_ARM_32
>
With minor notes,
Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 2/7] xen/arm: Remove flush_xen_text_tlb_local()
@ 2019-04-25 18:00 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-25 18:00 UTC (permalink / raw)
To: Julien Grall, xen-devel; +Cc: Oleksandr_Tyshchenko, sstabellini, Andrii_Anisov
Hello Julien,
On 17.04.19 20:58, Julien Grall wrote:
> The function flush_xen_text_tlb_local() has been misused and will result
> to invalidate the instruction cache more than necessary.
>
> For instance, there are no need to invalidate the instruction cache if
> we are setting SCTLR_EL2.WXN.
>
> There are effectively only one caller (i.e free_init_memory() would
> who need to invalidate the instruction cache.
>
> So rather than keeping around the function flush_xen_text_tlb_local()
> around, replace it with call to flush_xen_tlb_local() and explicitely
> flush the cache when necessary.
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
> ---
> xen/arch/arm/mm.c | 17 ++++++++++++++---
> xen/include/asm-arm/arm32/page.h | 23 +++++++++--------------
> xen/include/asm-arm/arm64/page.h | 21 +++++----------------
> 3 files changed, 28 insertions(+), 33 deletions(-)
>
> diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
> index 93ad118183..dfbe39c70a 100644
> --- a/xen/arch/arm/mm.c
> +++ b/xen/arch/arm/mm.c
> @@ -610,8 +610,12 @@ void __init remove_early_mappings(void)
> static void xen_pt_enforce_wnx(void)
> {
> WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
> - /* Flush everything after setting WXN bit. */
> - flush_xen_text_tlb_local();
> + /*
> + * The TLBs may cache SCTLR_EL2.WXN. So ensure it is synchronized
> + * before flushing the TLBs.
I'm not sure about the comment above, it looks a bit confusing to me.
As per my understanding flushing TLB is called to remove cached entries together with cached SCTLR_EL2.WXN.
And isb before to tlb flush ensures that WXN is set prior to flush so that all new TLB entries will be fetched
with this flag set.
> + */
> + isb();
> + flush_xen_data_tlb_local();
> }
>
> extern void switch_ttbr(uint64_t ttbr);
> @@ -1123,7 +1127,7 @@ static void set_pte_flags_on_range(const char *p, unsigned long l, enum mg mg)
> }
> write_pte(xen_xenmap + i, pte);
> }
> - flush_xen_text_tlb_local();
> + flush_xen_data_tlb_local();
> }
>
> /* Release all __init and __initdata ranges to be reused */
> @@ -1136,6 +1140,13 @@ void free_init_memory(void)
> uint32_t *p;
>
> set_pte_flags_on_range(__init_begin, len, mg_rw);
> +
> + /*
> + * From now on, init will not be used for execution anymore,
> + * so nuke the instruction cache to remove entries related to init.
> + */
> + invalidate_icache_local();
> +
> #ifdef CONFIG_ARM_32
> /* udf instruction i.e (see A8.8.247 in ARM DDI 0406C.c) */
> insn = 0xe7f000f0;
> diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h
> index ea4b312c70..40a77daa9d 100644
> --- a/xen/include/asm-arm/arm32/page.h
> +++ b/xen/include/asm-arm/arm32/page.h
> @@ -46,24 +46,19 @@ static inline void invalidate_icache(void)
> }
>
> /*
> - * Flush all hypervisor mappings from the TLB and branch predictor of
> - * the local processor.
> - *
> - * This is needed after changing Xen code mappings.
> - *
> - * The caller needs to issue the necessary DSB and D-cache flushes
> - * before calling flush_xen_text_tlb.
> + * Invalidate all instruction caches on the local processor to PoU.
> + * We also need to flush the branch predictor for ARMv7 as it may be
> + * architecturally visible to the software (see B2.2.4 in ARM DDI 0406C.b).
> */
> -static inline void flush_xen_text_tlb_local(void)
> +static inline void invalidate_icache_local(void)
> {
> asm volatile (
> - "isb;" /* Ensure synchronization with previous changes to text */
> - CMD_CP32(TLBIALLH) /* Flush hypervisor TLB */
> - CMD_CP32(ICIALLU) /* Flush I-cache */
> - CMD_CP32(BPIALL) /* Flush branch predictor */
> - "dsb;" /* Ensure completion of TLB+BP flush */
> - "isb;"
> + CMD_CP32(ICIALLU) /* Flush I-cache. */
> + CMD_CP32(BPIALL) /* Flush branch predictor. */
> : : : "memory");
> +
> + dsb(nsh); /* Ensure completion of the flush I-cache */
> + isb(); /* Synchronize fetched instruction stream. */
> }
>
> /*
> diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h
> index 23d778154d..6c36d0210f 100644
> --- a/xen/include/asm-arm/arm64/page.h
> +++ b/xen/include/asm-arm/arm64/page.h
> @@ -37,23 +37,12 @@ static inline void invalidate_icache(void)
> isb();
> }
>
> -/*
> - * Flush all hypervisor mappings from the TLB of the local processor.
> - *
> - * This is needed after changing Xen code mappings.
> - *
> - * The caller needs to issue the necessary DSB and D-cache flushes
> - * before calling flush_xen_text_tlb.
> - */
> -static inline void flush_xen_text_tlb_local(void)
> +/* Invalidate all instruction caches on the local processor to PoU */
> +static inline void invalidate_icache_local(void)
> {
> - asm volatile (
> - "isb;" /* Ensure synchronization with previous changes to text */
> - "tlbi alle2;" /* Flush hypervisor TLB */
> - "ic iallu;" /* Flush I-cache */
> - "dsb sy;" /* Ensure completion of TLB flush */
> - "isb;"
> - : : : "memory");
> + asm volatile ("ic iallu");
> + dsb(nsh); /* Ensure completion of the I-cache flush */
> + isb();
> }
>
> /*
>
With minor notes,
Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Xen-devel] [PATCH 2/7] xen/arm: Remove flush_xen_text_tlb_local()
@ 2019-04-25 18:00 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-25 18:00 UTC (permalink / raw)
To: Julien Grall, xen-devel; +Cc: Oleksandr_Tyshchenko, sstabellini, Andrii_Anisov
Hello Julien,
On 17.04.19 20:58, Julien Grall wrote:
> The function flush_xen_text_tlb_local() has been misused and will result
> to invalidate the instruction cache more than necessary.
>
> For instance, there are no need to invalidate the instruction cache if
> we are setting SCTLR_EL2.WXN.
>
> There are effectively only one caller (i.e free_init_memory() would
> who need to invalidate the instruction cache.
>
> So rather than keeping around the function flush_xen_text_tlb_local()
> around, replace it with call to flush_xen_tlb_local() and explicitely
> flush the cache when necessary.
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
> ---
> xen/arch/arm/mm.c | 17 ++++++++++++++---
> xen/include/asm-arm/arm32/page.h | 23 +++++++++--------------
> xen/include/asm-arm/arm64/page.h | 21 +++++----------------
> 3 files changed, 28 insertions(+), 33 deletions(-)
>
> diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
> index 93ad118183..dfbe39c70a 100644
> --- a/xen/arch/arm/mm.c
> +++ b/xen/arch/arm/mm.c
> @@ -610,8 +610,12 @@ void __init remove_early_mappings(void)
> static void xen_pt_enforce_wnx(void)
> {
> WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
> - /* Flush everything after setting WXN bit. */
> - flush_xen_text_tlb_local();
> + /*
> + * The TLBs may cache SCTLR_EL2.WXN. So ensure it is synchronized
> + * before flushing the TLBs.
I'm not sure about the comment above, it looks a bit confusing to me.
As per my understanding flushing TLB is called to remove cached entries together with cached SCTLR_EL2.WXN.
And isb before to tlb flush ensures that WXN is set prior to flush so that all new TLB entries will be fetched
with this flag set.
> + */
> + isb();
> + flush_xen_data_tlb_local();
> }
>
> extern void switch_ttbr(uint64_t ttbr);
> @@ -1123,7 +1127,7 @@ static void set_pte_flags_on_range(const char *p, unsigned long l, enum mg mg)
> }
> write_pte(xen_xenmap + i, pte);
> }
> - flush_xen_text_tlb_local();
> + flush_xen_data_tlb_local();
> }
>
> /* Release all __init and __initdata ranges to be reused */
> @@ -1136,6 +1140,13 @@ void free_init_memory(void)
> uint32_t *p;
>
> set_pte_flags_on_range(__init_begin, len, mg_rw);
> +
> + /*
> + * From now on, init will not be used for execution anymore,
> + * so nuke the instruction cache to remove entries related to init.
> + */
> + invalidate_icache_local();
> +
> #ifdef CONFIG_ARM_32
> /* udf instruction i.e (see A8.8.247 in ARM DDI 0406C.c) */
> insn = 0xe7f000f0;
> diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h
> index ea4b312c70..40a77daa9d 100644
> --- a/xen/include/asm-arm/arm32/page.h
> +++ b/xen/include/asm-arm/arm32/page.h
> @@ -46,24 +46,19 @@ static inline void invalidate_icache(void)
> }
>
> /*
> - * Flush all hypervisor mappings from the TLB and branch predictor of
> - * the local processor.
> - *
> - * This is needed after changing Xen code mappings.
> - *
> - * The caller needs to issue the necessary DSB and D-cache flushes
> - * before calling flush_xen_text_tlb.
> + * Invalidate all instruction caches on the local processor to PoU.
> + * We also need to flush the branch predictor for ARMv7 as it may be
> + * architecturally visible to the software (see B2.2.4 in ARM DDI 0406C.b).
> */
> -static inline void flush_xen_text_tlb_local(void)
> +static inline void invalidate_icache_local(void)
> {
> asm volatile (
> - "isb;" /* Ensure synchronization with previous changes to text */
> - CMD_CP32(TLBIALLH) /* Flush hypervisor TLB */
> - CMD_CP32(ICIALLU) /* Flush I-cache */
> - CMD_CP32(BPIALL) /* Flush branch predictor */
> - "dsb;" /* Ensure completion of TLB+BP flush */
> - "isb;"
> + CMD_CP32(ICIALLU) /* Flush I-cache. */
> + CMD_CP32(BPIALL) /* Flush branch predictor. */
> : : : "memory");
> +
> + dsb(nsh); /* Ensure completion of the flush I-cache */
> + isb(); /* Synchronize fetched instruction stream. */
> }
>
> /*
> diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h
> index 23d778154d..6c36d0210f 100644
> --- a/xen/include/asm-arm/arm64/page.h
> +++ b/xen/include/asm-arm/arm64/page.h
> @@ -37,23 +37,12 @@ static inline void invalidate_icache(void)
> isb();
> }
>
> -/*
> - * Flush all hypervisor mappings from the TLB of the local processor.
> - *
> - * This is needed after changing Xen code mappings.
> - *
> - * The caller needs to issue the necessary DSB and D-cache flushes
> - * before calling flush_xen_text_tlb.
> - */
> -static inline void flush_xen_text_tlb_local(void)
> +/* Invalidate all instruction caches on the local processor to PoU */
> +static inline void invalidate_icache_local(void)
> {
> - asm volatile (
> - "isb;" /* Ensure synchronization with previous changes to text */
> - "tlbi alle2;" /* Flush hypervisor TLB */
> - "ic iallu;" /* Flush I-cache */
> - "dsb sy;" /* Ensure completion of TLB flush */
> - "isb;"
> - : : : "memory");
> + asm volatile ("ic iallu");
> + dsb(nsh); /* Ensure completion of the I-cache flush */
> + isb();
> }
>
> /*
>
With minor notes,
Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 3/7] xen/arm: tlbflush: Clarify the TLB helpers name
@ 2019-04-25 18:00 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-25 18:00 UTC (permalink / raw)
To: Julien Grall, xen-devel; +Cc: Oleksandr_Tyshchenko, sstabellini, Andrii_Anisov
On 17.04.19 20:58, Julien Grall wrote:
> TLB helpers in the headers tlbflush.h are currently quite confusing to
> use the name may lead to think they are dealing with hypervisors TLBs
> while they actually deal with guest TLBs.
>
> Rename them to make it clearer that we are dealing with guest TLBs.
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Xen-devel] [PATCH 3/7] xen/arm: tlbflush: Clarify the TLB helpers name
@ 2019-04-25 18:00 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-25 18:00 UTC (permalink / raw)
To: Julien Grall, xen-devel; +Cc: Oleksandr_Tyshchenko, sstabellini, Andrii_Anisov
On 17.04.19 20:58, Julien Grall wrote:
> TLB helpers in the headers tlbflush.h are currently quite confusing to
> use the name may lead to think they are dealing with hypervisors TLBs
> while they actually deal with guest TLBs.
>
> Rename them to make it clearer that we are dealing with guest TLBs.
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 4/7] xen/arm: page: Clarify the Xen TLBs helpers name
@ 2019-04-25 18:00 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-25 18:00 UTC (permalink / raw)
To: Julien Grall, xen-devel; +Cc: Oleksandr_Tyshchenko, sstabellini, Andrii_Anisov
On 17.04.19 20:58, Julien Grall wrote:
> Now that we dropped flush_xen_text_tlb_local(), we have only one set of
> helpers acting on Xen TLBs. There naming are quite confusing because the
> TLB instructions used will act on both Data and Instruction TLBs.
>
> Take the opportunity to rework the documentation that can be confusing
> to read as they don't match the implementation.
>
> Lastly, switch from unsigned lont to vaddr_t as the function technically
> deal with virtual address.
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Xen-devel] [PATCH 4/7] xen/arm: page: Clarify the Xen TLBs helpers name
@ 2019-04-25 18:00 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-25 18:00 UTC (permalink / raw)
To: Julien Grall, xen-devel; +Cc: Oleksandr_Tyshchenko, sstabellini, Andrii_Anisov
On 17.04.19 20:58, Julien Grall wrote:
> Now that we dropped flush_xen_text_tlb_local(), we have only one set of
> helpers acting on Xen TLBs. There naming are quite confusing because the
> TLB instructions used will act on both Data and Instruction TLBs.
>
> Take the opportunity to rework the documentation that can be confusing
> to read as they don't match the implementation.
>
> Lastly, switch from unsigned lont to vaddr_t as the function technically
> deal with virtual address.
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 5/7] xen/arm: Gather all TLB flush helpers in tlbflush.h
@ 2019-04-25 18:01 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-25 18:01 UTC (permalink / raw)
To: Julien Grall, xen-devel; +Cc: Oleksandr_Tyshchenko, sstabellini, Andrii_Anisov
On 17.04.19 20:58, Julien Grall wrote:
> At the moment, TLB helpers are scattered in 2 headers: page.h (for
> Xen TLB helpers) and tlbflush.h (for guest TLB helpers).
>
> This patch is gathering all of them in tlbflush. This will help to
> uniformize and update the logic of the helpers in follow-up patches.
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Xen-devel] [PATCH 5/7] xen/arm: Gather all TLB flush helpers in tlbflush.h
@ 2019-04-25 18:01 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-25 18:01 UTC (permalink / raw)
To: Julien Grall, xen-devel; +Cc: Oleksandr_Tyshchenko, sstabellini, Andrii_Anisov
On 17.04.19 20:58, Julien Grall wrote:
> At the moment, TLB helpers are scattered in 2 headers: page.h (for
> Xen TLB helpers) and tlbflush.h (for guest TLB helpers).
>
> This patch is gathering all of them in tlbflush. This will help to
> uniformize and update the logic of the helpers in follow-up patches.
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 6/7] xen/arm: tlbflush: Rework TLB helpers
@ 2019-04-25 18:01 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-25 18:01 UTC (permalink / raw)
To: Julien Grall, xen-devel; +Cc: Oleksandr_Tyshchenko, sstabellini, Andrii_Anisov
On 17.04.19 20:58, Julien Grall wrote:
> All the TLBs helpers invalidate all the TLB entries are using the same
> pattern:
> DSB SY
> TLBI ...
> DSB SY
> ISB
>
> This pattern is following pattern recommended by the Arm Arm to ensure
> visibility of updates to translation tables (see K10-5610 in ARM DDI
> 0487.A.k).
I can't find 0487.A.k, only aj [1], next one is b.
I guess you are referring `Ensuring the visibility of updates to translation tables for a multiprocessor`?
[1] https://developer.arm.com/docs/ddi0487/aj
>
> We have been a bit too eager in Xen and use system-wide DSBs when this
> can be limited to the inner-shareable domain.
>
> Furthermore, the first DSB can be restrict further to only store in the
> inner-shareable domain. This is because the DSB is here to ensure
> visibility of the update to translation table walks.
>
> Lastly, there are a lack of documentation in most of the TLBs helper.
>
> Rather than trying to update the helpers one by one, this patch
> introduce a per-arch macro to generate the TLB helpers. This will be
> easier to update the TLBs helper in the future and the documentation.
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
> ---
> xen/include/asm-arm/arm32/flushtlb.h | 73 ++++++++++++++--------------------
> xen/include/asm-arm/arm64/flushtlb.h | 76 +++++++++++++++---------------------
> 2 files changed, 60 insertions(+), 89 deletions(-)
>
> diff --git a/xen/include/asm-arm/arm32/flushtlb.h b/xen/include/asm-arm/arm32/flushtlb.h
> index b629db61cb..9085e65011 100644
> --- a/xen/include/asm-arm/arm32/flushtlb.h
> +++ b/xen/include/asm-arm/arm32/flushtlb.h
> @@ -1,59 +1,44 @@
> #ifndef __ASM_ARM_ARM32_FLUSHTLB_H__
> #define __ASM_ARM_ARM32_FLUSHTLB_H__
>
> -/* Flush local TLBs, current VMID only */
> -static inline void flush_guest_tlb_local(void)
> -{
> - dsb(sy);
> -
> - WRITE_CP32((uint32_t) 0, TLBIALL);
> -
> - dsb(sy);
> - isb();
> +/*
> + * Every invalidation operation use the following patterns:
> + *
> + * DSB ISHST // Ensure prior page-tables updates have completed
> + * TLBI... // Invalidate the TLB
> + * DSB ISH // Ensure the TLB invalidation has completed
> + * ISB // See explanation below
> + *
> + * For Xen page-tables the ISB will discard any instructions fetched
> + * from the old mappings.
> + *
> + * For the Stage-2 page-tables the ISB ensures the completion of the DSB
> + * (and therefore the TLB invalidation) before continuing. So we know
> + * the TLBs cannot contain an entry for a mapping we may have removed.
> + */
> +#define TLB_HELPER(name, tlbop) \
> +static inline void name(void) \
> +{ \
> + dsb(ishst); \
> + WRITE_CP32(0, tlbop); \
> + dsb(ish); \
> + isb(); \
> }
>
> -/* Flush inner shareable TLBs, current VMID only */
> -static inline void flush_guest_tlb(void)
> -{
> - dsb(sy);
> -
> - WRITE_CP32((uint32_t) 0, TLBIALLIS);
> +/* Flush local TLBs, current VMID only */
> +TLB_HELPER(flush_guest_tlb_local, TLBIALL);
>
> - dsb(sy);
> - isb();
> -}
> +/* Flush inner shareable TLBs, current VMID only */
> +TLB_HELPER(flush_guest_tlb, TLBIALLIS);
>
> /* Flush local TLBs, all VMIDs, non-hypervisor mode */
> -static inline void flush_all_guests_tlb_local(void)
> -{
> - dsb(sy);
> -
> - WRITE_CP32((uint32_t) 0, TLBIALLNSNH);
> -
> - dsb(sy);
> - isb();
> -}
> +TLB_HELPER(flush_all_guests_tlb_local, TLBIALLNSNH);
>
> /* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */
> -static inline void flush_all_guests_tlb(void)
> -{
> - dsb(sy);
> -
> - WRITE_CP32((uint32_t) 0, TLBIALLNSNHIS);
> -
> - dsb(sy);
> - isb();
> -}
> +TLB_HELPER(flush_all_guests_tlb, TLBIALLNSNHIS);
>
> /* Flush all hypervisor mappings from the TLB of the local processor. */
> -static inline void flush_xen_tlb_local(void)
> -{
> - asm volatile("dsb;" /* Ensure preceding are visible */
> - CMD_CP32(TLBIALLH)
> - "dsb;" /* Ensure completion of the TLB flush */
> - "isb;"
> - : : : "memory");
> -}
> +TLB_HELPER(flush_xen_tlb_local, TLBIALLH);
>
> /* Flush TLB of local processor for address va. */
> static inline void __flush_xen_tlb_one_local(vaddr_t va)
> diff --git a/xen/include/asm-arm/arm64/flushtlb.h b/xen/include/asm-arm/arm64/flushtlb.h
> index 2fed34b2ec..ceec59542e 100644
> --- a/xen/include/asm-arm/arm64/flushtlb.h
> +++ b/xen/include/asm-arm/arm64/flushtlb.h
> @@ -1,60 +1,46 @@
> #ifndef __ASM_ARM_ARM64_FLUSHTLB_H__
> #define __ASM_ARM_ARM64_FLUSHTLB_H__
>
> -/* Flush local TLBs, current VMID only */
> -static inline void flush_guest_tlb_local(void)
> -{
> - asm volatile(
> - "dsb sy;"
> - "tlbi vmalls12e1;"
> - "dsb sy;"
> - "isb;"
> - : : : "memory");
> +/*
> + * Every invalidation operation use the following patterns:
> + *
> + * DSB ISHST // Ensure prior page-tables updates have completed
> + * TLBI... // Invalidate the TLB
> + * DSB ISH // Ensure the TLB invalidation has completed
> + * ISB // See explanation below
> + *
> + * For Xen page-tables the ISB will discard any instructions fetched
> + * from the old mappings.
> + *
> + * For the Stage-2 page-tables the ISB ensures the completion of the DSB
> + * (and therefore the TLB invalidation) before continuing. So we know
> + * the TLBs cannot contain an entry for a mapping we may have removed.
> + */
> +#define TLB_HELPER(name, tlbop) \
> +static inline void name(void) \
> +{ \
> + asm volatile( \
> + "dsb ishst;" \
> + "tlbi " # tlbop ";" \
> + "dsb ish;" \
> + "isb;" \
> + : : : "memory"); \
> }
>
> +/* Flush local TLBs, current VMID only. */
> +TLB_HELPER(flush_guest_tlb_local, vmalls12e1);
> +
> /* Flush innershareable TLBs, current VMID only */
> -static inline void flush_guest_tlb(void)
> -{
> - asm volatile(
> - "dsb sy;"
> - "tlbi vmalls12e1is;"
> - "dsb sy;"
> - "isb;"
> - : : : "memory");
> -}
> +TLB_HELPER(flush_guest_tlb, vmalls12e1is);
>
> /* Flush local TLBs, all VMIDs, non-hypervisor mode */
> -static inline void flush_all_guests_tlb_local(void)
> -{
> - asm volatile(
> - "dsb sy;"
> - "tlbi alle1;"
> - "dsb sy;"
> - "isb;"
> - : : : "memory");
> -}
> +TLB_HELPER(flush_all_guests_tlb_local, alle1);
>
> /* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */
> -static inline void flush_all_guests_tlb(void)
> -{
> - asm volatile(
> - "dsb sy;"
> - "tlbi alle1is;"
> - "dsb sy;"
> - "isb;"
> - : : : "memory");
> -}
> +TLB_HELPER(flush_all_guests_tlb, alle1is);
>
> /* Flush all hypervisor mappings from the TLB of the local processor. */
> -static inline void flush_xen_tlb_local(void)
> -{
> - asm volatile (
> - "dsb sy;" /* Ensure visibility of PTE writes */
> - "tlbi alle2;" /* Flush hypervisor TLB */
> - "dsb sy;" /* Ensure completion of TLB flush */
> - "isb;"
> - : : : "memory");
> -}
> +TLB_HELPER(flush_xen_tlb_local, alle2);
>
> /* Flush TLB of local processor for address va. */
> static inline void __flush_xen_tlb_one_local(vaddr_t va)
>
With minor notes,
Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Xen-devel] [PATCH 6/7] xen/arm: tlbflush: Rework TLB helpers
@ 2019-04-25 18:01 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-25 18:01 UTC (permalink / raw)
To: Julien Grall, xen-devel; +Cc: Oleksandr_Tyshchenko, sstabellini, Andrii_Anisov
On 17.04.19 20:58, Julien Grall wrote:
> All the TLBs helpers invalidate all the TLB entries are using the same
> pattern:
> DSB SY
> TLBI ...
> DSB SY
> ISB
>
> This pattern is following pattern recommended by the Arm Arm to ensure
> visibility of updates to translation tables (see K10-5610 in ARM DDI
> 0487.A.k).
I can't find 0487.A.k, only aj [1], next one is b.
I guess you are referring `Ensuring the visibility of updates to translation tables for a multiprocessor`?
[1] https://developer.arm.com/docs/ddi0487/aj
>
> We have been a bit too eager in Xen and use system-wide DSBs when this
> can be limited to the inner-shareable domain.
>
> Furthermore, the first DSB can be restrict further to only store in the
> inner-shareable domain. This is because the DSB is here to ensure
> visibility of the update to translation table walks.
>
> Lastly, there are a lack of documentation in most of the TLBs helper.
>
> Rather than trying to update the helpers one by one, this patch
> introduce a per-arch macro to generate the TLB helpers. This will be
> easier to update the TLBs helper in the future and the documentation.
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
> ---
> xen/include/asm-arm/arm32/flushtlb.h | 73 ++++++++++++++--------------------
> xen/include/asm-arm/arm64/flushtlb.h | 76 +++++++++++++++---------------------
> 2 files changed, 60 insertions(+), 89 deletions(-)
>
> diff --git a/xen/include/asm-arm/arm32/flushtlb.h b/xen/include/asm-arm/arm32/flushtlb.h
> index b629db61cb..9085e65011 100644
> --- a/xen/include/asm-arm/arm32/flushtlb.h
> +++ b/xen/include/asm-arm/arm32/flushtlb.h
> @@ -1,59 +1,44 @@
> #ifndef __ASM_ARM_ARM32_FLUSHTLB_H__
> #define __ASM_ARM_ARM32_FLUSHTLB_H__
>
> -/* Flush local TLBs, current VMID only */
> -static inline void flush_guest_tlb_local(void)
> -{
> - dsb(sy);
> -
> - WRITE_CP32((uint32_t) 0, TLBIALL);
> -
> - dsb(sy);
> - isb();
> +/*
> + * Every invalidation operation use the following patterns:
> + *
> + * DSB ISHST // Ensure prior page-tables updates have completed
> + * TLBI... // Invalidate the TLB
> + * DSB ISH // Ensure the TLB invalidation has completed
> + * ISB // See explanation below
> + *
> + * For Xen page-tables the ISB will discard any instructions fetched
> + * from the old mappings.
> + *
> + * For the Stage-2 page-tables the ISB ensures the completion of the DSB
> + * (and therefore the TLB invalidation) before continuing. So we know
> + * the TLBs cannot contain an entry for a mapping we may have removed.
> + */
> +#define TLB_HELPER(name, tlbop) \
> +static inline void name(void) \
> +{ \
> + dsb(ishst); \
> + WRITE_CP32(0, tlbop); \
> + dsb(ish); \
> + isb(); \
> }
>
> -/* Flush inner shareable TLBs, current VMID only */
> -static inline void flush_guest_tlb(void)
> -{
> - dsb(sy);
> -
> - WRITE_CP32((uint32_t) 0, TLBIALLIS);
> +/* Flush local TLBs, current VMID only */
> +TLB_HELPER(flush_guest_tlb_local, TLBIALL);
>
> - dsb(sy);
> - isb();
> -}
> +/* Flush inner shareable TLBs, current VMID only */
> +TLB_HELPER(flush_guest_tlb, TLBIALLIS);
>
> /* Flush local TLBs, all VMIDs, non-hypervisor mode */
> -static inline void flush_all_guests_tlb_local(void)
> -{
> - dsb(sy);
> -
> - WRITE_CP32((uint32_t) 0, TLBIALLNSNH);
> -
> - dsb(sy);
> - isb();
> -}
> +TLB_HELPER(flush_all_guests_tlb_local, TLBIALLNSNH);
>
> /* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */
> -static inline void flush_all_guests_tlb(void)
> -{
> - dsb(sy);
> -
> - WRITE_CP32((uint32_t) 0, TLBIALLNSNHIS);
> -
> - dsb(sy);
> - isb();
> -}
> +TLB_HELPER(flush_all_guests_tlb, TLBIALLNSNHIS);
>
> /* Flush all hypervisor mappings from the TLB of the local processor. */
> -static inline void flush_xen_tlb_local(void)
> -{
> - asm volatile("dsb;" /* Ensure preceding are visible */
> - CMD_CP32(TLBIALLH)
> - "dsb;" /* Ensure completion of the TLB flush */
> - "isb;"
> - : : : "memory");
> -}
> +TLB_HELPER(flush_xen_tlb_local, TLBIALLH);
>
> /* Flush TLB of local processor for address va. */
> static inline void __flush_xen_tlb_one_local(vaddr_t va)
> diff --git a/xen/include/asm-arm/arm64/flushtlb.h b/xen/include/asm-arm/arm64/flushtlb.h
> index 2fed34b2ec..ceec59542e 100644
> --- a/xen/include/asm-arm/arm64/flushtlb.h
> +++ b/xen/include/asm-arm/arm64/flushtlb.h
> @@ -1,60 +1,46 @@
> #ifndef __ASM_ARM_ARM64_FLUSHTLB_H__
> #define __ASM_ARM_ARM64_FLUSHTLB_H__
>
> -/* Flush local TLBs, current VMID only */
> -static inline void flush_guest_tlb_local(void)
> -{
> - asm volatile(
> - "dsb sy;"
> - "tlbi vmalls12e1;"
> - "dsb sy;"
> - "isb;"
> - : : : "memory");
> +/*
> + * Every invalidation operation use the following patterns:
> + *
> + * DSB ISHST // Ensure prior page-tables updates have completed
> + * TLBI... // Invalidate the TLB
> + * DSB ISH // Ensure the TLB invalidation has completed
> + * ISB // See explanation below
> + *
> + * For Xen page-tables the ISB will discard any instructions fetched
> + * from the old mappings.
> + *
> + * For the Stage-2 page-tables the ISB ensures the completion of the DSB
> + * (and therefore the TLB invalidation) before continuing. So we know
> + * the TLBs cannot contain an entry for a mapping we may have removed.
> + */
> +#define TLB_HELPER(name, tlbop) \
> +static inline void name(void) \
> +{ \
> + asm volatile( \
> + "dsb ishst;" \
> + "tlbi " # tlbop ";" \
> + "dsb ish;" \
> + "isb;" \
> + : : : "memory"); \
> }
>
> +/* Flush local TLBs, current VMID only. */
> +TLB_HELPER(flush_guest_tlb_local, vmalls12e1);
> +
> /* Flush innershareable TLBs, current VMID only */
> -static inline void flush_guest_tlb(void)
> -{
> - asm volatile(
> - "dsb sy;"
> - "tlbi vmalls12e1is;"
> - "dsb sy;"
> - "isb;"
> - : : : "memory");
> -}
> +TLB_HELPER(flush_guest_tlb, vmalls12e1is);
>
> /* Flush local TLBs, all VMIDs, non-hypervisor mode */
> -static inline void flush_all_guests_tlb_local(void)
> -{
> - asm volatile(
> - "dsb sy;"
> - "tlbi alle1;"
> - "dsb sy;"
> - "isb;"
> - : : : "memory");
> -}
> +TLB_HELPER(flush_all_guests_tlb_local, alle1);
>
> /* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */
> -static inline void flush_all_guests_tlb(void)
> -{
> - asm volatile(
> - "dsb sy;"
> - "tlbi alle1is;"
> - "dsb sy;"
> - "isb;"
> - : : : "memory");
> -}
> +TLB_HELPER(flush_all_guests_tlb, alle1is);
>
> /* Flush all hypervisor mappings from the TLB of the local processor. */
> -static inline void flush_xen_tlb_local(void)
> -{
> - asm volatile (
> - "dsb sy;" /* Ensure visibility of PTE writes */
> - "tlbi alle2;" /* Flush hypervisor TLB */
> - "dsb sy;" /* Ensure completion of TLB flush */
> - "isb;"
> - : : : "memory");
> -}
> +TLB_HELPER(flush_xen_tlb_local, alle2);
>
> /* Flush TLB of local processor for address va. */
> static inline void __flush_xen_tlb_one_local(vaddr_t va)
>
With minor notes,
Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 7/7] xen/arm: mm: Flush the TLBs even if a mapping failed in create_xen_entries
@ 2019-04-25 18:03 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-25 18:03 UTC (permalink / raw)
To: Julien Grall, xen-devel; +Cc: Oleksandr_Tyshchenko, sstabellini, Andrii_Anisov
On 17.04.19 20:58, Julien Grall wrote:
> At the moment, create_xen_entries will only flush the TLBs if the full
> range has successfully been updated. This may lead to leave unwanted
> entries in the TLBs if we fail to update some entries.
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
> ---
Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Xen-devel] [PATCH 7/7] xen/arm: mm: Flush the TLBs even if a mapping failed in create_xen_entries
@ 2019-04-25 18:03 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-25 18:03 UTC (permalink / raw)
To: Julien Grall, xen-devel; +Cc: Oleksandr_Tyshchenko, sstabellini, Andrii_Anisov
On 17.04.19 20:58, Julien Grall wrote:
> At the moment, create_xen_entries will only flush the TLBs if the full
> range has successfully been updated. This may lead to leave unwanted
> entries in the TLBs if we fail to update some entries.
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
> ---
Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 1/7] xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place
@ 2019-04-25 20:26 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-25 20:26 UTC (permalink / raw)
To: Andrii Anisov, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
Hi,
On 25/04/2019 19:00, Andrii Anisov wrote:
>
>
> On 17.04.19 20:58, Julien Grall wrote:
>> The logic to set SCTLR_EL2.WXN is the same for the boot CPU and
>> non-boot CPU. So introduce a function to set the bit and clear TBLs.
> s/TBL/TLB/
>
>>
>> This new function will help us to document and update the logic in a
>> single place.
>>
>> Signed-off-by: Julien Grall <julien.grall@arm.com>
>
>> ---
>> xen/arch/arm/mm.c | 22 +++++++++++++++-------
>> 1 file changed, 15 insertions(+), 7 deletions(-)
>>
>> diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
>> index 01ae2cccc0..93ad118183 100644
>> --- a/xen/arch/arm/mm.c
>> +++ b/xen/arch/arm/mm.c
>> @@ -601,6 +601,19 @@ void __init remove_early_mappings(void)
>> flush_xen_data_tlb_range_va(BOOT_FDT_VIRT_START,
>> BOOT_FDT_SLOT_SIZE);
>> }
>> +/*
>> + * After boot, Xen page-tables should not contain mapping that are both
>> + * Writable and eXecutables.
>> + *
>> + * This should be called on each CPU to enforce the policy.
>> + */
>> +static void xen_pt_enforce_wnx(void)
> Could it be inline?
Why can't we let the compiler deciding for us? The more that inline is
pretty broken. See:
https://www.kernel.org/doc/local/inline.html
>
>> +{
>> + WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
>> + /* Flush everything after setting WXN bit. */
>> + flush_xen_text_tlb_local();
>> +}
>> +
>> extern void switch_ttbr(uint64_t ttbr);
>> /* Clear a translation table and clean & invalidate the cache */
>> @@ -702,10 +715,7 @@ void __init setup_pagetables(unsigned long
>> boot_phys_offset)
>> clear_table(boot_second);
>> clear_table(boot_third);
>> - /* From now on, no mapping may be both writable and executable. */
>> - WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
>> - /* Flush everything after setting WXN bit. */
>> - flush_xen_text_tlb_local();
>> + xen_pt_enforce_wnx();
>> #ifdef CONFIG_ARM_32
>> per_cpu(xen_pgtable, 0) = cpu0_pgtable;
>> @@ -777,9 +787,7 @@ int init_secondary_pagetables(int cpu)
>> /* MMU setup for secondary CPUS (which already have paging enabled) */
>> void mmu_init_secondary_cpu(void)
>> {
>> - /* From now on, no mapping may be both writable and executable. */
>> - WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
>> - flush_xen_text_tlb_local();
>> + xen_pt_enforce_wnx();
>> }
>> #ifdef CONFIG_ARM_32
>>
>
> With minor notes,
>
> Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
Thank you!
Cheers,
--
Julien Grall
_______________________________________________
Xen-devel mailing list
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https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Xen-devel] [PATCH 1/7] xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place
@ 2019-04-25 20:26 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-25 20:26 UTC (permalink / raw)
To: Andrii Anisov, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
Hi,
On 25/04/2019 19:00, Andrii Anisov wrote:
>
>
> On 17.04.19 20:58, Julien Grall wrote:
>> The logic to set SCTLR_EL2.WXN is the same for the boot CPU and
>> non-boot CPU. So introduce a function to set the bit and clear TBLs.
> s/TBL/TLB/
>
>>
>> This new function will help us to document and update the logic in a
>> single place.
>>
>> Signed-off-by: Julien Grall <julien.grall@arm.com>
>
>> ---
>> xen/arch/arm/mm.c | 22 +++++++++++++++-------
>> 1 file changed, 15 insertions(+), 7 deletions(-)
>>
>> diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
>> index 01ae2cccc0..93ad118183 100644
>> --- a/xen/arch/arm/mm.c
>> +++ b/xen/arch/arm/mm.c
>> @@ -601,6 +601,19 @@ void __init remove_early_mappings(void)
>> flush_xen_data_tlb_range_va(BOOT_FDT_VIRT_START,
>> BOOT_FDT_SLOT_SIZE);
>> }
>> +/*
>> + * After boot, Xen page-tables should not contain mapping that are both
>> + * Writable and eXecutables.
>> + *
>> + * This should be called on each CPU to enforce the policy.
>> + */
>> +static void xen_pt_enforce_wnx(void)
> Could it be inline?
Why can't we let the compiler deciding for us? The more that inline is
pretty broken. See:
https://www.kernel.org/doc/local/inline.html
>
>> +{
>> + WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
>> + /* Flush everything after setting WXN bit. */
>> + flush_xen_text_tlb_local();
>> +}
>> +
>> extern void switch_ttbr(uint64_t ttbr);
>> /* Clear a translation table and clean & invalidate the cache */
>> @@ -702,10 +715,7 @@ void __init setup_pagetables(unsigned long
>> boot_phys_offset)
>> clear_table(boot_second);
>> clear_table(boot_third);
>> - /* From now on, no mapping may be both writable and executable. */
>> - WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
>> - /* Flush everything after setting WXN bit. */
>> - flush_xen_text_tlb_local();
>> + xen_pt_enforce_wnx();
>> #ifdef CONFIG_ARM_32
>> per_cpu(xen_pgtable, 0) = cpu0_pgtable;
>> @@ -777,9 +787,7 @@ int init_secondary_pagetables(int cpu)
>> /* MMU setup for secondary CPUS (which already have paging enabled) */
>> void mmu_init_secondary_cpu(void)
>> {
>> - /* From now on, no mapping may be both writable and executable. */
>> - WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
>> - flush_xen_text_tlb_local();
>> + xen_pt_enforce_wnx();
>> }
>> #ifdef CONFIG_ARM_32
>>
>
> With minor notes,
>
> Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
Thank you!
Cheers,
--
Julien Grall
_______________________________________________
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 2/7] xen/arm: Remove flush_xen_text_tlb_local()
@ 2019-04-25 20:37 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-25 20:37 UTC (permalink / raw)
To: Andrii Anisov, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
On 25/04/2019 19:00, Andrii Anisov wrote:
> Hello Julien,
Hi,
> On 17.04.19 20:58, Julien Grall wrote:
>> The function flush_xen_text_tlb_local() has been misused and will result
>> to invalidate the instruction cache more than necessary.
>>
>> For instance, there are no need to invalidate the instruction cache if
>> we are setting SCTLR_EL2.WXN.
>>
>> There are effectively only one caller (i.e free_init_memory() would
>> who need to invalidate the instruction cache.
>>
>> So rather than keeping around the function flush_xen_text_tlb_local()
>> around, replace it with call to flush_xen_tlb_local() and explicitely
>> flush the cache when necessary.
>>
>> Signed-off-by: Julien Grall <julien.grall@arm.com>
>> ---
>> xen/arch/arm/mm.c | 17 ++++++++++++++---
>> xen/include/asm-arm/arm32/page.h | 23 +++++++++--------------
>> xen/include/asm-arm/arm64/page.h | 21 +++++----------------
>> 3 files changed, 28 insertions(+), 33 deletions(-)
>>
>> diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
>> index 93ad118183..dfbe39c70a 100644
>> --- a/xen/arch/arm/mm.c
>> +++ b/xen/arch/arm/mm.c
>> @@ -610,8 +610,12 @@ void __init remove_early_mappings(void)
>> static void xen_pt_enforce_wnx(void)
>> {
>> WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
>> - /* Flush everything after setting WXN bit. */
>> - flush_xen_text_tlb_local();
>> + /*
>> + * The TLBs may cache SCTLR_EL2.WXN. So ensure it is synchronized
>> + * before flushing the TLBs.
> I'm not sure about the comment above, it looks a bit confusing to me.
> As per my understanding flushing TLB is called to remove cached entries
> together with cached SCTLR_EL2.WXN.
> And isb before to tlb flush ensures that WXN is set prior to flush so
> that all new TLB entries will be fetched
> with this flag set.
The understanding is correct. I am not entirely sure how I can improve
the comment.
To be honest, I am not entirely sure whether the isb() is necessary
here. At worst, an entry of an existing mappings is not cached with the
SCTLR_EL2.WXN set. This may only defer the problem is an entry is
incorrectly configured before the flush. This is done early at boot (and
will be done much earlier in [1]). So I am kind of tempted to drop the
isb() here.
[...]
> With minor notes,
>
> Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
>
Thank you!
Cheers,
[1]
https://lists.xenproject.org/archives/html/xen-devel/2019-04/msg01667.html
--
Julien Grall
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Xen-devel] [PATCH 2/7] xen/arm: Remove flush_xen_text_tlb_local()
@ 2019-04-25 20:37 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-25 20:37 UTC (permalink / raw)
To: Andrii Anisov, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
On 25/04/2019 19:00, Andrii Anisov wrote:
> Hello Julien,
Hi,
> On 17.04.19 20:58, Julien Grall wrote:
>> The function flush_xen_text_tlb_local() has been misused and will result
>> to invalidate the instruction cache more than necessary.
>>
>> For instance, there are no need to invalidate the instruction cache if
>> we are setting SCTLR_EL2.WXN.
>>
>> There are effectively only one caller (i.e free_init_memory() would
>> who need to invalidate the instruction cache.
>>
>> So rather than keeping around the function flush_xen_text_tlb_local()
>> around, replace it with call to flush_xen_tlb_local() and explicitely
>> flush the cache when necessary.
>>
>> Signed-off-by: Julien Grall <julien.grall@arm.com>
>> ---
>> xen/arch/arm/mm.c | 17 ++++++++++++++---
>> xen/include/asm-arm/arm32/page.h | 23 +++++++++--------------
>> xen/include/asm-arm/arm64/page.h | 21 +++++----------------
>> 3 files changed, 28 insertions(+), 33 deletions(-)
>>
>> diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
>> index 93ad118183..dfbe39c70a 100644
>> --- a/xen/arch/arm/mm.c
>> +++ b/xen/arch/arm/mm.c
>> @@ -610,8 +610,12 @@ void __init remove_early_mappings(void)
>> static void xen_pt_enforce_wnx(void)
>> {
>> WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
>> - /* Flush everything after setting WXN bit. */
>> - flush_xen_text_tlb_local();
>> + /*
>> + * The TLBs may cache SCTLR_EL2.WXN. So ensure it is synchronized
>> + * before flushing the TLBs.
> I'm not sure about the comment above, it looks a bit confusing to me.
> As per my understanding flushing TLB is called to remove cached entries
> together with cached SCTLR_EL2.WXN.
> And isb before to tlb flush ensures that WXN is set prior to flush so
> that all new TLB entries will be fetched
> with this flag set.
The understanding is correct. I am not entirely sure how I can improve
the comment.
To be honest, I am not entirely sure whether the isb() is necessary
here. At worst, an entry of an existing mappings is not cached with the
SCTLR_EL2.WXN set. This may only defer the problem is an entry is
incorrectly configured before the flush. This is done early at boot (and
will be done much earlier in [1]). So I am kind of tempted to drop the
isb() here.
[...]
> With minor notes,
>
> Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
>
Thank you!
Cheers,
[1]
https://lists.xenproject.org/archives/html/xen-devel/2019-04/msg01667.html
--
Julien Grall
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 6/7] xen/arm: tlbflush: Rework TLB helpers
@ 2019-04-25 20:42 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-25 20:42 UTC (permalink / raw)
To: Andrii Anisov, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
On 25/04/2019 19:01, Andrii Anisov wrote:
>
>
> On 17.04.19 20:58, Julien Grall wrote:
>> All the TLBs helpers invalidate all the TLB entries are using the same
>> pattern:
>> DSB SY
>> TLBI ...
>> DSB SY
>> ISB
>>
>> This pattern is following pattern recommended by the Arm Arm to ensure
>> visibility of updates to translation tables (see K10-5610 in ARM DDI
>> 0487.A.k).
>
> I can't find 0487.A.k, only aj [1], next one is b.
> I guess you are referring `Ensuring the visibility of updates to
> translation tables for a multiprocessor`?
Oh, I vaguely remember a version of the Arm Arm been re-issued because
of the mistakes during the release. This might well have been A.k.
I am not sure why I use A.k because this is a pretty old spec. I should
have used the last one (i.e D.a).
Anyway, I am indeed referring to `Ensuring the visibility of updates to
translation tables for a multiprocessor`. I will update the commit message.
[...]
>
> With minor notes,
>
> Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
Thank you!
Cheers,
--
Julien Grall
_______________________________________________
Xen-devel mailing list
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https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Xen-devel] [PATCH 6/7] xen/arm: tlbflush: Rework TLB helpers
@ 2019-04-25 20:42 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-25 20:42 UTC (permalink / raw)
To: Andrii Anisov, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
On 25/04/2019 19:01, Andrii Anisov wrote:
>
>
> On 17.04.19 20:58, Julien Grall wrote:
>> All the TLBs helpers invalidate all the TLB entries are using the same
>> pattern:
>> DSB SY
>> TLBI ...
>> DSB SY
>> ISB
>>
>> This pattern is following pattern recommended by the Arm Arm to ensure
>> visibility of updates to translation tables (see K10-5610 in ARM DDI
>> 0487.A.k).
>
> I can't find 0487.A.k, only aj [1], next one is b.
> I guess you are referring `Ensuring the visibility of updates to
> translation tables for a multiprocessor`?
Oh, I vaguely remember a version of the Arm Arm been re-issued because
of the mistakes during the release. This might well have been A.k.
I am not sure why I use A.k because this is a pretty old spec. I should
have used the last one (i.e D.a).
Anyway, I am indeed referring to `Ensuring the visibility of updates to
translation tables for a multiprocessor`. I will update the commit message.
[...]
>
> With minor notes,
>
> Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
Thank you!
Cheers,
--
Julien Grall
_______________________________________________
Xen-devel mailing list
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https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 1/7] xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place
@ 2019-04-26 13:48 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-26 13:48 UTC (permalink / raw)
To: Julien Grall, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
Hello Julien,
On 25.04.19 23:26, Julien Grall wrote:
> Why can't we let the compiler deciding for us? The more that inline is
> pretty broken. See:
>
> https://www.kernel.org/doc/local/inline.html
Ah, ok. So let it be.
--
Sincerely,
Andrii Anisov.
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Xen-devel] [PATCH 1/7] xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place
@ 2019-04-26 13:48 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-26 13:48 UTC (permalink / raw)
To: Julien Grall, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
Hello Julien,
On 25.04.19 23:26, Julien Grall wrote:
> Why can't we let the compiler deciding for us? The more that inline is
> pretty broken. See:
>
> https://www.kernel.org/doc/local/inline.html
Ah, ok. So let it be.
--
Sincerely,
Andrii Anisov.
_______________________________________________
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 6/7] xen/arm: tlbflush: Rework TLB helpers
@ 2019-04-26 13:49 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-26 13:49 UTC (permalink / raw)
To: Julien Grall, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
On 25.04.19 23:42, Julien Grall wrote:
> I am not sure why I use A.k because this is a pretty old spec.
I did mean that A.k. is not publicly available, even now, so it is not quite right to refer such a document, at least without mentioning it is internal.
> I should
> have used the last one (i.e D.a).
> Anyway, I am indeed referring to `Ensuring the visibility of updates to
> translation tables for a multiprocessor`. I will update the commit message.
Cool.
--
Sincerely,
Andrii Anisov.
_______________________________________________
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Xen-devel] [PATCH 6/7] xen/arm: tlbflush: Rework TLB helpers
@ 2019-04-26 13:49 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-26 13:49 UTC (permalink / raw)
To: Julien Grall, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
On 25.04.19 23:42, Julien Grall wrote:
> I am not sure why I use A.k because this is a pretty old spec.
I did mean that A.k. is not publicly available, even now, so it is not quite right to refer such a document, at least without mentioning it is internal.
> I should
> have used the last one (i.e D.a).
> Anyway, I am indeed referring to `Ensuring the visibility of updates to
> translation tables for a multiprocessor`. I will update the commit message.
Cool.
--
Sincerely,
Andrii Anisov.
_______________________________________________
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 2/7] xen/arm: Remove flush_xen_text_tlb_local()
@ 2019-04-26 13:50 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-26 13:50 UTC (permalink / raw)
To: Julien Grall, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
On 25.04.19 23:37, Julien Grall wrote:
> The understanding is correct. I am not entirely sure how I can improve
> the comment.
I've re-read the comment again, and realized it actually fits. So let it be.
>
> To be honest, I am not entirely sure whether the isb() is necessary
> here. At worst, an entry of an existing mappings is not cached with the
> SCTLR_EL2.WXN set. This may only defer the problem is an entry is
> incorrectly configured before the flush. This is done early at boot (and
> will be done much earlier in [1]).Well, following this logic we may finish with TLB flush is not needed here at all. Because entries, already reached TLB, were configured before, and are believed valid. All the next will have WXN set.
But in this case, ISB is needed as an exact point from which all new TLB entries will have WXN.
> So I am kind of tempted to drop the
> isb() here.
--
Sincerely,
Andrii Anisov.
_______________________________________________
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Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Xen-devel] [PATCH 2/7] xen/arm: Remove flush_xen_text_tlb_local()
@ 2019-04-26 13:50 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-26 13:50 UTC (permalink / raw)
To: Julien Grall, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
On 25.04.19 23:37, Julien Grall wrote:
> The understanding is correct. I am not entirely sure how I can improve
> the comment.
I've re-read the comment again, and realized it actually fits. So let it be.
>
> To be honest, I am not entirely sure whether the isb() is necessary
> here. At worst, an entry of an existing mappings is not cached with the
> SCTLR_EL2.WXN set. This may only defer the problem is an entry is
> incorrectly configured before the flush. This is done early at boot (and
> will be done much earlier in [1]).Well, following this logic we may finish with TLB flush is not needed here at all. Because entries, already reached TLB, were configured before, and are believed valid. All the next will have WXN set.
But in this case, ISB is needed as an exact point from which all new TLB entries will have WXN.
> So I am kind of tempted to drop the
> isb() here.
--
Sincerely,
Andrii Anisov.
_______________________________________________
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 6/7] xen/arm: tlbflush: Rework TLB helpers
@ 2019-04-26 14:06 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-26 14:06 UTC (permalink / raw)
To: Andrii Anisov, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
Hi,
On 26/04/2019 14:49, Andrii Anisov wrote:
>
>
> On 25.04.19 23:42, Julien Grall wrote:
>> I am not sure why I use A.k because this is a pretty old spec.
> I did mean that A.k. is not publicly available, even now, so it is not quite
> right to refer such a document, at least without mentioning it is internal
Please avoid to take my words out of context... As you read the sentence above,
you probably noticed that A.k was published with defects in it and probably the
reasons why it can't be found today.
I download all my specs from public website to avoid potential disclosure of
internal content. If you look at Google, the spec was actually public at some
point (see [1] for instance).
In what you quote, I merely pointed out that I should not have used it because
it is pretty old (~2 and half years).
Cheers,
[1] https://lkml.org/lkml/2017/3/3/247
--
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Xen-devel] [PATCH 6/7] xen/arm: tlbflush: Rework TLB helpers
@ 2019-04-26 14:06 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-26 14:06 UTC (permalink / raw)
To: Andrii Anisov, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
Hi,
On 26/04/2019 14:49, Andrii Anisov wrote:
>
>
> On 25.04.19 23:42, Julien Grall wrote:
>> I am not sure why I use A.k because this is a pretty old spec.
> I did mean that A.k. is not publicly available, even now, so it is not quite
> right to refer such a document, at least without mentioning it is internal
Please avoid to take my words out of context... As you read the sentence above,
you probably noticed that A.k was published with defects in it and probably the
reasons why it can't be found today.
I download all my specs from public website to avoid potential disclosure of
internal content. If you look at Google, the spec was actually public at some
point (see [1] for instance).
In what you quote, I merely pointed out that I should not have used it because
it is pretty old (~2 and half years).
Cheers,
[1] https://lkml.org/lkml/2017/3/3/247
--
Julien Grall
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 2/7] xen/arm: Remove flush_xen_text_tlb_local()
@ 2019-04-26 14:15 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-26 14:15 UTC (permalink / raw)
To: Julien Grall, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
Julien,
Sorry, reply format is broken. It should be as following:
On 26.04.19 16:50, Andrii Anisov wrote:
>> To be honest, I am not entirely sure whether the isb() is necessary
>> here. At worst, an entry of an existing mappings is not cached with the
>> SCTLR_EL2.WXN set. This may only defer the problem is an entry is
>> incorrectly configured before the flush. This is done early at boot (and
>> will be done much earlier in [1]).
Well, following this logic we may finish with TLB flush is not needed here at all. Because entries, already reached TLB, were configured before, and are believed valid. All the next will have WXN set.
But in this case, ISB is needed as an exact point from which all new TLB entries will have WXN.
>> So I am kind of tempted to drop the
>> isb() here.
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Xen-devel] [PATCH 2/7] xen/arm: Remove flush_xen_text_tlb_local()
@ 2019-04-26 14:15 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-26 14:15 UTC (permalink / raw)
To: Julien Grall, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
Julien,
Sorry, reply format is broken. It should be as following:
On 26.04.19 16:50, Andrii Anisov wrote:
>> To be honest, I am not entirely sure whether the isb() is necessary
>> here. At worst, an entry of an existing mappings is not cached with the
>> SCTLR_EL2.WXN set. This may only defer the problem is an entry is
>> incorrectly configured before the flush. This is done early at boot (and
>> will be done much earlier in [1]).
Well, following this logic we may finish with TLB flush is not needed here at all. Because entries, already reached TLB, were configured before, and are believed valid. All the next will have WXN set.
But in this case, ISB is needed as an exact point from which all new TLB entries will have WXN.
>> So I am kind of tempted to drop the
>> isb() here.
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 2/7] xen/arm: Remove flush_xen_text_tlb_local()
@ 2019-04-26 14:31 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-26 14:31 UTC (permalink / raw)
To: Andrii Anisov, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
On 26/04/2019 15:15, Andrii Anisov wrote:
> Julien,
>
> Sorry, reply format is broken. It should be as following:
>
> On 26.04.19 16:50, Andrii Anisov wrote:
>>> To be honest, I am not entirely sure whether the isb() is necessary
>>> here. At worst, an entry of an existing mappings is not cached with the
>>> SCTLR_EL2.WXN set. This may only defer the problem is an entry is
>>> incorrectly configured before the flush. This is done early at boot (and
>>> will be done much earlier in [1]).
>
>
> Well, following this logic we may finish with TLB flush is not needed here at
> all. Because entries, already reached TLB, were configured before, and are
> believed valid. All the next will have WXN set.
> But in this case, ISB is needed as an exact point from which all new TLB entries
> will have WXN.
I am not sure to follow your point here. It wasn't clear to me whether the isb()
between setting SCTLR_EL2.WXN and TLB flush is strictly necessary. The TLB flush
contain an isb() so, it may has well be enough here.
However, speaking with Mark Rutland, it would be best to keep the sequence
suggest in this patch. So SCTLR_EL2.WXN is visible before the flush and the
flush will ensure all current entries are removed. So none of the entries should
have WXN cleared.
So I will keep this patch as is.
Cheers,
--
Julien Grall
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Xen-devel] [PATCH 2/7] xen/arm: Remove flush_xen_text_tlb_local()
@ 2019-04-26 14:31 ` Julien Grall
0 siblings, 0 replies; 52+ messages in thread
From: Julien Grall @ 2019-04-26 14:31 UTC (permalink / raw)
To: Andrii Anisov, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
On 26/04/2019 15:15, Andrii Anisov wrote:
> Julien,
>
> Sorry, reply format is broken. It should be as following:
>
> On 26.04.19 16:50, Andrii Anisov wrote:
>>> To be honest, I am not entirely sure whether the isb() is necessary
>>> here. At worst, an entry of an existing mappings is not cached with the
>>> SCTLR_EL2.WXN set. This may only defer the problem is an entry is
>>> incorrectly configured before the flush. This is done early at boot (and
>>> will be done much earlier in [1]).
>
>
> Well, following this logic we may finish with TLB flush is not needed here at
> all. Because entries, already reached TLB, were configured before, and are
> believed valid. All the next will have WXN set.
> But in this case, ISB is needed as an exact point from which all new TLB entries
> will have WXN.
I am not sure to follow your point here. It wasn't clear to me whether the isb()
between setting SCTLR_EL2.WXN and TLB flush is strictly necessary. The TLB flush
contain an isb() so, it may has well be enough here.
However, speaking with Mark Rutland, it would be best to keep the sequence
suggest in this patch. So SCTLR_EL2.WXN is visible before the flush and the
flush will ensure all current entries are removed. So none of the entries should
have WXN cleared.
So I will keep this patch as is.
Cheers,
--
Julien Grall
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 2/7] xen/arm: Remove flush_xen_text_tlb_local()
@ 2019-04-26 15:08 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-26 15:08 UTC (permalink / raw)
To: Julien Grall, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
On 26.04.19 17:31, Julien Grall wrote:
> However, speaking with Mark Rutland, it would be best to keep the sequence suggest in this patch. So SCTLR_EL2.WXN is visible before the flush and the flush will ensure all current entries are removed. So none of the entries should have WXN cleared.
>
> So I will keep this patch as is.
And it is right from my point of view.
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Xen-devel] [PATCH 2/7] xen/arm: Remove flush_xen_text_tlb_local()
@ 2019-04-26 15:08 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-26 15:08 UTC (permalink / raw)
To: Julien Grall, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
On 26.04.19 17:31, Julien Grall wrote:
> However, speaking with Mark Rutland, it would be best to keep the sequence suggest in this patch. So SCTLR_EL2.WXN is visible before the flush and the flush will ensure all current entries are removed. So none of the entries should have WXN cleared.
>
> So I will keep this patch as is.
And it is right from my point of view.
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 6/7] xen/arm: tlbflush: Rework TLB helpers
@ 2019-04-26 15:17 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-26 15:17 UTC (permalink / raw)
To: Julien Grall, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
On 26.04.19 17:06, Julien Grall wrote:
> Hi,
>
> On 26/04/2019 14:49, Andrii Anisov wrote:
>>
>>
>> On 25.04.19 23:42, Julien Grall wrote:
>>> I am not sure why I use A.k because this is a pretty old spec.
>> I did mean that A.k. is not publicly available, even now, so it is not quite right to refer such a document, at least without mentioning it is internal
> Please avoid to take my words out of context... As you read the sentence above, you probably noticed that A.k was published with defects in it and probably the reasons why it can't be found today.
>
> I download all my specs from public website to avoid potential disclosure of internal content. If you look at Google, the spec was actually public at some point (see [1] for instance).
I understand that. But now, at this patch publication and review moment, the A.k. document is not available. And is a bit confusing.
> In what you quote, I merely pointed out that I should not have used it because it is pretty old (~2 and half years).
Referring the most up-to-date document is alway a good choice.
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Xen-devel] [PATCH 6/7] xen/arm: tlbflush: Rework TLB helpers
@ 2019-04-26 15:17 ` Andrii Anisov
0 siblings, 0 replies; 52+ messages in thread
From: Andrii Anisov @ 2019-04-26 15:17 UTC (permalink / raw)
To: Julien Grall, xen-devel
Cc: Oleksandr_Tyshchenko, nd, Andrii_Anisov, sstabellini
On 26.04.19 17:06, Julien Grall wrote:
> Hi,
>
> On 26/04/2019 14:49, Andrii Anisov wrote:
>>
>>
>> On 25.04.19 23:42, Julien Grall wrote:
>>> I am not sure why I use A.k because this is a pretty old spec.
>> I did mean that A.k. is not publicly available, even now, so it is not quite right to refer such a document, at least without mentioning it is internal
> Please avoid to take my words out of context... As you read the sentence above, you probably noticed that A.k was published with defects in it and probably the reasons why it can't be found today.
>
> I download all my specs from public website to avoid potential disclosure of internal content. If you look at Google, the spec was actually public at some point (see [1] for instance).
I understand that. But now, at this patch publication and review moment, the A.k. document is not available. And is a bit confusing.
> In what you quote, I merely pointed out that I should not have used it because it is pretty old (~2 and half years).
Referring the most up-to-date document is alway a good choice.
--
Sincerely,
Andrii Anisov.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 52+ messages in thread
end of thread, other threads:[~2019-04-26 15:17 UTC | newest]
Thread overview: 52+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-17 17:58 [PATCH 0/7] xen/arm: TLB flush helpers rework Julien Grall
2019-04-17 17:58 ` [Xen-devel] " Julien Grall
2019-04-17 17:58 ` [PATCH 1/7] xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place Julien Grall
2019-04-17 17:58 ` [Xen-devel] " Julien Grall
2019-04-25 18:00 ` Andrii Anisov
2019-04-25 18:00 ` [Xen-devel] " Andrii Anisov
2019-04-25 20:26 ` Julien Grall
2019-04-25 20:26 ` [Xen-devel] " Julien Grall
2019-04-26 13:48 ` Andrii Anisov
2019-04-26 13:48 ` [Xen-devel] " Andrii Anisov
2019-04-17 17:58 ` [PATCH 2/7] xen/arm: Remove flush_xen_text_tlb_local() Julien Grall
2019-04-17 17:58 ` [Xen-devel] " Julien Grall
2019-04-25 18:00 ` Andrii Anisov
2019-04-25 18:00 ` [Xen-devel] " Andrii Anisov
2019-04-25 20:37 ` Julien Grall
2019-04-25 20:37 ` [Xen-devel] " Julien Grall
2019-04-26 13:50 ` Andrii Anisov
2019-04-26 13:50 ` [Xen-devel] " Andrii Anisov
2019-04-26 14:15 ` Andrii Anisov
2019-04-26 14:15 ` [Xen-devel] " Andrii Anisov
2019-04-26 14:31 ` Julien Grall
2019-04-26 14:31 ` [Xen-devel] " Julien Grall
2019-04-26 15:08 ` Andrii Anisov
2019-04-26 15:08 ` [Xen-devel] " Andrii Anisov
2019-04-17 17:58 ` [PATCH 3/7] xen/arm: tlbflush: Clarify the TLB helpers name Julien Grall
2019-04-17 17:58 ` [Xen-devel] " Julien Grall
2019-04-25 18:00 ` Andrii Anisov
2019-04-25 18:00 ` [Xen-devel] " Andrii Anisov
2019-04-17 17:58 ` [PATCH 4/7] xen/arm: page: Clarify the Xen TLBs " Julien Grall
2019-04-17 17:58 ` [Xen-devel] " Julien Grall
2019-04-25 18:00 ` Andrii Anisov
2019-04-25 18:00 ` [Xen-devel] " Andrii Anisov
2019-04-17 17:58 ` [PATCH 5/7] xen/arm: Gather all TLB flush helpers in tlbflush.h Julien Grall
2019-04-17 17:58 ` [Xen-devel] " Julien Grall
2019-04-25 18:01 ` Andrii Anisov
2019-04-25 18:01 ` [Xen-devel] " Andrii Anisov
2019-04-17 17:58 ` [PATCH 6/7] xen/arm: tlbflush: Rework TLB helpers Julien Grall
2019-04-17 17:58 ` [Xen-devel] " Julien Grall
2019-04-25 18:01 ` Andrii Anisov
2019-04-25 18:01 ` [Xen-devel] " Andrii Anisov
2019-04-25 20:42 ` Julien Grall
2019-04-25 20:42 ` [Xen-devel] " Julien Grall
2019-04-26 13:49 ` Andrii Anisov
2019-04-26 13:49 ` [Xen-devel] " Andrii Anisov
2019-04-26 14:06 ` Julien Grall
2019-04-26 14:06 ` [Xen-devel] " Julien Grall
2019-04-26 15:17 ` Andrii Anisov
2019-04-26 15:17 ` [Xen-devel] " Andrii Anisov
2019-04-17 17:58 ` [PATCH 7/7] xen/arm: mm: Flush the TLBs even if a mapping failed in create_xen_entries Julien Grall
2019-04-17 17:58 ` [Xen-devel] " Julien Grall
2019-04-25 18:03 ` Andrii Anisov
2019-04-25 18:03 ` [Xen-devel] " Andrii Anisov
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