[PATCH v3 0/3] Do basic initialization things

[PATCH v3 0/3] Do basic initialization things

[Oleksii Kurochko]

The patch series groups and updates the following patches:
1. xen/riscv: disable fpu
2. xen/riscv: initialize .bss section
3. xen/riscv: read/save hart_id and dtb_base passed by bootloader

---
Changes since v2:
 * Patch [xen/riscv: disable fpu] was moved to the start of start()
   function  to detect illegal usage of floating point
   earlier.
 * Add dummy_bss variable to make .bss initialization code more simple.
 * Change comparison of addresses from signed to unsigned.
 * Add the comment for start() function with the explanation what and
   how OpenSBI pass to start() function.
 * Clean up start() code related to read&save hart_id & dtb_base.   
---
Changes since v1:
 * initialization of .bss was moved to head.S
 * read/save/pass of hart_id and  dtb_base passed by a bootloader
   were moved to head.S. Also, it was updated start_xen() arguments
   to recieve hard_id & dtb_base
---

Oleksii Kurochko (3):
  xen/riscv: disable fpu
  xen/riscv: read/save hart_id and dtb_base passed by bootloader
  xen/riscv: initialize .bss section

 xen/arch/riscv/riscv64/head.S | 21 +++++++++++++++++++++
 xen/arch/riscv/setup.c        | 11 ++++++++++-
 2 files changed, 31 insertions(+), 1 deletion(-)

-- 
2.39.0

[PATCH v3 1/3] xen/riscv: disable fpu

[Oleksii Kurochko]

Disable FPU to detect illegal usage of floating point in kernel
space.

Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/arch/riscv/riscv64/head.S | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S
index ffd95f9f89..52fa41c778 100644
--- a/xen/arch/riscv/riscv64/head.S
+++ b/xen/arch/riscv/riscv64/head.S
@@ -6,6 +6,13 @@ ENTRY(start)
         /* Mask all interrupts */
         csrw    CSR_SIE, zero
 
+        /*
+         * Disable FPU to detect illegal usage of
+         * floating point in kernel space
+         */
+        li      t0, SSTATUS_FS
+        csrc    CSR_SSTATUS, t0
+
         la      sp, cpu0_boot_stack
         li      t0, STACK_SIZE
         add     sp, sp, t0
-- 
2.39.0

Re: [PATCH v3 1/3] xen/riscv: disable fpu

[Andrew Cooper]

On 03/03/2023 10:24 am, Oleksii Kurochko wrote:
> Disable FPU to detect illegal usage of floating point in kernel
> space.
>
> Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>

Re: [PATCH v3 1/3] xen/riscv: disable fpu

[Bobby Eshleman]

On Fri, Mar 03, 2023 at 12:24:22PM +0200, Oleksii Kurochko wrote:
> Disable FPU to detect illegal usage of floating point in kernel
> space.
> 
> Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
> ---
>  xen/arch/riscv/riscv64/head.S | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S
> index ffd95f9f89..52fa41c778 100644
> --- a/xen/arch/riscv/riscv64/head.S
> +++ b/xen/arch/riscv/riscv64/head.S
> @@ -6,6 +6,13 @@ ENTRY(start)
>          /* Mask all interrupts */
>          csrw    CSR_SIE, zero
>  
> +        /*
> +         * Disable FPU to detect illegal usage of
> +         * floating point in kernel space
> +         */
> +        li      t0, SSTATUS_FS
> +        csrc    CSR_SSTATUS, t0
> +
>          la      sp, cpu0_boot_stack
>          li      t0, STACK_SIZE
>          add     sp, sp, t0
> -- 
> 2.39.0
> 
> 

Acked-by: Bobby Eshleman <bobbyeshleman@gmail.com>

Re: [PATCH v3 1/3] xen/riscv: disable fpu

[Bobby Eshleman]

On Fri, Mar 03, 2023 at 12:24:22PM +0200, Oleksii Kurochko wrote:
> Disable FPU to detect illegal usage of floating point in kernel
> space.
> 
> Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
> ---
>  xen/arch/riscv/riscv64/head.S | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S
> index ffd95f9f89..52fa41c778 100644
> --- a/xen/arch/riscv/riscv64/head.S
> +++ b/xen/arch/riscv/riscv64/head.S
> @@ -6,6 +6,13 @@ ENTRY(start)
>          /* Mask all interrupts */
>          csrw    CSR_SIE, zero
>  
> +        /*
> +         * Disable FPU to detect illegal usage of
> +         * floating point in kernel space
> +         */
> +        li      t0, SSTATUS_FS
> +        csrc    CSR_SSTATUS, t0
> +
>          la      sp, cpu0_boot_stack
>          li      t0, STACK_SIZE
>          add     sp, sp, t0
> -- 
> 2.39.0
> 
> 

My last email had the wrong trailer:

Reviewed-by: Bobby Eshleman <bobbyeshleman@gmail.com>

[PATCH v3 2/3] xen/riscv: read/save hart_id and dtb_base passed by bootloader

[Oleksii Kurochko]

Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
Changes since v2:
 * Add the comment for start() function with the explanation what and
   how OpenSBI pass to start() function.
 * Clean up start() code related to read&save hart_id & dtb_base.  
---
Changes since v1:
 * read/save/pass of hart_id and  dtb_base passed by a bootloader
   were moved to head.S. 
 * Update start_xen() to recieve hard_id & dtb_base
---
 xen/arch/riscv/riscv64/head.S | 5 +++++
 xen/arch/riscv/setup.c        | 3 ++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S
index 52fa41c778..adf5d6c74a 100644
--- a/xen/arch/riscv/riscv64/head.S
+++ b/xen/arch/riscv/riscv64/head.S
@@ -2,6 +2,11 @@
 
         .section .text.header, "ax", %progbits
 
+        /*
+         * OpenSBI pass to start():
+         *   a0 -> hart_id ( bootcpu_id )
+         *   a1 -> dtb_base 
+         */
 ENTRY(start)
         /* Mask all interrupts */
         csrw    CSR_SIE, zero
diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c
index 1c87899e8e..d9723fe1c0 100644
--- a/xen/arch/riscv/setup.c
+++ b/xen/arch/riscv/setup.c
@@ -7,7 +7,8 @@
 unsigned char __initdata cpu0_boot_stack[STACK_SIZE]
     __aligned(STACK_SIZE);
 
-void __init noreturn start_xen(void)
+void __init noreturn start_xen(unsigned long bootcpu_id,
+                               unsigned long dtb_base)
 {
     early_printk("Hello from C env\n");
 
-- 
2.39.0

Re: [PATCH v3 2/3] xen/riscv: read/save hart_id and dtb_base passed by bootloader

[Andrew Cooper]

On 03/03/2023 10:24 am, Oleksii Kurochko wrote:
> Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>, although it
occurs to me...

> diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c
> index 1c87899e8e..d9723fe1c0 100644
> --- a/xen/arch/riscv/setup.c
> +++ b/xen/arch/riscv/setup.c
> @@ -7,7 +7,8 @@
>  unsigned char __initdata cpu0_boot_stack[STACK_SIZE]
>      __aligned(STACK_SIZE);
>  
> -void __init noreturn start_xen(void)
> +void __init noreturn start_xen(unsigned long bootcpu_id,
> +                               unsigned long dtb_base)

dtb_base probably wants renaming to dtb_paddr as the pagetable series is
just about to make it a non-identity mapping between the two address spaces.

Can fix on commit if you're happy with the suggestion?

~Andrew

Re: [PATCH v3 2/3] xen/riscv: read/save hart_id and dtb_base passed by bootloader

[Oleksii]

On Fri, 2023-03-03 at 10:27 +0000, Andrew Cooper wrote:
> On 03/03/2023 10:24 am, Oleksii Kurochko wrote:
> > Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
> 
> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>, although it
> occurs to me...
> 
> > diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c
> > index 1c87899e8e..d9723fe1c0 100644
> > --- a/xen/arch/riscv/setup.c
> > +++ b/xen/arch/riscv/setup.c
> > @@ -7,7 +7,8 @@
> >  unsigned char __initdata cpu0_boot_stack[STACK_SIZE]
> >      __aligned(STACK_SIZE);
> >  
> > -void __init noreturn start_xen(void)
> > +void __init noreturn start_xen(unsigned long bootcpu_id,
> > +                               unsigned long dtb_base)
> 
> dtb_base probably wants renaming to dtb_paddr as the pagetable series
> is
> just about to make it a non-identity mapping between the two address
> spaces.
> 
> Can fix on commit if you're happy with the suggestion?
I will be happy with that.

Thanks.

~ Oleksii

Re: [PATCH v3 2/3] xen/riscv: read/save hart_id and dtb_base passed by bootloader

[Bobby Eshleman]

On Fri, Mar 03, 2023 at 12:24:23PM +0200, Oleksii Kurochko wrote:
> Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
> ---
> Changes since v2:
>  * Add the comment for start() function with the explanation what and
>    how OpenSBI pass to start() function.
>  * Clean up start() code related to read&save hart_id & dtb_base.  
> ---
> Changes since v1:
>  * read/save/pass of hart_id and  dtb_base passed by a bootloader
>    were moved to head.S. 
>  * Update start_xen() to recieve hard_id & dtb_base
> ---
>  xen/arch/riscv/riscv64/head.S | 5 +++++
>  xen/arch/riscv/setup.c        | 3 ++-
>  2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S
> index 52fa41c778..adf5d6c74a 100644
> --- a/xen/arch/riscv/riscv64/head.S
> +++ b/xen/arch/riscv/riscv64/head.S
> @@ -2,6 +2,11 @@
>  
>          .section .text.header, "ax", %progbits
>  
> +        /*
> +         * OpenSBI pass to start():
> +         *   a0 -> hart_id ( bootcpu_id )
> +         *   a1 -> dtb_base 
> +         */
>  ENTRY(start)
>          /* Mask all interrupts */
>          csrw    CSR_SIE, zero
> diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c
> index 1c87899e8e..d9723fe1c0 100644
> --- a/xen/arch/riscv/setup.c
> +++ b/xen/arch/riscv/setup.c
> @@ -7,7 +7,8 @@
>  unsigned char __initdata cpu0_boot_stack[STACK_SIZE]
>      __aligned(STACK_SIZE);
>  
> -void __init noreturn start_xen(void)
> +void __init noreturn start_xen(unsigned long bootcpu_id,
> +                               unsigned long dtb_base)
>  {
>      early_printk("Hello from C env\n");
>  
> -- 
> 2.39.0
> 
> 

Reviewed-by: Bobby Eshleman <bobbyeshleman@gmail.com>

[PATCH v3 3/3] xen/riscv: initialize .bss section

[Oleksii Kurochko]

Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
 xen/arch/riscv/riscv64/head.S | 9 +++++++++
 xen/arch/riscv/setup.c        | 8 ++++++++
 2 files changed, 17 insertions(+)

diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S
index adf5d6c74a..8887f0cbd4 100644
--- a/xen/arch/riscv/riscv64/head.S
+++ b/xen/arch/riscv/riscv64/head.S
@@ -1,3 +1,4 @@
+#include <asm/asm.h>
 #include <asm/riscv_encoding.h>
 
         .section .text.header, "ax", %progbits
@@ -18,6 +19,14 @@ ENTRY(start)
         li      t0, SSTATUS_FS
         csrc    CSR_SSTATUS, t0
 
+        /* Clear the BSS */
+        la      t3, __bss_start
+        la      t4, __bss_end
+.L_clear_bss:
+        REG_S   zero, (t3)
+        add     t3, t3, __SIZEOF_POINTER__
+        bltu    t3, t4, .L_clear_bss
+
         la      sp, cpu0_boot_stack
         li      t0, STACK_SIZE
         add     sp, sp, t0
diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c
index d9723fe1c0..929565720b 100644
--- a/xen/arch/riscv/setup.c
+++ b/xen/arch/riscv/setup.c
@@ -7,6 +7,14 @@
 unsigned char __initdata cpu0_boot_stack[STACK_SIZE]
     __aligned(STACK_SIZE);
 
+/*  
+ * To be sure that .bss isn't zero. It will simplify code of
+ * .bss initialization.
+ * TODO:
+ *   To be deleted when the first real .bss user appears
+ */
+int dummy_bss __attribute__((unused));
+
 void __init noreturn start_xen(unsigned long bootcpu_id,
                                unsigned long dtb_base)
 {
-- 
2.39.0

Re: [PATCH v3 3/3] xen/riscv: initialize .bss section

[Andrew Cooper]

On 03/03/2023 10:24 am, Oleksii Kurochko wrote:
> Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

> diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S
> index adf5d6c74a..8887f0cbd4 100644
> --- a/xen/arch/riscv/riscv64/head.S
> +++ b/xen/arch/riscv/riscv64/head.S
> @@ -18,6 +19,14 @@ ENTRY(start)
>          li      t0, SSTATUS_FS
>          csrc    CSR_SSTATUS, t0
>  
> +        /* Clear the BSS */
> +        la      t3, __bss_start
> +        la      t4, __bss_end
> +.L_clear_bss:
> +        REG_S   zero, (t3)
> +        add     t3, t3, __SIZEOF_POINTER__
> +        bltu    t3, t4, .L_clear_bss

Using t3/t4 is fine, but it would also have been fine to use t0/t1.

~Andrew

Re: [PATCH v3 3/3] xen/riscv: initialize .bss section

[Oleksii]

On Fri, 2023-03-03 at 10:33 +0000, Andrew Cooper wrote:
> On 03/03/2023 10:24 am, Oleksii Kurochko wrote:
> > Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
> 
> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
> 
> > diff --git a/xen/arch/riscv/riscv64/head.S
> > b/xen/arch/riscv/riscv64/head.S
> > index adf5d6c74a..8887f0cbd4 100644
> > --- a/xen/arch/riscv/riscv64/head.S
> > +++ b/xen/arch/riscv/riscv64/head.S
> > @@ -18,6 +19,14 @@ ENTRY(start)
> >          li      t0, SSTATUS_FS
> >          csrc    CSR_SSTATUS, t0
> >  
> > +        /* Clear the BSS */
> > +        la      t3, __bss_start
> > +        la      t4, __bss_end
> > +.L_clear_bss:
> > +        REG_S   zero, (t3)
> > +        add     t3, t3, __SIZEOF_POINTER__
> > +        bltu    t3, t4, .L_clear_bss
> 
> Using t3/t4 is fine, but it would also have been fine to use t0/t1.
Yeah, I understand that. It was easier to rename and not confuse
something.

Could you please rename them during commit?
Have I to send new patch version?

~ Oleksii

Re: [PATCH v3 3/3] xen/riscv: initialize .bss section

[Andrew Cooper]

On 03/03/2023 10:42 am, Oleksii wrote:
> On Fri, 2023-03-03 at 10:33 +0000, Andrew Cooper wrote:
>> On 03/03/2023 10:24 am, Oleksii Kurochko wrote:
>>> Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
>> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
>>
>>> diff --git a/xen/arch/riscv/riscv64/head.S
>>> b/xen/arch/riscv/riscv64/head.S
>>> index adf5d6c74a..8887f0cbd4 100644
>>> --- a/xen/arch/riscv/riscv64/head.S
>>> +++ b/xen/arch/riscv/riscv64/head.S
>>> @@ -18,6 +19,14 @@ ENTRY(start)
>>>          li      t0, SSTATUS_FS
>>>          csrc    CSR_SSTATUS, t0
>>>  
>>> +        /* Clear the BSS */
>>> +        la      t3, __bss_start
>>> +        la      t4, __bss_end
>>> +.L_clear_bss:
>>> +        REG_S   zero, (t3)
>>> +        add     t3, t3, __SIZEOF_POINTER__
>>> +        bltu    t3, t4, .L_clear_bss
>> Using t3/t4 is fine, but it would also have been fine to use t0/t1.
> Yeah, I understand that. It was easier to rename and not confuse
> something.
>
> Could you please rename them during commit?
> Have I to send new patch version?

No need to send another patch.  TBH, I wasn't intending to change it at
all - this was just supposed to be a note - but I can if you'd prefer.

~Andrew

Re: [PATCH v3 3/3] xen/riscv: initialize .bss section

[Oleksii]

On Fri, 2023-03-03 at 10:53 +0000, Andrew Cooper wrote:
> On 03/03/2023 10:42 am, Oleksii wrote:
> > On Fri, 2023-03-03 at 10:33 +0000, Andrew Cooper wrote:
> > > On 03/03/2023 10:24 am, Oleksii Kurochko wrote:
> > > > Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
> > > Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
> > > 
> > > > diff --git a/xen/arch/riscv/riscv64/head.S
> > > > b/xen/arch/riscv/riscv64/head.S
> > > > index adf5d6c74a..8887f0cbd4 100644
> > > > --- a/xen/arch/riscv/riscv64/head.S
> > > > +++ b/xen/arch/riscv/riscv64/head.S
> > > > @@ -18,6 +19,14 @@ ENTRY(start)
> > > >          li      t0, SSTATUS_FS
> > > >          csrc    CSR_SSTATUS, t0
> > > >  
> > > > +        /* Clear the BSS */
> > > > +        la      t3, __bss_start
> > > > +        la      t4, __bss_end
> > > > +.L_clear_bss:
> > > > +        REG_S   zero, (t3)
> > > > +        add     t3, t3, __SIZEOF_POINTER__
> > > > +        bltu    t3, t4, .L_clear_bss
> > > Using t3/t4 is fine, but it would also have been fine to use
> > > t0/t1.
> > Yeah, I understand that. It was easier to rename and not confuse
> > something.
> > 
> > Could you please rename them during commit?
> > Have I to send new patch version?
> 
> No need to send another patch.  TBH, I wasn't intending to change it
> at
> all - this was just supposed to be a note - but I can if you'd
> prefer.
Feel free to do that.

Thanks.

~ Oleksii

Re: [PATCH v3 3/3] xen/riscv: initialize .bss section

[Bobby Eshleman]

On Fri, Mar 03, 2023 at 12:24:24PM +0200, Oleksii Kurochko wrote:
> Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
> ---
>  xen/arch/riscv/riscv64/head.S | 9 +++++++++
>  xen/arch/riscv/setup.c        | 8 ++++++++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S
> index adf5d6c74a..8887f0cbd4 100644
> --- a/xen/arch/riscv/riscv64/head.S
> +++ b/xen/arch/riscv/riscv64/head.S
> @@ -1,3 +1,4 @@
> +#include <asm/asm.h>
>  #include <asm/riscv_encoding.h>
>  
>          .section .text.header, "ax", %progbits
> @@ -18,6 +19,14 @@ ENTRY(start)
>          li      t0, SSTATUS_FS
>          csrc    CSR_SSTATUS, t0
>  
> +        /* Clear the BSS */
> +        la      t3, __bss_start
> +        la      t4, __bss_end
> +.L_clear_bss:
> +        REG_S   zero, (t3)
> +        add     t3, t3, __SIZEOF_POINTER__
> +        bltu    t3, t4, .L_clear_bss
> +
>          la      sp, cpu0_boot_stack
>          li      t0, STACK_SIZE
>          add     sp, sp, t0
> diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c
> index d9723fe1c0..929565720b 100644
> --- a/xen/arch/riscv/setup.c
> +++ b/xen/arch/riscv/setup.c
> @@ -7,6 +7,14 @@
>  unsigned char __initdata cpu0_boot_stack[STACK_SIZE]
>      __aligned(STACK_SIZE);
>  
> +/*  
> + * To be sure that .bss isn't zero. It will simplify code of
> + * .bss initialization.
> + * TODO:
> + *   To be deleted when the first real .bss user appears
> + */
> +int dummy_bss __attribute__((unused));
> +
>  void __init noreturn start_xen(unsigned long bootcpu_id,
>                                 unsigned long dtb_base)
>  {
> -- 
> 2.39.0
> 
> 

Reviewed-by: Bobby Eshleman <bobbyeshleman@gmail.com>

Re: [PATCH v3 0/3] Do basic initialization things

[Bobby Eshleman]

[-- Attachment #1: Type: text/plain, Size: 1568 bytes --]

I just wanted to let you know I have this queued up to review, I’ve just
been very overloaded. I’ll give these a review in the coming week.

Best,
Bobby

On Fri, Mar 3, 2023 at 2:24 AM Oleksii Kurochko <oleksii.kurochko@gmail.com>
wrote:

> The patch series groups and updates the following patches:
> 1. xen/riscv: disable fpu
> 2. xen/riscv: initialize .bss section
> 3. xen/riscv: read/save hart_id and dtb_base passed by bootloader
>
> ---
> Changes since v2:
>  * Patch [xen/riscv: disable fpu] was moved to the start of start()
>    function  to detect illegal usage of floating point
>    earlier.
>  * Add dummy_bss variable to make .bss initialization code more simple.
>  * Change comparison of addresses from signed to unsigned.
>  * Add the comment for start() function with the explanation what and
>    how OpenSBI pass to start() function.
>  * Clean up start() code related to read&save hart_id & dtb_base.
> ---
> Changes since v1:
>  * initialization of .bss was moved to head.S
>  * read/save/pass of hart_id and  dtb_base passed by a bootloader
>    were moved to head.S. Also, it was updated start_xen() arguments
>    to recieve hard_id & dtb_base
> ---
>
> Oleksii Kurochko (3):
>   xen/riscv: disable fpu
>   xen/riscv: read/save hart_id and dtb_base passed by bootloader
>   xen/riscv: initialize .bss section
>
>  xen/arch/riscv/riscv64/head.S | 21 +++++++++++++++++++++
>  xen/arch/riscv/setup.c        | 11 ++++++++++-
>  2 files changed, 31 insertions(+), 1 deletion(-)
>
> --
> 2.39.0
>
>

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Re: [PATCH v3 0/3] Do basic initialization things

[Andrew Cooper]

On 05/03/2023 7:06 am, Bobby Eshleman wrote:
> I just wanted to let you know I have this queued up to review, I’ve
> just been very overloaded. I’ll give these a review in the coming week.

Any update on this?

FWIW, all 3 look ready to go in to me, so hopefully its very easy.

~Andrew