* [Intel-gfx] [PATCH v2 03/11] drm/edid: slightly restructure timing and non-timing descriptor structs
@ 2022-03-28 9:17 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2022-03-28 9:17 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula, intel-gfx
The pixel clock is conceptually part of the detailed timings, while it's
just zero padding for display descriptors. Modify the structures to
reflect this. Rename struct detailed_non_pixel to
edid_display_descriptor to better reflect spec while at it. (Further
struct renames are left for follow-up work.)
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++---
drivers/gpu/drm/drm_edid.c | 12 ++++++------
include/drm/drm_edid.h | 9 +++++----
3 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b30656959fd8..e477f4b42b6b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -11537,7 +11537,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
{
int i = 0;
struct detailed_timing *timing;
- struct detailed_non_pixel *data;
+ struct edid_display_descriptor *data;
struct detailed_data_monitor_range *range;
struct amdgpu_dm_connector *amdgpu_dm_connector =
to_amdgpu_dm_connector(connector);
@@ -11592,7 +11592,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
for (i = 0; i < 4; i++) {
timing = &edid->detailed_timings[i];
- data = &timing->data.other_data;
+ data = &timing->data.descriptor;
range = &data->data.range;
/*
* Check if monitor has continuous frequency mode
@@ -11629,7 +11629,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
if (i >= 0 && vsdb_info.freesync_supported) {
timing = &edid->detailed_timings[i];
- data = &timing->data.other_data;
+ data = &timing->data.descriptor;
amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 13d05062d68c..ac80681d64f6 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2742,7 +2742,7 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
mode->clock = 1088 * 10;
else
- mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
+ mode->clock = le16_to_cpu(pt->pixel_clock) * 10;
mode->hdisplay = hactive;
mode->hsync_start = mode->hdisplay + hsync_offset;
@@ -2984,7 +2984,7 @@ static void
do_inferred_modes(struct detailed_timing *timing, void *c)
{
struct detailed_mode_closure *closure = c;
- struct detailed_non_pixel *data = &timing->data.other_data;
+ struct edid_display_descriptor *data = &timing->data.descriptor;
struct detailed_data_monitor_range *range = &data->data.range;
if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
@@ -3117,7 +3117,7 @@ static void
do_standard_modes(struct detailed_timing *timing, void *c)
{
struct detailed_mode_closure *closure = c;
- struct detailed_non_pixel *data = &timing->data.other_data;
+ struct edid_display_descriptor *data = &timing->data.descriptor;
struct drm_connector *connector = closure->connector;
struct edid *edid = closure->edid;
int i;
@@ -3187,7 +3187,7 @@ static int drm_cvt_modes(struct drm_connector *connector,
for (i = 0; i < 4; i++) {
int width, height;
- cvt = &(timing->data.other_data.data.cvt[i]);
+ cvt = &(timing->data.descriptor.data.cvt[i]);
if (!memcmp(cvt->code, empty, 3))
continue;
@@ -4494,7 +4494,7 @@ monitor_name(struct detailed_timing *t, void *data)
if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
return;
- *(u8 **)data = t->data.other_data.data.str.str;
+ *(u8 **)data = t->data.descriptor.data.str.str;
}
static int get_monitor_name(struct edid *edid, char name[13])
@@ -5223,7 +5223,7 @@ void get_monitor_range(struct detailed_timing *timing,
void *info_monitor_range)
{
struct drm_monitor_range_info *monitor_range = info_monitor_range;
- const struct detailed_non_pixel *data = &timing->data.other_data;
+ const struct edid_display_descriptor *data = &timing->data.descriptor;
const struct detailed_data_monitor_range *range = &data->data.range;
if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 144c495b99c4..8e322ef173a8 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -68,6 +68,7 @@ struct std_timing {
/* If detailed data is pixel timing */
struct detailed_pixel_timing {
+ __le16 pixel_clock; /* non-zero, need to multiply by 10 KHz */
u8 hactive_lo;
u8 hblank_lo;
u8 hactive_hblank_hi;
@@ -142,8 +143,9 @@ struct cvt_timing {
u8 code[3];
} __attribute__((packed));
-struct detailed_non_pixel {
- u8 pad1;
+struct edid_display_descriptor {
+ u16 pad0; /* 0 for Display Descriptor */
+ u8 pad1; /* 0 for Display Descriptor */
u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
fb=color point data, fa=standard timing data,
f9=undefined, f8=mfg. reserved */
@@ -168,10 +170,9 @@ struct detailed_non_pixel {
#define EDID_DETAIL_MONITOR_SERIAL 0xff
struct detailed_timing {
- __le16 pixel_clock; /* need to multiply by 10 KHz */
union {
struct detailed_pixel_timing pixel_data;
- struct detailed_non_pixel other_data;
+ struct edid_display_descriptor descriptor;
} data;
} __attribute__((packed));
--
2.30.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v2 03/11] drm/edid: slightly restructure timing and non-timing descriptor structs
2022-03-28 9:17 ` [Intel-gfx] " Jani Nikula
(?)
@ 2022-03-28 9:44 ` Jani Nikula
-1 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2022-03-28 9:44 UTC (permalink / raw)
To: dri-devel; +Cc: Leo Li, intel-gfx, Rodrigo Siqueira, amd-gfx
On Mon, 28 Mar 2022, Jani Nikula <jani.nikula@intel.com> wrote:
> The pixel clock is conceptually part of the detailed timings, while it's
> just zero padding for display descriptors. Modify the structures to
> reflect this. Rename struct detailed_non_pixel to
> edid_display_descriptor to better reflect spec while at it. (Further
> struct renames are left for follow-up work.)
>
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This one's missing:
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: amd-gfx@lists.freedesktop.org
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++---
> drivers/gpu/drm/drm_edid.c | 12 ++++++------
> include/drm/drm_edid.h | 9 +++++----
> 3 files changed, 14 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index b30656959fd8..e477f4b42b6b 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -11537,7 +11537,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
> {
> int i = 0;
> struct detailed_timing *timing;
> - struct detailed_non_pixel *data;
> + struct edid_display_descriptor *data;
> struct detailed_data_monitor_range *range;
> struct amdgpu_dm_connector *amdgpu_dm_connector =
> to_amdgpu_dm_connector(connector);
> @@ -11592,7 +11592,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
> for (i = 0; i < 4; i++) {
>
> timing = &edid->detailed_timings[i];
> - data = &timing->data.other_data;
> + data = &timing->data.descriptor;
> range = &data->data.range;
> /*
> * Check if monitor has continuous frequency mode
> @@ -11629,7 +11629,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
> i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
> if (i >= 0 && vsdb_info.freesync_supported) {
> timing = &edid->detailed_timings[i];
> - data = &timing->data.other_data;
> + data = &timing->data.descriptor;
>
> amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
> amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 13d05062d68c..ac80681d64f6 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -2742,7 +2742,7 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
> if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
> mode->clock = 1088 * 10;
> else
> - mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
> + mode->clock = le16_to_cpu(pt->pixel_clock) * 10;
>
> mode->hdisplay = hactive;
> mode->hsync_start = mode->hdisplay + hsync_offset;
> @@ -2984,7 +2984,7 @@ static void
> do_inferred_modes(struct detailed_timing *timing, void *c)
> {
> struct detailed_mode_closure *closure = c;
> - struct detailed_non_pixel *data = &timing->data.other_data;
> + struct edid_display_descriptor *data = &timing->data.descriptor;
> struct detailed_data_monitor_range *range = &data->data.range;
>
> if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
> @@ -3117,7 +3117,7 @@ static void
> do_standard_modes(struct detailed_timing *timing, void *c)
> {
> struct detailed_mode_closure *closure = c;
> - struct detailed_non_pixel *data = &timing->data.other_data;
> + struct edid_display_descriptor *data = &timing->data.descriptor;
> struct drm_connector *connector = closure->connector;
> struct edid *edid = closure->edid;
> int i;
> @@ -3187,7 +3187,7 @@ static int drm_cvt_modes(struct drm_connector *connector,
> for (i = 0; i < 4; i++) {
> int width, height;
>
> - cvt = &(timing->data.other_data.data.cvt[i]);
> + cvt = &(timing->data.descriptor.data.cvt[i]);
>
> if (!memcmp(cvt->code, empty, 3))
> continue;
> @@ -4494,7 +4494,7 @@ monitor_name(struct detailed_timing *t, void *data)
> if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
> return;
>
> - *(u8 **)data = t->data.other_data.data.str.str;
> + *(u8 **)data = t->data.descriptor.data.str.str;
> }
>
> static int get_monitor_name(struct edid *edid, char name[13])
> @@ -5223,7 +5223,7 @@ void get_monitor_range(struct detailed_timing *timing,
> void *info_monitor_range)
> {
> struct drm_monitor_range_info *monitor_range = info_monitor_range;
> - const struct detailed_non_pixel *data = &timing->data.other_data;
> + const struct edid_display_descriptor *data = &timing->data.descriptor;
> const struct detailed_data_monitor_range *range = &data->data.range;
>
> if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
> diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
> index 144c495b99c4..8e322ef173a8 100644
> --- a/include/drm/drm_edid.h
> +++ b/include/drm/drm_edid.h
> @@ -68,6 +68,7 @@ struct std_timing {
>
> /* If detailed data is pixel timing */
> struct detailed_pixel_timing {
> + __le16 pixel_clock; /* non-zero, need to multiply by 10 KHz */
> u8 hactive_lo;
> u8 hblank_lo;
> u8 hactive_hblank_hi;
> @@ -142,8 +143,9 @@ struct cvt_timing {
> u8 code[3];
> } __attribute__((packed));
>
> -struct detailed_non_pixel {
> - u8 pad1;
> +struct edid_display_descriptor {
> + u16 pad0; /* 0 for Display Descriptor */
> + u8 pad1; /* 0 for Display Descriptor */
> u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
> fb=color point data, fa=standard timing data,
> f9=undefined, f8=mfg. reserved */
> @@ -168,10 +170,9 @@ struct detailed_non_pixel {
> #define EDID_DETAIL_MONITOR_SERIAL 0xff
>
> struct detailed_timing {
> - __le16 pixel_clock; /* need to multiply by 10 KHz */
> union {
> struct detailed_pixel_timing pixel_data;
> - struct detailed_non_pixel other_data;
> + struct edid_display_descriptor descriptor;
> } data;
> } __attribute__((packed));
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 03/11] drm/edid: slightly restructure timing and non-timing descriptor structs
@ 2022-03-28 9:44 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2022-03-28 9:44 UTC (permalink / raw)
To: dri-devel
Cc: Leo Li, intel-gfx, Rodrigo Siqueira, amd-gfx, Harry Wentland,
ville.syrjala
On Mon, 28 Mar 2022, Jani Nikula <jani.nikula@intel.com> wrote:
> The pixel clock is conceptually part of the detailed timings, while it's
> just zero padding for display descriptors. Modify the structures to
> reflect this. Rename struct detailed_non_pixel to
> edid_display_descriptor to better reflect spec while at it. (Further
> struct renames are left for follow-up work.)
>
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This one's missing:
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: amd-gfx@lists.freedesktop.org
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++---
> drivers/gpu/drm/drm_edid.c | 12 ++++++------
> include/drm/drm_edid.h | 9 +++++----
> 3 files changed, 14 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index b30656959fd8..e477f4b42b6b 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -11537,7 +11537,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
> {
> int i = 0;
> struct detailed_timing *timing;
> - struct detailed_non_pixel *data;
> + struct edid_display_descriptor *data;
> struct detailed_data_monitor_range *range;
> struct amdgpu_dm_connector *amdgpu_dm_connector =
> to_amdgpu_dm_connector(connector);
> @@ -11592,7 +11592,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
> for (i = 0; i < 4; i++) {
>
> timing = &edid->detailed_timings[i];
> - data = &timing->data.other_data;
> + data = &timing->data.descriptor;
> range = &data->data.range;
> /*
> * Check if monitor has continuous frequency mode
> @@ -11629,7 +11629,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
> i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
> if (i >= 0 && vsdb_info.freesync_supported) {
> timing = &edid->detailed_timings[i];
> - data = &timing->data.other_data;
> + data = &timing->data.descriptor;
>
> amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
> amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 13d05062d68c..ac80681d64f6 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -2742,7 +2742,7 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
> if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
> mode->clock = 1088 * 10;
> else
> - mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
> + mode->clock = le16_to_cpu(pt->pixel_clock) * 10;
>
> mode->hdisplay = hactive;
> mode->hsync_start = mode->hdisplay + hsync_offset;
> @@ -2984,7 +2984,7 @@ static void
> do_inferred_modes(struct detailed_timing *timing, void *c)
> {
> struct detailed_mode_closure *closure = c;
> - struct detailed_non_pixel *data = &timing->data.other_data;
> + struct edid_display_descriptor *data = &timing->data.descriptor;
> struct detailed_data_monitor_range *range = &data->data.range;
>
> if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
> @@ -3117,7 +3117,7 @@ static void
> do_standard_modes(struct detailed_timing *timing, void *c)
> {
> struct detailed_mode_closure *closure = c;
> - struct detailed_non_pixel *data = &timing->data.other_data;
> + struct edid_display_descriptor *data = &timing->data.descriptor;
> struct drm_connector *connector = closure->connector;
> struct edid *edid = closure->edid;
> int i;
> @@ -3187,7 +3187,7 @@ static int drm_cvt_modes(struct drm_connector *connector,
> for (i = 0; i < 4; i++) {
> int width, height;
>
> - cvt = &(timing->data.other_data.data.cvt[i]);
> + cvt = &(timing->data.descriptor.data.cvt[i]);
>
> if (!memcmp(cvt->code, empty, 3))
> continue;
> @@ -4494,7 +4494,7 @@ monitor_name(struct detailed_timing *t, void *data)
> if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
> return;
>
> - *(u8 **)data = t->data.other_data.data.str.str;
> + *(u8 **)data = t->data.descriptor.data.str.str;
> }
>
> static int get_monitor_name(struct edid *edid, char name[13])
> @@ -5223,7 +5223,7 @@ void get_monitor_range(struct detailed_timing *timing,
> void *info_monitor_range)
> {
> struct drm_monitor_range_info *monitor_range = info_monitor_range;
> - const struct detailed_non_pixel *data = &timing->data.other_data;
> + const struct edid_display_descriptor *data = &timing->data.descriptor;
> const struct detailed_data_monitor_range *range = &data->data.range;
>
> if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
> diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
> index 144c495b99c4..8e322ef173a8 100644
> --- a/include/drm/drm_edid.h
> +++ b/include/drm/drm_edid.h
> @@ -68,6 +68,7 @@ struct std_timing {
>
> /* If detailed data is pixel timing */
> struct detailed_pixel_timing {
> + __le16 pixel_clock; /* non-zero, need to multiply by 10 KHz */
> u8 hactive_lo;
> u8 hblank_lo;
> u8 hactive_hblank_hi;
> @@ -142,8 +143,9 @@ struct cvt_timing {
> u8 code[3];
> } __attribute__((packed));
>
> -struct detailed_non_pixel {
> - u8 pad1;
> +struct edid_display_descriptor {
> + u16 pad0; /* 0 for Display Descriptor */
> + u8 pad1; /* 0 for Display Descriptor */
> u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
> fb=color point data, fa=standard timing data,
> f9=undefined, f8=mfg. reserved */
> @@ -168,10 +170,9 @@ struct detailed_non_pixel {
> #define EDID_DETAIL_MONITOR_SERIAL 0xff
>
> struct detailed_timing {
> - __le16 pixel_clock; /* need to multiply by 10 KHz */
> union {
> struct detailed_pixel_timing pixel_data;
> - struct detailed_non_pixel other_data;
> + struct edid_display_descriptor descriptor;
> } data;
> } __attribute__((packed));
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v2 03/11] drm/edid: slightly restructure timing and non-timing descriptor structs
@ 2022-03-28 9:44 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2022-03-28 9:44 UTC (permalink / raw)
To: dri-devel; +Cc: Leo Li, intel-gfx, Rodrigo Siqueira, amd-gfx, Harry Wentland
On Mon, 28 Mar 2022, Jani Nikula <jani.nikula@intel.com> wrote:
> The pixel clock is conceptually part of the detailed timings, while it's
> just zero padding for display descriptors. Modify the structures to
> reflect this. Rename struct detailed_non_pixel to
> edid_display_descriptor to better reflect spec while at it. (Further
> struct renames are left for follow-up work.)
>
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This one's missing:
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: amd-gfx@lists.freedesktop.org
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++---
> drivers/gpu/drm/drm_edid.c | 12 ++++++------
> include/drm/drm_edid.h | 9 +++++----
> 3 files changed, 14 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index b30656959fd8..e477f4b42b6b 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -11537,7 +11537,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
> {
> int i = 0;
> struct detailed_timing *timing;
> - struct detailed_non_pixel *data;
> + struct edid_display_descriptor *data;
> struct detailed_data_monitor_range *range;
> struct amdgpu_dm_connector *amdgpu_dm_connector =
> to_amdgpu_dm_connector(connector);
> @@ -11592,7 +11592,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
> for (i = 0; i < 4; i++) {
>
> timing = &edid->detailed_timings[i];
> - data = &timing->data.other_data;
> + data = &timing->data.descriptor;
> range = &data->data.range;
> /*
> * Check if monitor has continuous frequency mode
> @@ -11629,7 +11629,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
> i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
> if (i >= 0 && vsdb_info.freesync_supported) {
> timing = &edid->detailed_timings[i];
> - data = &timing->data.other_data;
> + data = &timing->data.descriptor;
>
> amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
> amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 13d05062d68c..ac80681d64f6 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -2742,7 +2742,7 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
> if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
> mode->clock = 1088 * 10;
> else
> - mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
> + mode->clock = le16_to_cpu(pt->pixel_clock) * 10;
>
> mode->hdisplay = hactive;
> mode->hsync_start = mode->hdisplay + hsync_offset;
> @@ -2984,7 +2984,7 @@ static void
> do_inferred_modes(struct detailed_timing *timing, void *c)
> {
> struct detailed_mode_closure *closure = c;
> - struct detailed_non_pixel *data = &timing->data.other_data;
> + struct edid_display_descriptor *data = &timing->data.descriptor;
> struct detailed_data_monitor_range *range = &data->data.range;
>
> if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
> @@ -3117,7 +3117,7 @@ static void
> do_standard_modes(struct detailed_timing *timing, void *c)
> {
> struct detailed_mode_closure *closure = c;
> - struct detailed_non_pixel *data = &timing->data.other_data;
> + struct edid_display_descriptor *data = &timing->data.descriptor;
> struct drm_connector *connector = closure->connector;
> struct edid *edid = closure->edid;
> int i;
> @@ -3187,7 +3187,7 @@ static int drm_cvt_modes(struct drm_connector *connector,
> for (i = 0; i < 4; i++) {
> int width, height;
>
> - cvt = &(timing->data.other_data.data.cvt[i]);
> + cvt = &(timing->data.descriptor.data.cvt[i]);
>
> if (!memcmp(cvt->code, empty, 3))
> continue;
> @@ -4494,7 +4494,7 @@ monitor_name(struct detailed_timing *t, void *data)
> if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
> return;
>
> - *(u8 **)data = t->data.other_data.data.str.str;
> + *(u8 **)data = t->data.descriptor.data.str.str;
> }
>
> static int get_monitor_name(struct edid *edid, char name[13])
> @@ -5223,7 +5223,7 @@ void get_monitor_range(struct detailed_timing *timing,
> void *info_monitor_range)
> {
> struct drm_monitor_range_info *monitor_range = info_monitor_range;
> - const struct detailed_non_pixel *data = &timing->data.other_data;
> + const struct edid_display_descriptor *data = &timing->data.descriptor;
> const struct detailed_data_monitor_range *range = &data->data.range;
>
> if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
> diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
> index 144c495b99c4..8e322ef173a8 100644
> --- a/include/drm/drm_edid.h
> +++ b/include/drm/drm_edid.h
> @@ -68,6 +68,7 @@ struct std_timing {
>
> /* If detailed data is pixel timing */
> struct detailed_pixel_timing {
> + __le16 pixel_clock; /* non-zero, need to multiply by 10 KHz */
> u8 hactive_lo;
> u8 hblank_lo;
> u8 hactive_hblank_hi;
> @@ -142,8 +143,9 @@ struct cvt_timing {
> u8 code[3];
> } __attribute__((packed));
>
> -struct detailed_non_pixel {
> - u8 pad1;
> +struct edid_display_descriptor {
> + u16 pad0; /* 0 for Display Descriptor */
> + u8 pad1; /* 0 for Display Descriptor */
> u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
> fb=color point data, fa=standard timing data,
> f9=undefined, f8=mfg. reserved */
> @@ -168,10 +170,9 @@ struct detailed_non_pixel {
> #define EDID_DETAIL_MONITOR_SERIAL 0xff
>
> struct detailed_timing {
> - __le16 pixel_clock; /* need to multiply by 10 KHz */
> union {
> struct detailed_pixel_timing pixel_data;
> - struct detailed_non_pixel other_data;
> + struct edid_display_descriptor descriptor;
> } data;
> } __attribute__((packed));
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-gfx] [PATCH v2 03/11] drm/edid: slightly restructure timing and non-timing descriptor structs
2022-03-28 9:17 ` [Intel-gfx] " Jani Nikula
(?)
(?)
@ 2022-03-28 11:45 ` kernel test robot
2022-03-28 13:20 ` Jani Nikula
-1 siblings, 1 reply; 42+ messages in thread
From: kernel test robot @ 2022-03-28 11:45 UTC (permalink / raw)
To: Jani Nikula, dri-devel; +Cc: jani.nikula, intel-gfx, kbuild-all
Hi Jani,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm/drm-next]
[also build test WARNING on drm-intel/for-linux-next drm-tip/drm-tip v5.17 next-20220328]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Jani-Nikula/drm-edid-constify-EDID-parsing-with-some-fixes/20220328-171858
base: git://anongit.freedesktop.org/drm/drm drm-next
config: x86_64-randconfig-a003-20220328 (https://download.01.org/0day-ci/archive/20220328/202203281926.AthxJpnK-lkp@intel.com/config)
compiler: gcc-9 (Ubuntu 9.4.0-1ubuntu1~20.04.1) 9.4.0
reproduce (this is a W=1 build):
# https://github.com/intel-lab-lkp/linux/commit/f538c9296c54ce8f878432153584a68939ffc111
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jani-Nikula/drm-edid-constify-EDID-parsing-with-some-fixes/20220328-171858
git checkout f538c9296c54ce8f878432153584a68939ffc111
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/tiny/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
drivers/gpu/drm/tiny/gm12u320.c:478:4: error: 'struct detailed_timing' has no member named 'pixel_clock'
478 | .pixel_clock = 3383,
| ^~~~~~~~~~~
>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
464 | static struct edid gm12u320_edid = {
| ^
......
478 | .pixel_clock = 3383,
| {{ }}
479 | /* hactive = 848, hblank = 256 */
480 | .data.pixel_data.hactive_lo = 0x50,
| }}
481 | .data.pixel_data.hblank_lo = 0x00,
| }}
482 | .data.pixel_data.hactive_hblank_hi = 0x31,
| }}
483 | /* vactive = 480, vblank = 28 */
484 | .data.pixel_data.vactive_lo = 0xe0,
| }}
485 | .data.pixel_data.vblank_lo = 0x1c,
| }}
486 | .data.pixel_data.vactive_vblank_hi = 0x10,
| }}
487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
488 | .data.pixel_data.hsync_offset_lo = 0x28,
| }}
489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
| }}
490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
| }}
491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
| }}
......
494 | }, {
| }}
drivers/gpu/drm/tiny/gm12u320.c:495:4: error: 'struct detailed_timing' has no member named 'pixel_clock'
495 | .pixel_clock = 0,
| ^~~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:496:9: error: 'union <anonymous>' has no member named 'other_data'
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| ^~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:496:27: warning: initialized field overwritten [-Woverride-init]
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| ^~~~
drivers/gpu/drm/tiny/gm12u320.c:496:27: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
drivers/gpu/drm/tiny/gm12u320.c:497:9: error: 'union <anonymous>' has no member named 'other_data'
497 | .data.other_data.data.range.min_vfreq = 59,
| ^~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:497:43: warning: initialized field overwritten [-Woverride-init]
497 | .data.other_data.data.range.min_vfreq = 59,
| ^~
drivers/gpu/drm/tiny/gm12u320.c:497:43: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
drivers/gpu/drm/tiny/gm12u320.c:498:9: error: 'union <anonymous>' has no member named 'other_data'
498 | .data.other_data.data.range.max_vfreq = 61,
| ^~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:498:43: warning: initialized field overwritten [-Woverride-init]
498 | .data.other_data.data.range.max_vfreq = 61,
| ^~
drivers/gpu/drm/tiny/gm12u320.c:498:43: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
drivers/gpu/drm/tiny/gm12u320.c:499:9: error: 'union <anonymous>' has no member named 'other_data'
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| ^~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:499:47: warning: initialized field overwritten [-Woverride-init]
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| ^~
drivers/gpu/drm/tiny/gm12u320.c:499:47: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
drivers/gpu/drm/tiny/gm12u320.c:500:9: error: 'union <anonymous>' has no member named 'other_data'
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| ^~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:500:47: warning: initialized field overwritten [-Woverride-init]
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| ^~
drivers/gpu/drm/tiny/gm12u320.c:500:47: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
drivers/gpu/drm/tiny/gm12u320.c:501:9: error: 'union <anonymous>' has no member named 'other_data'
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| ^~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:501:49: warning: initialized field overwritten [-Woverride-init]
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| ^
drivers/gpu/drm/tiny/gm12u320.c:501:49: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
drivers/gpu/drm/tiny/gm12u320.c:502:9: error: 'union <anonymous>' has no member named 'other_data'
502 | .data.other_data.data.range.flags = 0,
| ^~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:502:39: warning: initialized field overwritten [-Woverride-init]
502 | .data.other_data.data.range.flags = 0,
| ^
drivers/gpu/drm/tiny/gm12u320.c:502:39: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
drivers/gpu/drm/tiny/gm12u320.c:503:9: error: 'union <anonymous>' has no member named 'other_data'
503 | .data.other_data.data.range.formula.cvt = {
| ^~~~~~~~~~
>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
464 | static struct edid gm12u320_edid = {
| ^
......
478 | .pixel_clock = 3383,
| {{ }}
479 | /* hactive = 848, hblank = 256 */
480 | .data.pixel_data.hactive_lo = 0x50,
| }}
481 | .data.pixel_data.hblank_lo = 0x00,
| }}
482 | .data.pixel_data.hactive_hblank_hi = 0x31,
| }}
483 | /* vactive = 480, vblank = 28 */
484 | .data.pixel_data.vactive_lo = 0xe0,
| }}
485 | .data.pixel_data.vblank_lo = 0x1c,
| }}
486 | .data.pixel_data.vactive_vblank_hi = 0x10,
| }}
487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
488 | .data.pixel_data.hsync_offset_lo = 0x28,
| }}
489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
| }}
490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
| }}
491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
| }}
......
494 | }, {
| }}
495 | .pixel_clock = 0,
| -
| {{0}}
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| { }}
497 | .data.other_data.data.range.min_vfreq = 59,
| { }}
498 | .data.other_data.data.range.max_vfreq = 61,
| { }}
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| { }}
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| { }}
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| {}}
502 | .data.other_data.data.range.flags = 0,
| {}}
drivers/gpu/drm/tiny/gm12u320.c:503:45: warning: initialized field overwritten [-Woverride-init]
503 | .data.other_data.data.range.formula.cvt = {
| ^
drivers/gpu/drm/tiny/gm12u320.c:503:45: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data')
>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
464 | static struct edid gm12u320_edid = {
| ^
......
478 | .pixel_clock = 3383,
| {{ }}
479 | /* hactive = 848, hblank = 256 */
480 | .data.pixel_data.hactive_lo = 0x50,
| }}
481 | .data.pixel_data.hblank_lo = 0x00,
| }}
482 | .data.pixel_data.hactive_hblank_hi = 0x31,
| }}
483 | /* vactive = 480, vblank = 28 */
484 | .data.pixel_data.vactive_lo = 0xe0,
| }}
485 | .data.pixel_data.vblank_lo = 0x1c,
| }}
486 | .data.pixel_data.vactive_vblank_hi = 0x10,
| }}
487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
488 | .data.pixel_data.hsync_offset_lo = 0x28,
| }}
489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
| }}
490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
| }}
491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
| }}
......
494 | }, {
| }}
495 | .pixel_clock = 0,
| -
| {{0}}
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| { }}
497 | .data.other_data.data.range.min_vfreq = 59,
| { }}
498 | .data.other_data.data.range.max_vfreq = 61,
| { }}
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| { }}
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| { }}
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| {}}
502 | .data.other_data.data.range.flags = 0,
| {}}
......
505 | }, {
| }
drivers/gpu/drm/tiny/gm12u320.c:506:4: error: 'struct detailed_timing' has no member named 'pixel_clock'
506 | .pixel_clock = 0,
| ^~~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:507:9: error: 'union <anonymous>' has no member named 'other_data'
507 | .data.other_data.type = 0xfc, /* Model string */
| ^~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:507:27: warning: initialized field overwritten [-Woverride-init]
507 | .data.other_data.type = 0xfc, /* Model string */
| ^~~~
drivers/gpu/drm/tiny/gm12u320.c:507:27: note: (near initialization for 'gm12u320_edid.detailed_timings[2].data.pixel_data.pixel_clock')
drivers/gpu/drm/tiny/gm12u320.c:508:9: error: 'union <anonymous>' has no member named 'other_data'
508 | .data.other_data.data.str.str = {
| ^~~~~~~~~~
>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
464 | static struct edid gm12u320_edid = {
| ^
......
478 | .pixel_clock = 3383,
| {{ }}
479 | /* hactive = 848, hblank = 256 */
480 | .data.pixel_data.hactive_lo = 0x50,
| }}
481 | .data.pixel_data.hblank_lo = 0x00,
| }}
482 | .data.pixel_data.hactive_hblank_hi = 0x31,
| }}
483 | /* vactive = 480, vblank = 28 */
484 | .data.pixel_data.vactive_lo = 0xe0,
| }}
485 | .data.pixel_data.vblank_lo = 0x1c,
| }}
486 | .data.pixel_data.vactive_vblank_hi = 0x10,
| }}
487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
488 | .data.pixel_data.hsync_offset_lo = 0x28,
| }}
489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
| }}
490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
| }}
491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
| }}
......
494 | }, {
| }}
495 | .pixel_clock = 0,
| -
| {{0}}
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| { }}
497 | .data.other_data.data.range.min_vfreq = 59,
| { }}
498 | .data.other_data.data.range.max_vfreq = 61,
| { }}
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| { }}
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| { }}
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| {}}
502 | .data.other_data.data.range.flags = 0,
| {}}
......
505 | }, {
| }
506 | .pixel_clock = 0,
| -
| {{0}}
507 | .data.other_data.type = 0xfc, /* Model string */
| { }}
drivers/gpu/drm/tiny/gm12u320.c:508:35: warning: initialized field overwritten [-Woverride-init]
508 | .data.other_data.data.str.str = {
| ^
drivers/gpu/drm/tiny/gm12u320.c:508:35: note: (near initialization for 'gm12u320_edid.detailed_timings[2].data.pixel_data')
>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
464 | static struct edid gm12u320_edid = {
| ^
......
478 | .pixel_clock = 3383,
| {{ }}
479 | /* hactive = 848, hblank = 256 */
480 | .data.pixel_data.hactive_lo = 0x50,
| }}
481 | .data.pixel_data.hblank_lo = 0x00,
| }}
482 | .data.pixel_data.hactive_hblank_hi = 0x31,
| }}
483 | /* vactive = 480, vblank = 28 */
484 | .data.pixel_data.vactive_lo = 0xe0,
| }}
485 | .data.pixel_data.vblank_lo = 0x1c,
| }}
486 | .data.pixel_data.vactive_vblank_hi = 0x10,
| }}
487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
488 | .data.pixel_data.hsync_offset_lo = 0x28,
| }}
489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
| }}
490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
| }}
491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
| }}
......
494 | }, {
| }}
495 | .pixel_clock = 0,
| -
| {{0}}
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| { }}
497 | .data.other_data.data.range.min_vfreq = 59,
| { }}
498 | .data.other_data.data.range.max_vfreq = 61,
| { }}
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| { }}
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| { }}
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| {}}
502 | .data.other_data.data.range.flags = 0,
| {}}
......
505 | }, {
| }
506 | .pixel_clock = 0,
| -
| {{0}}
507 | .data.other_data.type = 0xfc, /* Model string */
| { }}
......
511 | }, {
| }
drivers/gpu/drm/tiny/gm12u320.c:512:4: error: 'struct detailed_timing' has no member named 'pixel_clock'
512 | .pixel_clock = 0,
| ^~~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:513:9: error: 'union <anonymous>' has no member named 'other_data'
513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
| ^~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:513:27: warning: initialized field overwritten [-Woverride-init]
513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
| ^~~~
drivers/gpu/drm/tiny/gm12u320.c:513:27: note: (near initialization for 'gm12u320_edid.detailed_timings[3].data.pixel_data.pixel_clock')
drivers/gpu/drm/tiny/gm12u320.c:514:9: error: 'union <anonymous>' has no member named 'other_data'
514 | .data.other_data.data.str.str = {
| ^~~~~~~~~~
>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
464 | static struct edid gm12u320_edid = {
| ^
......
478 | .pixel_clock = 3383,
| {{ }}
479 | /* hactive = 848, hblank = 256 */
480 | .data.pixel_data.hactive_lo = 0x50,
| }}
481 | .data.pixel_data.hblank_lo = 0x00,
| }}
482 | .data.pixel_data.hactive_hblank_hi = 0x31,
| }}
483 | /* vactive = 480, vblank = 28 */
484 | .data.pixel_data.vactive_lo = 0xe0,
| }}
485 | .data.pixel_data.vblank_lo = 0x1c,
| }}
486 | .data.pixel_data.vactive_vblank_hi = 0x10,
| }}
487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
488 | .data.pixel_data.hsync_offset_lo = 0x28,
| }}
489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
| }}
490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
| }}
491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
| }}
......
494 | }, {
| }}
495 | .pixel_clock = 0,
| -
| {{0}}
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| { }}
497 | .data.other_data.data.range.min_vfreq = 59,
| { }}
498 | .data.other_data.data.range.max_vfreq = 61,
| { }}
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| { }}
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| { }}
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| {}}
502 | .data.other_data.data.range.flags = 0,
| {}}
......
505 | }, {
| }
506 | .pixel_clock = 0,
| -
| {{0}}
507 | .data.other_data.type = 0xfc, /* Model string */
| { }}
......
511 | }, {
| }
512 | .pixel_clock = 0,
| -
| {{0}}
513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
| { }}
drivers/gpu/drm/tiny/gm12u320.c:514:35: warning: initialized field overwritten [-Woverride-init]
514 | .data.other_data.data.str.str = {
| ^
drivers/gpu/drm/tiny/gm12u320.c:514:35: note: (near initialization for 'gm12u320_edid.detailed_timings[3].data.pixel_data')
>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
464 | static struct edid gm12u320_edid = {
| ^
......
478 | .pixel_clock = 3383,
| {{ }}
479 | /* hactive = 848, hblank = 256 */
480 | .data.pixel_data.hactive_lo = 0x50,
| }}
481 | .data.pixel_data.hblank_lo = 0x00,
| }}
482 | .data.pixel_data.hactive_hblank_hi = 0x31,
| }}
483 | /* vactive = 480, vblank = 28 */
484 | .data.pixel_data.vactive_lo = 0xe0,
| }}
485 | .data.pixel_data.vblank_lo = 0x1c,
| }}
486 | .data.pixel_data.vactive_vblank_hi = 0x10,
| }}
487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
488 | .data.pixel_data.hsync_offset_lo = 0x28,
| }}
489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
| }}
490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
| }}
491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
| }}
......
494 | }, {
| }}
495 | .pixel_clock = 0,
| -
| {{0}}
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| { }}
497 | .data.other_data.data.range.min_vfreq = 59,
| { }}
498 | .data.other_data.data.range.max_vfreq = 61,
| { }}
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| { }}
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| { }}
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| {}}
502 | .data.other_data.data.range.flags = 0,
| {}}
......
505 | }, {
| }
506 | .pixel_clock = 0,
| -
| {{0}}
507 | .data.other_data.type = 0xfc, /* Model string */
| { }}
......
511 | }, {
| }
512 | .pixel_clock = 0,
| -
| {{0}}
513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
| { }}
......
517 | } },
| }
>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
464 | static struct edid gm12u320_edid = {
| ^
......
478 | .pixel_clock = 3383,
| {{ }}
479 | /* hactive = 848, hblank = 256 */
480 | .data.pixel_data.hactive_lo = 0x50,
| }}
481 | .data.pixel_data.hblank_lo = 0x00,
| }}
482 | .data.pixel_data.hactive_hblank_hi = 0x31,
| }}
483 | /* vactive = 480, vblank = 28 */
484 | .data.pixel_data.vactive_lo = 0xe0,
| }}
485 | .data.pixel_data.vblank_lo = 0x1c,
| }}
486 | .data.pixel_data.vactive_vblank_hi = 0x10,
| }}
487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
488 | .data.pixel_data.hsync_offset_lo = 0x28,
| }}
489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
| }}
490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
| }}
491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
| }}
......
494 | }, {
| }}
495 | .pixel_clock = 0,
| -
| {{0}}
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| { }}
497 | .data.other_data.data.range.min_vfreq = 59,
| { }}
498 | .data.other_data.data.range.max_vfreq = 61,
| { }}
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| { }}
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| { }}
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| {}}
502 | .data.other_data.data.range.flags = 0,
| {}}
......
505 | }, {
| }
506 | .pixel_clock = 0,
| -
| {{0}}
507 | .data.other_data.type = 0xfc, /* Model string */
| { }}
......
511 | }, {
| }
512 | .pixel_clock = 0,
| -
| {{0}}
513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
| { }}
......
517 | } },
| }
>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
464 | static struct edid gm12u320_edid = {
| ^
......
478 | .pixel_clock = 3383,
| {{ }}
479 | /* hactive = 848, hblank = 256 */
480 | .data.pixel_data.hactive_lo = 0x50,
| }}
481 | .data.pixel_data.hblank_lo = 0x00,
| }}
482 | .data.pixel_data.hactive_hblank_hi = 0x31,
| }}
483 | /* vactive = 480, vblank = 28 */
484 | .data.pixel_data.vactive_lo = 0xe0,
| }}
485 | .data.pixel_data.vblank_lo = 0x1c,
| }}
486 | .data.pixel_data.vactive_vblank_hi = 0x10,
| }}
487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
488 | .data.pixel_data.hsync_offset_lo = 0x28,
| }}
489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
| }}
490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
| }}
491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
| }}
......
494 | }, {
| }}
495 | .pixel_clock = 0,
| -
| {{0}}
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| { }}
497 | .data.other_data.data.range.min_vfreq = 59,
| { }}
498 | .data.other_data.data.range.max_vfreq = 61,
| { }}
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| { }}
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| { }}
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| {}}
502 | .data.other_data.data.range.flags = 0,
| {}}
......
505 | }, {
| }
506 | .pixel_clock = 0,
| -
| {{0}}
507 | .data.other_data.type = 0xfc, /* Model string */
| { }}
......
511 | }, {
| }
512 | .pixel_clock = 0,
| -
| {{0}}
513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
| { }}
......
517 | } },
| }
vim +464 drivers/gpu/drm/tiny/gm12u320.c
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 457
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 458 /*
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 459 * We use fake EDID info so that userspace know that it is dealing with
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 460 * an Acer projector, rather then listing this as an "unknown" monitor.
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 461 * Note this assumes this driver is only ever used with the Acer C120, if we
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 462 * add support for other devices the vendor and model should be parameterized.
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 463 */
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 @464 static struct edid gm12u320_edid = {
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 465 .header = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 },
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 466 .mfg_id = { 0x04, 0x72 }, /* "ACR" */
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 467 .prod_code = { 0x20, 0xc1 }, /* C120h */
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 468 .serial = 0xaa55aa55,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 469 .mfg_week = 1,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 470 .mfg_year = 16,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 471 .version = 1, /* EDID 1.3 */
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 472 .revision = 3, /* EDID 1.3 */
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 473 .input = 0x08, /* Analog input */
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 474 .features = 0x0a, /* Pref timing in DTD 1 */
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 475 .standard_timings = { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 },
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 476 { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } },
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 477 .detailed_timings = { {
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 478 .pixel_clock = 3383,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 479 /* hactive = 848, hblank = 256 */
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 480 .data.pixel_data.hactive_lo = 0x50,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 481 .data.pixel_data.hblank_lo = 0x00,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 482 .data.pixel_data.hactive_hblank_hi = 0x31,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 483 /* vactive = 480, vblank = 28 */
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 484 .data.pixel_data.vactive_lo = 0xe0,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 485 .data.pixel_data.vblank_lo = 0x1c,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 486 .data.pixel_data.vactive_vblank_hi = 0x10,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 487 /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 488 .data.pixel_data.hsync_offset_lo = 0x28,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 489 .data.pixel_data.hsync_pulse_width_lo = 0x80,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 490 .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 491 .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 492 /* Digital separate syncs, hsync+, vsync+ */
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 493 .data.pixel_data.misc = 0x1e,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 494 }, {
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 495 .pixel_clock = 0,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 496 .data.other_data.type = 0xfd, /* Monitor ranges */
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 497 .data.other_data.data.range.min_vfreq = 59,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 498 .data.other_data.data.range.max_vfreq = 61,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 499 .data.other_data.data.range.min_hfreq_khz = 29,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 500 .data.other_data.data.range.max_hfreq_khz = 32,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 501 .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 502 .data.other_data.data.range.flags = 0,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 503 .data.other_data.data.range.formula.cvt = {
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 504 0xa0, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 },
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 505 }, {
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 506 .pixel_clock = 0,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 507 .data.other_data.type = 0xfc, /* Model string */
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 508 .data.other_data.data.str.str = {
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 509 'P', 'r', 'o', 'j', 'e', 'c', 't', 'o', 'r', '\n',
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 510 ' ', ' ', ' ' },
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 511 }, {
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 512 .pixel_clock = 0,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 513 .data.other_data.type = 0xfe, /* Unspecified text / padding */
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 514 .data.other_data.data.str.str = {
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 515 '\n', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ',
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 516 ' ', ' ', ' ' },
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 517 } },
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 518 .checksum = 0x13,
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 519 };
e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 520
--
0-DAY CI Kernel Test Service
https://01.org/lkp
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v2 03/11] drm/edid: slightly restructure timing and non-timing descriptor structs
2022-03-28 11:45 ` kernel test robot
2022-03-28 13:20 ` Jani Nikula
@ 2022-03-28 13:20 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2022-03-28 13:20 UTC (permalink / raw)
To: kernel test robot, dri-devel
Cc: kbuild-all, Leo Li, intel-gfx, Rodrigo Siqueira, amd-gfx
I think I'm just going to revert back to my original plan of leaving the
struct restructuring to another time in the future.
BR,
Jani.
On Mon, 28 Mar 2022, kernel test robot <lkp@intel.com> wrote:
> Hi Jani,
>
> I love your patch! Perhaps something to improve:
>
> [auto build test WARNING on drm/drm-next]
> [also build test WARNING on drm-intel/for-linux-next drm-tip/drm-tip v5.17 next-20220328]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url: https://github.com/intel-lab-lkp/linux/commits/Jani-Nikula/drm-edid-constify-EDID-parsing-with-some-fixes/20220328-171858
> base: git://anongit.freedesktop.org/drm/drm drm-next
> config: x86_64-randconfig-a003-20220328 (https://download.01.org/0day-ci/archive/20220328/202203281926.AthxJpnK-lkp@intel.com/config)
> compiler: gcc-9 (Ubuntu 9.4.0-1ubuntu1~20.04.1) 9.4.0
> reproduce (this is a W=1 build):
> # https://github.com/intel-lab-lkp/linux/commit/f538c9296c54ce8f878432153584a68939ffc111
> git remote add linux-review https://github.com/intel-lab-lkp/linux
> git fetch --no-tags linux-review Jani-Nikula/drm-edid-constify-EDID-parsing-with-some-fixes/20220328-171858
> git checkout f538c9296c54ce8f878432153584a68939ffc111
> # save the config file to linux build tree
> mkdir build_dir
> make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/tiny/
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
>
> All warnings (new ones prefixed by >>):
>
> drivers/gpu/drm/tiny/gm12u320.c:478:4: error: 'struct detailed_timing' has no member named 'pixel_clock'
> 478 | .pixel_clock = 3383,
> | ^~~~~~~~~~~
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> drivers/gpu/drm/tiny/gm12u320.c:495:4: error: 'struct detailed_timing' has no member named 'pixel_clock'
> 495 | .pixel_clock = 0,
> | ^~~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:496:9: error: 'union <anonymous>' has no member named 'other_data'
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:496:27: warning: initialized field overwritten [-Woverride-init]
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | ^~~~
> drivers/gpu/drm/tiny/gm12u320.c:496:27: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:497:9: error: 'union <anonymous>' has no member named 'other_data'
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:497:43: warning: initialized field overwritten [-Woverride-init]
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | ^~
> drivers/gpu/drm/tiny/gm12u320.c:497:43: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:498:9: error: 'union <anonymous>' has no member named 'other_data'
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:498:43: warning: initialized field overwritten [-Woverride-init]
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | ^~
> drivers/gpu/drm/tiny/gm12u320.c:498:43: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:499:9: error: 'union <anonymous>' has no member named 'other_data'
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:499:47: warning: initialized field overwritten [-Woverride-init]
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | ^~
> drivers/gpu/drm/tiny/gm12u320.c:499:47: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:500:9: error: 'union <anonymous>' has no member named 'other_data'
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:500:47: warning: initialized field overwritten [-Woverride-init]
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | ^~
> drivers/gpu/drm/tiny/gm12u320.c:500:47: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:501:9: error: 'union <anonymous>' has no member named 'other_data'
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:501:49: warning: initialized field overwritten [-Woverride-init]
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | ^
> drivers/gpu/drm/tiny/gm12u320.c:501:49: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:502:9: error: 'union <anonymous>' has no member named 'other_data'
> 502 | .data.other_data.data.range.flags = 0,
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:502:39: warning: initialized field overwritten [-Woverride-init]
> 502 | .data.other_data.data.range.flags = 0,
> | ^
> drivers/gpu/drm/tiny/gm12u320.c:502:39: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:503:9: error: 'union <anonymous>' has no member named 'other_data'
> 503 | .data.other_data.data.range.formula.cvt = {
> | ^~~~~~~~~~
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> drivers/gpu/drm/tiny/gm12u320.c:503:45: warning: initialized field overwritten [-Woverride-init]
> 503 | .data.other_data.data.range.formula.cvt = {
> | ^
> drivers/gpu/drm/tiny/gm12u320.c:503:45: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data')
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> drivers/gpu/drm/tiny/gm12u320.c:506:4: error: 'struct detailed_timing' has no member named 'pixel_clock'
> 506 | .pixel_clock = 0,
> | ^~~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:507:9: error: 'union <anonymous>' has no member named 'other_data'
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:507:27: warning: initialized field overwritten [-Woverride-init]
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | ^~~~
> drivers/gpu/drm/tiny/gm12u320.c:507:27: note: (near initialization for 'gm12u320_edid.detailed_timings[2].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:508:9: error: 'union <anonymous>' has no member named 'other_data'
> 508 | .data.other_data.data.str.str = {
> | ^~~~~~~~~~
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> 506 | .pixel_clock = 0,
> | -
> | {{0}}
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | { }}
> drivers/gpu/drm/tiny/gm12u320.c:508:35: warning: initialized field overwritten [-Woverride-init]
> 508 | .data.other_data.data.str.str = {
> | ^
> drivers/gpu/drm/tiny/gm12u320.c:508:35: note: (near initialization for 'gm12u320_edid.detailed_timings[2].data.pixel_data')
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> 506 | .pixel_clock = 0,
> | -
> | {{0}}
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | { }}
> ......
> 511 | }, {
> | }
> drivers/gpu/drm/tiny/gm12u320.c:512:4: error: 'struct detailed_timing' has no member named 'pixel_clock'
> 512 | .pixel_clock = 0,
> | ^~~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:513:9: error: 'union <anonymous>' has no member named 'other_data'
> 513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:513:27: warning: initialized field overwritten [-Woverride-init]
> 513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
> | ^~~~
> drivers/gpu/drm/tiny/gm12u320.c:513:27: note: (near initialization for 'gm12u320_edid.detailed_timings[3].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:514:9: error: 'union <anonymous>' has no member named 'other_data'
> 514 | .data.other_data.data.str.str = {
> | ^~~~~~~~~~
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> 506 | .pixel_clock = 0,
> | -
> | {{0}}
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | { }}
> ......
> 511 | }, {
> | }
> 512 | .pixel_clock = 0,
> | -
> | {{0}}
> 513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
> | { }}
> drivers/gpu/drm/tiny/gm12u320.c:514:35: warning: initialized field overwritten [-Woverride-init]
> 514 | .data.other_data.data.str.str = {
> | ^
> drivers/gpu/drm/tiny/gm12u320.c:514:35: note: (near initialization for 'gm12u320_edid.detailed_timings[3].data.pixel_data')
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> 506 | .pixel_clock = 0,
> | -
> | {{0}}
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | { }}
> ......
> 511 | }, {
> | }
> 512 | .pixel_clock = 0,
> | -
> | {{0}}
> 513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
> | { }}
> ......
> 517 | } },
> | }
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> 506 | .pixel_clock = 0,
> | -
> | {{0}}
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | { }}
> ......
> 511 | }, {
> | }
> 512 | .pixel_clock = 0,
> | -
> | {{0}}
> 513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
> | { }}
> ......
> 517 | } },
> | }
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> 506 | .pixel_clock = 0,
> | -
> | {{0}}
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | { }}
> ......
> 511 | }, {
> | }
> 512 | .pixel_clock = 0,
> | -
> | {{0}}
> 513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
> | { }}
> ......
> 517 | } },
> | }
>
>
> vim +464 drivers/gpu/drm/tiny/gm12u320.c
>
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 457
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 458 /*
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 459 * We use fake EDID info so that userspace know that it is dealing with
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 460 * an Acer projector, rather then listing this as an "unknown" monitor.
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 461 * Note this assumes this driver is only ever used with the Acer C120, if we
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 462 * add support for other devices the vendor and model should be parameterized.
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 463 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 @464 static struct edid gm12u320_edid = {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 465 .header = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 466 .mfg_id = { 0x04, 0x72 }, /* "ACR" */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 467 .prod_code = { 0x20, 0xc1 }, /* C120h */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 468 .serial = 0xaa55aa55,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 469 .mfg_week = 1,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 470 .mfg_year = 16,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 471 .version = 1, /* EDID 1.3 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 472 .revision = 3, /* EDID 1.3 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 473 .input = 0x08, /* Analog input */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 474 .features = 0x0a, /* Pref timing in DTD 1 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 475 .standard_timings = { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 476 { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 477 .detailed_timings = { {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 478 .pixel_clock = 3383,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 479 /* hactive = 848, hblank = 256 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 480 .data.pixel_data.hactive_lo = 0x50,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 481 .data.pixel_data.hblank_lo = 0x00,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 482 .data.pixel_data.hactive_hblank_hi = 0x31,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 483 /* vactive = 480, vblank = 28 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 484 .data.pixel_data.vactive_lo = 0xe0,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 485 .data.pixel_data.vblank_lo = 0x1c,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 486 .data.pixel_data.vactive_vblank_hi = 0x10,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 487 /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 488 .data.pixel_data.hsync_offset_lo = 0x28,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 489 .data.pixel_data.hsync_pulse_width_lo = 0x80,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 490 .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 491 .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 492 /* Digital separate syncs, hsync+, vsync+ */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 493 .data.pixel_data.misc = 0x1e,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 494 }, {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 495 .pixel_clock = 0,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 496 .data.other_data.type = 0xfd, /* Monitor ranges */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 497 .data.other_data.data.range.min_vfreq = 59,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 498 .data.other_data.data.range.max_vfreq = 61,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 499 .data.other_data.data.range.min_hfreq_khz = 29,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 500 .data.other_data.data.range.max_hfreq_khz = 32,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 501 .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 502 .data.other_data.data.range.flags = 0,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 503 .data.other_data.data.range.formula.cvt = {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 504 0xa0, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 505 }, {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 506 .pixel_clock = 0,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 507 .data.other_data.type = 0xfc, /* Model string */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 508 .data.other_data.data.str.str = {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 509 'P', 'r', 'o', 'j', 'e', 'c', 't', 'o', 'r', '\n',
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 510 ' ', ' ', ' ' },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 511 }, {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 512 .pixel_clock = 0,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 513 .data.other_data.type = 0xfe, /* Unspecified text / padding */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 514 .data.other_data.data.str.str = {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 515 '\n', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ',
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 516 ' ', ' ', ' ' },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 517 } },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 518 .checksum = 0x13,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 519 };
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 520
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v2 03/11] drm/edid: slightly restructure timing and non-timing descriptor structs
@ 2022-03-28 13:20 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2022-03-28 13:20 UTC (permalink / raw)
To: kernel test robot, dri-devel
Cc: kbuild-all, Leo Li, intel-gfx, Rodrigo Siqueira, amd-gfx,
Harry Wentland, ville.syrjala
I think I'm just going to revert back to my original plan of leaving the
struct restructuring to another time in the future.
BR,
Jani.
On Mon, 28 Mar 2022, kernel test robot <lkp@intel.com> wrote:
> Hi Jani,
>
> I love your patch! Perhaps something to improve:
>
> [auto build test WARNING on drm/drm-next]
> [also build test WARNING on drm-intel/for-linux-next drm-tip/drm-tip v5.17 next-20220328]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url: https://github.com/intel-lab-lkp/linux/commits/Jani-Nikula/drm-edid-constify-EDID-parsing-with-some-fixes/20220328-171858
> base: git://anongit.freedesktop.org/drm/drm drm-next
> config: x86_64-randconfig-a003-20220328 (https://download.01.org/0day-ci/archive/20220328/202203281926.AthxJpnK-lkp@intel.com/config)
> compiler: gcc-9 (Ubuntu 9.4.0-1ubuntu1~20.04.1) 9.4.0
> reproduce (this is a W=1 build):
> # https://github.com/intel-lab-lkp/linux/commit/f538c9296c54ce8f878432153584a68939ffc111
> git remote add linux-review https://github.com/intel-lab-lkp/linux
> git fetch --no-tags linux-review Jani-Nikula/drm-edid-constify-EDID-parsing-with-some-fixes/20220328-171858
> git checkout f538c9296c54ce8f878432153584a68939ffc111
> # save the config file to linux build tree
> mkdir build_dir
> make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/tiny/
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
>
> All warnings (new ones prefixed by >>):
>
> drivers/gpu/drm/tiny/gm12u320.c:478:4: error: 'struct detailed_timing' has no member named 'pixel_clock'
> 478 | .pixel_clock = 3383,
> | ^~~~~~~~~~~
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> drivers/gpu/drm/tiny/gm12u320.c:495:4: error: 'struct detailed_timing' has no member named 'pixel_clock'
> 495 | .pixel_clock = 0,
> | ^~~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:496:9: error: 'union <anonymous>' has no member named 'other_data'
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:496:27: warning: initialized field overwritten [-Woverride-init]
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | ^~~~
> drivers/gpu/drm/tiny/gm12u320.c:496:27: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:497:9: error: 'union <anonymous>' has no member named 'other_data'
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:497:43: warning: initialized field overwritten [-Woverride-init]
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | ^~
> drivers/gpu/drm/tiny/gm12u320.c:497:43: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:498:9: error: 'union <anonymous>' has no member named 'other_data'
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:498:43: warning: initialized field overwritten [-Woverride-init]
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | ^~
> drivers/gpu/drm/tiny/gm12u320.c:498:43: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:499:9: error: 'union <anonymous>' has no member named 'other_data'
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:499:47: warning: initialized field overwritten [-Woverride-init]
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | ^~
> drivers/gpu/drm/tiny/gm12u320.c:499:47: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:500:9: error: 'union <anonymous>' has no member named 'other_data'
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:500:47: warning: initialized field overwritten [-Woverride-init]
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | ^~
> drivers/gpu/drm/tiny/gm12u320.c:500:47: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:501:9: error: 'union <anonymous>' has no member named 'other_data'
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:501:49: warning: initialized field overwritten [-Woverride-init]
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | ^
> drivers/gpu/drm/tiny/gm12u320.c:501:49: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:502:9: error: 'union <anonymous>' has no member named 'other_data'
> 502 | .data.other_data.data.range.flags = 0,
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:502:39: warning: initialized field overwritten [-Woverride-init]
> 502 | .data.other_data.data.range.flags = 0,
> | ^
> drivers/gpu/drm/tiny/gm12u320.c:502:39: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:503:9: error: 'union <anonymous>' has no member named 'other_data'
> 503 | .data.other_data.data.range.formula.cvt = {
> | ^~~~~~~~~~
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> drivers/gpu/drm/tiny/gm12u320.c:503:45: warning: initialized field overwritten [-Woverride-init]
> 503 | .data.other_data.data.range.formula.cvt = {
> | ^
> drivers/gpu/drm/tiny/gm12u320.c:503:45: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data')
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> drivers/gpu/drm/tiny/gm12u320.c:506:4: error: 'struct detailed_timing' has no member named 'pixel_clock'
> 506 | .pixel_clock = 0,
> | ^~~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:507:9: error: 'union <anonymous>' has no member named 'other_data'
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:507:27: warning: initialized field overwritten [-Woverride-init]
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | ^~~~
> drivers/gpu/drm/tiny/gm12u320.c:507:27: note: (near initialization for 'gm12u320_edid.detailed_timings[2].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:508:9: error: 'union <anonymous>' has no member named 'other_data'
> 508 | .data.other_data.data.str.str = {
> | ^~~~~~~~~~
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> 506 | .pixel_clock = 0,
> | -
> | {{0}}
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | { }}
> drivers/gpu/drm/tiny/gm12u320.c:508:35: warning: initialized field overwritten [-Woverride-init]
> 508 | .data.other_data.data.str.str = {
> | ^
> drivers/gpu/drm/tiny/gm12u320.c:508:35: note: (near initialization for 'gm12u320_edid.detailed_timings[2].data.pixel_data')
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> 506 | .pixel_clock = 0,
> | -
> | {{0}}
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | { }}
> ......
> 511 | }, {
> | }
> drivers/gpu/drm/tiny/gm12u320.c:512:4: error: 'struct detailed_timing' has no member named 'pixel_clock'
> 512 | .pixel_clock = 0,
> | ^~~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:513:9: error: 'union <anonymous>' has no member named 'other_data'
> 513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:513:27: warning: initialized field overwritten [-Woverride-init]
> 513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
> | ^~~~
> drivers/gpu/drm/tiny/gm12u320.c:513:27: note: (near initialization for 'gm12u320_edid.detailed_timings[3].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:514:9: error: 'union <anonymous>' has no member named 'other_data'
> 514 | .data.other_data.data.str.str = {
> | ^~~~~~~~~~
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> 506 | .pixel_clock = 0,
> | -
> | {{0}}
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | { }}
> ......
> 511 | }, {
> | }
> 512 | .pixel_clock = 0,
> | -
> | {{0}}
> 513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
> | { }}
> drivers/gpu/drm/tiny/gm12u320.c:514:35: warning: initialized field overwritten [-Woverride-init]
> 514 | .data.other_data.data.str.str = {
> | ^
> drivers/gpu/drm/tiny/gm12u320.c:514:35: note: (near initialization for 'gm12u320_edid.detailed_timings[3].data.pixel_data')
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> 506 | .pixel_clock = 0,
> | -
> | {{0}}
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | { }}
> ......
> 511 | }, {
> | }
> 512 | .pixel_clock = 0,
> | -
> | {{0}}
> 513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
> | { }}
> ......
> 517 | } },
> | }
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> 506 | .pixel_clock = 0,
> | -
> | {{0}}
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | { }}
> ......
> 511 | }, {
> | }
> 512 | .pixel_clock = 0,
> | -
> | {{0}}
> 513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
> | { }}
> ......
> 517 | } },
> | }
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> 506 | .pixel_clock = 0,
> | -
> | {{0}}
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | { }}
> ......
> 511 | }, {
> | }
> 512 | .pixel_clock = 0,
> | -
> | {{0}}
> 513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
> | { }}
> ......
> 517 | } },
> | }
>
>
> vim +464 drivers/gpu/drm/tiny/gm12u320.c
>
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 457
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 458 /*
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 459 * We use fake EDID info so that userspace know that it is dealing with
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 460 * an Acer projector, rather then listing this as an "unknown" monitor.
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 461 * Note this assumes this driver is only ever used with the Acer C120, if we
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 462 * add support for other devices the vendor and model should be parameterized.
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 463 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 @464 static struct edid gm12u320_edid = {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 465 .header = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 466 .mfg_id = { 0x04, 0x72 }, /* "ACR" */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 467 .prod_code = { 0x20, 0xc1 }, /* C120h */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 468 .serial = 0xaa55aa55,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 469 .mfg_week = 1,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 470 .mfg_year = 16,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 471 .version = 1, /* EDID 1.3 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 472 .revision = 3, /* EDID 1.3 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 473 .input = 0x08, /* Analog input */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 474 .features = 0x0a, /* Pref timing in DTD 1 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 475 .standard_timings = { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 476 { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 477 .detailed_timings = { {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 478 .pixel_clock = 3383,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 479 /* hactive = 848, hblank = 256 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 480 .data.pixel_data.hactive_lo = 0x50,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 481 .data.pixel_data.hblank_lo = 0x00,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 482 .data.pixel_data.hactive_hblank_hi = 0x31,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 483 /* vactive = 480, vblank = 28 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 484 .data.pixel_data.vactive_lo = 0xe0,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 485 .data.pixel_data.vblank_lo = 0x1c,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 486 .data.pixel_data.vactive_vblank_hi = 0x10,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 487 /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 488 .data.pixel_data.hsync_offset_lo = 0x28,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 489 .data.pixel_data.hsync_pulse_width_lo = 0x80,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 490 .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 491 .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 492 /* Digital separate syncs, hsync+, vsync+ */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 493 .data.pixel_data.misc = 0x1e,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 494 }, {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 495 .pixel_clock = 0,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 496 .data.other_data.type = 0xfd, /* Monitor ranges */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 497 .data.other_data.data.range.min_vfreq = 59,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 498 .data.other_data.data.range.max_vfreq = 61,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 499 .data.other_data.data.range.min_hfreq_khz = 29,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 500 .data.other_data.data.range.max_hfreq_khz = 32,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 501 .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 502 .data.other_data.data.range.flags = 0,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 503 .data.other_data.data.range.formula.cvt = {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 504 0xa0, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 505 }, {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 506 .pixel_clock = 0,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 507 .data.other_data.type = 0xfc, /* Model string */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 508 .data.other_data.data.str.str = {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 509 'P', 'r', 'o', 'j', 'e', 'c', 't', 'o', 'r', '\n',
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 510 ' ', ' ', ' ' },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 511 }, {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 512 .pixel_clock = 0,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 513 .data.other_data.type = 0xfe, /* Unspecified text / padding */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 514 .data.other_data.data.str.str = {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 515 '\n', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ',
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 516 ' ', ' ', ' ' },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 517 } },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 518 .checksum = 0x13,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 519 };
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 520
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v2 03/11] drm/edid: slightly restructure timing and non-timing descriptor structs
@ 2022-03-28 13:20 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2022-03-28 13:20 UTC (permalink / raw)
To: kernel test robot, dri-devel
Cc: kbuild-all, Leo Li, intel-gfx, Rodrigo Siqueira, amd-gfx, Harry Wentland
I think I'm just going to revert back to my original plan of leaving the
struct restructuring to another time in the future.
BR,
Jani.
On Mon, 28 Mar 2022, kernel test robot <lkp@intel.com> wrote:
> Hi Jani,
>
> I love your patch! Perhaps something to improve:
>
> [auto build test WARNING on drm/drm-next]
> [also build test WARNING on drm-intel/for-linux-next drm-tip/drm-tip v5.17 next-20220328]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url: https://github.com/intel-lab-lkp/linux/commits/Jani-Nikula/drm-edid-constify-EDID-parsing-with-some-fixes/20220328-171858
> base: git://anongit.freedesktop.org/drm/drm drm-next
> config: x86_64-randconfig-a003-20220328 (https://download.01.org/0day-ci/archive/20220328/202203281926.AthxJpnK-lkp@intel.com/config)
> compiler: gcc-9 (Ubuntu 9.4.0-1ubuntu1~20.04.1) 9.4.0
> reproduce (this is a W=1 build):
> # https://github.com/intel-lab-lkp/linux/commit/f538c9296c54ce8f878432153584a68939ffc111
> git remote add linux-review https://github.com/intel-lab-lkp/linux
> git fetch --no-tags linux-review Jani-Nikula/drm-edid-constify-EDID-parsing-with-some-fixes/20220328-171858
> git checkout f538c9296c54ce8f878432153584a68939ffc111
> # save the config file to linux build tree
> mkdir build_dir
> make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/tiny/
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
>
> All warnings (new ones prefixed by >>):
>
> drivers/gpu/drm/tiny/gm12u320.c:478:4: error: 'struct detailed_timing' has no member named 'pixel_clock'
> 478 | .pixel_clock = 3383,
> | ^~~~~~~~~~~
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> drivers/gpu/drm/tiny/gm12u320.c:495:4: error: 'struct detailed_timing' has no member named 'pixel_clock'
> 495 | .pixel_clock = 0,
> | ^~~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:496:9: error: 'union <anonymous>' has no member named 'other_data'
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:496:27: warning: initialized field overwritten [-Woverride-init]
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | ^~~~
> drivers/gpu/drm/tiny/gm12u320.c:496:27: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:497:9: error: 'union <anonymous>' has no member named 'other_data'
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:497:43: warning: initialized field overwritten [-Woverride-init]
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | ^~
> drivers/gpu/drm/tiny/gm12u320.c:497:43: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:498:9: error: 'union <anonymous>' has no member named 'other_data'
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:498:43: warning: initialized field overwritten [-Woverride-init]
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | ^~
> drivers/gpu/drm/tiny/gm12u320.c:498:43: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:499:9: error: 'union <anonymous>' has no member named 'other_data'
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:499:47: warning: initialized field overwritten [-Woverride-init]
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | ^~
> drivers/gpu/drm/tiny/gm12u320.c:499:47: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:500:9: error: 'union <anonymous>' has no member named 'other_data'
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:500:47: warning: initialized field overwritten [-Woverride-init]
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | ^~
> drivers/gpu/drm/tiny/gm12u320.c:500:47: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:501:9: error: 'union <anonymous>' has no member named 'other_data'
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:501:49: warning: initialized field overwritten [-Woverride-init]
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | ^
> drivers/gpu/drm/tiny/gm12u320.c:501:49: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:502:9: error: 'union <anonymous>' has no member named 'other_data'
> 502 | .data.other_data.data.range.flags = 0,
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:502:39: warning: initialized field overwritten [-Woverride-init]
> 502 | .data.other_data.data.range.flags = 0,
> | ^
> drivers/gpu/drm/tiny/gm12u320.c:502:39: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:503:9: error: 'union <anonymous>' has no member named 'other_data'
> 503 | .data.other_data.data.range.formula.cvt = {
> | ^~~~~~~~~~
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> drivers/gpu/drm/tiny/gm12u320.c:503:45: warning: initialized field overwritten [-Woverride-init]
> 503 | .data.other_data.data.range.formula.cvt = {
> | ^
> drivers/gpu/drm/tiny/gm12u320.c:503:45: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data')
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> drivers/gpu/drm/tiny/gm12u320.c:506:4: error: 'struct detailed_timing' has no member named 'pixel_clock'
> 506 | .pixel_clock = 0,
> | ^~~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:507:9: error: 'union <anonymous>' has no member named 'other_data'
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:507:27: warning: initialized field overwritten [-Woverride-init]
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | ^~~~
> drivers/gpu/drm/tiny/gm12u320.c:507:27: note: (near initialization for 'gm12u320_edid.detailed_timings[2].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:508:9: error: 'union <anonymous>' has no member named 'other_data'
> 508 | .data.other_data.data.str.str = {
> | ^~~~~~~~~~
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> 506 | .pixel_clock = 0,
> | -
> | {{0}}
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | { }}
> drivers/gpu/drm/tiny/gm12u320.c:508:35: warning: initialized field overwritten [-Woverride-init]
> 508 | .data.other_data.data.str.str = {
> | ^
> drivers/gpu/drm/tiny/gm12u320.c:508:35: note: (near initialization for 'gm12u320_edid.detailed_timings[2].data.pixel_data')
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> 506 | .pixel_clock = 0,
> | -
> | {{0}}
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | { }}
> ......
> 511 | }, {
> | }
> drivers/gpu/drm/tiny/gm12u320.c:512:4: error: 'struct detailed_timing' has no member named 'pixel_clock'
> 512 | .pixel_clock = 0,
> | ^~~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:513:9: error: 'union <anonymous>' has no member named 'other_data'
> 513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
> | ^~~~~~~~~~
> drivers/gpu/drm/tiny/gm12u320.c:513:27: warning: initialized field overwritten [-Woverride-init]
> 513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
> | ^~~~
> drivers/gpu/drm/tiny/gm12u320.c:513:27: note: (near initialization for 'gm12u320_edid.detailed_timings[3].data.pixel_data.pixel_clock')
> drivers/gpu/drm/tiny/gm12u320.c:514:9: error: 'union <anonymous>' has no member named 'other_data'
> 514 | .data.other_data.data.str.str = {
> | ^~~~~~~~~~
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> 506 | .pixel_clock = 0,
> | -
> | {{0}}
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | { }}
> ......
> 511 | }, {
> | }
> 512 | .pixel_clock = 0,
> | -
> | {{0}}
> 513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
> | { }}
> drivers/gpu/drm/tiny/gm12u320.c:514:35: warning: initialized field overwritten [-Woverride-init]
> 514 | .data.other_data.data.str.str = {
> | ^
> drivers/gpu/drm/tiny/gm12u320.c:514:35: note: (near initialization for 'gm12u320_edid.detailed_timings[3].data.pixel_data')
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> 506 | .pixel_clock = 0,
> | -
> | {{0}}
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | { }}
> ......
> 511 | }, {
> | }
> 512 | .pixel_clock = 0,
> | -
> | {{0}}
> 513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
> | { }}
> ......
> 517 | } },
> | }
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> 506 | .pixel_clock = 0,
> | -
> | {{0}}
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | { }}
> ......
> 511 | }, {
> | }
> 512 | .pixel_clock = 0,
> | -
> | {{0}}
> 513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
> | { }}
> ......
> 517 | } },
> | }
>>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
> 464 | static struct edid gm12u320_edid = {
> | ^
> ......
> 478 | .pixel_clock = 3383,
> | {{ }}
> 479 | /* hactive = 848, hblank = 256 */
> 480 | .data.pixel_data.hactive_lo = 0x50,
> | }}
> 481 | .data.pixel_data.hblank_lo = 0x00,
> | }}
> 482 | .data.pixel_data.hactive_hblank_hi = 0x31,
> | }}
> 483 | /* vactive = 480, vblank = 28 */
> 484 | .data.pixel_data.vactive_lo = 0xe0,
> | }}
> 485 | .data.pixel_data.vblank_lo = 0x1c,
> | }}
> 486 | .data.pixel_data.vactive_vblank_hi = 0x10,
> | }}
> 487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> 488 | .data.pixel_data.hsync_offset_lo = 0x28,
> | }}
> 489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
> | }}
> 490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> | }}
> 491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> | }}
> ......
> 494 | }, {
> | }}
> 495 | .pixel_clock = 0,
> | -
> | {{0}}
> 496 | .data.other_data.type = 0xfd, /* Monitor ranges */
> | { }}
> 497 | .data.other_data.data.range.min_vfreq = 59,
> | { }}
> 498 | .data.other_data.data.range.max_vfreq = 61,
> | { }}
> 499 | .data.other_data.data.range.min_hfreq_khz = 29,
> | { }}
> 500 | .data.other_data.data.range.max_hfreq_khz = 32,
> | { }}
> 501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> | {}}
> 502 | .data.other_data.data.range.flags = 0,
> | {}}
> ......
> 505 | }, {
> | }
> 506 | .pixel_clock = 0,
> | -
> | {{0}}
> 507 | .data.other_data.type = 0xfc, /* Model string */
> | { }}
> ......
> 511 | }, {
> | }
> 512 | .pixel_clock = 0,
> | -
> | {{0}}
> 513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
> | { }}
> ......
> 517 | } },
> | }
>
>
> vim +464 drivers/gpu/drm/tiny/gm12u320.c
>
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 457
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 458 /*
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 459 * We use fake EDID info so that userspace know that it is dealing with
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 460 * an Acer projector, rather then listing this as an "unknown" monitor.
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 461 * Note this assumes this driver is only ever used with the Acer C120, if we
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 462 * add support for other devices the vendor and model should be parameterized.
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 463 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 @464 static struct edid gm12u320_edid = {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 465 .header = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 466 .mfg_id = { 0x04, 0x72 }, /* "ACR" */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 467 .prod_code = { 0x20, 0xc1 }, /* C120h */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 468 .serial = 0xaa55aa55,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 469 .mfg_week = 1,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 470 .mfg_year = 16,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 471 .version = 1, /* EDID 1.3 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 472 .revision = 3, /* EDID 1.3 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 473 .input = 0x08, /* Analog input */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 474 .features = 0x0a, /* Pref timing in DTD 1 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 475 .standard_timings = { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 476 { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 477 .detailed_timings = { {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 478 .pixel_clock = 3383,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 479 /* hactive = 848, hblank = 256 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 480 .data.pixel_data.hactive_lo = 0x50,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 481 .data.pixel_data.hblank_lo = 0x00,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 482 .data.pixel_data.hactive_hblank_hi = 0x31,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 483 /* vactive = 480, vblank = 28 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 484 .data.pixel_data.vactive_lo = 0xe0,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 485 .data.pixel_data.vblank_lo = 0x1c,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 486 .data.pixel_data.vactive_vblank_hi = 0x10,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 487 /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 488 .data.pixel_data.hsync_offset_lo = 0x28,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 489 .data.pixel_data.hsync_pulse_width_lo = 0x80,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 490 .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 491 .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 492 /* Digital separate syncs, hsync+, vsync+ */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 493 .data.pixel_data.misc = 0x1e,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 494 }, {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 495 .pixel_clock = 0,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 496 .data.other_data.type = 0xfd, /* Monitor ranges */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 497 .data.other_data.data.range.min_vfreq = 59,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 498 .data.other_data.data.range.max_vfreq = 61,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 499 .data.other_data.data.range.min_hfreq_khz = 29,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 500 .data.other_data.data.range.max_hfreq_khz = 32,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 501 .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 502 .data.other_data.data.range.flags = 0,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 503 .data.other_data.data.range.formula.cvt = {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 504 0xa0, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 505 }, {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 506 .pixel_clock = 0,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 507 .data.other_data.type = 0xfc, /* Model string */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 508 .data.other_data.data.str.str = {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 509 'P', 'r', 'o', 'j', 'e', 'c', 't', 'o', 'r', '\n',
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 510 ' ', ' ', ' ' },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 511 }, {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 512 .pixel_clock = 0,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 513 .data.other_data.type = 0xfe, /* Unspecified text / padding */
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 514 .data.other_data.data.str.str = {
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 515 '\n', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ',
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 516 ' ', ' ', ' ' },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 517 } },
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 518 .checksum = 0x13,
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 519 };
> e4f86e43716443e drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 520
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-gfx] [PATCH v2 03/11] drm/edid: slightly restructure timing and non-timing descriptor structs
2022-03-28 9:17 ` [Intel-gfx] " Jani Nikula
@ 2022-03-28 12:26 ` kernel test robot
-1 siblings, 0 replies; 42+ messages in thread
From: kernel test robot @ 2022-03-28 12:26 UTC (permalink / raw)
To: Jani Nikula, dri-devel; +Cc: jani.nikula, intel-gfx, llvm, kbuild-all
Hi Jani,
I love your patch! Yet something to improve:
[auto build test ERROR on drm/drm-next]
[also build test ERROR on drm-intel/for-linux-next drm-tip/drm-tip v5.17 next-20220328]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Jani-Nikula/drm-edid-constify-EDID-parsing-with-some-fixes/20220328-171858
base: git://anongit.freedesktop.org/drm/drm drm-next
config: i386-randconfig-a012-20220328 (https://download.01.org/0day-ci/archive/20220328/202203282045.xd3D6oF8-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 0f6d9501cf49ce02937099350d08f20c4af86f3d)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/f538c9296c54ce8f878432153584a68939ffc111
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jani-Nikula/drm-edid-constify-EDID-parsing-with-some-fixes/20220328-171858
git checkout f538c9296c54ce8f878432153584a68939ffc111
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/tiny/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/tiny/gm12u320.c:478:4: error: field designator 'pixel_clock' does not refer to any field in type 'struct detailed_timing'
.pixel_clock = 3383,
^
drivers/gpu/drm/tiny/gm12u320.c:495:4: error: field designator 'pixel_clock' does not refer to any field in type 'struct detailed_timing'
.pixel_clock = 0,
^
>> drivers/gpu/drm/tiny/gm12u320.c:496:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.type = 0xfd, /* Monitor ranges */
^
drivers/gpu/drm/tiny/gm12u320.c:497:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.data.range.min_vfreq = 59,
^
drivers/gpu/drm/tiny/gm12u320.c:498:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.data.range.max_vfreq = 61,
^
drivers/gpu/drm/tiny/gm12u320.c:499:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.data.range.min_hfreq_khz = 29,
^
drivers/gpu/drm/tiny/gm12u320.c:500:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.data.range.max_hfreq_khz = 32,
^
drivers/gpu/drm/tiny/gm12u320.c:501:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
^
drivers/gpu/drm/tiny/gm12u320.c:502:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.data.range.flags = 0,
^
drivers/gpu/drm/tiny/gm12u320.c:503:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.data.range.formula.cvt = {
^
drivers/gpu/drm/tiny/gm12u320.c:506:4: error: field designator 'pixel_clock' does not refer to any field in type 'struct detailed_timing'
.pixel_clock = 0,
^
drivers/gpu/drm/tiny/gm12u320.c:507:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.type = 0xfc, /* Model string */
^
drivers/gpu/drm/tiny/gm12u320.c:508:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.data.str.str = {
^
drivers/gpu/drm/tiny/gm12u320.c:512:4: error: field designator 'pixel_clock' does not refer to any field in type 'struct detailed_timing'
.pixel_clock = 0,
^
drivers/gpu/drm/tiny/gm12u320.c:513:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.type = 0xfe, /* Unspecified text / padding */
^
drivers/gpu/drm/tiny/gm12u320.c:514:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.data.str.str = {
^
16 errors generated.
vim +478 drivers/gpu/drm/tiny/gm12u320.c
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 457
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 458 /*
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 459 * We use fake EDID info so that userspace know that it is dealing with
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 460 * an Acer projector, rather then listing this as an "unknown" monitor.
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 461 * Note this assumes this driver is only ever used with the Acer C120, if we
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 462 * add support for other devices the vendor and model should be parameterized.
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 463 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 464 static struct edid gm12u320_edid = {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 465 .header = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 466 .mfg_id = { 0x04, 0x72 }, /* "ACR" */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 467 .prod_code = { 0x20, 0xc1 }, /* C120h */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 468 .serial = 0xaa55aa55,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 469 .mfg_week = 1,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 470 .mfg_year = 16,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 471 .version = 1, /* EDID 1.3 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 472 .revision = 3, /* EDID 1.3 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 473 .input = 0x08, /* Analog input */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 474 .features = 0x0a, /* Pref timing in DTD 1 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 475 .standard_timings = { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 476 { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 477 .detailed_timings = { {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 @478 .pixel_clock = 3383,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 479 /* hactive = 848, hblank = 256 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 480 .data.pixel_data.hactive_lo = 0x50,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 481 .data.pixel_data.hblank_lo = 0x00,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 482 .data.pixel_data.hactive_hblank_hi = 0x31,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 483 /* vactive = 480, vblank = 28 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 484 .data.pixel_data.vactive_lo = 0xe0,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 485 .data.pixel_data.vblank_lo = 0x1c,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 486 .data.pixel_data.vactive_vblank_hi = 0x10,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 487 /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 488 .data.pixel_data.hsync_offset_lo = 0x28,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 489 .data.pixel_data.hsync_pulse_width_lo = 0x80,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 490 .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 491 .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 492 /* Digital separate syncs, hsync+, vsync+ */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 493 .data.pixel_data.misc = 0x1e,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 494 }, {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 495 .pixel_clock = 0,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 @496 .data.other_data.type = 0xfd, /* Monitor ranges */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 497 .data.other_data.data.range.min_vfreq = 59,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 498 .data.other_data.data.range.max_vfreq = 61,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 499 .data.other_data.data.range.min_hfreq_khz = 29,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 500 .data.other_data.data.range.max_hfreq_khz = 32,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 501 .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 502 .data.other_data.data.range.flags = 0,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 503 .data.other_data.data.range.formula.cvt = {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 504 0xa0, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 505 }, {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 506 .pixel_clock = 0,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 507 .data.other_data.type = 0xfc, /* Model string */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 508 .data.other_data.data.str.str = {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 509 'P', 'r', 'o', 'j', 'e', 'c', 't', 'o', 'r', '\n',
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 510 ' ', ' ', ' ' },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 511 }, {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 512 .pixel_clock = 0,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 513 .data.other_data.type = 0xfe, /* Unspecified text / padding */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 514 .data.other_data.data.str.str = {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 515 '\n', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ',
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 516 ' ', ' ', ' ' },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 517 } },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 518 .checksum = 0x13,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 519 };
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 520
--
0-DAY CI Kernel Test Service
https://01.org/lkp
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Intel-gfx] [PATCH v2 03/11] drm/edid: slightly restructure timing and non-timing descriptor structs
@ 2022-03-28 12:26 ` kernel test robot
0 siblings, 0 replies; 42+ messages in thread
From: kernel test robot @ 2022-03-28 12:26 UTC (permalink / raw)
To: Jani Nikula, dri-devel; +Cc: llvm, kbuild-all, jani.nikula, intel-gfx
Hi Jani,
I love your patch! Yet something to improve:
[auto build test ERROR on drm/drm-next]
[also build test ERROR on drm-intel/for-linux-next drm-tip/drm-tip v5.17 next-20220328]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Jani-Nikula/drm-edid-constify-EDID-parsing-with-some-fixes/20220328-171858
base: git://anongit.freedesktop.org/drm/drm drm-next
config: i386-randconfig-a012-20220328 (https://download.01.org/0day-ci/archive/20220328/202203282045.xd3D6oF8-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 0f6d9501cf49ce02937099350d08f20c4af86f3d)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/f538c9296c54ce8f878432153584a68939ffc111
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jani-Nikula/drm-edid-constify-EDID-parsing-with-some-fixes/20220328-171858
git checkout f538c9296c54ce8f878432153584a68939ffc111
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/tiny/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/tiny/gm12u320.c:478:4: error: field designator 'pixel_clock' does not refer to any field in type 'struct detailed_timing'
.pixel_clock = 3383,
^
drivers/gpu/drm/tiny/gm12u320.c:495:4: error: field designator 'pixel_clock' does not refer to any field in type 'struct detailed_timing'
.pixel_clock = 0,
^
>> drivers/gpu/drm/tiny/gm12u320.c:496:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.type = 0xfd, /* Monitor ranges */
^
drivers/gpu/drm/tiny/gm12u320.c:497:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.data.range.min_vfreq = 59,
^
drivers/gpu/drm/tiny/gm12u320.c:498:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.data.range.max_vfreq = 61,
^
drivers/gpu/drm/tiny/gm12u320.c:499:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.data.range.min_hfreq_khz = 29,
^
drivers/gpu/drm/tiny/gm12u320.c:500:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.data.range.max_hfreq_khz = 32,
^
drivers/gpu/drm/tiny/gm12u320.c:501:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
^
drivers/gpu/drm/tiny/gm12u320.c:502:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.data.range.flags = 0,
^
drivers/gpu/drm/tiny/gm12u320.c:503:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.data.range.formula.cvt = {
^
drivers/gpu/drm/tiny/gm12u320.c:506:4: error: field designator 'pixel_clock' does not refer to any field in type 'struct detailed_timing'
.pixel_clock = 0,
^
drivers/gpu/drm/tiny/gm12u320.c:507:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.type = 0xfc, /* Model string */
^
drivers/gpu/drm/tiny/gm12u320.c:508:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.data.str.str = {
^
drivers/gpu/drm/tiny/gm12u320.c:512:4: error: field designator 'pixel_clock' does not refer to any field in type 'struct detailed_timing'
.pixel_clock = 0,
^
drivers/gpu/drm/tiny/gm12u320.c:513:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.type = 0xfe, /* Unspecified text / padding */
^
drivers/gpu/drm/tiny/gm12u320.c:514:9: error: field designator 'other_data' does not refer to any field in type 'union (unnamed union at include/drm/drm_edid.h:173:2)'
.data.other_data.data.str.str = {
^
16 errors generated.
vim +478 drivers/gpu/drm/tiny/gm12u320.c
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 457
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 458 /*
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 459 * We use fake EDID info so that userspace know that it is dealing with
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 460 * an Acer projector, rather then listing this as an "unknown" monitor.
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 461 * Note this assumes this driver is only ever used with the Acer C120, if we
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 462 * add support for other devices the vendor and model should be parameterized.
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 463 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 464 static struct edid gm12u320_edid = {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 465 .header = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 466 .mfg_id = { 0x04, 0x72 }, /* "ACR" */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 467 .prod_code = { 0x20, 0xc1 }, /* C120h */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 468 .serial = 0xaa55aa55,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 469 .mfg_week = 1,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 470 .mfg_year = 16,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 471 .version = 1, /* EDID 1.3 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 472 .revision = 3, /* EDID 1.3 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 473 .input = 0x08, /* Analog input */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 474 .features = 0x0a, /* Pref timing in DTD 1 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 475 .standard_timings = { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 476 { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 477 .detailed_timings = { {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 @478 .pixel_clock = 3383,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 479 /* hactive = 848, hblank = 256 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 480 .data.pixel_data.hactive_lo = 0x50,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 481 .data.pixel_data.hblank_lo = 0x00,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 482 .data.pixel_data.hactive_hblank_hi = 0x31,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 483 /* vactive = 480, vblank = 28 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 484 .data.pixel_data.vactive_lo = 0xe0,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 485 .data.pixel_data.vblank_lo = 0x1c,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 486 .data.pixel_data.vactive_vblank_hi = 0x10,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 487 /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 488 .data.pixel_data.hsync_offset_lo = 0x28,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 489 .data.pixel_data.hsync_pulse_width_lo = 0x80,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 490 .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 491 .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 492 /* Digital separate syncs, hsync+, vsync+ */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 493 .data.pixel_data.misc = 0x1e,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 494 }, {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 495 .pixel_clock = 0,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 @496 .data.other_data.type = 0xfd, /* Monitor ranges */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 497 .data.other_data.data.range.min_vfreq = 59,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 498 .data.other_data.data.range.max_vfreq = 61,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 499 .data.other_data.data.range.min_hfreq_khz = 29,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 500 .data.other_data.data.range.max_hfreq_khz = 32,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 501 .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 502 .data.other_data.data.range.flags = 0,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 503 .data.other_data.data.range.formula.cvt = {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 504 0xa0, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 505 }, {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 506 .pixel_clock = 0,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 507 .data.other_data.type = 0xfc, /* Model string */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 508 .data.other_data.data.str.str = {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 509 'P', 'r', 'o', 'j', 'e', 'c', 't', 'o', 'r', '\n',
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 510 ' ', ' ', ' ' },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 511 }, {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 512 .pixel_clock = 0,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 513 .data.other_data.type = 0xfe, /* Unspecified text / padding */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 514 .data.other_data.data.str.str = {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 515 '\n', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ',
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 516 ' ', ' ', ' ' },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 517 } },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 518 .checksum = 0x13,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 519 };
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 520
--
0-DAY CI Kernel Test Service
https://01.org/lkp
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-gfx] [PATCH v2 03/11] drm/edid: slightly restructure timing and non-timing descriptor structs
2022-03-28 9:17 ` [Intel-gfx] " Jani Nikula
` (3 preceding siblings ...)
(?)
@ 2022-03-28 12:46 ` kernel test robot
-1 siblings, 0 replies; 42+ messages in thread
From: kernel test robot @ 2022-03-28 12:46 UTC (permalink / raw)
To: Jani Nikula, dri-devel; +Cc: jani.nikula, intel-gfx, kbuild-all
Hi Jani,
I love your patch! Yet something to improve:
[auto build test ERROR on drm/drm-next]
[also build test ERROR on drm-intel/for-linux-next drm-tip/drm-tip v5.17 next-20220328]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Jani-Nikula/drm-edid-constify-EDID-parsing-with-some-fixes/20220328-171858
base: git://anongit.freedesktop.org/drm/drm drm-next
config: mips-randconfig-r005-20220327 (https://download.01.org/0day-ci/archive/20220328/202203282023.nkTeTLA5-lkp@intel.com/config)
compiler: mips-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/f538c9296c54ce8f878432153584a68939ffc111
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jani-Nikula/drm-edid-constify-EDID-parsing-with-some-fixes/20220328-171858
git checkout f538c9296c54ce8f878432153584a68939ffc111
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=mips SHELL=/bin/bash drivers/gpu/drm/tiny/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All error/warnings (new ones prefixed by >>):
>> drivers/gpu/drm/tiny/gm12u320.c:478:18: error: 'struct detailed_timing' has no member named 'pixel_clock'
478 | .pixel_clock = 3383,
| ^~~~~~~~~~~
>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
464 | static struct edid gm12u320_edid = {
| ^
......
478 | .pixel_clock = 3383,
| {{ }}
479 | /* hactive = 848, hblank = 256 */
480 | .data.pixel_data.hactive_lo = 0x50,
| }}
481 | .data.pixel_data.hblank_lo = 0x00,
| }}
482 | .data.pixel_data.hactive_hblank_hi = 0x31,
| }}
483 | /* vactive = 480, vblank = 28 */
484 | .data.pixel_data.vactive_lo = 0xe0,
| }}
485 | .data.pixel_data.vblank_lo = 0x1c,
| }}
486 | .data.pixel_data.vactive_vblank_hi = 0x10,
| }}
487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
488 | .data.pixel_data.hsync_offset_lo = 0x28,
| }}
489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
| }}
490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
| }}
491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
| }}
......
494 | }, {
| }}
drivers/gpu/drm/tiny/gm12u320.c:495:18: error: 'struct detailed_timing' has no member named 'pixel_clock'
495 | .pixel_clock = 0,
| ^~~~~~~~~~~
>> drivers/gpu/drm/tiny/gm12u320.c:496:23: error: 'union <anonymous>' has no member named 'other_data'
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| ^~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:496:41: warning: initialized field overwritten [-Woverride-init]
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| ^~~~
drivers/gpu/drm/tiny/gm12u320.c:496:41: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
drivers/gpu/drm/tiny/gm12u320.c:497:23: error: 'union <anonymous>' has no member named 'other_data'
497 | .data.other_data.data.range.min_vfreq = 59,
| ^~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:497:57: warning: initialized field overwritten [-Woverride-init]
497 | .data.other_data.data.range.min_vfreq = 59,
| ^~
drivers/gpu/drm/tiny/gm12u320.c:497:57: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
drivers/gpu/drm/tiny/gm12u320.c:498:23: error: 'union <anonymous>' has no member named 'other_data'
498 | .data.other_data.data.range.max_vfreq = 61,
| ^~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:498:57: warning: initialized field overwritten [-Woverride-init]
498 | .data.other_data.data.range.max_vfreq = 61,
| ^~
drivers/gpu/drm/tiny/gm12u320.c:498:57: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
drivers/gpu/drm/tiny/gm12u320.c:499:23: error: 'union <anonymous>' has no member named 'other_data'
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| ^~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:499:61: warning: initialized field overwritten [-Woverride-init]
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| ^~
drivers/gpu/drm/tiny/gm12u320.c:499:61: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
drivers/gpu/drm/tiny/gm12u320.c:500:23: error: 'union <anonymous>' has no member named 'other_data'
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| ^~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:500:61: warning: initialized field overwritten [-Woverride-init]
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| ^~
drivers/gpu/drm/tiny/gm12u320.c:500:61: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
drivers/gpu/drm/tiny/gm12u320.c:501:23: error: 'union <anonymous>' has no member named 'other_data'
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| ^~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:501:63: warning: initialized field overwritten [-Woverride-init]
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| ^
drivers/gpu/drm/tiny/gm12u320.c:501:63: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
drivers/gpu/drm/tiny/gm12u320.c:502:23: error: 'union <anonymous>' has no member named 'other_data'
502 | .data.other_data.data.range.flags = 0,
| ^~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:502:53: warning: initialized field overwritten [-Woverride-init]
502 | .data.other_data.data.range.flags = 0,
| ^
drivers/gpu/drm/tiny/gm12u320.c:502:53: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data.pixel_clock')
drivers/gpu/drm/tiny/gm12u320.c:503:23: error: 'union <anonymous>' has no member named 'other_data'
503 | .data.other_data.data.range.formula.cvt = {
| ^~~~~~~~~~
>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
464 | static struct edid gm12u320_edid = {
| ^
......
478 | .pixel_clock = 3383,
| {{ }}
479 | /* hactive = 848, hblank = 256 */
480 | .data.pixel_data.hactive_lo = 0x50,
| }}
481 | .data.pixel_data.hblank_lo = 0x00,
| }}
482 | .data.pixel_data.hactive_hblank_hi = 0x31,
| }}
483 | /* vactive = 480, vblank = 28 */
484 | .data.pixel_data.vactive_lo = 0xe0,
| }}
485 | .data.pixel_data.vblank_lo = 0x1c,
| }}
486 | .data.pixel_data.vactive_vblank_hi = 0x10,
| }}
487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
488 | .data.pixel_data.hsync_offset_lo = 0x28,
| }}
489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
| }}
490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
| }}
491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
| }}
......
494 | }, {
| }}
495 | .pixel_clock = 0,
| -
| {{0}}
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| { }}
497 | .data.other_data.data.range.min_vfreq = 59,
| { }}
498 | .data.other_data.data.range.max_vfreq = 61,
| { }}
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| { }}
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| { }}
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| {}}
502 | .data.other_data.data.range.flags = 0,
| {}}
drivers/gpu/drm/tiny/gm12u320.c:503:59: warning: initialized field overwritten [-Woverride-init]
503 | .data.other_data.data.range.formula.cvt = {
| ^
drivers/gpu/drm/tiny/gm12u320.c:503:59: note: (near initialization for 'gm12u320_edid.detailed_timings[1].data.pixel_data')
>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
464 | static struct edid gm12u320_edid = {
| ^
......
478 | .pixel_clock = 3383,
| {{ }}
479 | /* hactive = 848, hblank = 256 */
480 | .data.pixel_data.hactive_lo = 0x50,
| }}
481 | .data.pixel_data.hblank_lo = 0x00,
| }}
482 | .data.pixel_data.hactive_hblank_hi = 0x31,
| }}
483 | /* vactive = 480, vblank = 28 */
484 | .data.pixel_data.vactive_lo = 0xe0,
| }}
485 | .data.pixel_data.vblank_lo = 0x1c,
| }}
486 | .data.pixel_data.vactive_vblank_hi = 0x10,
| }}
487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
488 | .data.pixel_data.hsync_offset_lo = 0x28,
| }}
489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
| }}
490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
| }}
491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
| }}
......
494 | }, {
| }}
495 | .pixel_clock = 0,
| -
| {{0}}
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| { }}
497 | .data.other_data.data.range.min_vfreq = 59,
| { }}
498 | .data.other_data.data.range.max_vfreq = 61,
| { }}
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| { }}
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| { }}
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| {}}
502 | .data.other_data.data.range.flags = 0,
| {}}
......
505 | }, {
| }
drivers/gpu/drm/tiny/gm12u320.c:506:18: error: 'struct detailed_timing' has no member named 'pixel_clock'
506 | .pixel_clock = 0,
| ^~~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:507:23: error: 'union <anonymous>' has no member named 'other_data'
507 | .data.other_data.type = 0xfc, /* Model string */
| ^~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:507:41: warning: initialized field overwritten [-Woverride-init]
507 | .data.other_data.type = 0xfc, /* Model string */
| ^~~~
drivers/gpu/drm/tiny/gm12u320.c:507:41: note: (near initialization for 'gm12u320_edid.detailed_timings[2].data.pixel_data.pixel_clock')
drivers/gpu/drm/tiny/gm12u320.c:508:23: error: 'union <anonymous>' has no member named 'other_data'
508 | .data.other_data.data.str.str = {
| ^~~~~~~~~~
>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
464 | static struct edid gm12u320_edid = {
| ^
......
478 | .pixel_clock = 3383,
| {{ }}
479 | /* hactive = 848, hblank = 256 */
480 | .data.pixel_data.hactive_lo = 0x50,
| }}
481 | .data.pixel_data.hblank_lo = 0x00,
| }}
482 | .data.pixel_data.hactive_hblank_hi = 0x31,
| }}
483 | /* vactive = 480, vblank = 28 */
484 | .data.pixel_data.vactive_lo = 0xe0,
| }}
485 | .data.pixel_data.vblank_lo = 0x1c,
| }}
486 | .data.pixel_data.vactive_vblank_hi = 0x10,
| }}
487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
488 | .data.pixel_data.hsync_offset_lo = 0x28,
| }}
489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
| }}
490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
| }}
491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
| }}
......
494 | }, {
| }}
495 | .pixel_clock = 0,
| -
| {{0}}
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| { }}
497 | .data.other_data.data.range.min_vfreq = 59,
| { }}
498 | .data.other_data.data.range.max_vfreq = 61,
| { }}
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| { }}
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| { }}
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| {}}
502 | .data.other_data.data.range.flags = 0,
| {}}
......
505 | }, {
| }
506 | .pixel_clock = 0,
| -
| {{0}}
507 | .data.other_data.type = 0xfc, /* Model string */
| { }}
drivers/gpu/drm/tiny/gm12u320.c:508:49: warning: initialized field overwritten [-Woverride-init]
508 | .data.other_data.data.str.str = {
| ^
drivers/gpu/drm/tiny/gm12u320.c:508:49: note: (near initialization for 'gm12u320_edid.detailed_timings[2].data.pixel_data')
>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
464 | static struct edid gm12u320_edid = {
| ^
......
478 | .pixel_clock = 3383,
| {{ }}
479 | /* hactive = 848, hblank = 256 */
480 | .data.pixel_data.hactive_lo = 0x50,
| }}
481 | .data.pixel_data.hblank_lo = 0x00,
| }}
482 | .data.pixel_data.hactive_hblank_hi = 0x31,
| }}
483 | /* vactive = 480, vblank = 28 */
484 | .data.pixel_data.vactive_lo = 0xe0,
| }}
485 | .data.pixel_data.vblank_lo = 0x1c,
| }}
486 | .data.pixel_data.vactive_vblank_hi = 0x10,
| }}
487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
488 | .data.pixel_data.hsync_offset_lo = 0x28,
| }}
489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
| }}
490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
| }}
491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
| }}
......
494 | }, {
| }}
495 | .pixel_clock = 0,
| -
| {{0}}
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| { }}
497 | .data.other_data.data.range.min_vfreq = 59,
| { }}
498 | .data.other_data.data.range.max_vfreq = 61,
| { }}
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| { }}
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| { }}
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| {}}
502 | .data.other_data.data.range.flags = 0,
| {}}
......
505 | }, {
| }
506 | .pixel_clock = 0,
| -
| {{0}}
507 | .data.other_data.type = 0xfc, /* Model string */
| { }}
......
511 | }, {
| }
drivers/gpu/drm/tiny/gm12u320.c:512:18: error: 'struct detailed_timing' has no member named 'pixel_clock'
512 | .pixel_clock = 0,
| ^~~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:513:23: error: 'union <anonymous>' has no member named 'other_data'
513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
| ^~~~~~~~~~
drivers/gpu/drm/tiny/gm12u320.c:513:41: warning: initialized field overwritten [-Woverride-init]
513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
| ^~~~
drivers/gpu/drm/tiny/gm12u320.c:513:41: note: (near initialization for 'gm12u320_edid.detailed_timings[3].data.pixel_data.pixel_clock')
drivers/gpu/drm/tiny/gm12u320.c:514:23: error: 'union <anonymous>' has no member named 'other_data'
514 | .data.other_data.data.str.str = {
| ^~~~~~~~~~
>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
464 | static struct edid gm12u320_edid = {
| ^
......
478 | .pixel_clock = 3383,
| {{ }}
479 | /* hactive = 848, hblank = 256 */
480 | .data.pixel_data.hactive_lo = 0x50,
| }}
481 | .data.pixel_data.hblank_lo = 0x00,
| }}
482 | .data.pixel_data.hactive_hblank_hi = 0x31,
| }}
483 | /* vactive = 480, vblank = 28 */
484 | .data.pixel_data.vactive_lo = 0xe0,
| }}
485 | .data.pixel_data.vblank_lo = 0x1c,
| }}
486 | .data.pixel_data.vactive_vblank_hi = 0x10,
| }}
487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
488 | .data.pixel_data.hsync_offset_lo = 0x28,
| }}
489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
| }}
490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
| }}
491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
| }}
......
494 | }, {
| }}
495 | .pixel_clock = 0,
| -
| {{0}}
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| { }}
497 | .data.other_data.data.range.min_vfreq = 59,
| { }}
498 | .data.other_data.data.range.max_vfreq = 61,
| { }}
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| { }}
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| { }}
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| {}}
502 | .data.other_data.data.range.flags = 0,
| {}}
......
505 | }, {
| }
506 | .pixel_clock = 0,
| -
| {{0}}
507 | .data.other_data.type = 0xfc, /* Model string */
| { }}
......
511 | }, {
| }
512 | .pixel_clock = 0,
| -
| {{0}}
513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
| { }}
drivers/gpu/drm/tiny/gm12u320.c:514:49: warning: initialized field overwritten [-Woverride-init]
514 | .data.other_data.data.str.str = {
| ^
drivers/gpu/drm/tiny/gm12u320.c:514:49: note: (near initialization for 'gm12u320_edid.detailed_timings[3].data.pixel_data')
>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
464 | static struct edid gm12u320_edid = {
| ^
......
478 | .pixel_clock = 3383,
| {{ }}
479 | /* hactive = 848, hblank = 256 */
480 | .data.pixel_data.hactive_lo = 0x50,
| }}
481 | .data.pixel_data.hblank_lo = 0x00,
| }}
482 | .data.pixel_data.hactive_hblank_hi = 0x31,
| }}
483 | /* vactive = 480, vblank = 28 */
484 | .data.pixel_data.vactive_lo = 0xe0,
| }}
485 | .data.pixel_data.vblank_lo = 0x1c,
| }}
486 | .data.pixel_data.vactive_vblank_hi = 0x10,
| }}
487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
488 | .data.pixel_data.hsync_offset_lo = 0x28,
| }}
489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
| }}
490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
| }}
491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
| }}
......
494 | }, {
| }}
495 | .pixel_clock = 0,
| -
| {{0}}
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| { }}
497 | .data.other_data.data.range.min_vfreq = 59,
| { }}
498 | .data.other_data.data.range.max_vfreq = 61,
| { }}
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| { }}
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| { }}
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| {}}
502 | .data.other_data.data.range.flags = 0,
| {}}
......
505 | }, {
| }
506 | .pixel_clock = 0,
| -
| {{0}}
507 | .data.other_data.type = 0xfc, /* Model string */
| { }}
......
511 | }, {
| }
512 | .pixel_clock = 0,
| -
| {{0}}
513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
| { }}
......
517 | } },
| }
>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
464 | static struct edid gm12u320_edid = {
| ^
......
478 | .pixel_clock = 3383,
| {{ }}
479 | /* hactive = 848, hblank = 256 */
480 | .data.pixel_data.hactive_lo = 0x50,
| }}
481 | .data.pixel_data.hblank_lo = 0x00,
| }}
482 | .data.pixel_data.hactive_hblank_hi = 0x31,
| }}
483 | /* vactive = 480, vblank = 28 */
484 | .data.pixel_data.vactive_lo = 0xe0,
| }}
485 | .data.pixel_data.vblank_lo = 0x1c,
| }}
486 | .data.pixel_data.vactive_vblank_hi = 0x10,
| }}
487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
488 | .data.pixel_data.hsync_offset_lo = 0x28,
| }}
489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
| }}
490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
| }}
491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
| }}
......
494 | }, {
| }}
495 | .pixel_clock = 0,
| -
| {{0}}
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| { }}
497 | .data.other_data.data.range.min_vfreq = 59,
| { }}
498 | .data.other_data.data.range.max_vfreq = 61,
| { }}
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| { }}
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| { }}
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| {}}
502 | .data.other_data.data.range.flags = 0,
| {}}
......
505 | }, {
| }
506 | .pixel_clock = 0,
| -
| {{0}}
507 | .data.other_data.type = 0xfc, /* Model string */
| { }}
......
511 | }, {
| }
512 | .pixel_clock = 0,
| -
| {{0}}
513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
| { }}
......
517 | } },
| }
>> drivers/gpu/drm/tiny/gm12u320.c:464:36: warning: missing braces around initializer [-Wmissing-braces]
464 | static struct edid gm12u320_edid = {
| ^
......
478 | .pixel_clock = 3383,
| {{ }}
479 | /* hactive = 848, hblank = 256 */
480 | .data.pixel_data.hactive_lo = 0x50,
| }}
481 | .data.pixel_data.hblank_lo = 0x00,
| }}
482 | .data.pixel_data.hactive_hblank_hi = 0x31,
| }}
483 | /* vactive = 480, vblank = 28 */
484 | .data.pixel_data.vactive_lo = 0xe0,
| }}
485 | .data.pixel_data.vblank_lo = 0x1c,
| }}
486 | .data.pixel_data.vactive_vblank_hi = 0x10,
| }}
487 | /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
488 | .data.pixel_data.hsync_offset_lo = 0x28,
| }}
489 | .data.pixel_data.hsync_pulse_width_lo = 0x80,
| }}
490 | .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
| }}
491 | .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
| }}
......
494 | }, {
| }}
495 | .pixel_clock = 0,
| -
| {{0}}
496 | .data.other_data.type = 0xfd, /* Monitor ranges */
| { }}
497 | .data.other_data.data.range.min_vfreq = 59,
| { }}
498 | .data.other_data.data.range.max_vfreq = 61,
| { }}
499 | .data.other_data.data.range.min_hfreq_khz = 29,
| { }}
500 | .data.other_data.data.range.max_hfreq_khz = 32,
| { }}
501 | .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
| {}}
502 | .data.other_data.data.range.flags = 0,
| {}}
......
505 | }, {
| }
506 | .pixel_clock = 0,
| -
| {{0}}
507 | .data.other_data.type = 0xfc, /* Model string */
| { }}
......
511 | }, {
| }
512 | .pixel_clock = 0,
| -
| {{0}}
513 | .data.other_data.type = 0xfe, /* Unspecified text / padding */
| { }}
......
517 | } },
| }
vim +478 drivers/gpu/drm/tiny/gm12u320.c
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 457
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 458 /*
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 459 * We use fake EDID info so that userspace know that it is dealing with
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 460 * an Acer projector, rather then listing this as an "unknown" monitor.
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 461 * Note this assumes this driver is only ever used with the Acer C120, if we
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 462 * add support for other devices the vendor and model should be parameterized.
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 463 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 @464 static struct edid gm12u320_edid = {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 465 .header = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 466 .mfg_id = { 0x04, 0x72 }, /* "ACR" */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 467 .prod_code = { 0x20, 0xc1 }, /* C120h */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 468 .serial = 0xaa55aa55,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 469 .mfg_week = 1,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 470 .mfg_year = 16,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 471 .version = 1, /* EDID 1.3 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 472 .revision = 3, /* EDID 1.3 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 473 .input = 0x08, /* Analog input */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 474 .features = 0x0a, /* Pref timing in DTD 1 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 475 .standard_timings = { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 476 { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 477 .detailed_timings = { {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 @478 .pixel_clock = 3383,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 479 /* hactive = 848, hblank = 256 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 480 .data.pixel_data.hactive_lo = 0x50,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 481 .data.pixel_data.hblank_lo = 0x00,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 482 .data.pixel_data.hactive_hblank_hi = 0x31,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 483 /* vactive = 480, vblank = 28 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 484 .data.pixel_data.vactive_lo = 0xe0,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 485 .data.pixel_data.vblank_lo = 0x1c,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 486 .data.pixel_data.vactive_vblank_hi = 0x10,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 487 /* hsync offset 40 pw 128, vsync offset 1 pw 4 */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 488 .data.pixel_data.hsync_offset_lo = 0x28,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 489 .data.pixel_data.hsync_pulse_width_lo = 0x80,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 490 .data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 491 .data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 492 /* Digital separate syncs, hsync+, vsync+ */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 493 .data.pixel_data.misc = 0x1e,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 494 }, {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 495 .pixel_clock = 0,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 @496 .data.other_data.type = 0xfd, /* Monitor ranges */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 497 .data.other_data.data.range.min_vfreq = 59,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 498 .data.other_data.data.range.max_vfreq = 61,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 499 .data.other_data.data.range.min_hfreq_khz = 29,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 500 .data.other_data.data.range.max_hfreq_khz = 32,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 501 .data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 502 .data.other_data.data.range.flags = 0,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 503 .data.other_data.data.range.formula.cvt = {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 504 0xa0, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 505 }, {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 506 .pixel_clock = 0,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 507 .data.other_data.type = 0xfc, /* Model string */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 508 .data.other_data.data.str.str = {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 509 'P', 'r', 'o', 'j', 'e', 'c', 't', 'o', 'r', '\n',
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 510 ' ', ' ', ' ' },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 511 }, {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 512 .pixel_clock = 0,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 513 .data.other_data.type = 0xfe, /* Unspecified text / padding */
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 514 .data.other_data.data.str.str = {
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 515 '\n', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ',
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 516 ' ', ' ', ' ' },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 517 } },
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 518 .checksum = 0x13,
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 519 };
e4f86e43716443 drivers/gpu/drm/gm12u320/gm12u320.c Hans de Goede 2019-07-21 520
--
0-DAY CI Kernel Test Service
https://01.org/lkp
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