* [PATCH v7 0/3] arm64: mvebu: Support for Marvell 98DX2530 (and variants) @ 2022-05-12 4:24 ` Chris Packham 0 siblings, 0 replies; 26+ messages in thread From: Chris Packham @ 2022-05-12 4:24 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan Cc: devicetree, linux-kernel, linux-arm-kernel, Chris Packham This series adds support for the Marvell 98DX2530 SoC which is the Control and Management CPU integrated into the AlleyCat5/AlleyCat5X series of Marvell switches. The CPU core is an ARM Cortex-A55 with neon, simd and crypto extensions. This is fairly similar to the Armada-3700 SoC so most of the required peripherals are already supported. This series adds a devicetree and pinctrl driver for the SoC and the RD-AC5X-32G16HVG6HLG reference board. The pinctrl changes from v4 have been picked up and are in linux-next so I haven't included them in this round. That leaves just the dts files and a minor Kconfig update for arm64. Chris Packham (3): dt-bindings: marvell: Document the AC5/AC5X compatibles arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board arm64: marvell: enable the 98DX2530 pinctrl driver .../bindings/arm/marvell/armada-98dx25xx.yaml | 32 ++ arch/arm64/Kconfig.platforms | 2 + arch/arm64/boot/dts/marvell/Makefile | 1 + .../boot/dts/marvell/armada-98dx25xx.dtsi | 295 ++++++++++++++++++ .../boot/dts/marvell/armada-98dx35xx-rd.dts | 101 ++++++ .../boot/dts/marvell/armada-98dx35xx.dtsi | 13 + 6 files changed, 444 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/marvell/armada-98dx25xx.yaml create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi -- 2.36.0 ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v7 0/3] arm64: mvebu: Support for Marvell 98DX2530 (and variants) @ 2022-05-12 4:24 ` Chris Packham 0 siblings, 0 replies; 26+ messages in thread From: Chris Packham @ 2022-05-12 4:24 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan Cc: devicetree, linux-kernel, linux-arm-kernel, Chris Packham This series adds support for the Marvell 98DX2530 SoC which is the Control and Management CPU integrated into the AlleyCat5/AlleyCat5X series of Marvell switches. The CPU core is an ARM Cortex-A55 with neon, simd and crypto extensions. This is fairly similar to the Armada-3700 SoC so most of the required peripherals are already supported. This series adds a devicetree and pinctrl driver for the SoC and the RD-AC5X-32G16HVG6HLG reference board. The pinctrl changes from v4 have been picked up and are in linux-next so I haven't included them in this round. That leaves just the dts files and a minor Kconfig update for arm64. Chris Packham (3): dt-bindings: marvell: Document the AC5/AC5X compatibles arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board arm64: marvell: enable the 98DX2530 pinctrl driver .../bindings/arm/marvell/armada-98dx25xx.yaml | 32 ++ arch/arm64/Kconfig.platforms | 2 + arch/arm64/boot/dts/marvell/Makefile | 1 + .../boot/dts/marvell/armada-98dx25xx.dtsi | 295 ++++++++++++++++++ .../boot/dts/marvell/armada-98dx35xx-rd.dts | 101 ++++++ .../boot/dts/marvell/armada-98dx35xx.dtsi | 13 + 6 files changed, 444 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/marvell/armada-98dx25xx.yaml create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi -- 2.36.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v7 1/3] dt-bindings: marvell: Document the AC5/AC5X compatibles 2022-05-12 4:24 ` Chris Packham @ 2022-05-12 4:24 ` Chris Packham -1 siblings, 0 replies; 26+ messages in thread From: Chris Packham @ 2022-05-12 4:24 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan Cc: devicetree, linux-kernel, linux-arm-kernel, Chris Packham Describe the compatible properties for the Marvell Alleycat5/5X switches with integrated CPUs. Alleycat5: * 98DX2538: 24x1G + 2x10G + 2x10G Stack * 98DX2535: 24x1G + 4x1G Stack * 98DX2532: 8x1G + 2x10G + 2x1G Stack * 98DX2531: 8x1G + 4x1G Stack * 98DX2528: 24x1G + 2x10G + 2x10G Stack * 98DX2525: 24x1G + 4x1G Stack * 98DX2522: 8x1G + 2x10G + 2x1G Stack * 98DX2521: 8x1G + 4x1G Stack * 98DX2518: 24x1G + 2x10G + 2x10G Stack * 98DX2515: 24x1G + 4x1G Stack * 98DX2512: 8x1G + 2x10G + 2x1G Stack * 98DX2511: 8x1G + 4x1G Stack Alleycat5X: * 98DX3500: 24x1G + 6x25G * 98DX3501: 16x1G + 6x10G * 98DX3510: 48x1G + 6x25G * 98DX3520: 24x2.5G + 6x25G * 98DX3530: 48x2.5G + 6x25G * 98DX3540: 12x5G/6x10G + 6x25G * 98DX3550: 24x5G/12x10G + 6x25G Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> --- Notes: Changes in v7: - Add rd-ac5 and rd-ac5x boards to binding. - Rename to armada-98dx25xx.yaml Changes in v6: - New .../bindings/arm/marvell/armada-98dx25xx.yaml | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/marvell/armada-98dx25xx.yaml diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-98dx25xx.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-98dx25xx.yaml new file mode 100644 index 000000000000..b99cfb096277 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/armada-98dx25xx.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/armada-98dx25xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Alleycat5/5X Platforms + +maintainers: + - Chris Packham <chris.packham@alliedtelesis.co.nz> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Alleycat5 (98DX25xx) Reference Design + items: + - enum: + - marvell,rd-ac5 + - const: marvell,ac5 + + - description: Alleycat5X (98DX35xx) Reference Design + items: + - enum: + - marvell,rd-ac5x + - const: marvell,ac5x + - const: marvell,ac5 + +additionalProperties: true + +... -- 2.36.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v7 1/3] dt-bindings: marvell: Document the AC5/AC5X compatibles @ 2022-05-12 4:24 ` Chris Packham 0 siblings, 0 replies; 26+ messages in thread From: Chris Packham @ 2022-05-12 4:24 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan Cc: devicetree, linux-kernel, linux-arm-kernel, Chris Packham Describe the compatible properties for the Marvell Alleycat5/5X switches with integrated CPUs. Alleycat5: * 98DX2538: 24x1G + 2x10G + 2x10G Stack * 98DX2535: 24x1G + 4x1G Stack * 98DX2532: 8x1G + 2x10G + 2x1G Stack * 98DX2531: 8x1G + 4x1G Stack * 98DX2528: 24x1G + 2x10G + 2x10G Stack * 98DX2525: 24x1G + 4x1G Stack * 98DX2522: 8x1G + 2x10G + 2x1G Stack * 98DX2521: 8x1G + 4x1G Stack * 98DX2518: 24x1G + 2x10G + 2x10G Stack * 98DX2515: 24x1G + 4x1G Stack * 98DX2512: 8x1G + 2x10G + 2x1G Stack * 98DX2511: 8x1G + 4x1G Stack Alleycat5X: * 98DX3500: 24x1G + 6x25G * 98DX3501: 16x1G + 6x10G * 98DX3510: 48x1G + 6x25G * 98DX3520: 24x2.5G + 6x25G * 98DX3530: 48x2.5G + 6x25G * 98DX3540: 12x5G/6x10G + 6x25G * 98DX3550: 24x5G/12x10G + 6x25G Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> --- Notes: Changes in v7: - Add rd-ac5 and rd-ac5x boards to binding. - Rename to armada-98dx25xx.yaml Changes in v6: - New .../bindings/arm/marvell/armada-98dx25xx.yaml | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/marvell/armada-98dx25xx.yaml diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-98dx25xx.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-98dx25xx.yaml new file mode 100644 index 000000000000..b99cfb096277 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/armada-98dx25xx.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/armada-98dx25xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Alleycat5/5X Platforms + +maintainers: + - Chris Packham <chris.packham@alliedtelesis.co.nz> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Alleycat5 (98DX25xx) Reference Design + items: + - enum: + - marvell,rd-ac5 + - const: marvell,ac5 + + - description: Alleycat5X (98DX35xx) Reference Design + items: + - enum: + - marvell,rd-ac5x + - const: marvell,ac5x + - const: marvell,ac5 + +additionalProperties: true + +... -- 2.36.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH v7 1/3] dt-bindings: marvell: Document the AC5/AC5X compatibles 2022-05-12 4:24 ` Chris Packham @ 2022-05-13 9:12 ` Krzysztof Kozlowski -1 siblings, 0 replies; 26+ messages in thread From: Krzysztof Kozlowski @ 2022-05-13 9:12 UTC (permalink / raw) To: Chris Packham, robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan Cc: devicetree, linux-kernel, linux-arm-kernel On 12/05/2022 06:24, Chris Packham wrote: > Describe the compatible properties for the Marvell Alleycat5/5X switches > with integrated CPUs. > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v7 1/3] dt-bindings: marvell: Document the AC5/AC5X compatibles @ 2022-05-13 9:12 ` Krzysztof Kozlowski 0 siblings, 0 replies; 26+ messages in thread From: Krzysztof Kozlowski @ 2022-05-13 9:12 UTC (permalink / raw) To: Chris Packham, robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan Cc: devicetree, linux-kernel, linux-arm-kernel On 12/05/2022 06:24, Chris Packham wrote: > Describe the compatible properties for the Marvell Alleycat5/5X switches > with integrated CPUs. > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board 2022-05-12 4:24 ` Chris Packham @ 2022-05-12 4:25 ` Chris Packham -1 siblings, 0 replies; 26+ messages in thread From: Chris Packham @ 2022-05-12 4:25 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan Cc: devicetree, linux-kernel, linux-arm-kernel, Chris Packham The 98DX2530 SoC is the Control and Management CPU integrated into the Marvell 98DX25xx and 98DX35xx series of switch chip (internally referred to as AlleyCat5 and AlleyCat5X). These files have been taken from the Marvell SDK and lightly cleaned up with the License and copyright retained. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> --- Notes: The Marvell SDK has a number of new compatible strings. I've brought through some of the drivers or where possible used an in-tree alternative (e.g. there is SDK code for a ac5-gpio but two instances of the existing marvell,orion-gpio seems to cover what is needed if you use an appropriate binding). I expect that there will a new series of patches when I get some different hardware (or additions to this series depending on if/when it lands). Changes in v7: - Add missing compatible on usb1 - Add "rd-ac5x" compatible for board - Move aliases to board dts - Move board specific usb info to board dts - Consolidate usb1 board settings and remove unnecessary compatible - Add Allied Telesis copyright - Rename files after mailng-list discussion Changes in v6: - Move CPU nodes above the SoC (Krzysztof) - Minor formatting clean ups (Krzysztof) - Run through `make dtbs_check` - Move gic nodes inside SoC - Group clocks under a clock node Changes in v5: - add #{address,size}-cells property to i2c nodes - make i2c nodes disabled in the SoC and enable them in the board - add interrupt controller attributes to gpio nodes - Move fixed-clock nodes up a level and remove unnecessary @0 Changes in v4: - use 'phy-handle' instead of 'phy' - move status="okay" on usb nodes to board dts - Add review from Andrew Changes in v3: - Move memory node to board - Use single digit reg value for phy address - Remove MMC node (driver needs work) - Remove syscon & simple-mfd for pinctrl Changes in v2: - Make pinctrl a child node of a syscon node - Use marvell,armada-8k-gpio instead of orion-gpio - Remove nand peripheral. The Marvell SDK does have some changes for the ac5-nand-controller but I currently lack hardware with NAND fitted so I can't test it right now. I've therefore chosen to omit the node and not attempted to bring in the driver or binding. - Remove pcie peripheral. Again there are changes in the SDK and I have no way of testing them. - Remove prestera node. - Remove "marvell,ac5-ehci" compatible from USB node as "marvell,orion-ehci" is sufficient - Remove watchdog node. There is a buggy driver for the ac5 watchdog in the SDK but it needs some work so I've dropped the node for now. arch/arm64/boot/dts/marvell/Makefile | 1 + .../boot/dts/marvell/armada-98dx25xx.dtsi | 295 ++++++++++++++++++ .../boot/dts/marvell/armada-98dx35xx-rd.dts | 101 ++++++ .../boot/dts/marvell/armada-98dx35xx.dtsi | 13 + 4 files changed, 410 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 1c794cdcb8e6..b7a4c715afbb 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb +dtb-$(CONFIG_ARCH_MVEBU) += armada-98dx35xx-rd.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi new file mode 100644 index 000000000000..55ab4cd843a9 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For AC5. + * + * Copyright (C) 2021 Marvell + * Copyright (C) 2022 Allied Telesis Labs + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Marvell AC5 SoC"; + compatible = "marvell,ac5"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + }; + }; + + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <25000000>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + internal-regs@7f000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + /* 16M internal register @ 0x7f00_0000 */ + ranges = <0x0 0x0 0x7f000000 0x1000000>; + dma-coherent; + + uart0: serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clock-frequency = <328000000>; + status = "okay"; + }; + + mdio: mdio@22004 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x22004 0x4>; + clocks = <&core_clock>; + }; + + i2c0: i2c@11000{ + compatible = "marvell,mv78230-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&core_clock>; + clock-names = "core"; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency=<100000>; + + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c0_pins>; + pinctrl-1 = <&i2c0_gpio>; + scl_gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; + sda_gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + i2c1: i2c@11100{ + compatible = "marvell,mv78230-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&core_clock>; + clock-names = "core"; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency=<100000>; + + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c1_pins>; + pinctrl-1 = <&i2c1_gpio>; + scl_gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; + sda_gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl0 0 0 32>; + marvell,pwm-offset = <0x1f0>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@18140 { + reg = <0x18140 0x40>; + compatible = "marvell,orion-gpio"; + ngpios = <14>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl0 0 32 14>; + marvell,pwm-offset = <0x1f0>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + /* + * Dedicated section for devices behind 32bit controllers so we + * can configure specific DMA mapping for them + */ + behind-32bit-controller@7f000000 { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>; + /* Host phy ram starts at 0x200M */ + dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>; + dma-coherent; + + eth0: ethernet@20000 { + compatible = "marvell,armada-ac5-neta"; + reg = <0x0 0x20000 0x0 0x4000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&core_clock>; + phy-mode = "sgmii"; + status = "disabled"; + }; + + eth1: ethernet@24000 { + compatible = "marvell,armada-ac5-neta"; + reg = <0x0 0x24000 0x0 0x4000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&core_clock>; + phy-mode = "sgmii"; + status = "disabled"; + }; + + usb0: usb@80000 { + compatible = "marvell,orion-ehci"; + reg = <0x0 0x80000 0x0 0x500>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + usb1: usb@a0000 { + compatible = "marvell,orion-ehci"; + reg = <0x0 0xa0000 0x0 0x500>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + + pinctrl0: pinctrl@80020100 { + compatible = "marvell,ac5-pinctrl"; + reg = <0 0x80020100 0 0x20>; + + i2c0_pins: i2c0-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c0"; + }; + + i2c0_gpio: i2c0-gpio-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "gpio"; + }; + + i2c1_pins: i2c1-pins { + marvell,pins = "mpp20", "mpp21"; + marvell,function = "i2c1"; + }; + + i2c1_gpio: i2c1-gpio-pins { + marvell,pins = "mpp20", "mpp21"; + marvell,function = "i2c1"; + }; + }; + + spi0: spi@805a0000 { + compatible = "marvell,armada-3700-spi"; + reg = <0x0 0x805a0000 0x0 0x50>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <&spi_clock>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <1>; + status = "disabled"; + }; + + spi1: spi@805a8000 { + compatible = "marvell,armada-3700-spi"; + reg = <0x0 0x805a8000 0x0 0x50>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <&spi_clock>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <1>; + status = "disabled"; + }; + + gic: interrupt-controller@80600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + /*#redistributor-regions = <1>;*/ + redistributor-stride = <0x0 0x20000>; // 128kB stride + reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ + <0x0 0x80660000 0x0 0x40000>; /* GICR */ + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + clocks { + core_clock: core-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + + axi_clock: axi-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <325000000>; + }; + + spi_clock: spi-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts b/arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts new file mode 100644 index 000000000000..c20e032410fa --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For RD-AC5X. + * + * Copyright (C) 2021 Marvell + * Copyright (C) 2022 Allied Telesis Labs + */ +/* + * Device Tree file for Marvell Alleycat 5X development board + * This board file supports the B configuration of the board + */ + +/dts-v1/; + +#include "armada-98dx35xx.dtsi" + +/ { + model = "Marvell RD-AC5X Board"; + compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5"; + + aliases { + serial0 = &uart0; + spiflash0 = &spiflash0; + gpio0 = &gpio0; + gpio1 = &gpio1; + ethernet0 = ð0; + ethernet1 = ð1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x2 0x00000000 0x0 0x40000000>; + }; + + usb1phy: usb-phy { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +ð0 { + status = "okay"; + phy-handle = <&phy0>; +}; + +/* USB0 is a host USB */ +&usb0 { + status = "okay"; +}; + +/* USB1 is a peripheral USB */ +&usb1 { + status = "okay"; + phys = <&usb1phy>; + phy-names = "usb-phy"; + dr_mode = "peripheral"; +}; + +&spi0 { + status = "okay"; + + spiflash0: flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ + spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ + reg = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "spi_flash_part0"; + reg = <0x0 0x800000>; + }; + + parition@1 { + label = "spi_flash_part1"; + reg = <0x800000 0x700000>; + }; + + parition@2 { + label = "spi_flash_part2"; + reg = <0xF00000 0x100000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi b/arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi new file mode 100644 index 000000000000..62d2650513aa --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For AC5X. + * + * Copyright (C) 2022 Allied Telesis Labs + */ + +#include "armada-98dx25xx.dtsi" + +/ { + model = "Marvell AC5X SoC"; + compatible = "marvell,ac5x", "marvell,ac5"; +}; -- 2.36.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board @ 2022-05-12 4:25 ` Chris Packham 0 siblings, 0 replies; 26+ messages in thread From: Chris Packham @ 2022-05-12 4:25 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan Cc: devicetree, linux-kernel, linux-arm-kernel, Chris Packham The 98DX2530 SoC is the Control and Management CPU integrated into the Marvell 98DX25xx and 98DX35xx series of switch chip (internally referred to as AlleyCat5 and AlleyCat5X). These files have been taken from the Marvell SDK and lightly cleaned up with the License and copyright retained. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> --- Notes: The Marvell SDK has a number of new compatible strings. I've brought through some of the drivers or where possible used an in-tree alternative (e.g. there is SDK code for a ac5-gpio but two instances of the existing marvell,orion-gpio seems to cover what is needed if you use an appropriate binding). I expect that there will a new series of patches when I get some different hardware (or additions to this series depending on if/when it lands). Changes in v7: - Add missing compatible on usb1 - Add "rd-ac5x" compatible for board - Move aliases to board dts - Move board specific usb info to board dts - Consolidate usb1 board settings and remove unnecessary compatible - Add Allied Telesis copyright - Rename files after mailng-list discussion Changes in v6: - Move CPU nodes above the SoC (Krzysztof) - Minor formatting clean ups (Krzysztof) - Run through `make dtbs_check` - Move gic nodes inside SoC - Group clocks under a clock node Changes in v5: - add #{address,size}-cells property to i2c nodes - make i2c nodes disabled in the SoC and enable them in the board - add interrupt controller attributes to gpio nodes - Move fixed-clock nodes up a level and remove unnecessary @0 Changes in v4: - use 'phy-handle' instead of 'phy' - move status="okay" on usb nodes to board dts - Add review from Andrew Changes in v3: - Move memory node to board - Use single digit reg value for phy address - Remove MMC node (driver needs work) - Remove syscon & simple-mfd for pinctrl Changes in v2: - Make pinctrl a child node of a syscon node - Use marvell,armada-8k-gpio instead of orion-gpio - Remove nand peripheral. The Marvell SDK does have some changes for the ac5-nand-controller but I currently lack hardware with NAND fitted so I can't test it right now. I've therefore chosen to omit the node and not attempted to bring in the driver or binding. - Remove pcie peripheral. Again there are changes in the SDK and I have no way of testing them. - Remove prestera node. - Remove "marvell,ac5-ehci" compatible from USB node as "marvell,orion-ehci" is sufficient - Remove watchdog node. There is a buggy driver for the ac5 watchdog in the SDK but it needs some work so I've dropped the node for now. arch/arm64/boot/dts/marvell/Makefile | 1 + .../boot/dts/marvell/armada-98dx25xx.dtsi | 295 ++++++++++++++++++ .../boot/dts/marvell/armada-98dx35xx-rd.dts | 101 ++++++ .../boot/dts/marvell/armada-98dx35xx.dtsi | 13 + 4 files changed, 410 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 1c794cdcb8e6..b7a4c715afbb 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb +dtb-$(CONFIG_ARCH_MVEBU) += armada-98dx35xx-rd.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi new file mode 100644 index 000000000000..55ab4cd843a9 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For AC5. + * + * Copyright (C) 2021 Marvell + * Copyright (C) 2022 Allied Telesis Labs + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Marvell AC5 SoC"; + compatible = "marvell,ac5"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + }; + }; + + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <25000000>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + internal-regs@7f000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + /* 16M internal register @ 0x7f00_0000 */ + ranges = <0x0 0x0 0x7f000000 0x1000000>; + dma-coherent; + + uart0: serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clock-frequency = <328000000>; + status = "okay"; + }; + + mdio: mdio@22004 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x22004 0x4>; + clocks = <&core_clock>; + }; + + i2c0: i2c@11000{ + compatible = "marvell,mv78230-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&core_clock>; + clock-names = "core"; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency=<100000>; + + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c0_pins>; + pinctrl-1 = <&i2c0_gpio>; + scl_gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; + sda_gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + i2c1: i2c@11100{ + compatible = "marvell,mv78230-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&core_clock>; + clock-names = "core"; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency=<100000>; + + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c1_pins>; + pinctrl-1 = <&i2c1_gpio>; + scl_gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; + sda_gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl0 0 0 32>; + marvell,pwm-offset = <0x1f0>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@18140 { + reg = <0x18140 0x40>; + compatible = "marvell,orion-gpio"; + ngpios = <14>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl0 0 32 14>; + marvell,pwm-offset = <0x1f0>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + /* + * Dedicated section for devices behind 32bit controllers so we + * can configure specific DMA mapping for them + */ + behind-32bit-controller@7f000000 { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>; + /* Host phy ram starts at 0x200M */ + dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>; + dma-coherent; + + eth0: ethernet@20000 { + compatible = "marvell,armada-ac5-neta"; + reg = <0x0 0x20000 0x0 0x4000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&core_clock>; + phy-mode = "sgmii"; + status = "disabled"; + }; + + eth1: ethernet@24000 { + compatible = "marvell,armada-ac5-neta"; + reg = <0x0 0x24000 0x0 0x4000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&core_clock>; + phy-mode = "sgmii"; + status = "disabled"; + }; + + usb0: usb@80000 { + compatible = "marvell,orion-ehci"; + reg = <0x0 0x80000 0x0 0x500>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + usb1: usb@a0000 { + compatible = "marvell,orion-ehci"; + reg = <0x0 0xa0000 0x0 0x500>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + + pinctrl0: pinctrl@80020100 { + compatible = "marvell,ac5-pinctrl"; + reg = <0 0x80020100 0 0x20>; + + i2c0_pins: i2c0-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c0"; + }; + + i2c0_gpio: i2c0-gpio-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "gpio"; + }; + + i2c1_pins: i2c1-pins { + marvell,pins = "mpp20", "mpp21"; + marvell,function = "i2c1"; + }; + + i2c1_gpio: i2c1-gpio-pins { + marvell,pins = "mpp20", "mpp21"; + marvell,function = "i2c1"; + }; + }; + + spi0: spi@805a0000 { + compatible = "marvell,armada-3700-spi"; + reg = <0x0 0x805a0000 0x0 0x50>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <&spi_clock>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <1>; + status = "disabled"; + }; + + spi1: spi@805a8000 { + compatible = "marvell,armada-3700-spi"; + reg = <0x0 0x805a8000 0x0 0x50>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <&spi_clock>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <1>; + status = "disabled"; + }; + + gic: interrupt-controller@80600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + /*#redistributor-regions = <1>;*/ + redistributor-stride = <0x0 0x20000>; // 128kB stride + reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ + <0x0 0x80660000 0x0 0x40000>; /* GICR */ + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + clocks { + core_clock: core-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + + axi_clock: axi-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <325000000>; + }; + + spi_clock: spi-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts b/arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts new file mode 100644 index 000000000000..c20e032410fa --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For RD-AC5X. + * + * Copyright (C) 2021 Marvell + * Copyright (C) 2022 Allied Telesis Labs + */ +/* + * Device Tree file for Marvell Alleycat 5X development board + * This board file supports the B configuration of the board + */ + +/dts-v1/; + +#include "armada-98dx35xx.dtsi" + +/ { + model = "Marvell RD-AC5X Board"; + compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5"; + + aliases { + serial0 = &uart0; + spiflash0 = &spiflash0; + gpio0 = &gpio0; + gpio1 = &gpio1; + ethernet0 = ð0; + ethernet1 = ð1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x2 0x00000000 0x0 0x40000000>; + }; + + usb1phy: usb-phy { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +ð0 { + status = "okay"; + phy-handle = <&phy0>; +}; + +/* USB0 is a host USB */ +&usb0 { + status = "okay"; +}; + +/* USB1 is a peripheral USB */ +&usb1 { + status = "okay"; + phys = <&usb1phy>; + phy-names = "usb-phy"; + dr_mode = "peripheral"; +}; + +&spi0 { + status = "okay"; + + spiflash0: flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ + spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ + reg = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "spi_flash_part0"; + reg = <0x0 0x800000>; + }; + + parition@1 { + label = "spi_flash_part1"; + reg = <0x800000 0x700000>; + }; + + parition@2 { + label = "spi_flash_part2"; + reg = <0xF00000 0x100000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi b/arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi new file mode 100644 index 000000000000..62d2650513aa --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For AC5X. + * + * Copyright (C) 2022 Allied Telesis Labs + */ + +#include "armada-98dx25xx.dtsi" + +/ { + model = "Marvell AC5X SoC"; + compatible = "marvell,ac5x", "marvell,ac5"; +}; -- 2.36.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board 2022-05-12 4:25 ` Chris Packham @ 2022-05-12 7:38 ` Marc Zyngier -1 siblings, 0 replies; 26+ messages in thread From: Marc Zyngier @ 2022-05-12 7:38 UTC (permalink / raw) To: Chris Packham Cc: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan, devicetree, linux-kernel, linux-arm-kernel On Thu, 12 May 2022 05:25:00 +0100, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: > > The 98DX2530 SoC is the Control and Management CPU integrated into > the Marvell 98DX25xx and 98DX35xx series of switch chip (internally > referred to as AlleyCat5 and AlleyCat5X). > > These files have been taken from the Marvell SDK and lightly cleaned > up with the License and copyright retained. > > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > Reviewed-by: Andrew Lunn <andrew@lunn.ch> > --- > > Notes: > The Marvell SDK has a number of new compatible strings. I've brought > through some of the drivers or where possible used an in-tree > alternative (e.g. there is SDK code for a ac5-gpio but two instances of > the existing marvell,orion-gpio seems to cover what is needed if you use > an appropriate binding). I expect that there will a new series of > patches when I get some different hardware (or additions to this series > depending on if/when it lands). > > Changes in v7: > - Add missing compatible on usb1 > - Add "rd-ac5x" compatible for board > - Move aliases to board dts > - Move board specific usb info to board dts > - Consolidate usb1 board settings and remove unnecessary compatible > - Add Allied Telesis copyright > - Rename files after mailng-list discussion > Changes in v6: > - Move CPU nodes above the SoC (Krzysztof) > - Minor formatting clean ups (Krzysztof) > - Run through `make dtbs_check` > - Move gic nodes inside SoC > - Group clocks under a clock node > Changes in v5: > - add #{address,size}-cells property to i2c nodes > - make i2c nodes disabled in the SoC and enable them in the board > - add interrupt controller attributes to gpio nodes > - Move fixed-clock nodes up a level and remove unnecessary @0 > Changes in v4: > - use 'phy-handle' instead of 'phy' > - move status="okay" on usb nodes to board dts > - Add review from Andrew > Changes in v3: > - Move memory node to board > - Use single digit reg value for phy address > - Remove MMC node (driver needs work) > - Remove syscon & simple-mfd for pinctrl > Changes in v2: > - Make pinctrl a child node of a syscon node > - Use marvell,armada-8k-gpio instead of orion-gpio > - Remove nand peripheral. The Marvell SDK does have some changes for the > ac5-nand-controller but I currently lack hardware with NAND fitted so > I can't test it right now. I've therefore chosen to omit the node and > not attempted to bring in the driver or binding. > - Remove pcie peripheral. Again there are changes in the SDK and I have > no way of testing them. > - Remove prestera node. > - Remove "marvell,ac5-ehci" compatible from USB node as > "marvell,orion-ehci" is sufficient > - Remove watchdog node. There is a buggy driver for the ac5 watchdog in > the SDK but it needs some work so I've dropped the node for now. > > arch/arm64/boot/dts/marvell/Makefile | 1 + > .../boot/dts/marvell/armada-98dx25xx.dtsi | 295 ++++++++++++++++++ > .../boot/dts/marvell/armada-98dx35xx-rd.dts | 101 ++++++ > .../boot/dts/marvell/armada-98dx35xx.dtsi | 13 + > 4 files changed, 410 insertions(+) > create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts > create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi > > diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile > index 1c794cdcb8e6..b7a4c715afbb 100644 > --- a/arch/arm64/boot/dts/marvell/Makefile > +++ b/arch/arm64/boot/dts/marvell/Makefile > @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb > dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb > dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb > dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb > +dtb-$(CONFIG_ARCH_MVEBU) += armada-98dx35xx-rd.dtb > diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > new file mode 100644 > index 000000000000..55ab4cd843a9 > --- /dev/null > +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > @@ -0,0 +1,295 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Device Tree For AC5. > + * > + * Copyright (C) 2021 Marvell > + * Copyright (C) 2022 Allied Telesis Labs > + */ > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + model = "Marvell AC5 SoC"; > + compatible = "marvell,ac5"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + next-level-cache = <&l2>; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + next-level-cache = <&l2>; > + }; > + > + l2: l2-cache { > + compatible = "cache"; > + }; > + }; > + > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > + clock-frequency = <25000000>; I said no to this hack in a past version of this patch, and I'm going to say it *again*. Please fix your firmware to program CNTFRQ_EL0, and remove this useless property. You are also missing a PPI for the EL2 virtual timer which is present on any ARMv8.1+ CPU (and since this system is using A55, it definitely has it). [...] > + > + gic: interrupt-controller@80600000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + interrupt-controller; > + /*#redistributor-regions = <1>;*/ > + redistributor-stride = <0x0 0x20000>; // 128kB stride You don't need this at all. This is the architected value for GICv3. > + reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ > + <0x0 0x80660000 0x0 0x40000>; /* GICR */ > + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; Thanks, M. -- Without deviation from the norm, progress is not possible. ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board @ 2022-05-12 7:38 ` Marc Zyngier 0 siblings, 0 replies; 26+ messages in thread From: Marc Zyngier @ 2022-05-12 7:38 UTC (permalink / raw) To: Chris Packham Cc: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan, devicetree, linux-kernel, linux-arm-kernel On Thu, 12 May 2022 05:25:00 +0100, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: > > The 98DX2530 SoC is the Control and Management CPU integrated into > the Marvell 98DX25xx and 98DX35xx series of switch chip (internally > referred to as AlleyCat5 and AlleyCat5X). > > These files have been taken from the Marvell SDK and lightly cleaned > up with the License and copyright retained. > > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > Reviewed-by: Andrew Lunn <andrew@lunn.ch> > --- > > Notes: > The Marvell SDK has a number of new compatible strings. I've brought > through some of the drivers or where possible used an in-tree > alternative (e.g. there is SDK code for a ac5-gpio but two instances of > the existing marvell,orion-gpio seems to cover what is needed if you use > an appropriate binding). I expect that there will a new series of > patches when I get some different hardware (or additions to this series > depending on if/when it lands). > > Changes in v7: > - Add missing compatible on usb1 > - Add "rd-ac5x" compatible for board > - Move aliases to board dts > - Move board specific usb info to board dts > - Consolidate usb1 board settings and remove unnecessary compatible > - Add Allied Telesis copyright > - Rename files after mailng-list discussion > Changes in v6: > - Move CPU nodes above the SoC (Krzysztof) > - Minor formatting clean ups (Krzysztof) > - Run through `make dtbs_check` > - Move gic nodes inside SoC > - Group clocks under a clock node > Changes in v5: > - add #{address,size}-cells property to i2c nodes > - make i2c nodes disabled in the SoC and enable them in the board > - add interrupt controller attributes to gpio nodes > - Move fixed-clock nodes up a level and remove unnecessary @0 > Changes in v4: > - use 'phy-handle' instead of 'phy' > - move status="okay" on usb nodes to board dts > - Add review from Andrew > Changes in v3: > - Move memory node to board > - Use single digit reg value for phy address > - Remove MMC node (driver needs work) > - Remove syscon & simple-mfd for pinctrl > Changes in v2: > - Make pinctrl a child node of a syscon node > - Use marvell,armada-8k-gpio instead of orion-gpio > - Remove nand peripheral. The Marvell SDK does have some changes for the > ac5-nand-controller but I currently lack hardware with NAND fitted so > I can't test it right now. I've therefore chosen to omit the node and > not attempted to bring in the driver or binding. > - Remove pcie peripheral. Again there are changes in the SDK and I have > no way of testing them. > - Remove prestera node. > - Remove "marvell,ac5-ehci" compatible from USB node as > "marvell,orion-ehci" is sufficient > - Remove watchdog node. There is a buggy driver for the ac5 watchdog in > the SDK but it needs some work so I've dropped the node for now. > > arch/arm64/boot/dts/marvell/Makefile | 1 + > .../boot/dts/marvell/armada-98dx25xx.dtsi | 295 ++++++++++++++++++ > .../boot/dts/marvell/armada-98dx35xx-rd.dts | 101 ++++++ > .../boot/dts/marvell/armada-98dx35xx.dtsi | 13 + > 4 files changed, 410 insertions(+) > create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts > create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi > > diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile > index 1c794cdcb8e6..b7a4c715afbb 100644 > --- a/arch/arm64/boot/dts/marvell/Makefile > +++ b/arch/arm64/boot/dts/marvell/Makefile > @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb > dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb > dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb > dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb > +dtb-$(CONFIG_ARCH_MVEBU) += armada-98dx35xx-rd.dtb > diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > new file mode 100644 > index 000000000000..55ab4cd843a9 > --- /dev/null > +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > @@ -0,0 +1,295 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Device Tree For AC5. > + * > + * Copyright (C) 2021 Marvell > + * Copyright (C) 2022 Allied Telesis Labs > + */ > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + model = "Marvell AC5 SoC"; > + compatible = "marvell,ac5"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + next-level-cache = <&l2>; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + next-level-cache = <&l2>; > + }; > + > + l2: l2-cache { > + compatible = "cache"; > + }; > + }; > + > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > + clock-frequency = <25000000>; I said no to this hack in a past version of this patch, and I'm going to say it *again*. Please fix your firmware to program CNTFRQ_EL0, and remove this useless property. You are also missing a PPI for the EL2 virtual timer which is present on any ARMv8.1+ CPU (and since this system is using A55, it definitely has it). [...] > + > + gic: interrupt-controller@80600000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + interrupt-controller; > + /*#redistributor-regions = <1>;*/ > + redistributor-stride = <0x0 0x20000>; // 128kB stride You don't need this at all. This is the architected value for GICv3. > + reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ > + <0x0 0x80660000 0x0 0x40000>; /* GICR */ > + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board 2022-05-12 7:38 ` Marc Zyngier @ 2022-05-12 22:10 ` Chris Packham -1 siblings, 0 replies; 26+ messages in thread From: Chris Packham @ 2022-05-12 22:10 UTC (permalink / raw) To: Marc Zyngier Cc: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan, devicetree, linux-kernel, linux-arm-kernel Hi Marc, On 12/05/22 19:38, Marc Zyngier wrote: > On Thu, 12 May 2022 05:25:00 +0100, > Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: >> The 98DX2530 SoC is the Control and Management CPU integrated into >> the Marvell 98DX25xx and 98DX35xx series of switch chip (internally >> referred to as AlleyCat5 and AlleyCat5X). >> >> These files have been taken from the Marvell SDK and lightly cleaned >> up with the License and copyright retained. >> >> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> >> Reviewed-by: Andrew Lunn <andrew@lunn.ch> >> --- >> >> Notes: >> The Marvell SDK has a number of new compatible strings. I've brought >> through some of the drivers or where possible used an in-tree >> alternative (e.g. there is SDK code for a ac5-gpio but two instances of >> the existing marvell,orion-gpio seems to cover what is needed if you use >> an appropriate binding). I expect that there will a new series of >> patches when I get some different hardware (or additions to this series >> depending on if/when it lands). >> >> Changes in v7: >> - Add missing compatible on usb1 >> - Add "rd-ac5x" compatible for board >> - Move aliases to board dts >> - Move board specific usb info to board dts >> - Consolidate usb1 board settings and remove unnecessary compatible >> - Add Allied Telesis copyright >> - Rename files after mailng-list discussion >> Changes in v6: >> - Move CPU nodes above the SoC (Krzysztof) >> - Minor formatting clean ups (Krzysztof) >> - Run through `make dtbs_check` >> - Move gic nodes inside SoC >> - Group clocks under a clock node >> Changes in v5: >> - add #{address,size}-cells property to i2c nodes >> - make i2c nodes disabled in the SoC and enable them in the board >> - add interrupt controller attributes to gpio nodes >> - Move fixed-clock nodes up a level and remove unnecessary @0 >> Changes in v4: >> - use 'phy-handle' instead of 'phy' >> - move status="okay" on usb nodes to board dts >> - Add review from Andrew >> Changes in v3: >> - Move memory node to board >> - Use single digit reg value for phy address >> - Remove MMC node (driver needs work) >> - Remove syscon & simple-mfd for pinctrl >> Changes in v2: >> - Make pinctrl a child node of a syscon node >> - Use marvell,armada-8k-gpio instead of orion-gpio >> - Remove nand peripheral. The Marvell SDK does have some changes for the >> ac5-nand-controller but I currently lack hardware with NAND fitted so >> I can't test it right now. I've therefore chosen to omit the node and >> not attempted to bring in the driver or binding. >> - Remove pcie peripheral. Again there are changes in the SDK and I have >> no way of testing them. >> - Remove prestera node. >> - Remove "marvell,ac5-ehci" compatible from USB node as >> "marvell,orion-ehci" is sufficient >> - Remove watchdog node. There is a buggy driver for the ac5 watchdog in >> the SDK but it needs some work so I've dropped the node for now. >> >> arch/arm64/boot/dts/marvell/Makefile | 1 + >> .../boot/dts/marvell/armada-98dx25xx.dtsi | 295 ++++++++++++++++++ >> .../boot/dts/marvell/armada-98dx35xx-rd.dts | 101 ++++++ >> .../boot/dts/marvell/armada-98dx35xx.dtsi | 13 + >> 4 files changed, 410 insertions(+) >> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts >> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi >> >> diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile >> index 1c794cdcb8e6..b7a4c715afbb 100644 >> --- a/arch/arm64/boot/dts/marvell/Makefile >> +++ b/arch/arm64/boot/dts/marvell/Makefile >> @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb >> dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb >> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb >> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb >> +dtb-$(CONFIG_ARCH_MVEBU) += armada-98dx35xx-rd.dtb >> diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >> new file mode 100644 >> index 000000000000..55ab4cd843a9 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >> @@ -0,0 +1,295 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Device Tree For AC5. >> + * >> + * Copyright (C) 2021 Marvell >> + * Copyright (C) 2022 Allied Telesis Labs >> + */ >> + >> +#include <dt-bindings/gpio/gpio.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> +/ { >> + model = "Marvell AC5 SoC"; >> + compatible = "marvell,ac5"; >> + interrupt-parent = <&gic>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + cpus { >> + #address-cells = <2>; >> + #size-cells = <0>; >> + >> + cpu-map { >> + cluster0 { >> + core0 { >> + cpu = <&cpu0>; >> + }; >> + core1 { >> + cpu = <&cpu1>; >> + }; >> + }; >> + }; >> + >> + cpu0: cpu@0 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x0 0x0>; >> + enable-method = "psci"; >> + next-level-cache = <&l2>; >> + }; >> + >> + cpu1: cpu@1 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x0 0x100>; >> + enable-method = "psci"; >> + next-level-cache = <&l2>; >> + }; >> + >> + l2: l2-cache { >> + compatible = "cache"; >> + }; >> + }; >> + >> + >> + psci { >> + compatible = "arm,psci-0.2"; >> + method = "smc"; >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; >> + clock-frequency = <25000000>; > I said no to this hack in a past version of this patch, and I'm going > to say it *again*. Sorry I must have missed it. > Please fix your firmware to program CNTFRQ_EL0, and > remove this useless property. I'm kind of at the mercy of what Marvell have provided for ATF. I am working on the bootloader portion in parallel and am getting things ready for submitting the u-boot support upstream. I was hoping to leave ATF alone I can at least see if they haven't fixed this already (the original dtsi I started with was fairly old) and if they haven't I'll raise it via their support system. > You are also missing a PPI for the EL2 virtual timer which is present > on any ARMv8.1+ CPU (and since this system is using A55, it definitely > has it). > > [...] Will add. >> + >> + gic: interrupt-controller@80600000 { >> + compatible = "arm,gic-v3"; >> + #interrupt-cells = <3>; >> + interrupt-controller; >> + /*#redistributor-regions = <1>;*/ >> + redistributor-stride = <0x0 0x20000>; // 128kB stride > You don't need this at all. This is the architected value for GICv3. Will remove. > >> + reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ >> + <0x0 0x80660000 0x0 0x40000>; /* GICR */ >> + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + }; > Thanks, > > M. > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board @ 2022-05-12 22:10 ` Chris Packham 0 siblings, 0 replies; 26+ messages in thread From: Chris Packham @ 2022-05-12 22:10 UTC (permalink / raw) To: Marc Zyngier Cc: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan, devicetree, linux-kernel, linux-arm-kernel Hi Marc, On 12/05/22 19:38, Marc Zyngier wrote: > On Thu, 12 May 2022 05:25:00 +0100, > Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: >> The 98DX2530 SoC is the Control and Management CPU integrated into >> the Marvell 98DX25xx and 98DX35xx series of switch chip (internally >> referred to as AlleyCat5 and AlleyCat5X). >> >> These files have been taken from the Marvell SDK and lightly cleaned >> up with the License and copyright retained. >> >> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> >> Reviewed-by: Andrew Lunn <andrew@lunn.ch> >> --- >> >> Notes: >> The Marvell SDK has a number of new compatible strings. I've brought >> through some of the drivers or where possible used an in-tree >> alternative (e.g. there is SDK code for a ac5-gpio but two instances of >> the existing marvell,orion-gpio seems to cover what is needed if you use >> an appropriate binding). I expect that there will a new series of >> patches when I get some different hardware (or additions to this series >> depending on if/when it lands). >> >> Changes in v7: >> - Add missing compatible on usb1 >> - Add "rd-ac5x" compatible for board >> - Move aliases to board dts >> - Move board specific usb info to board dts >> - Consolidate usb1 board settings and remove unnecessary compatible >> - Add Allied Telesis copyright >> - Rename files after mailng-list discussion >> Changes in v6: >> - Move CPU nodes above the SoC (Krzysztof) >> - Minor formatting clean ups (Krzysztof) >> - Run through `make dtbs_check` >> - Move gic nodes inside SoC >> - Group clocks under a clock node >> Changes in v5: >> - add #{address,size}-cells property to i2c nodes >> - make i2c nodes disabled in the SoC and enable them in the board >> - add interrupt controller attributes to gpio nodes >> - Move fixed-clock nodes up a level and remove unnecessary @0 >> Changes in v4: >> - use 'phy-handle' instead of 'phy' >> - move status="okay" on usb nodes to board dts >> - Add review from Andrew >> Changes in v3: >> - Move memory node to board >> - Use single digit reg value for phy address >> - Remove MMC node (driver needs work) >> - Remove syscon & simple-mfd for pinctrl >> Changes in v2: >> - Make pinctrl a child node of a syscon node >> - Use marvell,armada-8k-gpio instead of orion-gpio >> - Remove nand peripheral. The Marvell SDK does have some changes for the >> ac5-nand-controller but I currently lack hardware with NAND fitted so >> I can't test it right now. I've therefore chosen to omit the node and >> not attempted to bring in the driver or binding. >> - Remove pcie peripheral. Again there are changes in the SDK and I have >> no way of testing them. >> - Remove prestera node. >> - Remove "marvell,ac5-ehci" compatible from USB node as >> "marvell,orion-ehci" is sufficient >> - Remove watchdog node. There is a buggy driver for the ac5 watchdog in >> the SDK but it needs some work so I've dropped the node for now. >> >> arch/arm64/boot/dts/marvell/Makefile | 1 + >> .../boot/dts/marvell/armada-98dx25xx.dtsi | 295 ++++++++++++++++++ >> .../boot/dts/marvell/armada-98dx35xx-rd.dts | 101 ++++++ >> .../boot/dts/marvell/armada-98dx35xx.dtsi | 13 + >> 4 files changed, 410 insertions(+) >> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts >> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi >> >> diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile >> index 1c794cdcb8e6..b7a4c715afbb 100644 >> --- a/arch/arm64/boot/dts/marvell/Makefile >> +++ b/arch/arm64/boot/dts/marvell/Makefile >> @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb >> dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb >> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb >> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb >> +dtb-$(CONFIG_ARCH_MVEBU) += armada-98dx35xx-rd.dtb >> diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >> new file mode 100644 >> index 000000000000..55ab4cd843a9 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >> @@ -0,0 +1,295 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Device Tree For AC5. >> + * >> + * Copyright (C) 2021 Marvell >> + * Copyright (C) 2022 Allied Telesis Labs >> + */ >> + >> +#include <dt-bindings/gpio/gpio.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> +/ { >> + model = "Marvell AC5 SoC"; >> + compatible = "marvell,ac5"; >> + interrupt-parent = <&gic>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + cpus { >> + #address-cells = <2>; >> + #size-cells = <0>; >> + >> + cpu-map { >> + cluster0 { >> + core0 { >> + cpu = <&cpu0>; >> + }; >> + core1 { >> + cpu = <&cpu1>; >> + }; >> + }; >> + }; >> + >> + cpu0: cpu@0 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x0 0x0>; >> + enable-method = "psci"; >> + next-level-cache = <&l2>; >> + }; >> + >> + cpu1: cpu@1 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x0 0x100>; >> + enable-method = "psci"; >> + next-level-cache = <&l2>; >> + }; >> + >> + l2: l2-cache { >> + compatible = "cache"; >> + }; >> + }; >> + >> + >> + psci { >> + compatible = "arm,psci-0.2"; >> + method = "smc"; >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; >> + clock-frequency = <25000000>; > I said no to this hack in a past version of this patch, and I'm going > to say it *again*. Sorry I must have missed it. > Please fix your firmware to program CNTFRQ_EL0, and > remove this useless property. I'm kind of at the mercy of what Marvell have provided for ATF. I am working on the bootloader portion in parallel and am getting things ready for submitting the u-boot support upstream. I was hoping to leave ATF alone I can at least see if they haven't fixed this already (the original dtsi I started with was fairly old) and if they haven't I'll raise it via their support system. > You are also missing a PPI for the EL2 virtual timer which is present > on any ARMv8.1+ CPU (and since this system is using A55, it definitely > has it). > > [...] Will add. >> + >> + gic: interrupt-controller@80600000 { >> + compatible = "arm,gic-v3"; >> + #interrupt-cells = <3>; >> + interrupt-controller; >> + /*#redistributor-regions = <1>;*/ >> + redistributor-stride = <0x0 0x20000>; // 128kB stride > You don't need this at all. This is the architected value for GICv3. Will remove. > >> + reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ >> + <0x0 0x80660000 0x0 0x40000>; /* GICR */ >> + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + }; > Thanks, > > M. > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board 2022-05-12 22:10 ` Chris Packham @ 2022-05-13 1:26 ` Chris Packham -1 siblings, 0 replies; 26+ messages in thread From: Chris Packham @ 2022-05-13 1:26 UTC (permalink / raw) To: Marc Zyngier Cc: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan, devicetree, linux-kernel, linux-arm-kernel Hi Marc, On 13/05/22 10:10, Chris Packham wrote: > Hi Marc, > > On 12/05/22 19:38, Marc Zyngier wrote: >> On Thu, 12 May 2022 05:25:00 +0100, >> Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: >>> The 98DX2530 SoC is the Control and Management CPU integrated into >>> the Marvell 98DX25xx and 98DX35xx series of switch chip (internally >>> referred to as AlleyCat5 and AlleyCat5X). >>> >>> These files have been taken from the Marvell SDK and lightly cleaned >>> up with the License and copyright retained. >>> >>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> >>> Reviewed-by: Andrew Lunn <andrew@lunn.ch> >>> --- >>> >>> Notes: >>> The Marvell SDK has a number of new compatible strings. I've >>> brought >>> through some of the drivers or where possible used an in-tree >>> alternative (e.g. there is SDK code for a ac5-gpio but two >>> instances of >>> the existing marvell,orion-gpio seems to cover what is needed >>> if you use >>> an appropriate binding). I expect that there will a new series of >>> patches when I get some different hardware (or additions to >>> this series >>> depending on if/when it lands). >>> Changes in v7: >>> - Add missing compatible on usb1 >>> - Add "rd-ac5x" compatible for board >>> - Move aliases to board dts >>> - Move board specific usb info to board dts >>> - Consolidate usb1 board settings and remove unnecessary >>> compatible >>> - Add Allied Telesis copyright >>> - Rename files after mailng-list discussion >>> Changes in v6: >>> - Move CPU nodes above the SoC (Krzysztof) >>> - Minor formatting clean ups (Krzysztof) >>> - Run through `make dtbs_check` >>> - Move gic nodes inside SoC >>> - Group clocks under a clock node >>> Changes in v5: >>> - add #{address,size}-cells property to i2c nodes >>> - make i2c nodes disabled in the SoC and enable them in the board >>> - add interrupt controller attributes to gpio nodes >>> - Move fixed-clock nodes up a level and remove unnecessary @0 >>> Changes in v4: >>> - use 'phy-handle' instead of 'phy' >>> - move status="okay" on usb nodes to board dts >>> - Add review from Andrew >>> Changes in v3: >>> - Move memory node to board >>> - Use single digit reg value for phy address >>> - Remove MMC node (driver needs work) >>> - Remove syscon & simple-mfd for pinctrl >>> Changes in v2: >>> - Make pinctrl a child node of a syscon node >>> - Use marvell,armada-8k-gpio instead of orion-gpio >>> - Remove nand peripheral. The Marvell SDK does have some >>> changes for the >>> ac5-nand-controller but I currently lack hardware with NAND >>> fitted so >>> I can't test it right now. I've therefore chosen to omit the >>> node and >>> not attempted to bring in the driver or binding. >>> - Remove pcie peripheral. Again there are changes in the SDK >>> and I have >>> no way of testing them. >>> - Remove prestera node. >>> - Remove "marvell,ac5-ehci" compatible from USB node as >>> "marvell,orion-ehci" is sufficient >>> - Remove watchdog node. There is a buggy driver for the ac5 >>> watchdog in >>> the SDK but it needs some work so I've dropped the node for now. >>> >>> arch/arm64/boot/dts/marvell/Makefile | 1 + >>> .../boot/dts/marvell/armada-98dx25xx.dtsi | 295 >>> ++++++++++++++++++ >>> .../boot/dts/marvell/armada-98dx35xx-rd.dts | 101 ++++++ >>> .../boot/dts/marvell/armada-98dx35xx.dtsi | 13 + >>> 4 files changed, 410 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >>> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts >>> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi >>> >>> diff --git a/arch/arm64/boot/dts/marvell/Makefile >>> b/arch/arm64/boot/dts/marvell/Makefile >>> index 1c794cdcb8e6..b7a4c715afbb 100644 >>> --- a/arch/arm64/boot/dts/marvell/Makefile >>> +++ b/arch/arm64/boot/dts/marvell/Makefile >>> @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb >>> dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb >>> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb >>> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb >>> +dtb-$(CONFIG_ARCH_MVEBU) += armada-98dx35xx-rd.dtb >>> diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >>> b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >>> new file mode 100644 >>> index 000000000000..55ab4cd843a9 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >>> @@ -0,0 +1,295 @@ >>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >>> +/* >>> + * Device Tree For AC5. >>> + * >>> + * Copyright (C) 2021 Marvell >>> + * Copyright (C) 2022 Allied Telesis Labs >>> + */ >>> + >>> +#include <dt-bindings/gpio/gpio.h> >>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>> + >>> +/ { >>> + model = "Marvell AC5 SoC"; >>> + compatible = "marvell,ac5"; >>> + interrupt-parent = <&gic>; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + >>> + cpus { >>> + #address-cells = <2>; >>> + #size-cells = <0>; >>> + >>> + cpu-map { >>> + cluster0 { >>> + core0 { >>> + cpu = <&cpu0>; >>> + }; >>> + core1 { >>> + cpu = <&cpu1>; >>> + }; >>> + }; >>> + }; >>> + >>> + cpu0: cpu@0 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x0 0x0>; >>> + enable-method = "psci"; >>> + next-level-cache = <&l2>; >>> + }; >>> + >>> + cpu1: cpu@1 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x0 0x100>; >>> + enable-method = "psci"; >>> + next-level-cache = <&l2>; >>> + }; >>> + >>> + l2: l2-cache { >>> + compatible = "cache"; >>> + }; >>> + }; >>> + >>> + >>> + psci { >>> + compatible = "arm,psci-0.2"; >>> + method = "smc"; >>> + }; >>> + >>> + timer { >>> + compatible = "arm,armv8-timer"; >>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; >>> + clock-frequency = <25000000>; >> I said no to this hack in a past version of this patch, and I'm going >> to say it *again*. > Sorry I must have missed it. >> Please fix your firmware to program CNTFRQ_EL0, and >> remove this useless property. > I'm kind of at the mercy of what Marvell have provided for ATF. I am > working on the bootloader portion in parallel and am getting things > ready for submitting the u-boot support upstream. I was hoping to > leave ATF alone I can at least see if they haven't fixed this already > (the original dtsi I started with was fairly old) and if they haven't > I'll raise it via their support system. Seems to work fine without the clock so I'll drop it. >> You are also missing a PPI for the EL2 virtual timer which is present >> on any ARMv8.1+ CPU (and since this system is using A55, it definitely >> has it). >> >> [...] > Will add. I assume you're talking about the 5th PPI per the timer/arm,arch_timer.yaml ("hypervisor virtual timer irq"). Helpfully Marvell don't include the PPI interrupt numbers in their datasheet. But then I also notice that none of the other boards that have a "arm,armv8-timer" provide a 5th interrupt either, have I misunderstood something? >>> + >>> + gic: interrupt-controller@80600000 { >>> + compatible = "arm,gic-v3"; >>> + #interrupt-cells = <3>; >>> + interrupt-controller; >>> + /*#redistributor-regions = <1>;*/ >>> + redistributor-stride = <0x0 0x20000>; // 128kB stride >> You don't need this at all. This is the architected value for GICv3. > Will remove. >> >>> + reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ >>> + <0x0 0x80660000 0x0 0x40000>; /* GICR */ >>> + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; >>> + }; >>> + }; >> Thanks, >> >> M. >> ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board @ 2022-05-13 1:26 ` Chris Packham 0 siblings, 0 replies; 26+ messages in thread From: Chris Packham @ 2022-05-13 1:26 UTC (permalink / raw) To: Marc Zyngier Cc: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan, devicetree, linux-kernel, linux-arm-kernel Hi Marc, On 13/05/22 10:10, Chris Packham wrote: > Hi Marc, > > On 12/05/22 19:38, Marc Zyngier wrote: >> On Thu, 12 May 2022 05:25:00 +0100, >> Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: >>> The 98DX2530 SoC is the Control and Management CPU integrated into >>> the Marvell 98DX25xx and 98DX35xx series of switch chip (internally >>> referred to as AlleyCat5 and AlleyCat5X). >>> >>> These files have been taken from the Marvell SDK and lightly cleaned >>> up with the License and copyright retained. >>> >>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> >>> Reviewed-by: Andrew Lunn <andrew@lunn.ch> >>> --- >>> >>> Notes: >>> The Marvell SDK has a number of new compatible strings. I've >>> brought >>> through some of the drivers or where possible used an in-tree >>> alternative (e.g. there is SDK code for a ac5-gpio but two >>> instances of >>> the existing marvell,orion-gpio seems to cover what is needed >>> if you use >>> an appropriate binding). I expect that there will a new series of >>> patches when I get some different hardware (or additions to >>> this series >>> depending on if/when it lands). >>> Changes in v7: >>> - Add missing compatible on usb1 >>> - Add "rd-ac5x" compatible for board >>> - Move aliases to board dts >>> - Move board specific usb info to board dts >>> - Consolidate usb1 board settings and remove unnecessary >>> compatible >>> - Add Allied Telesis copyright >>> - Rename files after mailng-list discussion >>> Changes in v6: >>> - Move CPU nodes above the SoC (Krzysztof) >>> - Minor formatting clean ups (Krzysztof) >>> - Run through `make dtbs_check` >>> - Move gic nodes inside SoC >>> - Group clocks under a clock node >>> Changes in v5: >>> - add #{address,size}-cells property to i2c nodes >>> - make i2c nodes disabled in the SoC and enable them in the board >>> - add interrupt controller attributes to gpio nodes >>> - Move fixed-clock nodes up a level and remove unnecessary @0 >>> Changes in v4: >>> - use 'phy-handle' instead of 'phy' >>> - move status="okay" on usb nodes to board dts >>> - Add review from Andrew >>> Changes in v3: >>> - Move memory node to board >>> - Use single digit reg value for phy address >>> - Remove MMC node (driver needs work) >>> - Remove syscon & simple-mfd for pinctrl >>> Changes in v2: >>> - Make pinctrl a child node of a syscon node >>> - Use marvell,armada-8k-gpio instead of orion-gpio >>> - Remove nand peripheral. The Marvell SDK does have some >>> changes for the >>> ac5-nand-controller but I currently lack hardware with NAND >>> fitted so >>> I can't test it right now. I've therefore chosen to omit the >>> node and >>> not attempted to bring in the driver or binding. >>> - Remove pcie peripheral. Again there are changes in the SDK >>> and I have >>> no way of testing them. >>> - Remove prestera node. >>> - Remove "marvell,ac5-ehci" compatible from USB node as >>> "marvell,orion-ehci" is sufficient >>> - Remove watchdog node. There is a buggy driver for the ac5 >>> watchdog in >>> the SDK but it needs some work so I've dropped the node for now. >>> >>> arch/arm64/boot/dts/marvell/Makefile | 1 + >>> .../boot/dts/marvell/armada-98dx25xx.dtsi | 295 >>> ++++++++++++++++++ >>> .../boot/dts/marvell/armada-98dx35xx-rd.dts | 101 ++++++ >>> .../boot/dts/marvell/armada-98dx35xx.dtsi | 13 + >>> 4 files changed, 410 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >>> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts >>> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi >>> >>> diff --git a/arch/arm64/boot/dts/marvell/Makefile >>> b/arch/arm64/boot/dts/marvell/Makefile >>> index 1c794cdcb8e6..b7a4c715afbb 100644 >>> --- a/arch/arm64/boot/dts/marvell/Makefile >>> +++ b/arch/arm64/boot/dts/marvell/Makefile >>> @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb >>> dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb >>> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb >>> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb >>> +dtb-$(CONFIG_ARCH_MVEBU) += armada-98dx35xx-rd.dtb >>> diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >>> b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >>> new file mode 100644 >>> index 000000000000..55ab4cd843a9 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >>> @@ -0,0 +1,295 @@ >>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >>> +/* >>> + * Device Tree For AC5. >>> + * >>> + * Copyright (C) 2021 Marvell >>> + * Copyright (C) 2022 Allied Telesis Labs >>> + */ >>> + >>> +#include <dt-bindings/gpio/gpio.h> >>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>> + >>> +/ { >>> + model = "Marvell AC5 SoC"; >>> + compatible = "marvell,ac5"; >>> + interrupt-parent = <&gic>; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + >>> + cpus { >>> + #address-cells = <2>; >>> + #size-cells = <0>; >>> + >>> + cpu-map { >>> + cluster0 { >>> + core0 { >>> + cpu = <&cpu0>; >>> + }; >>> + core1 { >>> + cpu = <&cpu1>; >>> + }; >>> + }; >>> + }; >>> + >>> + cpu0: cpu@0 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x0 0x0>; >>> + enable-method = "psci"; >>> + next-level-cache = <&l2>; >>> + }; >>> + >>> + cpu1: cpu@1 { >>> + device_type = "cpu"; >>> + compatible = "arm,armv8"; >>> + reg = <0x0 0x100>; >>> + enable-method = "psci"; >>> + next-level-cache = <&l2>; >>> + }; >>> + >>> + l2: l2-cache { >>> + compatible = "cache"; >>> + }; >>> + }; >>> + >>> + >>> + psci { >>> + compatible = "arm,psci-0.2"; >>> + method = "smc"; >>> + }; >>> + >>> + timer { >>> + compatible = "arm,armv8-timer"; >>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; >>> + clock-frequency = <25000000>; >> I said no to this hack in a past version of this patch, and I'm going >> to say it *again*. > Sorry I must have missed it. >> Please fix your firmware to program CNTFRQ_EL0, and >> remove this useless property. > I'm kind of at the mercy of what Marvell have provided for ATF. I am > working on the bootloader portion in parallel and am getting things > ready for submitting the u-boot support upstream. I was hoping to > leave ATF alone I can at least see if they haven't fixed this already > (the original dtsi I started with was fairly old) and if they haven't > I'll raise it via their support system. Seems to work fine without the clock so I'll drop it. >> You are also missing a PPI for the EL2 virtual timer which is present >> on any ARMv8.1+ CPU (and since this system is using A55, it definitely >> has it). >> >> [...] > Will add. I assume you're talking about the 5th PPI per the timer/arm,arch_timer.yaml ("hypervisor virtual timer irq"). Helpfully Marvell don't include the PPI interrupt numbers in their datasheet. But then I also notice that none of the other boards that have a "arm,armv8-timer" provide a 5th interrupt either, have I misunderstood something? >>> + >>> + gic: interrupt-controller@80600000 { >>> + compatible = "arm,gic-v3"; >>> + #interrupt-cells = <3>; >>> + interrupt-controller; >>> + /*#redistributor-regions = <1>;*/ >>> + redistributor-stride = <0x0 0x20000>; // 128kB stride >> You don't need this at all. This is the architected value for GICv3. > Will remove. >> >>> + reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ >>> + <0x0 0x80660000 0x0 0x40000>; /* GICR */ >>> + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; >>> + }; >>> + }; >> Thanks, >> >> M. >> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board 2022-05-13 1:26 ` Chris Packham @ 2022-05-16 9:48 ` Marc Zyngier -1 siblings, 0 replies; 26+ messages in thread From: Marc Zyngier @ 2022-05-16 9:48 UTC (permalink / raw) To: Chris Packham Cc: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan, devicetree, linux-kernel, linux-arm-kernel On Fri, 13 May 2022 02:26:21 +0100, Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote: > > Hi Marc, > > On 13/05/22 10:10, Chris Packham wrote: > > Hi Marc, > > > > On 12/05/22 19:38, Marc Zyngier wrote: > >> On Thu, 12 May 2022 05:25:00 +0100, > >> Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: > >>> The 98DX2530 SoC is the Control and Management CPU integrated into > >>> the Marvell 98DX25xx and 98DX35xx series of switch chip (internally > >>> referred to as AlleyCat5 and AlleyCat5X). > >>> > >>> These files have been taken from the Marvell SDK and lightly cleaned > >>> up with the License and copyright retained. > >>> > >>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > >>> Reviewed-by: Andrew Lunn <andrew@lunn.ch> > >>> --- > >>> > >>> Notes: > >>> The Marvell SDK has a number of new compatible strings. I've > >>> brought > >>> through some of the drivers or where possible used an in-tree > >>> alternative (e.g. there is SDK code for a ac5-gpio but two > >>> instances of > >>> the existing marvell,orion-gpio seems to cover what is needed > >>> if you use > >>> an appropriate binding). I expect that there will a new series of > >>> patches when I get some different hardware (or additions to > >>> this series > >>> depending on if/when it lands). > >>> Changes in v7: > >>> - Add missing compatible on usb1 > >>> - Add "rd-ac5x" compatible for board > >>> - Move aliases to board dts > >>> - Move board specific usb info to board dts > >>> - Consolidate usb1 board settings and remove unnecessary > >>> compatible > >>> - Add Allied Telesis copyright > >>> - Rename files after mailng-list discussion > >>> Changes in v6: > >>> - Move CPU nodes above the SoC (Krzysztof) > >>> - Minor formatting clean ups (Krzysztof) > >>> - Run through `make dtbs_check` > >>> - Move gic nodes inside SoC > >>> - Group clocks under a clock node > >>> Changes in v5: > >>> - add #{address,size}-cells property to i2c nodes > >>> - make i2c nodes disabled in the SoC and enable them in the board > >>> - add interrupt controller attributes to gpio nodes > >>> - Move fixed-clock nodes up a level and remove unnecessary @0 > >>> Changes in v4: > >>> - use 'phy-handle' instead of 'phy' > >>> - move status="okay" on usb nodes to board dts > >>> - Add review from Andrew > >>> Changes in v3: > >>> - Move memory node to board > >>> - Use single digit reg value for phy address > >>> - Remove MMC node (driver needs work) > >>> - Remove syscon & simple-mfd for pinctrl > >>> Changes in v2: > >>> - Make pinctrl a child node of a syscon node > >>> - Use marvell,armada-8k-gpio instead of orion-gpio > >>> - Remove nand peripheral. The Marvell SDK does have some > >>> changes for the > >>> ac5-nand-controller but I currently lack hardware with NAND > >>> fitted so > >>> I can't test it right now. I've therefore chosen to omit the > >>> node and > >>> not attempted to bring in the driver or binding. > >>> - Remove pcie peripheral. Again there are changes in the SDK > >>> and I have > >>> no way of testing them. > >>> - Remove prestera node. > >>> - Remove "marvell,ac5-ehci" compatible from USB node as > >>> "marvell,orion-ehci" is sufficient > >>> - Remove watchdog node. There is a buggy driver for the ac5 > >>> watchdog in > >>> the SDK but it needs some work so I've dropped the node for now. > >>> > >>> arch/arm64/boot/dts/marvell/Makefile | 1 + > >>> .../boot/dts/marvell/armada-98dx25xx.dtsi | 295 > >>> ++++++++++++++++++ > >>> .../boot/dts/marvell/armada-98dx35xx-rd.dts | 101 ++++++ > >>> .../boot/dts/marvell/armada-98dx35xx.dtsi | 13 + > >>> 4 files changed, 410 insertions(+) > >>> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > >>> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts > >>> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi > >>> > >>> diff --git a/arch/arm64/boot/dts/marvell/Makefile > >>> b/arch/arm64/boot/dts/marvell/Makefile > >>> index 1c794cdcb8e6..b7a4c715afbb 100644 > >>> --- a/arch/arm64/boot/dts/marvell/Makefile > >>> +++ b/arch/arm64/boot/dts/marvell/Makefile > >>> @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb > >>> dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb > >>> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb > >>> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb > >>> +dtb-$(CONFIG_ARCH_MVEBU) += armada-98dx35xx-rd.dtb > >>> diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > >>> b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > >>> new file mode 100644 > >>> index 000000000000..55ab4cd843a9 > >>> --- /dev/null > >>> +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > >>> @@ -0,0 +1,295 @@ > >>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > >>> +/* > >>> + * Device Tree For AC5. > >>> + * > >>> + * Copyright (C) 2021 Marvell > >>> + * Copyright (C) 2022 Allied Telesis Labs > >>> + */ > >>> + > >>> +#include <dt-bindings/gpio/gpio.h> > >>> +#include <dt-bindings/interrupt-controller/arm-gic.h> > >>> + > >>> +/ { > >>> + model = "Marvell AC5 SoC"; > >>> + compatible = "marvell,ac5"; > >>> + interrupt-parent = <&gic>; > >>> + #address-cells = <2>; > >>> + #size-cells = <2>; > >>> + > >>> + cpus { > >>> + #address-cells = <2>; > >>> + #size-cells = <0>; > >>> + > >>> + cpu-map { > >>> + cluster0 { > >>> + core0 { > >>> + cpu = <&cpu0>; > >>> + }; > >>> + core1 { > >>> + cpu = <&cpu1>; > >>> + }; > >>> + }; > >>> + }; > >>> + > >>> + cpu0: cpu@0 { > >>> + device_type = "cpu"; > >>> + compatible = "arm,armv8"; > >>> + reg = <0x0 0x0>; > >>> + enable-method = "psci"; > >>> + next-level-cache = <&l2>; > >>> + }; > >>> + > >>> + cpu1: cpu@1 { > >>> + device_type = "cpu"; > >>> + compatible = "arm,armv8"; > >>> + reg = <0x0 0x100>; > >>> + enable-method = "psci"; > >>> + next-level-cache = <&l2>; > >>> + }; > >>> + > >>> + l2: l2-cache { > >>> + compatible = "cache"; > >>> + }; > >>> + }; > >>> + > >>> + > >>> + psci { > >>> + compatible = "arm,psci-0.2"; > >>> + method = "smc"; > >>> + }; > >>> + > >>> + timer { > >>> + compatible = "arm,armv8-timer"; > >>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>, > >>> + <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, > >>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, > >>> + <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > >>> + clock-frequency = <25000000>; > >> I said no to this hack in a past version of this patch, and I'm going > >> to say it *again*. > > Sorry I must have missed it. > >> Please fix your firmware to program CNTFRQ_EL0, and > >> remove this useless property. > > I'm kind of at the mercy of what Marvell have provided for ATF. I am > > working on the bootloader portion in parallel and am getting things > > ready for submitting the u-boot support upstream. I was hoping to > > leave ATF alone I can at least see if they haven't fixed this already > > (the original dtsi I started with was fairly old) and if they haven't > > I'll raise it via their support system. > Seems to work fine without the clock so I'll drop it. Thanks. If you can, please verify that this is set on both CPUs (I have seen plenty of firmware only setting it on CPU0 in the past). > >> You are also missing a PPI for the EL2 virtual timer which is present > >> on any ARMv8.1+ CPU (and since this system is using A55, it definitely > >> has it). > >> > >> [...] > > Will add. > I assume you're talking about the 5th PPI per the > timer/arm,arch_timer.yaml ("hypervisor virtual timer irq"). Indeed. > Helpfully > Marvell don't include the PPI interrupt numbers in their datasheet. But > then I also notice that none of the other boards that have a > "arm,armv8-timer" provide a 5th interrupt either, have I misunderstood > something? This was only recently added to the DT binding, but the interrupt definitely exist at the CPU level for anything that implements ARMv8.1 and up. AFAIK, the M1 is the only machine to expose this interrupt in DT, but this doesn't mean the interrupt doesn't exist on all the other systems that have the same architecture revision. If you have contacts in Marvell, maybe try and find out whether they have simply decided not to wire the interrupt (I wouldn't be surprised). In this case, please add a comment. Thanks, M. -- Without deviation from the norm, progress is not possible. ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board @ 2022-05-16 9:48 ` Marc Zyngier 0 siblings, 0 replies; 26+ messages in thread From: Marc Zyngier @ 2022-05-16 9:48 UTC (permalink / raw) To: Chris Packham Cc: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan, devicetree, linux-kernel, linux-arm-kernel On Fri, 13 May 2022 02:26:21 +0100, Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote: > > Hi Marc, > > On 13/05/22 10:10, Chris Packham wrote: > > Hi Marc, > > > > On 12/05/22 19:38, Marc Zyngier wrote: > >> On Thu, 12 May 2022 05:25:00 +0100, > >> Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: > >>> The 98DX2530 SoC is the Control and Management CPU integrated into > >>> the Marvell 98DX25xx and 98DX35xx series of switch chip (internally > >>> referred to as AlleyCat5 and AlleyCat5X). > >>> > >>> These files have been taken from the Marvell SDK and lightly cleaned > >>> up with the License and copyright retained. > >>> > >>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > >>> Reviewed-by: Andrew Lunn <andrew@lunn.ch> > >>> --- > >>> > >>> Notes: > >>> The Marvell SDK has a number of new compatible strings. I've > >>> brought > >>> through some of the drivers or where possible used an in-tree > >>> alternative (e.g. there is SDK code for a ac5-gpio but two > >>> instances of > >>> the existing marvell,orion-gpio seems to cover what is needed > >>> if you use > >>> an appropriate binding). I expect that there will a new series of > >>> patches when I get some different hardware (or additions to > >>> this series > >>> depending on if/when it lands). > >>> Changes in v7: > >>> - Add missing compatible on usb1 > >>> - Add "rd-ac5x" compatible for board > >>> - Move aliases to board dts > >>> - Move board specific usb info to board dts > >>> - Consolidate usb1 board settings and remove unnecessary > >>> compatible > >>> - Add Allied Telesis copyright > >>> - Rename files after mailng-list discussion > >>> Changes in v6: > >>> - Move CPU nodes above the SoC (Krzysztof) > >>> - Minor formatting clean ups (Krzysztof) > >>> - Run through `make dtbs_check` > >>> - Move gic nodes inside SoC > >>> - Group clocks under a clock node > >>> Changes in v5: > >>> - add #{address,size}-cells property to i2c nodes > >>> - make i2c nodes disabled in the SoC and enable them in the board > >>> - add interrupt controller attributes to gpio nodes > >>> - Move fixed-clock nodes up a level and remove unnecessary @0 > >>> Changes in v4: > >>> - use 'phy-handle' instead of 'phy' > >>> - move status="okay" on usb nodes to board dts > >>> - Add review from Andrew > >>> Changes in v3: > >>> - Move memory node to board > >>> - Use single digit reg value for phy address > >>> - Remove MMC node (driver needs work) > >>> - Remove syscon & simple-mfd for pinctrl > >>> Changes in v2: > >>> - Make pinctrl a child node of a syscon node > >>> - Use marvell,armada-8k-gpio instead of orion-gpio > >>> - Remove nand peripheral. The Marvell SDK does have some > >>> changes for the > >>> ac5-nand-controller but I currently lack hardware with NAND > >>> fitted so > >>> I can't test it right now. I've therefore chosen to omit the > >>> node and > >>> not attempted to bring in the driver or binding. > >>> - Remove pcie peripheral. Again there are changes in the SDK > >>> and I have > >>> no way of testing them. > >>> - Remove prestera node. > >>> - Remove "marvell,ac5-ehci" compatible from USB node as > >>> "marvell,orion-ehci" is sufficient > >>> - Remove watchdog node. There is a buggy driver for the ac5 > >>> watchdog in > >>> the SDK but it needs some work so I've dropped the node for now. > >>> > >>> arch/arm64/boot/dts/marvell/Makefile | 1 + > >>> .../boot/dts/marvell/armada-98dx25xx.dtsi | 295 > >>> ++++++++++++++++++ > >>> .../boot/dts/marvell/armada-98dx35xx-rd.dts | 101 ++++++ > >>> .../boot/dts/marvell/armada-98dx35xx.dtsi | 13 + > >>> 4 files changed, 410 insertions(+) > >>> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > >>> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts > >>> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi > >>> > >>> diff --git a/arch/arm64/boot/dts/marvell/Makefile > >>> b/arch/arm64/boot/dts/marvell/Makefile > >>> index 1c794cdcb8e6..b7a4c715afbb 100644 > >>> --- a/arch/arm64/boot/dts/marvell/Makefile > >>> +++ b/arch/arm64/boot/dts/marvell/Makefile > >>> @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb > >>> dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb > >>> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb > >>> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb > >>> +dtb-$(CONFIG_ARCH_MVEBU) += armada-98dx35xx-rd.dtb > >>> diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > >>> b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > >>> new file mode 100644 > >>> index 000000000000..55ab4cd843a9 > >>> --- /dev/null > >>> +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > >>> @@ -0,0 +1,295 @@ > >>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > >>> +/* > >>> + * Device Tree For AC5. > >>> + * > >>> + * Copyright (C) 2021 Marvell > >>> + * Copyright (C) 2022 Allied Telesis Labs > >>> + */ > >>> + > >>> +#include <dt-bindings/gpio/gpio.h> > >>> +#include <dt-bindings/interrupt-controller/arm-gic.h> > >>> + > >>> +/ { > >>> + model = "Marvell AC5 SoC"; > >>> + compatible = "marvell,ac5"; > >>> + interrupt-parent = <&gic>; > >>> + #address-cells = <2>; > >>> + #size-cells = <2>; > >>> + > >>> + cpus { > >>> + #address-cells = <2>; > >>> + #size-cells = <0>; > >>> + > >>> + cpu-map { > >>> + cluster0 { > >>> + core0 { > >>> + cpu = <&cpu0>; > >>> + }; > >>> + core1 { > >>> + cpu = <&cpu1>; > >>> + }; > >>> + }; > >>> + }; > >>> + > >>> + cpu0: cpu@0 { > >>> + device_type = "cpu"; > >>> + compatible = "arm,armv8"; > >>> + reg = <0x0 0x0>; > >>> + enable-method = "psci"; > >>> + next-level-cache = <&l2>; > >>> + }; > >>> + > >>> + cpu1: cpu@1 { > >>> + device_type = "cpu"; > >>> + compatible = "arm,armv8"; > >>> + reg = <0x0 0x100>; > >>> + enable-method = "psci"; > >>> + next-level-cache = <&l2>; > >>> + }; > >>> + > >>> + l2: l2-cache { > >>> + compatible = "cache"; > >>> + }; > >>> + }; > >>> + > >>> + > >>> + psci { > >>> + compatible = "arm,psci-0.2"; > >>> + method = "smc"; > >>> + }; > >>> + > >>> + timer { > >>> + compatible = "arm,armv8-timer"; > >>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>, > >>> + <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, > >>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, > >>> + <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > >>> + clock-frequency = <25000000>; > >> I said no to this hack in a past version of this patch, and I'm going > >> to say it *again*. > > Sorry I must have missed it. > >> Please fix your firmware to program CNTFRQ_EL0, and > >> remove this useless property. > > I'm kind of at the mercy of what Marvell have provided for ATF. I am > > working on the bootloader portion in parallel and am getting things > > ready for submitting the u-boot support upstream. I was hoping to > > leave ATF alone I can at least see if they haven't fixed this already > > (the original dtsi I started with was fairly old) and if they haven't > > I'll raise it via their support system. > Seems to work fine without the clock so I'll drop it. Thanks. If you can, please verify that this is set on both CPUs (I have seen plenty of firmware only setting it on CPU0 in the past). > >> You are also missing a PPI for the EL2 virtual timer which is present > >> on any ARMv8.1+ CPU (and since this system is using A55, it definitely > >> has it). > >> > >> [...] > > Will add. > I assume you're talking about the 5th PPI per the > timer/arm,arch_timer.yaml ("hypervisor virtual timer irq"). Indeed. > Helpfully > Marvell don't include the PPI interrupt numbers in their datasheet. But > then I also notice that none of the other boards that have a > "arm,armv8-timer" provide a 5th interrupt either, have I misunderstood > something? This was only recently added to the DT binding, but the interrupt definitely exist at the CPU level for anything that implements ARMv8.1 and up. AFAIK, the M1 is the only machine to expose this interrupt in DT, but this doesn't mean the interrupt doesn't exist on all the other systems that have the same architecture revision. If you have contacts in Marvell, maybe try and find out whether they have simply decided not to wire the interrupt (I wouldn't be surprised). In this case, please add a comment. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board 2022-05-16 9:48 ` Marc Zyngier @ 2022-05-16 21:56 ` Chris Packham -1 siblings, 0 replies; 26+ messages in thread From: Chris Packham @ 2022-05-16 21:56 UTC (permalink / raw) To: Marc Zyngier Cc: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan, devicetree, linux-kernel, linux-arm-kernel On 16/05/22 21:48, Marc Zyngier wrote: > On Fri, 13 May 2022 02:26:21 +0100, > Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote: >> Hi Marc, >> >> On 13/05/22 10:10, Chris Packham wrote: >>> Hi Marc, >>> >>> On 12/05/22 19:38, Marc Zyngier wrote: >>>> On Thu, 12 May 2022 05:25:00 +0100, >>>> Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: >>>>> The 98DX2530 SoC is the Control and Management CPU integrated into >>>>> the Marvell 98DX25xx and 98DX35xx series of switch chip (internally >>>>> referred to as AlleyCat5 and AlleyCat5X). >>>>> >>>>> These files have been taken from the Marvell SDK and lightly cleaned >>>>> up with the License and copyright retained. >>>>> >>>>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> >>>>> Reviewed-by: Andrew Lunn <andrew@lunn.ch> >>>>> --- >>>>> >>>>> Notes: >>>>> The Marvell SDK has a number of new compatible strings. I've >>>>> brought >>>>> through some of the drivers or where possible used an in-tree >>>>> alternative (e.g. there is SDK code for a ac5-gpio but two >>>>> instances of >>>>> the existing marvell,orion-gpio seems to cover what is needed >>>>> if you use >>>>> an appropriate binding). I expect that there will a new series of >>>>> patches when I get some different hardware (or additions to >>>>> this series >>>>> depending on if/when it lands). >>>>> Changes in v7: >>>>> - Add missing compatible on usb1 >>>>> - Add "rd-ac5x" compatible for board >>>>> - Move aliases to board dts >>>>> - Move board specific usb info to board dts >>>>> - Consolidate usb1 board settings and remove unnecessary >>>>> compatible >>>>> - Add Allied Telesis copyright >>>>> - Rename files after mailng-list discussion >>>>> Changes in v6: >>>>> - Move CPU nodes above the SoC (Krzysztof) >>>>> - Minor formatting clean ups (Krzysztof) >>>>> - Run through `make dtbs_check` >>>>> - Move gic nodes inside SoC >>>>> - Group clocks under a clock node >>>>> Changes in v5: >>>>> - add #{address,size}-cells property to i2c nodes >>>>> - make i2c nodes disabled in the SoC and enable them in the board >>>>> - add interrupt controller attributes to gpio nodes >>>>> - Move fixed-clock nodes up a level and remove unnecessary @0 >>>>> Changes in v4: >>>>> - use 'phy-handle' instead of 'phy' >>>>> - move status="okay" on usb nodes to board dts >>>>> - Add review from Andrew >>>>> Changes in v3: >>>>> - Move memory node to board >>>>> - Use single digit reg value for phy address >>>>> - Remove MMC node (driver needs work) >>>>> - Remove syscon & simple-mfd for pinctrl >>>>> Changes in v2: >>>>> - Make pinctrl a child node of a syscon node >>>>> - Use marvell,armada-8k-gpio instead of orion-gpio >>>>> - Remove nand peripheral. The Marvell SDK does have some >>>>> changes for the >>>>> ac5-nand-controller but I currently lack hardware with NAND >>>>> fitted so >>>>> I can't test it right now. I've therefore chosen to omit the >>>>> node and >>>>> not attempted to bring in the driver or binding. >>>>> - Remove pcie peripheral. Again there are changes in the SDK >>>>> and I have >>>>> no way of testing them. >>>>> - Remove prestera node. >>>>> - Remove "marvell,ac5-ehci" compatible from USB node as >>>>> "marvell,orion-ehci" is sufficient >>>>> - Remove watchdog node. There is a buggy driver for the ac5 >>>>> watchdog in >>>>> the SDK but it needs some work so I've dropped the node for now. >>>>> >>>>> arch/arm64/boot/dts/marvell/Makefile | 1 + >>>>> .../boot/dts/marvell/armada-98dx25xx.dtsi | 295 >>>>> ++++++++++++++++++ >>>>> .../boot/dts/marvell/armada-98dx35xx-rd.dts | 101 ++++++ >>>>> .../boot/dts/marvell/armada-98dx35xx.dtsi | 13 + >>>>> 4 files changed, 410 insertions(+) >>>>> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >>>>> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts >>>>> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi >>>>> >>>>> diff --git a/arch/arm64/boot/dts/marvell/Makefile >>>>> b/arch/arm64/boot/dts/marvell/Makefile >>>>> index 1c794cdcb8e6..b7a4c715afbb 100644 >>>>> --- a/arch/arm64/boot/dts/marvell/Makefile >>>>> +++ b/arch/arm64/boot/dts/marvell/Makefile >>>>> @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb >>>>> dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb >>>>> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb >>>>> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb >>>>> +dtb-$(CONFIG_ARCH_MVEBU) += armada-98dx35xx-rd.dtb >>>>> diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >>>>> b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >>>>> new file mode 100644 >>>>> index 000000000000..55ab4cd843a9 >>>>> --- /dev/null >>>>> +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >>>>> @@ -0,0 +1,295 @@ >>>>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >>>>> +/* >>>>> + * Device Tree For AC5. >>>>> + * >>>>> + * Copyright (C) 2021 Marvell >>>>> + * Copyright (C) 2022 Allied Telesis Labs >>>>> + */ >>>>> + >>>>> +#include <dt-bindings/gpio/gpio.h> >>>>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>>>> + >>>>> +/ { >>>>> + model = "Marvell AC5 SoC"; >>>>> + compatible = "marvell,ac5"; >>>>> + interrupt-parent = <&gic>; >>>>> + #address-cells = <2>; >>>>> + #size-cells = <2>; >>>>> + >>>>> + cpus { >>>>> + #address-cells = <2>; >>>>> + #size-cells = <0>; >>>>> + >>>>> + cpu-map { >>>>> + cluster0 { >>>>> + core0 { >>>>> + cpu = <&cpu0>; >>>>> + }; >>>>> + core1 { >>>>> + cpu = <&cpu1>; >>>>> + }; >>>>> + }; >>>>> + }; >>>>> + >>>>> + cpu0: cpu@0 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x0 0x0>; >>>>> + enable-method = "psci"; >>>>> + next-level-cache = <&l2>; >>>>> + }; >>>>> + >>>>> + cpu1: cpu@1 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x0 0x100>; >>>>> + enable-method = "psci"; >>>>> + next-level-cache = <&l2>; >>>>> + }; >>>>> + >>>>> + l2: l2-cache { >>>>> + compatible = "cache"; >>>>> + }; >>>>> + }; >>>>> + >>>>> + >>>>> + psci { >>>>> + compatible = "arm,psci-0.2"; >>>>> + method = "smc"; >>>>> + }; >>>>> + >>>>> + timer { >>>>> + compatible = "arm,armv8-timer"; >>>>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; >>>>> + clock-frequency = <25000000>; >>>> I said no to this hack in a past version of this patch, and I'm going >>>> to say it *again*. >>> Sorry I must have missed it. >>>> Please fix your firmware to program CNTFRQ_EL0, and >>>> remove this useless property. >>> I'm kind of at the mercy of what Marvell have provided for ATF. I am >>> working on the bootloader portion in parallel and am getting things >>> ready for submitting the u-boot support upstream. I was hoping to >>> leave ATF alone I can at least see if they haven't fixed this already >>> (the original dtsi I started with was fairly old) and if they haven't >>> I'll raise it via their support system. >> Seems to work fine without the clock so I'll drop it. > Thanks. If you can, please verify that this is set on both CPUs (I > have seen plenty of firmware only setting it on CPU0 in the past). The arch_timer interrupts are counting up on both CPUs and things generally seem to be getting scheduled (I don't have much of a userland at the moment so it's not exactly a stress test). Do you think that is sufficient to say the clock property is unnecessary and whatever firmware I have is working as expected. >>>> You are also missing a PPI for the EL2 virtual timer which is present >>>> on any ARMv8.1+ CPU (and since this system is using A55, it definitely >>>> has it). >>>> >>>> [...] >>> Will add. >> I assume you're talking about the 5th PPI per the >> timer/arm,arch_timer.yaml ("hypervisor virtual timer irq"). > Indeed. > >> Helpfully >> Marvell don't include the PPI interrupt numbers in their datasheet. But >> then I also notice that none of the other boards that have a >> "arm,armv8-timer" provide a 5th interrupt either, have I misunderstood >> something? > This was only recently added to the DT binding, but the interrupt > definitely exist at the CPU level for anything that implements ARMv8.1 > and up. AFAIK, the M1 is the only machine to expose this interrupt in > DT, but this doesn't mean the interrupt doesn't exist on all the other > systems that have the same architecture revision. > > If you have contacts in Marvell, maybe try and find out whether they > have simply decided not to wire the interrupt (I wouldn't be > surprised). In this case, please add a comment. I've reached out via their customer support portal. So far they just want to know why I'm refusing to use their out of date SDK (maybe I should direct them at some of Jon Corbet's presentations :P). These integrated chips are sometimes a bit problematic because the support goes via the Switching group but these questions are really about IP blocks that have been taken from the SoC group. It may take a while before I get a response from someone that actually knows the internals. > > Thanks, > > M. > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board @ 2022-05-16 21:56 ` Chris Packham 0 siblings, 0 replies; 26+ messages in thread From: Chris Packham @ 2022-05-16 21:56 UTC (permalink / raw) To: Marc Zyngier Cc: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan, devicetree, linux-kernel, linux-arm-kernel On 16/05/22 21:48, Marc Zyngier wrote: > On Fri, 13 May 2022 02:26:21 +0100, > Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote: >> Hi Marc, >> >> On 13/05/22 10:10, Chris Packham wrote: >>> Hi Marc, >>> >>> On 12/05/22 19:38, Marc Zyngier wrote: >>>> On Thu, 12 May 2022 05:25:00 +0100, >>>> Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: >>>>> The 98DX2530 SoC is the Control and Management CPU integrated into >>>>> the Marvell 98DX25xx and 98DX35xx series of switch chip (internally >>>>> referred to as AlleyCat5 and AlleyCat5X). >>>>> >>>>> These files have been taken from the Marvell SDK and lightly cleaned >>>>> up with the License and copyright retained. >>>>> >>>>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> >>>>> Reviewed-by: Andrew Lunn <andrew@lunn.ch> >>>>> --- >>>>> >>>>> Notes: >>>>> The Marvell SDK has a number of new compatible strings. I've >>>>> brought >>>>> through some of the drivers or where possible used an in-tree >>>>> alternative (e.g. there is SDK code for a ac5-gpio but two >>>>> instances of >>>>> the existing marvell,orion-gpio seems to cover what is needed >>>>> if you use >>>>> an appropriate binding). I expect that there will a new series of >>>>> patches when I get some different hardware (or additions to >>>>> this series >>>>> depending on if/when it lands). >>>>> Changes in v7: >>>>> - Add missing compatible on usb1 >>>>> - Add "rd-ac5x" compatible for board >>>>> - Move aliases to board dts >>>>> - Move board specific usb info to board dts >>>>> - Consolidate usb1 board settings and remove unnecessary >>>>> compatible >>>>> - Add Allied Telesis copyright >>>>> - Rename files after mailng-list discussion >>>>> Changes in v6: >>>>> - Move CPU nodes above the SoC (Krzysztof) >>>>> - Minor formatting clean ups (Krzysztof) >>>>> - Run through `make dtbs_check` >>>>> - Move gic nodes inside SoC >>>>> - Group clocks under a clock node >>>>> Changes in v5: >>>>> - add #{address,size}-cells property to i2c nodes >>>>> - make i2c nodes disabled in the SoC and enable them in the board >>>>> - add interrupt controller attributes to gpio nodes >>>>> - Move fixed-clock nodes up a level and remove unnecessary @0 >>>>> Changes in v4: >>>>> - use 'phy-handle' instead of 'phy' >>>>> - move status="okay" on usb nodes to board dts >>>>> - Add review from Andrew >>>>> Changes in v3: >>>>> - Move memory node to board >>>>> - Use single digit reg value for phy address >>>>> - Remove MMC node (driver needs work) >>>>> - Remove syscon & simple-mfd for pinctrl >>>>> Changes in v2: >>>>> - Make pinctrl a child node of a syscon node >>>>> - Use marvell,armada-8k-gpio instead of orion-gpio >>>>> - Remove nand peripheral. The Marvell SDK does have some >>>>> changes for the >>>>> ac5-nand-controller but I currently lack hardware with NAND >>>>> fitted so >>>>> I can't test it right now. I've therefore chosen to omit the >>>>> node and >>>>> not attempted to bring in the driver or binding. >>>>> - Remove pcie peripheral. Again there are changes in the SDK >>>>> and I have >>>>> no way of testing them. >>>>> - Remove prestera node. >>>>> - Remove "marvell,ac5-ehci" compatible from USB node as >>>>> "marvell,orion-ehci" is sufficient >>>>> - Remove watchdog node. There is a buggy driver for the ac5 >>>>> watchdog in >>>>> the SDK but it needs some work so I've dropped the node for now. >>>>> >>>>> arch/arm64/boot/dts/marvell/Makefile | 1 + >>>>> .../boot/dts/marvell/armada-98dx25xx.dtsi | 295 >>>>> ++++++++++++++++++ >>>>> .../boot/dts/marvell/armada-98dx35xx-rd.dts | 101 ++++++ >>>>> .../boot/dts/marvell/armada-98dx35xx.dtsi | 13 + >>>>> 4 files changed, 410 insertions(+) >>>>> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >>>>> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts >>>>> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi >>>>> >>>>> diff --git a/arch/arm64/boot/dts/marvell/Makefile >>>>> b/arch/arm64/boot/dts/marvell/Makefile >>>>> index 1c794cdcb8e6..b7a4c715afbb 100644 >>>>> --- a/arch/arm64/boot/dts/marvell/Makefile >>>>> +++ b/arch/arm64/boot/dts/marvell/Makefile >>>>> @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb >>>>> dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb >>>>> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb >>>>> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb >>>>> +dtb-$(CONFIG_ARCH_MVEBU) += armada-98dx35xx-rd.dtb >>>>> diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >>>>> b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >>>>> new file mode 100644 >>>>> index 000000000000..55ab4cd843a9 >>>>> --- /dev/null >>>>> +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >>>>> @@ -0,0 +1,295 @@ >>>>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >>>>> +/* >>>>> + * Device Tree For AC5. >>>>> + * >>>>> + * Copyright (C) 2021 Marvell >>>>> + * Copyright (C) 2022 Allied Telesis Labs >>>>> + */ >>>>> + >>>>> +#include <dt-bindings/gpio/gpio.h> >>>>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>>>> + >>>>> +/ { >>>>> + model = "Marvell AC5 SoC"; >>>>> + compatible = "marvell,ac5"; >>>>> + interrupt-parent = <&gic>; >>>>> + #address-cells = <2>; >>>>> + #size-cells = <2>; >>>>> + >>>>> + cpus { >>>>> + #address-cells = <2>; >>>>> + #size-cells = <0>; >>>>> + >>>>> + cpu-map { >>>>> + cluster0 { >>>>> + core0 { >>>>> + cpu = <&cpu0>; >>>>> + }; >>>>> + core1 { >>>>> + cpu = <&cpu1>; >>>>> + }; >>>>> + }; >>>>> + }; >>>>> + >>>>> + cpu0: cpu@0 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x0 0x0>; >>>>> + enable-method = "psci"; >>>>> + next-level-cache = <&l2>; >>>>> + }; >>>>> + >>>>> + cpu1: cpu@1 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,armv8"; >>>>> + reg = <0x0 0x100>; >>>>> + enable-method = "psci"; >>>>> + next-level-cache = <&l2>; >>>>> + }; >>>>> + >>>>> + l2: l2-cache { >>>>> + compatible = "cache"; >>>>> + }; >>>>> + }; >>>>> + >>>>> + >>>>> + psci { >>>>> + compatible = "arm,psci-0.2"; >>>>> + method = "smc"; >>>>> + }; >>>>> + >>>>> + timer { >>>>> + compatible = "arm,armv8-timer"; >>>>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; >>>>> + clock-frequency = <25000000>; >>>> I said no to this hack in a past version of this patch, and I'm going >>>> to say it *again*. >>> Sorry I must have missed it. >>>> Please fix your firmware to program CNTFRQ_EL0, and >>>> remove this useless property. >>> I'm kind of at the mercy of what Marvell have provided for ATF. I am >>> working on the bootloader portion in parallel and am getting things >>> ready for submitting the u-boot support upstream. I was hoping to >>> leave ATF alone I can at least see if they haven't fixed this already >>> (the original dtsi I started with was fairly old) and if they haven't >>> I'll raise it via their support system. >> Seems to work fine without the clock so I'll drop it. > Thanks. If you can, please verify that this is set on both CPUs (I > have seen plenty of firmware only setting it on CPU0 in the past). The arch_timer interrupts are counting up on both CPUs and things generally seem to be getting scheduled (I don't have much of a userland at the moment so it's not exactly a stress test). Do you think that is sufficient to say the clock property is unnecessary and whatever firmware I have is working as expected. >>>> You are also missing a PPI for the EL2 virtual timer which is present >>>> on any ARMv8.1+ CPU (and since this system is using A55, it definitely >>>> has it). >>>> >>>> [...] >>> Will add. >> I assume you're talking about the 5th PPI per the >> timer/arm,arch_timer.yaml ("hypervisor virtual timer irq"). > Indeed. > >> Helpfully >> Marvell don't include the PPI interrupt numbers in their datasheet. But >> then I also notice that none of the other boards that have a >> "arm,armv8-timer" provide a 5th interrupt either, have I misunderstood >> something? > This was only recently added to the DT binding, but the interrupt > definitely exist at the CPU level for anything that implements ARMv8.1 > and up. AFAIK, the M1 is the only machine to expose this interrupt in > DT, but this doesn't mean the interrupt doesn't exist on all the other > systems that have the same architecture revision. > > If you have contacts in Marvell, maybe try and find out whether they > have simply decided not to wire the interrupt (I wouldn't be > surprised). In this case, please add a comment. I've reached out via their customer support portal. So far they just want to know why I'm refusing to use their out of date SDK (maybe I should direct them at some of Jon Corbet's presentations :P). These integrated chips are sometimes a bit problematic because the support goes via the Switching group but these questions are really about IP blocks that have been taken from the SoC group. It may take a while before I get a response from someone that actually knows the internals. > > Thanks, > > M. > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board 2022-05-16 21:56 ` Chris Packham @ 2022-05-17 6:42 ` Marc Zyngier -1 siblings, 0 replies; 26+ messages in thread From: Marc Zyngier @ 2022-05-17 6:42 UTC (permalink / raw) To: Chris Packham Cc: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan, devicetree, linux-kernel, linux-arm-kernel On Mon, 16 May 2022 22:56:44 +0100, Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote: > > >>>> Please fix your firmware to program CNTFRQ_EL0, and > >>>> remove this useless property. > >>> I'm kind of at the mercy of what Marvell have provided for ATF. I am > >>> working on the bootloader portion in parallel and am getting things > >>> ready for submitting the u-boot support upstream. I was hoping to > >>> leave ATF alone I can at least see if they haven't fixed this already > >>> (the original dtsi I started with was fairly old) and if they haven't > >>> I'll raise it via their support system. > >> Seems to work fine without the clock so I'll drop it. > > Thanks. If you can, please verify that this is set on both CPUs (I > > have seen plenty of firmware only setting it on CPU0 in the past). > The arch_timer interrupts are counting up on both CPUs and things > generally seem to be getting scheduled (I don't have much of a userland > at the moment so it's not exactly a stress test). Do you think that is > sufficient to say the clock property is unnecessary and whatever > firmware I have is working as expected. No, the counter always count, and CNTFRQ_EL0 is only an indication of the frequency for SW to find out. You can directly read CNTFRQ_EL0 from userspace on each CPU and find whether they have the same value. > >>>> You are also missing a PPI for the EL2 virtual timer which is present > >>>> on any ARMv8.1+ CPU (and since this system is using A55, it definitely > >>>> has it). > >>>> > >>>> [...] > >>> Will add. > >> I assume you're talking about the 5th PPI per the > >> timer/arm,arch_timer.yaml ("hypervisor virtual timer irq"). > > Indeed. > > > >> Helpfully > >> Marvell don't include the PPI interrupt numbers in their datasheet. But > >> then I also notice that none of the other boards that have a > >> "arm,armv8-timer" provide a 5th interrupt either, have I misunderstood > >> something? > > This was only recently added to the DT binding, but the interrupt > > definitely exist at the CPU level for anything that implements ARMv8.1 > > and up. AFAIK, the M1 is the only machine to expose this interrupt in > > DT, but this doesn't mean the interrupt doesn't exist on all the other > > systems that have the same architecture revision. > > > > If you have contacts in Marvell, maybe try and find out whether they > > have simply decided not to wire the interrupt (I wouldn't be > > surprised). In this case, please add a comment. > > I've reached out via their customer support portal. So far they just > want to know why I'm refusing to use their out of date SDK (maybe I > should direct them at some of Jon Corbet's presentations :P). The fact that they are asking is already saying everything there is to know, sadly... > These integrated chips are sometimes a bit problematic because the > support goes via the Switching group but these questions are really > about IP blocks that have been taken from the SoC group. It may take a > while before I get a response from someone that actually knows the > internals. Fair enough. Until then, please drop a comment in the DT indicating that the fate of this PPI is unknown. If you eventually find out, just add it to the DT (it is easy to add things, much harder to remove them). Thanks, M. -- Without deviation from the norm, progress is not possible. ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board @ 2022-05-17 6:42 ` Marc Zyngier 0 siblings, 0 replies; 26+ messages in thread From: Marc Zyngier @ 2022-05-17 6:42 UTC (permalink / raw) To: Chris Packham Cc: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan, devicetree, linux-kernel, linux-arm-kernel On Mon, 16 May 2022 22:56:44 +0100, Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote: > > >>>> Please fix your firmware to program CNTFRQ_EL0, and > >>>> remove this useless property. > >>> I'm kind of at the mercy of what Marvell have provided for ATF. I am > >>> working on the bootloader portion in parallel and am getting things > >>> ready for submitting the u-boot support upstream. I was hoping to > >>> leave ATF alone I can at least see if they haven't fixed this already > >>> (the original dtsi I started with was fairly old) and if they haven't > >>> I'll raise it via their support system. > >> Seems to work fine without the clock so I'll drop it. > > Thanks. If you can, please verify that this is set on both CPUs (I > > have seen plenty of firmware only setting it on CPU0 in the past). > The arch_timer interrupts are counting up on both CPUs and things > generally seem to be getting scheduled (I don't have much of a userland > at the moment so it's not exactly a stress test). Do you think that is > sufficient to say the clock property is unnecessary and whatever > firmware I have is working as expected. No, the counter always count, and CNTFRQ_EL0 is only an indication of the frequency for SW to find out. You can directly read CNTFRQ_EL0 from userspace on each CPU and find whether they have the same value. > >>>> You are also missing a PPI for the EL2 virtual timer which is present > >>>> on any ARMv8.1+ CPU (and since this system is using A55, it definitely > >>>> has it). > >>>> > >>>> [...] > >>> Will add. > >> I assume you're talking about the 5th PPI per the > >> timer/arm,arch_timer.yaml ("hypervisor virtual timer irq"). > > Indeed. > > > >> Helpfully > >> Marvell don't include the PPI interrupt numbers in their datasheet. But > >> then I also notice that none of the other boards that have a > >> "arm,armv8-timer" provide a 5th interrupt either, have I misunderstood > >> something? > > This was only recently added to the DT binding, but the interrupt > > definitely exist at the CPU level for anything that implements ARMv8.1 > > and up. AFAIK, the M1 is the only machine to expose this interrupt in > > DT, but this doesn't mean the interrupt doesn't exist on all the other > > systems that have the same architecture revision. > > > > If you have contacts in Marvell, maybe try and find out whether they > > have simply decided not to wire the interrupt (I wouldn't be > > surprised). In this case, please add a comment. > > I've reached out via their customer support portal. So far they just > want to know why I'm refusing to use their out of date SDK (maybe I > should direct them at some of Jon Corbet's presentations :P). The fact that they are asking is already saying everything there is to know, sadly... > These integrated chips are sometimes a bit problematic because the > support goes via the Switching group but these questions are really > about IP blocks that have been taken from the SoC group. It may take a > while before I get a response from someone that actually knows the > internals. Fair enough. Until then, please drop a comment in the DT indicating that the fate of this PPI is unknown. If you eventually find out, just add it to the DT (it is easy to add things, much harder to remove them). Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board 2022-05-17 6:42 ` Marc Zyngier @ 2022-05-17 22:56 ` Chris Packham -1 siblings, 0 replies; 26+ messages in thread From: Chris Packham @ 2022-05-17 22:56 UTC (permalink / raw) To: Marc Zyngier Cc: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan, devicetree, linux-kernel, linux-arm-kernel On 17/05/22 18:42, Marc Zyngier wrote: > On Mon, 16 May 2022 22:56:44 +0100, > Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote: >>>>>> Please fix your firmware to program CNTFRQ_EL0, and >>>>>> remove this useless property. >>>>> I'm kind of at the mercy of what Marvell have provided for ATF. I am >>>>> working on the bootloader portion in parallel and am getting things >>>>> ready for submitting the u-boot support upstream. I was hoping to >>>>> leave ATF alone I can at least see if they haven't fixed this already >>>>> (the original dtsi I started with was fairly old) and if they haven't >>>>> I'll raise it via their support system. >>>> Seems to work fine without the clock so I'll drop it. >>> Thanks. If you can, please verify that this is set on both CPUs (I >>> have seen plenty of firmware only setting it on CPU0 in the past). >> The arch_timer interrupts are counting up on both CPUs and things >> generally seem to be getting scheduled (I don't have much of a userland >> at the moment so it's not exactly a stress test). Do you think that is >> sufficient to say the clock property is unnecessary and whatever >> firmware I have is working as expected. > No, the counter always count, and CNTFRQ_EL0 is only an indication of > the frequency for SW to find out. You can directly read CNTFRQ_EL0 > from userspace on each CPU and find whether they have the same value. Here's my test program $ cat CNTFRQ_EL0.c #include <stdio.h> #include <stdint.h> #include <inttypes.h> int main(int argc, char *argv[]) { uint64_t val; asm volatile("mrs %0, CNTFRQ_EL0" : "=r" (val)); printf("CNTFRQ_EL0 = %" PRIu64 "\n", val); return 0; } And running on the RD-AC5X board [root@linuxbox tmp]# taskset 0x1 ./CNTFRQ_EL0 CNTFRQ_EL0 = 25000000 [root@linuxbox tmp]# taskset 0x2 ./CNTFRQ_EL0 CNTFRQ_EL0 = 25000000 > >>>>>> You are also missing a PPI for the EL2 virtual timer which is present >>>>>> on any ARMv8.1+ CPU (and since this system is using A55, it definitely >>>>>> has it). >>>>>> >>>>>> [...] >>>>> Will add. >>>> I assume you're talking about the 5th PPI per the >>>> timer/arm,arch_timer.yaml ("hypervisor virtual timer irq"). >>> Indeed. >>> >>>> Helpfully >>>> Marvell don't include the PPI interrupt numbers in their datasheet. But >>>> then I also notice that none of the other boards that have a >>>> "arm,armv8-timer" provide a 5th interrupt either, have I misunderstood >>>> something? >>> This was only recently added to the DT binding, but the interrupt >>> definitely exist at the CPU level for anything that implements ARMv8.1 >>> and up. AFAIK, the M1 is the only machine to expose this interrupt in >>> DT, but this doesn't mean the interrupt doesn't exist on all the other >>> systems that have the same architecture revision. >>> >>> If you have contacts in Marvell, maybe try and find out whether they >>> have simply decided not to wire the interrupt (I wouldn't be >>> surprised). In this case, please add a comment. >> I've reached out via their customer support portal. So far they just >> want to know why I'm refusing to use their out of date SDK (maybe I >> should direct them at some of Jon Corbet's presentations :P). > The fact that they are asking is already saying everything there is to > know, sadly... > >> These integrated chips are sometimes a bit problematic because the >> support goes via the Switching group but these questions are really >> about IP blocks that have been taken from the SoC group. It may take a >> while before I get a response from someone that actually knows the >> internals. > Fair enough. Until then, please drop a comment in the DT indicating > that the fate of this PPI is unknown. If you eventually find out, just > add it to the DT (it is easy to add things, much harder to remove > them). I'll include the following in the next round diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi index 88edc741c008..7a3693a2ad04 100644 --- a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi @@ -63,6 +63,7 @@ timer { <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + /* PPI for EL2 virtual timer is undocumented */ }; pmu { > Thanks, > > M. > ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board @ 2022-05-17 22:56 ` Chris Packham 0 siblings, 0 replies; 26+ messages in thread From: Chris Packham @ 2022-05-17 22:56 UTC (permalink / raw) To: Marc Zyngier Cc: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan, devicetree, linux-kernel, linux-arm-kernel On 17/05/22 18:42, Marc Zyngier wrote: > On Mon, 16 May 2022 22:56:44 +0100, > Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote: >>>>>> Please fix your firmware to program CNTFRQ_EL0, and >>>>>> remove this useless property. >>>>> I'm kind of at the mercy of what Marvell have provided for ATF. I am >>>>> working on the bootloader portion in parallel and am getting things >>>>> ready for submitting the u-boot support upstream. I was hoping to >>>>> leave ATF alone I can at least see if they haven't fixed this already >>>>> (the original dtsi I started with was fairly old) and if they haven't >>>>> I'll raise it via their support system. >>>> Seems to work fine without the clock so I'll drop it. >>> Thanks. If you can, please verify that this is set on both CPUs (I >>> have seen plenty of firmware only setting it on CPU0 in the past). >> The arch_timer interrupts are counting up on both CPUs and things >> generally seem to be getting scheduled (I don't have much of a userland >> at the moment so it's not exactly a stress test). Do you think that is >> sufficient to say the clock property is unnecessary and whatever >> firmware I have is working as expected. > No, the counter always count, and CNTFRQ_EL0 is only an indication of > the frequency for SW to find out. You can directly read CNTFRQ_EL0 > from userspace on each CPU and find whether they have the same value. Here's my test program $ cat CNTFRQ_EL0.c #include <stdio.h> #include <stdint.h> #include <inttypes.h> int main(int argc, char *argv[]) { uint64_t val; asm volatile("mrs %0, CNTFRQ_EL0" : "=r" (val)); printf("CNTFRQ_EL0 = %" PRIu64 "\n", val); return 0; } And running on the RD-AC5X board [root@linuxbox tmp]# taskset 0x1 ./CNTFRQ_EL0 CNTFRQ_EL0 = 25000000 [root@linuxbox tmp]# taskset 0x2 ./CNTFRQ_EL0 CNTFRQ_EL0 = 25000000 > >>>>>> You are also missing a PPI for the EL2 virtual timer which is present >>>>>> on any ARMv8.1+ CPU (and since this system is using A55, it definitely >>>>>> has it). >>>>>> >>>>>> [...] >>>>> Will add. >>>> I assume you're talking about the 5th PPI per the >>>> timer/arm,arch_timer.yaml ("hypervisor virtual timer irq"). >>> Indeed. >>> >>>> Helpfully >>>> Marvell don't include the PPI interrupt numbers in their datasheet. But >>>> then I also notice that none of the other boards that have a >>>> "arm,armv8-timer" provide a 5th interrupt either, have I misunderstood >>>> something? >>> This was only recently added to the DT binding, but the interrupt >>> definitely exist at the CPU level for anything that implements ARMv8.1 >>> and up. AFAIK, the M1 is the only machine to expose this interrupt in >>> DT, but this doesn't mean the interrupt doesn't exist on all the other >>> systems that have the same architecture revision. >>> >>> If you have contacts in Marvell, maybe try and find out whether they >>> have simply decided not to wire the interrupt (I wouldn't be >>> surprised). In this case, please add a comment. >> I've reached out via their customer support portal. So far they just >> want to know why I'm refusing to use their out of date SDK (maybe I >> should direct them at some of Jon Corbet's presentations :P). > The fact that they are asking is already saying everything there is to > know, sadly... > >> These integrated chips are sometimes a bit problematic because the >> support goes via the Switching group but these questions are really >> about IP blocks that have been taken from the SoC group. It may take a >> while before I get a response from someone that actually knows the >> internals. > Fair enough. Until then, please drop a comment in the DT indicating > that the fate of this PPI is unknown. If you eventually find out, just > add it to the DT (it is easy to add things, much harder to remove > them). I'll include the following in the next round diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi index 88edc741c008..7a3693a2ad04 100644 --- a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi @@ -63,6 +63,7 @@ timer { <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + /* PPI for EL2 virtual timer is undocumented */ }; pmu { > Thanks, > > M. > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board 2022-05-17 22:56 ` Chris Packham @ 2022-05-18 7:11 ` Marc Zyngier -1 siblings, 0 replies; 26+ messages in thread From: Marc Zyngier @ 2022-05-18 7:11 UTC (permalink / raw) To: Chris Packham Cc: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan, devicetree, linux-kernel, linux-arm-kernel On 2022-05-17 23:56, Chris Packham wrote: > On 17/05/22 18:42, Marc Zyngier wrote: >> On Mon, 16 May 2022 22:56:44 +0100, >> Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote: >>>>>>> Please fix your firmware to program CNTFRQ_EL0, and >>>>>>> remove this useless property. >>>>>> I'm kind of at the mercy of what Marvell have provided for ATF. I >>>>>> am >>>>>> working on the bootloader portion in parallel and am getting >>>>>> things >>>>>> ready for submitting the u-boot support upstream. I was hoping to >>>>>> leave ATF alone I can at least see if they haven't fixed this >>>>>> already >>>>>> (the original dtsi I started with was fairly old) and if they >>>>>> haven't >>>>>> I'll raise it via their support system. >>>>> Seems to work fine without the clock so I'll drop it. >>>> Thanks. If you can, please verify that this is set on both CPUs (I >>>> have seen plenty of firmware only setting it on CPU0 in the past). >>> The arch_timer interrupts are counting up on both CPUs and things >>> generally seem to be getting scheduled (I don't have much of a >>> userland >>> at the moment so it's not exactly a stress test). Do you think that >>> is >>> sufficient to say the clock property is unnecessary and whatever >>> firmware I have is working as expected. >> No, the counter always count, and CNTFRQ_EL0 is only an indication of >> the frequency for SW to find out. You can directly read CNTFRQ_EL0 >> from userspace on each CPU and find whether they have the same value. > > Here's my test program > > $ cat CNTFRQ_EL0.c > #include <stdio.h> > #include <stdint.h> > #include <inttypes.h> > > int main(int argc, char *argv[]) > { > uint64_t val; > > asm volatile("mrs %0, CNTFRQ_EL0" : "=r" (val)); > printf("CNTFRQ_EL0 = %" PRIu64 "\n", val); > > return 0; > } > > And running on the RD-AC5X board > > [root@linuxbox tmp]# taskset 0x1 ./CNTFRQ_EL0 > CNTFRQ_EL0 = 25000000 > [root@linuxbox tmp]# taskset 0x2 ./CNTFRQ_EL0 > CNTFRQ_EL0 = 25000000 Great. So the DT attribute was only cargo-culted by MRVL, and they don't realise what that's for... Thanks for going the extra mile and checking this! > >> >>>>>>> You are also missing a PPI for the EL2 virtual timer which is >>>>>>> present >>>>>>> on any ARMv8.1+ CPU (and since this system is using A55, it >>>>>>> definitely >>>>>>> has it). >>>>>>> >>>>>>> [...] >>>>>> Will add. >>>>> I assume you're talking about the 5th PPI per the >>>>> timer/arm,arch_timer.yaml ("hypervisor virtual timer irq"). >>>> Indeed. >>>> >>>>> Helpfully >>>>> Marvell don't include the PPI interrupt numbers in their datasheet. >>>>> But >>>>> then I also notice that none of the other boards that have a >>>>> "arm,armv8-timer" provide a 5th interrupt either, have I >>>>> misunderstood >>>>> something? >>>> This was only recently added to the DT binding, but the interrupt >>>> definitely exist at the CPU level for anything that implements >>>> ARMv8.1 >>>> and up. AFAIK, the M1 is the only machine to expose this interrupt >>>> in >>>> DT, but this doesn't mean the interrupt doesn't exist on all the >>>> other >>>> systems that have the same architecture revision. >>>> >>>> If you have contacts in Marvell, maybe try and find out whether they >>>> have simply decided not to wire the interrupt (I wouldn't be >>>> surprised). In this case, please add a comment. >>> I've reached out via their customer support portal. So far they just >>> want to know why I'm refusing to use their out of date SDK (maybe I >>> should direct them at some of Jon Corbet's presentations :P). >> The fact that they are asking is already saying everything there is to >> know, sadly... >> >>> These integrated chips are sometimes a bit problematic because the >>> support goes via the Switching group but these questions are really >>> about IP blocks that have been taken from the SoC group. It may take >>> a >>> while before I get a response from someone that actually knows the >>> internals. >> Fair enough. Until then, please drop a comment in the DT indicating >> that the fate of this PPI is unknown. If you eventually find out, just >> add it to the DT (it is easy to add things, much harder to remove >> them). > > I'll include the following in the next round > > diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > index 88edc741c008..7a3693a2ad04 100644 > --- a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > @@ -63,6 +63,7 @@ timer { > <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, > <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, > <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > + /* PPI for EL2 virtual timer is > undocumented */ > }; > > pmu { Looks good, thank you. M. -- Jazz is not dead. It just smells funny... ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board @ 2022-05-18 7:11 ` Marc Zyngier 0 siblings, 0 replies; 26+ messages in thread From: Marc Zyngier @ 2022-05-18 7:11 UTC (permalink / raw) To: Chris Packham Cc: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan, devicetree, linux-kernel, linux-arm-kernel On 2022-05-17 23:56, Chris Packham wrote: > On 17/05/22 18:42, Marc Zyngier wrote: >> On Mon, 16 May 2022 22:56:44 +0100, >> Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote: >>>>>>> Please fix your firmware to program CNTFRQ_EL0, and >>>>>>> remove this useless property. >>>>>> I'm kind of at the mercy of what Marvell have provided for ATF. I >>>>>> am >>>>>> working on the bootloader portion in parallel and am getting >>>>>> things >>>>>> ready for submitting the u-boot support upstream. I was hoping to >>>>>> leave ATF alone I can at least see if they haven't fixed this >>>>>> already >>>>>> (the original dtsi I started with was fairly old) and if they >>>>>> haven't >>>>>> I'll raise it via their support system. >>>>> Seems to work fine without the clock so I'll drop it. >>>> Thanks. If you can, please verify that this is set on both CPUs (I >>>> have seen plenty of firmware only setting it on CPU0 in the past). >>> The arch_timer interrupts are counting up on both CPUs and things >>> generally seem to be getting scheduled (I don't have much of a >>> userland >>> at the moment so it's not exactly a stress test). Do you think that >>> is >>> sufficient to say the clock property is unnecessary and whatever >>> firmware I have is working as expected. >> No, the counter always count, and CNTFRQ_EL0 is only an indication of >> the frequency for SW to find out. You can directly read CNTFRQ_EL0 >> from userspace on each CPU and find whether they have the same value. > > Here's my test program > > $ cat CNTFRQ_EL0.c > #include <stdio.h> > #include <stdint.h> > #include <inttypes.h> > > int main(int argc, char *argv[]) > { > uint64_t val; > > asm volatile("mrs %0, CNTFRQ_EL0" : "=r" (val)); > printf("CNTFRQ_EL0 = %" PRIu64 "\n", val); > > return 0; > } > > And running on the RD-AC5X board > > [root@linuxbox tmp]# taskset 0x1 ./CNTFRQ_EL0 > CNTFRQ_EL0 = 25000000 > [root@linuxbox tmp]# taskset 0x2 ./CNTFRQ_EL0 > CNTFRQ_EL0 = 25000000 Great. So the DT attribute was only cargo-culted by MRVL, and they don't realise what that's for... Thanks for going the extra mile and checking this! > >> >>>>>>> You are also missing a PPI for the EL2 virtual timer which is >>>>>>> present >>>>>>> on any ARMv8.1+ CPU (and since this system is using A55, it >>>>>>> definitely >>>>>>> has it). >>>>>>> >>>>>>> [...] >>>>>> Will add. >>>>> I assume you're talking about the 5th PPI per the >>>>> timer/arm,arch_timer.yaml ("hypervisor virtual timer irq"). >>>> Indeed. >>>> >>>>> Helpfully >>>>> Marvell don't include the PPI interrupt numbers in their datasheet. >>>>> But >>>>> then I also notice that none of the other boards that have a >>>>> "arm,armv8-timer" provide a 5th interrupt either, have I >>>>> misunderstood >>>>> something? >>>> This was only recently added to the DT binding, but the interrupt >>>> definitely exist at the CPU level for anything that implements >>>> ARMv8.1 >>>> and up. AFAIK, the M1 is the only machine to expose this interrupt >>>> in >>>> DT, but this doesn't mean the interrupt doesn't exist on all the >>>> other >>>> systems that have the same architecture revision. >>>> >>>> If you have contacts in Marvell, maybe try and find out whether they >>>> have simply decided not to wire the interrupt (I wouldn't be >>>> surprised). In this case, please add a comment. >>> I've reached out via their customer support portal. So far they just >>> want to know why I'm refusing to use their out of date SDK (maybe I >>> should direct them at some of Jon Corbet's presentations :P). >> The fact that they are asking is already saying everything there is to >> know, sadly... >> >>> These integrated chips are sometimes a bit problematic because the >>> support goes via the Switching group but these questions are really >>> about IP blocks that have been taken from the SoC group. It may take >>> a >>> while before I get a response from someone that actually knows the >>> internals. >> Fair enough. Until then, please drop a comment in the DT indicating >> that the fate of this PPI is unknown. If you eventually find out, just >> add it to the DT (it is easy to add things, much harder to remove >> them). > > I'll include the following in the next round > > diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > index 88edc741c008..7a3693a2ad04 100644 > --- a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi > @@ -63,6 +63,7 @@ timer { > <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, > <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, > <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > + /* PPI for EL2 virtual timer is > undocumented */ > }; > > pmu { Looks good, thank you. M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v7 3/3] arm64: marvell: enable the 98DX2530 pinctrl driver 2022-05-12 4:24 ` Chris Packham @ 2022-05-12 4:25 ` Chris Packham -1 siblings, 0 replies; 26+ messages in thread From: Chris Packham @ 2022-05-12 4:25 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan Cc: devicetree, linux-kernel, linux-arm-kernel, Chris Packham This commit makes sure the drivers for the 98DX2530 pin controller is enabled. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> --- Notes: Changes in v7: - None Changes in v6: - None Changes in v5: - None Changes in v4: - None Changes in v3: - Add review from Andrew Changes in v2: - None arch/arm64/Kconfig.platforms | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 30b123cde02c..229571d57496 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -183,11 +183,13 @@ config ARCH_MVEBU select PINCTRL_ARMADA_37XX select PINCTRL_ARMADA_AP806 select PINCTRL_ARMADA_CP110 + select PINCTRL_AC5 help This enables support for Marvell EBU familly, including: - Armada 3700 SoC Family - Armada 7K SoC Family - Armada 8K SoC Family + - 98DX2530 SoC Family config ARCH_MXC bool "ARMv8 based NXP i.MX SoC family" -- 2.36.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v7 3/3] arm64: marvell: enable the 98DX2530 pinctrl driver @ 2022-05-12 4:25 ` Chris Packham 0 siblings, 0 replies; 26+ messages in thread From: Chris Packham @ 2022-05-12 4:25 UTC (permalink / raw) To: robh+dt, krzysztof.kozlowski+dt, catalin.marinas, will, andrew, gregory.clement, sebastian.hesselbarth, kostap, robert.marko, vadym.kochan Cc: devicetree, linux-kernel, linux-arm-kernel, Chris Packham This commit makes sure the drivers for the 98DX2530 pin controller is enabled. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> --- Notes: Changes in v7: - None Changes in v6: - None Changes in v5: - None Changes in v4: - None Changes in v3: - Add review from Andrew Changes in v2: - None arch/arm64/Kconfig.platforms | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 30b123cde02c..229571d57496 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -183,11 +183,13 @@ config ARCH_MVEBU select PINCTRL_ARMADA_37XX select PINCTRL_ARMADA_AP806 select PINCTRL_ARMADA_CP110 + select PINCTRL_AC5 help This enables support for Marvell EBU familly, including: - Armada 3700 SoC Family - Armada 7K SoC Family - Armada 8K SoC Family + - 98DX2530 SoC Family config ARCH_MXC bool "ARMv8 based NXP i.MX SoC family" -- 2.36.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 26+ messages in thread
end of thread, other threads:[~2022-05-18 7:13 UTC | newest] Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-05-12 4:24 [PATCH v7 0/3] arm64: mvebu: Support for Marvell 98DX2530 (and variants) Chris Packham 2022-05-12 4:24 ` Chris Packham 2022-05-12 4:24 ` [PATCH v7 1/3] dt-bindings: marvell: Document the AC5/AC5X compatibles Chris Packham 2022-05-12 4:24 ` Chris Packham 2022-05-13 9:12 ` Krzysztof Kozlowski 2022-05-13 9:12 ` Krzysztof Kozlowski 2022-05-12 4:25 ` [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board Chris Packham 2022-05-12 4:25 ` Chris Packham 2022-05-12 7:38 ` Marc Zyngier 2022-05-12 7:38 ` Marc Zyngier 2022-05-12 22:10 ` Chris Packham 2022-05-12 22:10 ` Chris Packham 2022-05-13 1:26 ` Chris Packham 2022-05-13 1:26 ` Chris Packham 2022-05-16 9:48 ` Marc Zyngier 2022-05-16 9:48 ` Marc Zyngier 2022-05-16 21:56 ` Chris Packham 2022-05-16 21:56 ` Chris Packham 2022-05-17 6:42 ` Marc Zyngier 2022-05-17 6:42 ` Marc Zyngier 2022-05-17 22:56 ` Chris Packham 2022-05-17 22:56 ` Chris Packham 2022-05-18 7:11 ` Marc Zyngier 2022-05-18 7:11 ` Marc Zyngier 2022-05-12 4:25 ` [PATCH v7 3/3] arm64: marvell: enable the 98DX2530 pinctrl driver Chris Packham 2022-05-12 4:25 ` Chris Packham
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