All of lore.kernel.org
 help / color / mirror / Atom feed
From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [PATCH v1 1/2] clk: socfpga: Read the clock parent's register base in probe function
Date: Thu, 2 Apr 2020 21:50:50 +0200	[thread overview]
Message-ID: <dd416b3d-1490-a63b-92e5-d4ba2e3cf3d8@denx.de> (raw)
In-Reply-To: <CAPnjgZ2VE1=_avJUqSi+OWtHV=r6tAVS0V1NfADumrfubTWcqg@mail.gmail.com>

On 4/2/20 9:49 PM, Simon Glass wrote:
> Hi Marek,
> 
> On Thu, 2 Apr 2020 at 13:45, Marek Vasut <marex@denx.de> wrote:
>>
>> On 4/2/20 8:50 PM, Simon Glass wrote:
>>> Hi.
>>
>> Hi,
>>
>> [...]
>>
>>>>>>>>>> I suspect we could change this, so that
>>>>>>>>>> device_ofdata_to_platdata() first calls itself on its parent.
>>>>>>>>>>
>>>>>>>>>> I can think of various reasons why this change might be desirable.
>>>>>>>>>
>>>>>>>>> I think this is how it worked before already.
>>>>>>>>
>>>>>>>> Well effectively, yes, because ofdata and probe were joined together.
>>>>>>
>>>>>>> Simon, do you have plan to fix this DM core issue ?
>>>>>>
>>>>>> I'm not sure it definitely should be changed. But I'll do a patch and
>>>>>> see how it looks.
>>>>>
>>>>> Do I understand it correctly that the patch
>>>>> 82de42fa14682d408da935adfb0f935354c5008f actually completely breaks
>>>>> SoCFPGA ? Then I would say this is a release blocker ?
>>>> Yes. A10 SPL won't boot at all. It crashes during the clock manager setup.
>>>
>>> This came in right at the beginning of the cycle. I thought the
>>> purpose of the 3-month cycle was to allow time to test?
>>
>> It was ... altera ?
>>
>>> I do plan to try out changing the behaviour to read a parent's ofdata
>>> before the child, but I am not comfortable adding such a major change
>>> just before a release. It could have any number of ill effects.
>>>
>>> Can you update the clock driver? E.g. you could move some of the code
>>> from socfpga_a10_ofdata_to_platdata() to a probe() method?
>>
>> Can we revert the patch which broke arria10 instead ? It did work
>> before, so who knows how many other ill side effects there are ...
> 
> No, sorry, we need to fix Altera. Other boards have fixed driver bugs
> exposed by the patch.

How is altera broken again ? It used to work fine.

> BTW what is a good Altera board to get that doesn't cost too much?

With arria10 ? I think there's only one, the a10 socdk ...

  reply	other threads:[~2020-04-02 19:50 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-09  8:21 [PATCH v1 0/2] Fix A10 clock driver crash after changes in DM core chee.hong.ang at intel.com
2020-03-09  8:21 ` [PATCH v1 1/2] clk: socfpga: Read the clock parent's register base in probe function chee.hong.ang at intel.com
2020-03-09  9:05   ` Tan, Ley Foon
2020-03-09 12:28   ` Marek Vasut
2020-03-09 12:52     ` Ang, Chee Hong
2020-03-09 12:53       ` Marek Vasut
2020-03-11 11:50   ` Simon Glass
2020-03-11 11:54     ` Marek Vasut
2020-03-11 12:27       ` Simon Glass
2020-04-01  2:33         ` Ang, Chee Hong
2020-04-02  2:34           ` Simon Glass
2020-04-02  2:40             ` Marek Vasut
2020-04-02  2:44               ` Ang, Chee Hong
2020-04-02 18:50                 ` Simon Glass
2020-04-02 19:45                   ` Marek Vasut
2020-04-02 19:49                     ` Simon Glass
2020-04-02 19:50                       ` Marek Vasut [this message]
2020-04-02 19:53                       ` Simon Goldschmidt
2020-04-02 19:54                         ` Marek Vasut
2020-04-02 19:56                           ` Simon Glass
2020-04-02 19:58                           ` Simon Goldschmidt
2020-04-02 20:54                     ` Tom Rini
2020-04-02 21:07                       ` Marek Vasut
2020-04-02 21:52                         ` Simon Glass
2020-04-02 22:10                         ` Tom Rini
2020-04-02 22:47                           ` Marek Vasut
2020-04-03  3:52                             ` Tan, Ley Foon
2020-04-03 12:21                               ` Tom Rini
2020-04-06  8:57                                 ` Tan, Ley Foon
2020-04-06 11:28   ` Tom Rini
2020-04-06 11:34     ` Marek Vasut
2020-03-09  8:22 ` [PATCH v1 2/2] clk: socfpga: Switch to use ofnode API chee.hong.ang at intel.com
2020-03-09  9:05   ` Tan, Ley Foon

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=dd416b3d-1490-a63b-92e5-d4ba2e3cf3d8@denx.de \
    --to=marex@denx.de \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.