From: Tom Rini <trini@konsulko.com>
To: u-boot@lists.denx.de
Subject: [PATCH v1 1/2] clk: socfpga: Read the clock parent's register base in probe function
Date: Thu, 2 Apr 2020 18:10:31 -0400 [thread overview]
Message-ID: <20200402221031.GV27133@bill-the-cat> (raw)
In-Reply-To: <2a2c9b8d-dfee-c4ff-8602-119f8d2dbe60@denx.de>
On Thu, Apr 02, 2020 at 11:07:31PM +0200, Marek Vasut wrote:
> On 4/2/20 10:54 PM, Tom Rini wrote:
> [...]
>
> >>>>>> I'm not sure it definitely should be changed. But I'll do a patch and
> >>>>>> see how it looks.
> >>>>>
> >>>>> Do I understand it correctly that the patch
> >>>>> 82de42fa14682d408da935adfb0f935354c5008f actually completely breaks
> >>>>> SoCFPGA ? Then I would say this is a release blocker ?
> >>>> Yes. A10 SPL won't boot at all. It crashes during the clock manager setup.
> >>>
> >>> This came in right at the beginning of the cycle. I thought the
> >>> purpose of the 3-month cycle was to allow time to test?
> >>
> >> It was ... altera ?
> >
> > Sorry, I'm missing how that's an answer to the question. This came in
> > basically right at the start of the merge window.
>
> I don't have an A10 available right now, so what can I do ?
Ah, so the answer is "I can't test this platform myself". That's what
then, thanks.
--
Tom
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next prev parent reply other threads:[~2020-04-02 22:10 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-09 8:21 [PATCH v1 0/2] Fix A10 clock driver crash after changes in DM core chee.hong.ang at intel.com
2020-03-09 8:21 ` [PATCH v1 1/2] clk: socfpga: Read the clock parent's register base in probe function chee.hong.ang at intel.com
2020-03-09 9:05 ` Tan, Ley Foon
2020-03-09 12:28 ` Marek Vasut
2020-03-09 12:52 ` Ang, Chee Hong
2020-03-09 12:53 ` Marek Vasut
2020-03-11 11:50 ` Simon Glass
2020-03-11 11:54 ` Marek Vasut
2020-03-11 12:27 ` Simon Glass
2020-04-01 2:33 ` Ang, Chee Hong
2020-04-02 2:34 ` Simon Glass
2020-04-02 2:40 ` Marek Vasut
2020-04-02 2:44 ` Ang, Chee Hong
2020-04-02 18:50 ` Simon Glass
2020-04-02 19:45 ` Marek Vasut
2020-04-02 19:49 ` Simon Glass
2020-04-02 19:50 ` Marek Vasut
2020-04-02 19:53 ` Simon Goldschmidt
2020-04-02 19:54 ` Marek Vasut
2020-04-02 19:56 ` Simon Glass
2020-04-02 19:58 ` Simon Goldschmidt
2020-04-02 20:54 ` Tom Rini
2020-04-02 21:07 ` Marek Vasut
2020-04-02 21:52 ` Simon Glass
2020-04-02 22:10 ` Tom Rini [this message]
2020-04-02 22:47 ` Marek Vasut
2020-04-03 3:52 ` Tan, Ley Foon
2020-04-03 12:21 ` Tom Rini
2020-04-06 8:57 ` Tan, Ley Foon
2020-04-06 11:28 ` Tom Rini
2020-04-06 11:34 ` Marek Vasut
2020-03-09 8:22 ` [PATCH v1 2/2] clk: socfpga: Switch to use ofnode API chee.hong.ang at intel.com
2020-03-09 9:05 ` Tan, Ley Foon
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