[PATCH v4 00/11] consolidated i.MX8MP HSIO/MEDIA/HDMI blk-ctrl series

[PATCH v4 00/11] consolidated i.MX8MP HSIO/MEDIA/HDMI blk-ctrl series

[Lucas Stach]

Hi all,

this series adds a bunch more power domains that integrate with the blk-ctrls
to the i.MX8MP. It depends on the i.MX8MP GPCv2 support series posted in [1].

The HSIO blk-ctrl bindings are already applied upstream, so they are not part
of this series anymore. The DT description hasn't changed, but the
implementation of the HSIO blk-ctrl driver is reworked quite a bit from the
last round of patches, so I've dropped the review/tested-by tags.

I've also picked up the pretty thoroughly reviewed and tested MEDIA blk-ctrl
patches from Paul and Laurent into this series, as they would conflict with
other patches from this series when applied separately. This should hopefully
make it easier for Shawn to pick things up.

Finally this now also adds the HDMI blk-ctrl, not part of any previous series.
This one is pretty complex and the documentation in the reference manual
appears to be inaccurate. I found at least the following issues:

1. GLOBAL_XTAL24M_CLK_EN does not actually gate the 24MHz reference clock,
the PHY PLL happily locks and provides correct clocks without this clock being
ungated. It seems to gate some clock input of the HDMI TX controller instead,
register access to this controller fails without this clock.

2. HDMI_RTX_RESET_CTL0 bits 6 and 7 are marked as "reserved" in the manual,
but they are actually required to be configured. Bit 6 seems to keep something
in the display pixel clock path in inactive state and Bit 7 seems to reset
the HDMI TX i2c controller.

The HDMI blk-ctrl part is tested quite extensively with a PoC HDMI support
patchset, which I will send out in a bit, so I'm pretty sure that the
support as implemented is working. I've put the patches last in the series
in case that this turns out to be controversial, so the other patches can
be applied independent from the HDMI support.

Regards,
Lucas

[1] https://lore.kernel.org/all/20220330104620.3600159-1-l.stach@pengutronix.de/


Laurent Pinchart (1):
  arm64: dts: imx8mp: Add MEDIAMIX power domains

Lucas Stach (7):
  soc: imx: imx8m-blk-ctrl: set power device name
  soc: imx: add i.MX8MP HSIO blk-ctrl
  dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains
  dt-bindings: soc: add binding for i.MX8MP HDMI blk-ctrl
  soc: imx: add i.MX8MP HDMI blk-ctrl
  arm64: dts: imx8mp: add HSIO power-domains
  arm64: dts: imx8mp: add HDMI power-domains

Paul Elder (3):
  dt-bindings: soc: Add i.MX8MP media block control DT bindings
  soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
  arm64: dts: imx8mp: Add MEDIA_BLK_CTRL

 .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml     |  84 +++
 .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 104 +++
 arch/arm64/boot/dts/freescale/imx8mp.dtsi     | 153 +++-
 drivers/soc/imx/Makefile                      |   1 +
 drivers/soc/imx/imx8m-blk-ctrl.c              | 124 +++-
 drivers/soc/imx/imx8mp-blk-ctrl.c             | 696 ++++++++++++++++++
 include/dt-bindings/power/imx8mp-power.h      |  18 +
 7 files changed, 1172 insertions(+), 8 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
 create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c

-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 00/11] consolidated i.MX8MP HSIO/MEDIA/HDMI blk-ctrl series

[Lucas Stach]

Hi all,

this series adds a bunch more power domains that integrate with the blk-ctrls
to the i.MX8MP. It depends on the i.MX8MP GPCv2 support series posted in [1].

The HSIO blk-ctrl bindings are already applied upstream, so they are not part
of this series anymore. The DT description hasn't changed, but the
implementation of the HSIO blk-ctrl driver is reworked quite a bit from the
last round of patches, so I've dropped the review/tested-by tags.

I've also picked up the pretty thoroughly reviewed and tested MEDIA blk-ctrl
patches from Paul and Laurent into this series, as they would conflict with
other patches from this series when applied separately. This should hopefully
make it easier for Shawn to pick things up.

Finally this now also adds the HDMI blk-ctrl, not part of any previous series.
This one is pretty complex and the documentation in the reference manual
appears to be inaccurate. I found at least the following issues:

1. GLOBAL_XTAL24M_CLK_EN does not actually gate the 24MHz reference clock,
the PHY PLL happily locks and provides correct clocks without this clock being
ungated. It seems to gate some clock input of the HDMI TX controller instead,
register access to this controller fails without this clock.

2. HDMI_RTX_RESET_CTL0 bits 6 and 7 are marked as "reserved" in the manual,
but they are actually required to be configured. Bit 6 seems to keep something
in the display pixel clock path in inactive state and Bit 7 seems to reset
the HDMI TX i2c controller.

The HDMI blk-ctrl part is tested quite extensively with a PoC HDMI support
patchset, which I will send out in a bit, so I'm pretty sure that the
support as implemented is working. I've put the patches last in the series
in case that this turns out to be controversial, so the other patches can
be applied independent from the HDMI support.

Regards,
Lucas

[1] https://lore.kernel.org/all/20220330104620.3600159-1-l.stach@pengutronix.de/


Laurent Pinchart (1):
  arm64: dts: imx8mp: Add MEDIAMIX power domains

Lucas Stach (7):
  soc: imx: imx8m-blk-ctrl: set power device name
  soc: imx: add i.MX8MP HSIO blk-ctrl
  dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains
  dt-bindings: soc: add binding for i.MX8MP HDMI blk-ctrl
  soc: imx: add i.MX8MP HDMI blk-ctrl
  arm64: dts: imx8mp: add HSIO power-domains
  arm64: dts: imx8mp: add HDMI power-domains

Paul Elder (3):
  dt-bindings: soc: Add i.MX8MP media block control DT bindings
  soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
  arm64: dts: imx8mp: Add MEDIA_BLK_CTRL

 .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml     |  84 +++
 .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 104 +++
 arch/arm64/boot/dts/freescale/imx8mp.dtsi     | 153 +++-
 drivers/soc/imx/Makefile                      |   1 +
 drivers/soc/imx/imx8m-blk-ctrl.c              | 124 +++-
 drivers/soc/imx/imx8mp-blk-ctrl.c             | 696 ++++++++++++++++++
 include/dt-bindings/power/imx8mp-power.h      |  18 +
 7 files changed, 1172 insertions(+), 8 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
 create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c

-- 
2.30.2

[PATCH v4 01/11] soc: imx: imx8m-blk-ctrl: set power device name

[Lucas Stach]

Set the name for the virtual power device to the name of the attached
blk-ctrl domain. Makes the debug output for the power domains a lot
more pleasant to read.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/imx8m-blk-ctrl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
index 122f9c884b38..3071a8eca8ef 100644
--- a/drivers/soc/imx/imx8m-blk-ctrl.c
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -241,6 +241,7 @@ static int imx8m_blk_ctrl_probe(struct platform_device *pdev)
 			ret = PTR_ERR(domain->power_dev);
 			goto cleanup_pds;
 		}
+		dev_set_name(domain->power_dev, "%s", data->name);
 
 		domain->genpd.name = data->name;
 		domain->genpd.power_on = imx8m_blk_ctrl_power_on;
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 01/11] soc: imx: imx8m-blk-ctrl: set power device name

[Lucas Stach]

Set the name for the virtual power device to the name of the attached
blk-ctrl domain. Makes the debug output for the power domains a lot
more pleasant to read.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/imx8m-blk-ctrl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
index 122f9c884b38..3071a8eca8ef 100644
--- a/drivers/soc/imx/imx8m-blk-ctrl.c
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -241,6 +241,7 @@ static int imx8m_blk_ctrl_probe(struct platform_device *pdev)
 			ret = PTR_ERR(domain->power_dev);
 			goto cleanup_pds;
 		}
+		dev_set_name(domain->power_dev, "%s", data->name);
 
 		domain->genpd.name = data->name;
 		domain->genpd.power_on = imx8m_blk_ctrl_power_on;
-- 
2.30.2

[PATCH v4 02/11] soc: imx: add i.MX8MP HSIO blk-ctrl

[Lucas Stach]

The i.MX8MP added some blk-ctrl peripherals that don't follow the regular
structure of the blk-ctrls in the previous SoCs. Add a new file for those
with currently only the HSIO blk-ctrl being supported. Others will be added
later on.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/Makefile          |   1 +
 drivers/soc/imx/imx8mp-blk-ctrl.c | 503 ++++++++++++++++++++++++++++++
 2 files changed, 504 insertions(+)
 create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c

diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile
index 8a707077914c..63cd29f6d4d2 100644
--- a/drivers/soc/imx/Makefile
+++ b/drivers/soc/imx/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
 obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
 obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o
 obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o
+obj-$(CONFIG_SOC_IMX8M) += imx8mp-blk-ctrl.o
diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
new file mode 100644
index 000000000000..97cc8f08911e
--- /dev/null
+++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
@@ -0,0 +1,503 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/power/imx8mp-power.h>
+
+#define GPR_REG0		0x0
+#define  PCIE_CLOCK_MODULE_EN	BIT(0)
+#define  USB_CLOCK_MODULE_EN	BIT(1)
+
+struct imx8mp_blk_ctrl_domain;
+
+struct imx8mp_blk_ctrl {
+	struct device *dev;
+	struct notifier_block power_nb;
+	struct device *bus_power_dev;
+	struct regmap *regmap;
+	struct imx8mp_blk_ctrl_domain *domains;
+	struct genpd_onecell_data onecell_data;
+	void (*power_off) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
+	void (*power_on) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
+};
+
+struct imx8mp_blk_ctrl_domain_data {
+	const char *name;
+	const char * const *clk_names;
+	int num_clks;
+	const char *gpc_name;
+};
+
+#define DOMAIN_MAX_CLKS 2
+
+struct imx8mp_blk_ctrl_domain {
+	struct generic_pm_domain genpd;
+	const struct imx8mp_blk_ctrl_domain_data *data;
+	struct clk_bulk_data clks[DOMAIN_MAX_CLKS];
+	struct device *power_dev;
+	struct imx8mp_blk_ctrl *bc;
+	int id;
+};
+
+struct imx8mp_blk_ctrl_data {
+	int max_reg;
+	notifier_fn_t power_notifier_fn;
+	void (*power_off) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
+	void (*power_on) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
+	const struct imx8mp_blk_ctrl_domain_data *domains;
+	int num_domains;
+};
+
+static inline struct imx8mp_blk_ctrl_domain *
+to_imx8mp_blk_ctrl_domain(struct generic_pm_domain *genpd)
+{
+	return container_of(genpd, struct imx8mp_blk_ctrl_domain, genpd);
+}
+
+static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
+					  struct imx8mp_blk_ctrl_domain *domain)
+{
+	switch (domain->id) {
+	case IMX8MP_HSIOBLK_PD_USB:
+		regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+		break;
+	case IMX8MP_HSIOBLK_PD_PCIE:
+		regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
+		break;
+	default:
+		break;
+	}
+}
+
+static void imx8mp_hsio_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
+					   struct imx8mp_blk_ctrl_domain *domain)
+{
+	switch (domain->id) {
+	case IMX8MP_HSIOBLK_PD_USB:
+		regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+		break;
+	case IMX8MP_HSIOBLK_PD_PCIE:
+		regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
+		break;
+	default:
+		break;
+	}
+}
+
+static int imx8mp_hsio_power_notifier(struct notifier_block *nb,
+				      unsigned long action, void *data)
+{
+	struct imx8mp_blk_ctrl *bc = container_of(nb, struct imx8mp_blk_ctrl,
+						 power_nb);
+	struct clk_bulk_data *usb_clk = bc->domains[IMX8MP_HSIOBLK_PD_USB].clks;
+	int num_clks = bc->domains[IMX8MP_HSIOBLK_PD_USB].data->num_clks;
+	int ret;
+
+	switch (action) {
+	case GENPD_NOTIFY_ON:
+		/*
+		 * enable USB clock for a moment for the power-on ADB handshake
+		 * to proceed
+		 */
+		ret = clk_bulk_prepare_enable(num_clks, usb_clk);
+		if (ret)
+			return NOTIFY_BAD;
+		regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+
+		udelay(5);
+
+		regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+		clk_bulk_disable_unprepare(num_clks, usb_clk);
+		break;
+	case GENPD_NOTIFY_PRE_OFF:
+		/* enable USB clock for the power-down ADB handshake to work */
+		ret = clk_bulk_prepare_enable(num_clks, usb_clk);
+		if (ret)
+			return NOTIFY_BAD;
+
+		regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+		break;
+	case GENPD_NOTIFY_OFF:
+		clk_bulk_disable_unprepare(num_clks, usb_clk);
+		break;
+	default:
+		break;
+	}
+
+	return NOTIFY_OK;
+}
+
+static const struct imx8mp_blk_ctrl_domain_data imx8mp_hsio_domain_data[] = {
+	[IMX8MP_HSIOBLK_PD_USB] = {
+		.name = "hsioblk-usb",
+		.clk_names = (const char *[]){ "usb" },
+		.num_clks = 1,
+		.gpc_name = "usb",
+	},
+	[IMX8MP_HSIOBLK_PD_USB_PHY1] = {
+		.name = "hsioblk-usb-phy1",
+		.gpc_name = "usb-phy1",
+	},
+	[IMX8MP_HSIOBLK_PD_USB_PHY2] = {
+		.name = "hsioblk-usb-phy2",
+		.gpc_name = "usb-phy2",
+	},
+	[IMX8MP_HSIOBLK_PD_PCIE] = {
+		.name = "hsioblk-pcie",
+		.clk_names = (const char *[]){ "pcie" },
+		.num_clks = 1,
+		.gpc_name = "pcie",
+	},
+	[IMX8MP_HSIOBLK_PD_PCIE_PHY] = {
+		.name = "hsioblk-pcie-phy",
+		.gpc_name = "pcie-phy",
+	},
+};
+
+static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = {
+	.max_reg = 0x24,
+	.power_on = imx8mp_hsio_blk_ctrl_power_on,
+	.power_off = imx8mp_hsio_blk_ctrl_power_off,
+	.power_notifier_fn = imx8mp_hsio_power_notifier,
+	.domains = imx8mp_hsio_domain_data,
+	.num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data),
+};
+
+static int imx8mp_blk_ctrl_power_on(struct generic_pm_domain *genpd)
+{
+	struct imx8mp_blk_ctrl_domain *domain = to_imx8mp_blk_ctrl_domain(genpd);
+	const struct imx8mp_blk_ctrl_domain_data *data = domain->data;
+	struct imx8mp_blk_ctrl *bc = domain->bc;
+	int ret;
+
+	/* make sure bus domain is awake */
+	ret = pm_runtime_resume_and_get(bc->bus_power_dev);
+	if (ret < 0) {
+		dev_err(bc->dev, "failed to power up bus domain\n");
+		return ret;
+	}
+
+	/* enable upstream clocks */
+	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);;
+	if (ret) {
+		dev_err(bc->dev, "failed to enable clocks\n");
+		goto bus_put;
+	}
+
+	/* domain specific blk-ctrl manipulation */
+	bc->power_on(bc, domain);
+
+	/* power up upstream GPC domain */
+	ret = pm_runtime_resume_and_get(domain->power_dev);
+	if (ret < 0) {
+		dev_err(bc->dev, "failed to power up peripheral domain\n");
+		goto clk_disable;
+	}
+
+	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
+
+	return 0;
+
+clk_disable:
+	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
+bus_put:
+	pm_runtime_put(bc->bus_power_dev);
+
+	return ret;
+}
+
+static int imx8mp_blk_ctrl_power_off(struct generic_pm_domain *genpd)
+{
+	struct imx8mp_blk_ctrl_domain *domain = to_imx8mp_blk_ctrl_domain(genpd);
+	const struct imx8mp_blk_ctrl_domain_data *data = domain->data;
+	struct imx8mp_blk_ctrl *bc = domain->bc;
+	int ret;
+
+	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);;
+	if (ret) {
+		dev_err(bc->dev, "failed to enable clocks\n");
+		return ret;
+	}
+
+	/* domain specific blk-ctrl manipulation */
+	bc->power_off(bc, domain);
+
+	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
+
+	/* power down upstream GPC domain */
+	pm_runtime_put(domain->power_dev);
+
+	/* allow bus domain to suspend */
+	pm_runtime_put(bc->bus_power_dev);
+
+	return 0;
+}
+
+static struct generic_pm_domain *
+imx8m_blk_ctrl_xlate(struct of_phandle_args *args, void *data)
+{
+	struct genpd_onecell_data *onecell_data = data;
+	unsigned int index = args->args[0];
+
+	if (args->args_count != 1 ||
+	    index >= onecell_data->num_domains)
+		return ERR_PTR(-EINVAL);
+
+	return onecell_data->domains[index];
+}
+
+static struct lock_class_key blk_ctrl_genpd_lock_class;
+
+static int imx8mp_blk_ctrl_probe(struct platform_device *pdev)
+{
+	const struct imx8mp_blk_ctrl_data *bc_data;
+	struct device *dev = &pdev->dev;
+	struct imx8mp_blk_ctrl *bc;
+	void __iomem *base;
+	int num_domains, i, ret;
+
+	struct regmap_config regmap_config = {
+		.reg_bits	= 32,
+		.val_bits	= 32,
+		.reg_stride	= 4,
+	};
+
+	bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
+	if (!bc)
+		return -ENOMEM;
+
+	bc->dev = dev;
+
+	bc_data = of_device_get_match_data(dev);
+	num_domains = bc_data->num_domains;
+
+	base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	regmap_config.max_register = bc_data->max_reg;
+	bc->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
+	if (IS_ERR(bc->regmap))
+		return dev_err_probe(dev, PTR_ERR(bc->regmap),
+				     "failed to init regmap\n");
+
+	bc->domains = devm_kcalloc(dev, num_domains,
+				   sizeof(struct imx8mp_blk_ctrl_domain),
+				   GFP_KERNEL);
+	if (!bc->domains)
+		return -ENOMEM;
+
+	bc->onecell_data.num_domains = num_domains;
+	bc->onecell_data.xlate = imx8m_blk_ctrl_xlate;
+	bc->onecell_data.domains =
+		devm_kcalloc(dev, num_domains,
+			     sizeof(struct generic_pm_domain *), GFP_KERNEL);
+	if (!bc->onecell_data.domains)
+		return -ENOMEM;
+
+	bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus");
+	if (IS_ERR(bc->bus_power_dev))
+		return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),
+				     "failed to attach bus power domain\n");
+
+	bc->power_off = bc_data->power_off;
+	bc->power_on = bc_data->power_on;
+
+	for (i = 0; i < num_domains; i++) {
+		const struct imx8mp_blk_ctrl_domain_data *data = &bc_data->domains[i];
+		struct imx8mp_blk_ctrl_domain *domain = &bc->domains[i];
+		int j;
+
+		domain->data = data;
+
+		for (j = 0; j < data->num_clks; j++)
+			domain->clks[j].id = data->clk_names[j];
+
+		ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks);
+		if (ret) {
+			dev_err_probe(dev, ret, "failed to get clock\n");
+			goto cleanup_pds;
+		}
+
+		domain->power_dev =
+			dev_pm_domain_attach_by_name(dev, data->gpc_name);
+		if (IS_ERR(domain->power_dev)) {
+			dev_err_probe(dev, PTR_ERR(domain->power_dev),
+				      "failed to attach power domain %s\n",
+				      data->gpc_name);
+			ret = PTR_ERR(domain->power_dev);
+			goto cleanup_pds;
+		}
+		dev_set_name(domain->power_dev, "%s", data->name);
+
+		domain->genpd.name = data->name;
+		domain->genpd.power_on = imx8mp_blk_ctrl_power_on;
+		domain->genpd.power_off = imx8mp_blk_ctrl_power_off;
+		domain->bc = bc;
+		domain->id = i;
+
+		ret = pm_genpd_init(&domain->genpd, NULL, true);
+		if (ret) {
+			dev_err_probe(dev, ret, "failed to init power domain\n");
+			dev_pm_domain_detach(domain->power_dev, true);
+			goto cleanup_pds;
+		}
+
+		/*
+		 * We use runtime PM to trigger power on/off of the upstream GPC
+		 * domain, as a strict hierarchical parent/child power domain
+		 * setup doesn't allow us to meet the sequencing requirements.
+		 * This means we have nested locking of genpd locks, without the
+		 * nesting being visible at the genpd level, so we need a
+		 * separate lock class to make lockdep aware of the fact that
+		 * this are separate domain locks that can be nested without a
+		 * self-deadlock.
+		 */
+		lockdep_set_class(&domain->genpd.mlock,
+				  &blk_ctrl_genpd_lock_class);
+
+		bc->onecell_data.domains[i] = &domain->genpd;
+	}
+
+	ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
+	if (ret) {
+		dev_err_probe(dev, ret, "failed to add power domain provider\n");
+		goto cleanup_pds;
+	}
+
+	bc->power_nb.notifier_call = bc_data->power_notifier_fn;
+	ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb);
+	if (ret) {
+		dev_err_probe(dev, ret, "failed to add power notifier\n");
+		goto cleanup_provider;
+	}
+
+	dev_set_drvdata(dev, bc);
+
+	return 0;
+
+cleanup_provider:
+	of_genpd_del_provider(dev->of_node);
+cleanup_pds:
+	for (i--; i >= 0; i--) {
+		pm_genpd_remove(&bc->domains[i].genpd);
+		dev_pm_domain_detach(bc->domains[i].power_dev, true);
+	}
+
+	dev_pm_domain_detach(bc->bus_power_dev, true);
+
+	return ret;
+}
+
+static int imx8mp_blk_ctrl_remove(struct platform_device *pdev)
+{
+	struct imx8mp_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
+	int i;
+
+	of_genpd_del_provider(pdev->dev.of_node);
+
+	for (i = 0; bc->onecell_data.num_domains; i++) {
+		struct imx8mp_blk_ctrl_domain *domain = &bc->domains[i];
+
+		pm_genpd_remove(&domain->genpd);
+		dev_pm_domain_detach(domain->power_dev, true);
+	}
+
+	dev_pm_genpd_remove_notifier(bc->bus_power_dev);
+
+	dev_pm_domain_detach(bc->bus_power_dev, true);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int imx8mp_blk_ctrl_suspend(struct device *dev)
+{
+	struct imx8mp_blk_ctrl *bc = dev_get_drvdata(dev);
+	int ret, i;
+
+	/*
+	 * This may look strange, but is done so the generic PM_SLEEP code
+	 * can power down our domains and more importantly power them up again
+	 * after resume, without tripping over our usage of runtime PM to
+	 * control the upstream GPC domains. Things happen in the right order
+	 * in the system suspend/resume paths due to the device parent/child
+	 * hierarchy.
+	 */
+	ret = pm_runtime_get_sync(bc->bus_power_dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(bc->bus_power_dev);
+		return ret;
+	}
+
+	for (i = 0; i < bc->onecell_data.num_domains; i++) {
+		struct imx8mp_blk_ctrl_domain *domain = &bc->domains[i];
+
+		ret = pm_runtime_get_sync(domain->power_dev);
+		if (ret < 0) {
+			pm_runtime_put_noidle(domain->power_dev);
+			goto out_fail;
+		}
+	}
+
+	return 0;
+
+out_fail:
+	for (i--; i >= 0; i--)
+		pm_runtime_put(bc->domains[i].power_dev);
+
+	pm_runtime_put(bc->bus_power_dev);
+
+	return ret;
+}
+
+static int imx8mp_blk_ctrl_resume(struct device *dev)
+{
+	struct imx8mp_blk_ctrl *bc = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < bc->onecell_data.num_domains; i++)
+		pm_runtime_put(bc->domains[i].power_dev);
+
+	pm_runtime_put(bc->bus_power_dev);
+
+	return 0;
+}
+#endif
+
+static const struct dev_pm_ops imx8mp_blk_ctrl_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(imx8mp_blk_ctrl_suspend,
+				imx8mp_blk_ctrl_resume)
+};
+
+static const struct of_device_id imx8mp_blk_ctrl_of_match[] = {
+	{
+		.compatible = "fsl,imx8mp-hsio-blk-ctrl",
+		.data = &imx8mp_hsio_blk_ctl_dev_data,
+	}, {
+		/* Sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match);
+
+static struct platform_driver imx8mp_blk_ctrl_driver = {
+	.probe = imx8mp_blk_ctrl_probe,
+	.remove = imx8mp_blk_ctrl_remove,
+	.driver = {
+		.name = "imx8mp-blk-ctrl",
+		.pm = &imx8mp_blk_ctrl_pm_ops,
+		.of_match_table = imx8mp_blk_ctrl_of_match,
+	},
+};
+module_platform_driver(imx8mp_blk_ctrl_driver);
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 02/11] soc: imx: add i.MX8MP HSIO blk-ctrl

[Lucas Stach]

The i.MX8MP added some blk-ctrl peripherals that don't follow the regular
structure of the blk-ctrls in the previous SoCs. Add a new file for those
with currently only the HSIO blk-ctrl being supported. Others will be added
later on.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/Makefile          |   1 +
 drivers/soc/imx/imx8mp-blk-ctrl.c | 503 ++++++++++++++++++++++++++++++
 2 files changed, 504 insertions(+)
 create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c

diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile
index 8a707077914c..63cd29f6d4d2 100644
--- a/drivers/soc/imx/Makefile
+++ b/drivers/soc/imx/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
 obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
 obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o
 obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o
+obj-$(CONFIG_SOC_IMX8M) += imx8mp-blk-ctrl.o
diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
new file mode 100644
index 000000000000..97cc8f08911e
--- /dev/null
+++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
@@ -0,0 +1,503 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/power/imx8mp-power.h>
+
+#define GPR_REG0		0x0
+#define  PCIE_CLOCK_MODULE_EN	BIT(0)
+#define  USB_CLOCK_MODULE_EN	BIT(1)
+
+struct imx8mp_blk_ctrl_domain;
+
+struct imx8mp_blk_ctrl {
+	struct device *dev;
+	struct notifier_block power_nb;
+	struct device *bus_power_dev;
+	struct regmap *regmap;
+	struct imx8mp_blk_ctrl_domain *domains;
+	struct genpd_onecell_data onecell_data;
+	void (*power_off) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
+	void (*power_on) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
+};
+
+struct imx8mp_blk_ctrl_domain_data {
+	const char *name;
+	const char * const *clk_names;
+	int num_clks;
+	const char *gpc_name;
+};
+
+#define DOMAIN_MAX_CLKS 2
+
+struct imx8mp_blk_ctrl_domain {
+	struct generic_pm_domain genpd;
+	const struct imx8mp_blk_ctrl_domain_data *data;
+	struct clk_bulk_data clks[DOMAIN_MAX_CLKS];
+	struct device *power_dev;
+	struct imx8mp_blk_ctrl *bc;
+	int id;
+};
+
+struct imx8mp_blk_ctrl_data {
+	int max_reg;
+	notifier_fn_t power_notifier_fn;
+	void (*power_off) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
+	void (*power_on) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
+	const struct imx8mp_blk_ctrl_domain_data *domains;
+	int num_domains;
+};
+
+static inline struct imx8mp_blk_ctrl_domain *
+to_imx8mp_blk_ctrl_domain(struct generic_pm_domain *genpd)
+{
+	return container_of(genpd, struct imx8mp_blk_ctrl_domain, genpd);
+}
+
+static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
+					  struct imx8mp_blk_ctrl_domain *domain)
+{
+	switch (domain->id) {
+	case IMX8MP_HSIOBLK_PD_USB:
+		regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+		break;
+	case IMX8MP_HSIOBLK_PD_PCIE:
+		regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
+		break;
+	default:
+		break;
+	}
+}
+
+static void imx8mp_hsio_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
+					   struct imx8mp_blk_ctrl_domain *domain)
+{
+	switch (domain->id) {
+	case IMX8MP_HSIOBLK_PD_USB:
+		regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+		break;
+	case IMX8MP_HSIOBLK_PD_PCIE:
+		regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
+		break;
+	default:
+		break;
+	}
+}
+
+static int imx8mp_hsio_power_notifier(struct notifier_block *nb,
+				      unsigned long action, void *data)
+{
+	struct imx8mp_blk_ctrl *bc = container_of(nb, struct imx8mp_blk_ctrl,
+						 power_nb);
+	struct clk_bulk_data *usb_clk = bc->domains[IMX8MP_HSIOBLK_PD_USB].clks;
+	int num_clks = bc->domains[IMX8MP_HSIOBLK_PD_USB].data->num_clks;
+	int ret;
+
+	switch (action) {
+	case GENPD_NOTIFY_ON:
+		/*
+		 * enable USB clock for a moment for the power-on ADB handshake
+		 * to proceed
+		 */
+		ret = clk_bulk_prepare_enable(num_clks, usb_clk);
+		if (ret)
+			return NOTIFY_BAD;
+		regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+
+		udelay(5);
+
+		regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+		clk_bulk_disable_unprepare(num_clks, usb_clk);
+		break;
+	case GENPD_NOTIFY_PRE_OFF:
+		/* enable USB clock for the power-down ADB handshake to work */
+		ret = clk_bulk_prepare_enable(num_clks, usb_clk);
+		if (ret)
+			return NOTIFY_BAD;
+
+		regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+		break;
+	case GENPD_NOTIFY_OFF:
+		clk_bulk_disable_unprepare(num_clks, usb_clk);
+		break;
+	default:
+		break;
+	}
+
+	return NOTIFY_OK;
+}
+
+static const struct imx8mp_blk_ctrl_domain_data imx8mp_hsio_domain_data[] = {
+	[IMX8MP_HSIOBLK_PD_USB] = {
+		.name = "hsioblk-usb",
+		.clk_names = (const char *[]){ "usb" },
+		.num_clks = 1,
+		.gpc_name = "usb",
+	},
+	[IMX8MP_HSIOBLK_PD_USB_PHY1] = {
+		.name = "hsioblk-usb-phy1",
+		.gpc_name = "usb-phy1",
+	},
+	[IMX8MP_HSIOBLK_PD_USB_PHY2] = {
+		.name = "hsioblk-usb-phy2",
+		.gpc_name = "usb-phy2",
+	},
+	[IMX8MP_HSIOBLK_PD_PCIE] = {
+		.name = "hsioblk-pcie",
+		.clk_names = (const char *[]){ "pcie" },
+		.num_clks = 1,
+		.gpc_name = "pcie",
+	},
+	[IMX8MP_HSIOBLK_PD_PCIE_PHY] = {
+		.name = "hsioblk-pcie-phy",
+		.gpc_name = "pcie-phy",
+	},
+};
+
+static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = {
+	.max_reg = 0x24,
+	.power_on = imx8mp_hsio_blk_ctrl_power_on,
+	.power_off = imx8mp_hsio_blk_ctrl_power_off,
+	.power_notifier_fn = imx8mp_hsio_power_notifier,
+	.domains = imx8mp_hsio_domain_data,
+	.num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data),
+};
+
+static int imx8mp_blk_ctrl_power_on(struct generic_pm_domain *genpd)
+{
+	struct imx8mp_blk_ctrl_domain *domain = to_imx8mp_blk_ctrl_domain(genpd);
+	const struct imx8mp_blk_ctrl_domain_data *data = domain->data;
+	struct imx8mp_blk_ctrl *bc = domain->bc;
+	int ret;
+
+	/* make sure bus domain is awake */
+	ret = pm_runtime_resume_and_get(bc->bus_power_dev);
+	if (ret < 0) {
+		dev_err(bc->dev, "failed to power up bus domain\n");
+		return ret;
+	}
+
+	/* enable upstream clocks */
+	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);;
+	if (ret) {
+		dev_err(bc->dev, "failed to enable clocks\n");
+		goto bus_put;
+	}
+
+	/* domain specific blk-ctrl manipulation */
+	bc->power_on(bc, domain);
+
+	/* power up upstream GPC domain */
+	ret = pm_runtime_resume_and_get(domain->power_dev);
+	if (ret < 0) {
+		dev_err(bc->dev, "failed to power up peripheral domain\n");
+		goto clk_disable;
+	}
+
+	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
+
+	return 0;
+
+clk_disable:
+	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
+bus_put:
+	pm_runtime_put(bc->bus_power_dev);
+
+	return ret;
+}
+
+static int imx8mp_blk_ctrl_power_off(struct generic_pm_domain *genpd)
+{
+	struct imx8mp_blk_ctrl_domain *domain = to_imx8mp_blk_ctrl_domain(genpd);
+	const struct imx8mp_blk_ctrl_domain_data *data = domain->data;
+	struct imx8mp_blk_ctrl *bc = domain->bc;
+	int ret;
+
+	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);;
+	if (ret) {
+		dev_err(bc->dev, "failed to enable clocks\n");
+		return ret;
+	}
+
+	/* domain specific blk-ctrl manipulation */
+	bc->power_off(bc, domain);
+
+	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
+
+	/* power down upstream GPC domain */
+	pm_runtime_put(domain->power_dev);
+
+	/* allow bus domain to suspend */
+	pm_runtime_put(bc->bus_power_dev);
+
+	return 0;
+}
+
+static struct generic_pm_domain *
+imx8m_blk_ctrl_xlate(struct of_phandle_args *args, void *data)
+{
+	struct genpd_onecell_data *onecell_data = data;
+	unsigned int index = args->args[0];
+
+	if (args->args_count != 1 ||
+	    index >= onecell_data->num_domains)
+		return ERR_PTR(-EINVAL);
+
+	return onecell_data->domains[index];
+}
+
+static struct lock_class_key blk_ctrl_genpd_lock_class;
+
+static int imx8mp_blk_ctrl_probe(struct platform_device *pdev)
+{
+	const struct imx8mp_blk_ctrl_data *bc_data;
+	struct device *dev = &pdev->dev;
+	struct imx8mp_blk_ctrl *bc;
+	void __iomem *base;
+	int num_domains, i, ret;
+
+	struct regmap_config regmap_config = {
+		.reg_bits	= 32,
+		.val_bits	= 32,
+		.reg_stride	= 4,
+	};
+
+	bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
+	if (!bc)
+		return -ENOMEM;
+
+	bc->dev = dev;
+
+	bc_data = of_device_get_match_data(dev);
+	num_domains = bc_data->num_domains;
+
+	base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	regmap_config.max_register = bc_data->max_reg;
+	bc->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
+	if (IS_ERR(bc->regmap))
+		return dev_err_probe(dev, PTR_ERR(bc->regmap),
+				     "failed to init regmap\n");
+
+	bc->domains = devm_kcalloc(dev, num_domains,
+				   sizeof(struct imx8mp_blk_ctrl_domain),
+				   GFP_KERNEL);
+	if (!bc->domains)
+		return -ENOMEM;
+
+	bc->onecell_data.num_domains = num_domains;
+	bc->onecell_data.xlate = imx8m_blk_ctrl_xlate;
+	bc->onecell_data.domains =
+		devm_kcalloc(dev, num_domains,
+			     sizeof(struct generic_pm_domain *), GFP_KERNEL);
+	if (!bc->onecell_data.domains)
+		return -ENOMEM;
+
+	bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus");
+	if (IS_ERR(bc->bus_power_dev))
+		return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),
+				     "failed to attach bus power domain\n");
+
+	bc->power_off = bc_data->power_off;
+	bc->power_on = bc_data->power_on;
+
+	for (i = 0; i < num_domains; i++) {
+		const struct imx8mp_blk_ctrl_domain_data *data = &bc_data->domains[i];
+		struct imx8mp_blk_ctrl_domain *domain = &bc->domains[i];
+		int j;
+
+		domain->data = data;
+
+		for (j = 0; j < data->num_clks; j++)
+			domain->clks[j].id = data->clk_names[j];
+
+		ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks);
+		if (ret) {
+			dev_err_probe(dev, ret, "failed to get clock\n");
+			goto cleanup_pds;
+		}
+
+		domain->power_dev =
+			dev_pm_domain_attach_by_name(dev, data->gpc_name);
+		if (IS_ERR(domain->power_dev)) {
+			dev_err_probe(dev, PTR_ERR(domain->power_dev),
+				      "failed to attach power domain %s\n",
+				      data->gpc_name);
+			ret = PTR_ERR(domain->power_dev);
+			goto cleanup_pds;
+		}
+		dev_set_name(domain->power_dev, "%s", data->name);
+
+		domain->genpd.name = data->name;
+		domain->genpd.power_on = imx8mp_blk_ctrl_power_on;
+		domain->genpd.power_off = imx8mp_blk_ctrl_power_off;
+		domain->bc = bc;
+		domain->id = i;
+
+		ret = pm_genpd_init(&domain->genpd, NULL, true);
+		if (ret) {
+			dev_err_probe(dev, ret, "failed to init power domain\n");
+			dev_pm_domain_detach(domain->power_dev, true);
+			goto cleanup_pds;
+		}
+
+		/*
+		 * We use runtime PM to trigger power on/off of the upstream GPC
+		 * domain, as a strict hierarchical parent/child power domain
+		 * setup doesn't allow us to meet the sequencing requirements.
+		 * This means we have nested locking of genpd locks, without the
+		 * nesting being visible at the genpd level, so we need a
+		 * separate lock class to make lockdep aware of the fact that
+		 * this are separate domain locks that can be nested without a
+		 * self-deadlock.
+		 */
+		lockdep_set_class(&domain->genpd.mlock,
+				  &blk_ctrl_genpd_lock_class);
+
+		bc->onecell_data.domains[i] = &domain->genpd;
+	}
+
+	ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
+	if (ret) {
+		dev_err_probe(dev, ret, "failed to add power domain provider\n");
+		goto cleanup_pds;
+	}
+
+	bc->power_nb.notifier_call = bc_data->power_notifier_fn;
+	ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb);
+	if (ret) {
+		dev_err_probe(dev, ret, "failed to add power notifier\n");
+		goto cleanup_provider;
+	}
+
+	dev_set_drvdata(dev, bc);
+
+	return 0;
+
+cleanup_provider:
+	of_genpd_del_provider(dev->of_node);
+cleanup_pds:
+	for (i--; i >= 0; i--) {
+		pm_genpd_remove(&bc->domains[i].genpd);
+		dev_pm_domain_detach(bc->domains[i].power_dev, true);
+	}
+
+	dev_pm_domain_detach(bc->bus_power_dev, true);
+
+	return ret;
+}
+
+static int imx8mp_blk_ctrl_remove(struct platform_device *pdev)
+{
+	struct imx8mp_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
+	int i;
+
+	of_genpd_del_provider(pdev->dev.of_node);
+
+	for (i = 0; bc->onecell_data.num_domains; i++) {
+		struct imx8mp_blk_ctrl_domain *domain = &bc->domains[i];
+
+		pm_genpd_remove(&domain->genpd);
+		dev_pm_domain_detach(domain->power_dev, true);
+	}
+
+	dev_pm_genpd_remove_notifier(bc->bus_power_dev);
+
+	dev_pm_domain_detach(bc->bus_power_dev, true);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int imx8mp_blk_ctrl_suspend(struct device *dev)
+{
+	struct imx8mp_blk_ctrl *bc = dev_get_drvdata(dev);
+	int ret, i;
+
+	/*
+	 * This may look strange, but is done so the generic PM_SLEEP code
+	 * can power down our domains and more importantly power them up again
+	 * after resume, without tripping over our usage of runtime PM to
+	 * control the upstream GPC domains. Things happen in the right order
+	 * in the system suspend/resume paths due to the device parent/child
+	 * hierarchy.
+	 */
+	ret = pm_runtime_get_sync(bc->bus_power_dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(bc->bus_power_dev);
+		return ret;
+	}
+
+	for (i = 0; i < bc->onecell_data.num_domains; i++) {
+		struct imx8mp_blk_ctrl_domain *domain = &bc->domains[i];
+
+		ret = pm_runtime_get_sync(domain->power_dev);
+		if (ret < 0) {
+			pm_runtime_put_noidle(domain->power_dev);
+			goto out_fail;
+		}
+	}
+
+	return 0;
+
+out_fail:
+	for (i--; i >= 0; i--)
+		pm_runtime_put(bc->domains[i].power_dev);
+
+	pm_runtime_put(bc->bus_power_dev);
+
+	return ret;
+}
+
+static int imx8mp_blk_ctrl_resume(struct device *dev)
+{
+	struct imx8mp_blk_ctrl *bc = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < bc->onecell_data.num_domains; i++)
+		pm_runtime_put(bc->domains[i].power_dev);
+
+	pm_runtime_put(bc->bus_power_dev);
+
+	return 0;
+}
+#endif
+
+static const struct dev_pm_ops imx8mp_blk_ctrl_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(imx8mp_blk_ctrl_suspend,
+				imx8mp_blk_ctrl_resume)
+};
+
+static const struct of_device_id imx8mp_blk_ctrl_of_match[] = {
+	{
+		.compatible = "fsl,imx8mp-hsio-blk-ctrl",
+		.data = &imx8mp_hsio_blk_ctl_dev_data,
+	}, {
+		/* Sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match);
+
+static struct platform_driver imx8mp_blk_ctrl_driver = {
+	.probe = imx8mp_blk_ctrl_probe,
+	.remove = imx8mp_blk_ctrl_remove,
+	.driver = {
+		.name = "imx8mp-blk-ctrl",
+		.pm = &imx8mp_blk_ctrl_pm_ops,
+		.of_match_table = imx8mp_blk_ctrl_of_match,
+	},
+};
+module_platform_driver(imx8mp_blk_ctrl_driver);
-- 
2.30.2

[PATCH v4 03/11] dt-bindings: soc: Add i.MX8MP media block control DT bindings

[Lucas Stach]

From: Paul Elder <paul.elder@ideasonboard.com>

The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level
peripheral providing access to the NoC and ensuring proper power
sequencing of the peripherals within the MEDIAMIX domain. Add DT
bindings for it.

There is already a driver for block controls of other SoCs in the i.MX8M
family, so these bindings will expand upon that.

Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 104 ++++++++++++++++++
 include/dt-bindings/power/imx8mp-power.h      |  10 ++
 2 files changed, 114 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml

diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
new file mode 100644
index 000000000000..21d3ee486295
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MP Media Block Control
+
+maintainers:
+  - Paul Elder <paul.elder@ideasonboard.com>
+
+description:
+  The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
+  providing access to the NoC and ensuring proper power sequencing of the
+  peripherals within the MEDIAMIX domain.
+
+properties:
+  compatible:
+    items:
+      - const: fsl,imx8mp-media-blk-ctrl
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  power-domains:
+    maxItems: 10
+
+  power-domain-names:
+    items:
+      - const: bus
+      - const: mipi-dsi1
+      - const: mipi-csi1
+      - const: lcdif1
+      - const: isi
+      - const: mipi-csi2
+      - const: lcdif2
+      - const: isp
+      - const: dwe
+      - const: mipi-dsi2
+
+  clocks:
+    items:
+      - description: The APB clock
+      - description: The AXI clock
+      - description: The pixel clock for the first CSI2 receiver (aclk)
+      - description: The pixel clock for the second CSI2 receiver (aclk)
+      - description: The pixel clock for the first LCDIF (pix_clk)
+      - description: The pixel clock for the second LCDIF (pix_clk)
+      - description: The core clock for the ISP (clk)
+      - description: The MIPI-PHY reference clock used by DSI
+
+  clock-names:
+    items:
+      - const: apb
+      - const: axi
+      - const: cam1
+      - const: cam2
+      - const: disp1
+      - const: disp2
+      - const: isp
+      - const: phy
+
+required:
+  - compatible
+  - reg
+  - '#power-domain-cells'
+  - power-domains
+  - power-domain-names
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mp-clock.h>
+    #include <dt-bindings/power/imx8mp-power.h>
+
+    media_blk_ctl: blk-ctl@32ec0000 {
+        compatible = "fsl,imx8mp-media-blk-ctrl", "syscon";
+        reg = <0x32ec0000 0x138>;
+        power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>,
+                        <&mediamix_pd>, <&mediamix_pd>, <&mipi_phy2_pd>,
+                        <&mediamix_pd>, <&ispdwp_pd>, <&ispdwp_pd>,
+                        <&mipi_phy2_pd>;
+        power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
+                             "mipi-csi2", "lcdif2", "isp1", "dwe", "mipi-dsi2";
+        clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
+        clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2",
+                      "isp", "phy";
+        #power-domain-cells = <1>;
+    };
+...
diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h
index 9f90c40a2c6c..bc8458f1e725 100644
--- a/include/dt-bindings/power/imx8mp-power.h
+++ b/include/dt-bindings/power/imx8mp-power.h
@@ -32,4 +32,14 @@
 #define IMX8MP_HSIOBLK_PD_PCIE				3
 #define IMX8MP_HSIOBLK_PD_PCIE_PHY			4
 
+#define IMX8MP_MEDIABLK_PD_MIPI_DSI_1			0
+#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1			1
+#define IMX8MP_MEDIABLK_PD_LCDIF_1			2
+#define IMX8MP_MEDIABLK_PD_ISI				3
+#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2			4
+#define IMX8MP_MEDIABLK_PD_LCDIF_2			5
+#define IMX8MP_MEDIABLK_PD_ISP				6
+#define IMX8MP_MEDIABLK_PD_DWE				7
+#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2			8
+
 #endif
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 03/11] dt-bindings: soc: Add i.MX8MP media block control DT bindings

[Lucas Stach]

From: Paul Elder <paul.elder@ideasonboard.com>

The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level
peripheral providing access to the NoC and ensuring proper power
sequencing of the peripherals within the MEDIAMIX domain. Add DT
bindings for it.

There is already a driver for block controls of other SoCs in the i.MX8M
family, so these bindings will expand upon that.

Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 104 ++++++++++++++++++
 include/dt-bindings/power/imx8mp-power.h      |  10 ++
 2 files changed, 114 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml

diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
new file mode 100644
index 000000000000..21d3ee486295
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MP Media Block Control
+
+maintainers:
+  - Paul Elder <paul.elder@ideasonboard.com>
+
+description:
+  The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
+  providing access to the NoC and ensuring proper power sequencing of the
+  peripherals within the MEDIAMIX domain.
+
+properties:
+  compatible:
+    items:
+      - const: fsl,imx8mp-media-blk-ctrl
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  power-domains:
+    maxItems: 10
+
+  power-domain-names:
+    items:
+      - const: bus
+      - const: mipi-dsi1
+      - const: mipi-csi1
+      - const: lcdif1
+      - const: isi
+      - const: mipi-csi2
+      - const: lcdif2
+      - const: isp
+      - const: dwe
+      - const: mipi-dsi2
+
+  clocks:
+    items:
+      - description: The APB clock
+      - description: The AXI clock
+      - description: The pixel clock for the first CSI2 receiver (aclk)
+      - description: The pixel clock for the second CSI2 receiver (aclk)
+      - description: The pixel clock for the first LCDIF (pix_clk)
+      - description: The pixel clock for the second LCDIF (pix_clk)
+      - description: The core clock for the ISP (clk)
+      - description: The MIPI-PHY reference clock used by DSI
+
+  clock-names:
+    items:
+      - const: apb
+      - const: axi
+      - const: cam1
+      - const: cam2
+      - const: disp1
+      - const: disp2
+      - const: isp
+      - const: phy
+
+required:
+  - compatible
+  - reg
+  - '#power-domain-cells'
+  - power-domains
+  - power-domain-names
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mp-clock.h>
+    #include <dt-bindings/power/imx8mp-power.h>
+
+    media_blk_ctl: blk-ctl@32ec0000 {
+        compatible = "fsl,imx8mp-media-blk-ctrl", "syscon";
+        reg = <0x32ec0000 0x138>;
+        power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>,
+                        <&mediamix_pd>, <&mediamix_pd>, <&mipi_phy2_pd>,
+                        <&mediamix_pd>, <&ispdwp_pd>, <&ispdwp_pd>,
+                        <&mipi_phy2_pd>;
+        power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
+                             "mipi-csi2", "lcdif2", "isp1", "dwe", "mipi-dsi2";
+        clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
+        clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2",
+                      "isp", "phy";
+        #power-domain-cells = <1>;
+    };
+...
diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h
index 9f90c40a2c6c..bc8458f1e725 100644
--- a/include/dt-bindings/power/imx8mp-power.h
+++ b/include/dt-bindings/power/imx8mp-power.h
@@ -32,4 +32,14 @@
 #define IMX8MP_HSIOBLK_PD_PCIE				3
 #define IMX8MP_HSIOBLK_PD_PCIE_PHY			4
 
+#define IMX8MP_MEDIABLK_PD_MIPI_DSI_1			0
+#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1			1
+#define IMX8MP_MEDIABLK_PD_LCDIF_1			2
+#define IMX8MP_MEDIABLK_PD_ISI				3
+#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2			4
+#define IMX8MP_MEDIABLK_PD_LCDIF_2			5
+#define IMX8MP_MEDIABLK_PD_ISP				6
+#define IMX8MP_MEDIABLK_PD_DWE				7
+#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2			8
+
 #endif
-- 
2.30.2

[PATCH v4 04/11] soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl

[Lucas Stach]

From: Paul Elder <paul.elder@ideasonboard.com>

Add the description for the i.MX8MP media blk-ctrl.

Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de> # MX8MP LCDIF #1 and #2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/imx8m-blk-ctrl.c | 123 ++++++++++++++++++++++++++++++-
 1 file changed, 121 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
index 3071a8eca8ef..2b8c1e36a489 100644
--- a/drivers/soc/imx/imx8m-blk-ctrl.c
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -15,11 +15,12 @@
 
 #include <dt-bindings/power/imx8mm-power.h>
 #include <dt-bindings/power/imx8mn-power.h>
+#include <dt-bindings/power/imx8mp-power.h>
 #include <dt-bindings/power/imx8mq-power.h>
 
 #define BLK_SFT_RSTN	0x0
 #define BLK_CLK_EN	0x4
-#define BLK_MIPI_RESET_DIV	0x8 /* Mini/Nano DISPLAY_BLK_CTRL only */
+#define BLK_MIPI_RESET_DIV	0x8 /* Mini/Nano/Plus DISPLAY_BLK_CTRL only */
 
 struct imx8m_blk_ctrl_domain;
 
@@ -41,7 +42,7 @@ struct imx8m_blk_ctrl_domain_data {
 	u32 clk_mask;
 
 	/*
-	 * i.MX8M Mini and Nano have a third DISPLAY_BLK_CTRL register
+	 * i.MX8M Mini, Nano and Plus have a third DISPLAY_BLK_CTRL register
 	 * which is used to control the reset for the MIPI Phy.
 	 * Since it's only present in certain circumstances,
 	 * an if-statement should be used before setting and clearing this
@@ -591,6 +592,121 @@ static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {
 	.num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
 };
 
+static int imx8mp_media_power_notifier(struct notifier_block *nb,
+				unsigned long action, void *data)
+{
+	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
+						 power_nb);
+
+	if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
+		return NOTIFY_OK;
+
+	/* Enable bus clock and deassert bus reset */
+	regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));
+	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));
+
+	/*
+	 * On power up we have no software backchannel to the GPC to
+	 * wait for the ADB handshake to happen, so we just delay for a
+	 * bit. On power down the GPC driver waits for the handshake.
+	 */
+	if (action == GENPD_NOTIFY_ON)
+		udelay(5);
+
+	return NOTIFY_OK;
+}
+
+/*
+ * From i.MX 8M Plus Applications Processor Reference Manual, Rev. 1,
+ * section 13.2.2, 13.2.3
+ * isp-ahb and dwe are not in Figure 13-5. Media BLK_CTRL Clocks
+ */
+static const struct imx8m_blk_ctrl_domain_data imx8mp_media_blk_ctl_domain_data[] = {
+	[IMX8MP_MEDIABLK_PD_MIPI_DSI_1] = {
+		.name = "mediablk-mipi-dsi-1",
+		.clk_names = (const char *[]){ "apb", "phy", },
+		.num_clks = 2,
+		.gpc_name = "mipi-dsi1",
+		.rst_mask = BIT(0) | BIT(1),
+		.clk_mask = BIT(0) | BIT(1),
+		.mipi_phy_rst_mask = BIT(17),
+	},
+	[IMX8MP_MEDIABLK_PD_MIPI_CSI2_1] = {
+		.name = "mediablk-mipi-csi2-1",
+		.clk_names = (const char *[]){ "apb", "cam1" },
+		.num_clks = 2,
+		.gpc_name = "mipi-csi1",
+		.rst_mask = BIT(2) | BIT(3),
+		.clk_mask = BIT(2) | BIT(3),
+		.mipi_phy_rst_mask = BIT(16),
+	},
+	[IMX8MP_MEDIABLK_PD_LCDIF_1] = {
+		.name = "mediablk-lcdif-1",
+		.clk_names = (const char *[]){ "disp1", "apb", "axi", },
+		.num_clks = 3,
+		.gpc_name = "lcdif1",
+		.rst_mask = BIT(4) | BIT(5) | BIT(23),
+		.clk_mask = BIT(4) | BIT(5) | BIT(23),
+	},
+	[IMX8MP_MEDIABLK_PD_ISI] = {
+		.name = "mediablk-isi",
+		.clk_names = (const char *[]){ "axi", "apb" },
+		.num_clks = 2,
+		.gpc_name = "isi",
+		.rst_mask = BIT(6) | BIT(7),
+		.clk_mask = BIT(6) | BIT(7),
+	},
+	[IMX8MP_MEDIABLK_PD_MIPI_CSI2_2] = {
+		.name = "mediablk-mipi-csi2-2",
+		.clk_names = (const char *[]){ "apb", "cam2" },
+		.num_clks = 2,
+		.gpc_name = "mipi-csi2",
+		.rst_mask = BIT(9) | BIT(10),
+		.clk_mask = BIT(9) | BIT(10),
+		.mipi_phy_rst_mask = BIT(30),
+	},
+	[IMX8MP_MEDIABLK_PD_LCDIF_2] = {
+		.name = "mediablk-lcdif-2",
+		.clk_names = (const char *[]){ "disp1", "apb", "axi", },
+		.num_clks = 3,
+		.gpc_name = "lcdif2",
+		.rst_mask = BIT(11) | BIT(12) | BIT(24),
+		.clk_mask = BIT(11) | BIT(12) | BIT(24),
+	},
+	[IMX8MP_MEDIABLK_PD_ISP] = {
+		.name = "mediablk-isp",
+		.clk_names = (const char *[]){ "isp", "axi", "apb" },
+		.num_clks = 3,
+		.gpc_name = "isp",
+		.rst_mask = BIT(16) | BIT(17) | BIT(18),
+		.clk_mask = BIT(16) | BIT(17) | BIT(18),
+	},
+	[IMX8MP_MEDIABLK_PD_DWE] = {
+		.name = "mediablk-dwe",
+		.clk_names = (const char *[]){ "axi", "apb" },
+		.num_clks = 2,
+		.gpc_name = "dwe",
+		.rst_mask = BIT(19) | BIT(20) | BIT(21),
+		.clk_mask = BIT(19) | BIT(20) | BIT(21),
+	},
+	[IMX8MP_MEDIABLK_PD_MIPI_DSI_2] = {
+		.name = "mediablk-mipi-dsi-2",
+		.clk_names = (const char *[]){ "phy", },
+		.num_clks = 1,
+		.gpc_name = "mipi-dsi2",
+		.rst_mask = BIT(22),
+		.clk_mask = BIT(22),
+		.mipi_phy_rst_mask = BIT(29),
+	},
+};
+
+static const struct imx8m_blk_ctrl_data imx8mp_media_blk_ctl_dev_data = {
+	.max_reg = 0x138,
+	.power_notifier_fn = imx8mp_media_power_notifier,
+	.domains = imx8mp_media_blk_ctl_domain_data,
+	.num_domains = ARRAY_SIZE(imx8mp_media_blk_ctl_domain_data),
+};
+
 static int imx8mq_vpu_power_notifier(struct notifier_block *nb,
 				     unsigned long action, void *data)
 {
@@ -663,6 +779,9 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
 	}, {
 		.compatible = "fsl,imx8mn-disp-blk-ctrl",
 		.data = &imx8mn_disp_blk_ctl_dev_data
+	}, {
+		.compatible = "fsl,imx8mp-media-blk-ctrl",
+		.data = &imx8mp_media_blk_ctl_dev_data
 	}, {
 		.compatible = "fsl,imx8mq-vpu-blk-ctrl",
 		.data = &imx8mq_vpu_blk_ctl_dev_data
-- 
2.30.2


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[PATCH v4 04/11] soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl

[Lucas Stach]

From: Paul Elder <paul.elder@ideasonboard.com>

Add the description for the i.MX8MP media blk-ctrl.

Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de> # MX8MP LCDIF #1 and #2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/imx8m-blk-ctrl.c | 123 ++++++++++++++++++++++++++++++-
 1 file changed, 121 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
index 3071a8eca8ef..2b8c1e36a489 100644
--- a/drivers/soc/imx/imx8m-blk-ctrl.c
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -15,11 +15,12 @@
 
 #include <dt-bindings/power/imx8mm-power.h>
 #include <dt-bindings/power/imx8mn-power.h>
+#include <dt-bindings/power/imx8mp-power.h>
 #include <dt-bindings/power/imx8mq-power.h>
 
 #define BLK_SFT_RSTN	0x0
 #define BLK_CLK_EN	0x4
-#define BLK_MIPI_RESET_DIV	0x8 /* Mini/Nano DISPLAY_BLK_CTRL only */
+#define BLK_MIPI_RESET_DIV	0x8 /* Mini/Nano/Plus DISPLAY_BLK_CTRL only */
 
 struct imx8m_blk_ctrl_domain;
 
@@ -41,7 +42,7 @@ struct imx8m_blk_ctrl_domain_data {
 	u32 clk_mask;
 
 	/*
-	 * i.MX8M Mini and Nano have a third DISPLAY_BLK_CTRL register
+	 * i.MX8M Mini, Nano and Plus have a third DISPLAY_BLK_CTRL register
 	 * which is used to control the reset for the MIPI Phy.
 	 * Since it's only present in certain circumstances,
 	 * an if-statement should be used before setting and clearing this
@@ -591,6 +592,121 @@ static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {
 	.num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
 };
 
+static int imx8mp_media_power_notifier(struct notifier_block *nb,
+				unsigned long action, void *data)
+{
+	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
+						 power_nb);
+
+	if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
+		return NOTIFY_OK;
+
+	/* Enable bus clock and deassert bus reset */
+	regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));
+	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));
+
+	/*
+	 * On power up we have no software backchannel to the GPC to
+	 * wait for the ADB handshake to happen, so we just delay for a
+	 * bit. On power down the GPC driver waits for the handshake.
+	 */
+	if (action == GENPD_NOTIFY_ON)
+		udelay(5);
+
+	return NOTIFY_OK;
+}
+
+/*
+ * From i.MX 8M Plus Applications Processor Reference Manual, Rev. 1,
+ * section 13.2.2, 13.2.3
+ * isp-ahb and dwe are not in Figure 13-5. Media BLK_CTRL Clocks
+ */
+static const struct imx8m_blk_ctrl_domain_data imx8mp_media_blk_ctl_domain_data[] = {
+	[IMX8MP_MEDIABLK_PD_MIPI_DSI_1] = {
+		.name = "mediablk-mipi-dsi-1",
+		.clk_names = (const char *[]){ "apb", "phy", },
+		.num_clks = 2,
+		.gpc_name = "mipi-dsi1",
+		.rst_mask = BIT(0) | BIT(1),
+		.clk_mask = BIT(0) | BIT(1),
+		.mipi_phy_rst_mask = BIT(17),
+	},
+	[IMX8MP_MEDIABLK_PD_MIPI_CSI2_1] = {
+		.name = "mediablk-mipi-csi2-1",
+		.clk_names = (const char *[]){ "apb", "cam1" },
+		.num_clks = 2,
+		.gpc_name = "mipi-csi1",
+		.rst_mask = BIT(2) | BIT(3),
+		.clk_mask = BIT(2) | BIT(3),
+		.mipi_phy_rst_mask = BIT(16),
+	},
+	[IMX8MP_MEDIABLK_PD_LCDIF_1] = {
+		.name = "mediablk-lcdif-1",
+		.clk_names = (const char *[]){ "disp1", "apb", "axi", },
+		.num_clks = 3,
+		.gpc_name = "lcdif1",
+		.rst_mask = BIT(4) | BIT(5) | BIT(23),
+		.clk_mask = BIT(4) | BIT(5) | BIT(23),
+	},
+	[IMX8MP_MEDIABLK_PD_ISI] = {
+		.name = "mediablk-isi",
+		.clk_names = (const char *[]){ "axi", "apb" },
+		.num_clks = 2,
+		.gpc_name = "isi",
+		.rst_mask = BIT(6) | BIT(7),
+		.clk_mask = BIT(6) | BIT(7),
+	},
+	[IMX8MP_MEDIABLK_PD_MIPI_CSI2_2] = {
+		.name = "mediablk-mipi-csi2-2",
+		.clk_names = (const char *[]){ "apb", "cam2" },
+		.num_clks = 2,
+		.gpc_name = "mipi-csi2",
+		.rst_mask = BIT(9) | BIT(10),
+		.clk_mask = BIT(9) | BIT(10),
+		.mipi_phy_rst_mask = BIT(30),
+	},
+	[IMX8MP_MEDIABLK_PD_LCDIF_2] = {
+		.name = "mediablk-lcdif-2",
+		.clk_names = (const char *[]){ "disp1", "apb", "axi", },
+		.num_clks = 3,
+		.gpc_name = "lcdif2",
+		.rst_mask = BIT(11) | BIT(12) | BIT(24),
+		.clk_mask = BIT(11) | BIT(12) | BIT(24),
+	},
+	[IMX8MP_MEDIABLK_PD_ISP] = {
+		.name = "mediablk-isp",
+		.clk_names = (const char *[]){ "isp", "axi", "apb" },
+		.num_clks = 3,
+		.gpc_name = "isp",
+		.rst_mask = BIT(16) | BIT(17) | BIT(18),
+		.clk_mask = BIT(16) | BIT(17) | BIT(18),
+	},
+	[IMX8MP_MEDIABLK_PD_DWE] = {
+		.name = "mediablk-dwe",
+		.clk_names = (const char *[]){ "axi", "apb" },
+		.num_clks = 2,
+		.gpc_name = "dwe",
+		.rst_mask = BIT(19) | BIT(20) | BIT(21),
+		.clk_mask = BIT(19) | BIT(20) | BIT(21),
+	},
+	[IMX8MP_MEDIABLK_PD_MIPI_DSI_2] = {
+		.name = "mediablk-mipi-dsi-2",
+		.clk_names = (const char *[]){ "phy", },
+		.num_clks = 1,
+		.gpc_name = "mipi-dsi2",
+		.rst_mask = BIT(22),
+		.clk_mask = BIT(22),
+		.mipi_phy_rst_mask = BIT(29),
+	},
+};
+
+static const struct imx8m_blk_ctrl_data imx8mp_media_blk_ctl_dev_data = {
+	.max_reg = 0x138,
+	.power_notifier_fn = imx8mp_media_power_notifier,
+	.domains = imx8mp_media_blk_ctl_domain_data,
+	.num_domains = ARRAY_SIZE(imx8mp_media_blk_ctl_domain_data),
+};
+
 static int imx8mq_vpu_power_notifier(struct notifier_block *nb,
 				     unsigned long action, void *data)
 {
@@ -663,6 +779,9 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
 	}, {
 		.compatible = "fsl,imx8mn-disp-blk-ctrl",
 		.data = &imx8mn_disp_blk_ctl_dev_data
+	}, {
+		.compatible = "fsl,imx8mp-media-blk-ctrl",
+		.data = &imx8mp_media_blk_ctl_dev_data
 	}, {
 		.compatible = "fsl,imx8mq-vpu-blk-ctrl",
 		.data = &imx8mq_vpu_blk_ctl_dev_data
-- 
2.30.2

[PATCH v4 05/11] dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains

[Lucas Stach]

This adds the defines for the power domains provided by the HDMI
blk-ctrl on the i.MX8MP.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 include/dt-bindings/power/imx8mp-power.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h
index bc8458f1e725..7789bcca3223 100644
--- a/include/dt-bindings/power/imx8mp-power.h
+++ b/include/dt-bindings/power/imx8mp-power.h
@@ -42,4 +42,12 @@
 #define IMX8MP_MEDIABLK_PD_DWE				7
 #define IMX8MP_MEDIABLK_PD_MIPI_DSI_2			8
 
+#define IMX8MP_HDMIBLK_PD_IRQSTEER			0
+#define IMX8MP_HDMIBLK_PD_LCDIF				1
+#define IMX8MP_HDMIBLK_PD_PAI				2
+#define IMX8MP_HDMIBLK_PD_PVI				3
+#define IMX8MP_HDMIBLK_PD_TRNG				4
+#define IMX8MP_HDMIBLK_PD_HDMI_TX			5
+#define IMX8MP_HDMIBLK_PD_HDMI_TX_PHY			6
+
 #endif
-- 
2.30.2


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[PATCH v4 05/11] dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains

[Lucas Stach]

This adds the defines for the power domains provided by the HDMI
blk-ctrl on the i.MX8MP.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 include/dt-bindings/power/imx8mp-power.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h
index bc8458f1e725..7789bcca3223 100644
--- a/include/dt-bindings/power/imx8mp-power.h
+++ b/include/dt-bindings/power/imx8mp-power.h
@@ -42,4 +42,12 @@
 #define IMX8MP_MEDIABLK_PD_DWE				7
 #define IMX8MP_MEDIABLK_PD_MIPI_DSI_2			8
 
+#define IMX8MP_HDMIBLK_PD_IRQSTEER			0
+#define IMX8MP_HDMIBLK_PD_LCDIF				1
+#define IMX8MP_HDMIBLK_PD_PAI				2
+#define IMX8MP_HDMIBLK_PD_PVI				3
+#define IMX8MP_HDMIBLK_PD_TRNG				4
+#define IMX8MP_HDMIBLK_PD_HDMI_TX			5
+#define IMX8MP_HDMIBLK_PD_HDMI_TX_PHY			6
+
 #endif
-- 
2.30.2

[PATCH v4 06/11] dt-bindings: soc: add binding for i.MX8MP HDMI blk-ctrl

[Lucas Stach]

Add the DT binding for the HDMI blk-ctrl found on the i.MX8MP SoC.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml     | 84 +++++++++++++++++++
 1 file changed, 84 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml

diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
new file mode 100644
index 000000000000..563e1d0e327f
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MP HDMI blk-ctrl
+
+maintainers:
+  - Lucas Stach <l.stach@pengutronix.de>
+
+description:
+  The i.MX8MP HDMMI blk-ctrl is a top-level peripheral providing access to
+  the NoC and ensuring proper power sequencing of the display pipeline
+  peripherals located in the HDMI domain of the SoC.
+
+properties:
+  compatible:
+    items:
+      - const: fsl,imx8mp-hdmi-blk-ctrl
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  power-domains:
+    minItems: 8
+    maxItems: 8
+
+  power-domain-names:
+    items:
+      - const: bus
+      - const: irqsteer
+      - const: lcdif
+      - const: pai
+      - const: pvi
+      - const: trng
+      - const: hdmi-tx
+      - const: hdmi-tx-phy
+
+  clocks:
+    minItems: 4
+    maxItems: 4
+
+  clock-names:
+    items:
+      - const: apb
+      - const: axi
+      - const: ref_266m
+      - const: ref_24m
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - power-domain-names
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mp-clock.h>
+    #include <dt-bindings/power/imx8mp-power.h>
+
+    blk-ctrl@32fc0000 {
+        compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";
+        reg = <0x32fc0000 0x23c>;
+        clocks = <&clk IMX8MP_CLK_HDMI_APB>,
+                 <&clk IMX8MP_CLK_HDMI_ROOT>,
+                 <&clk IMX8MP_CLK_HDMI_REF_266M>,
+                 <&clk IMX8MP_CLK_HDMI_24M>;
+        clock-names = "apb", "axi", "ref_266m", "ref_24m";
+        power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>,
+                        <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>,
+                        <&pgc_hdmimix>, <&pgc_hdmi_phy>;
+        power-domain-names = "bus", "irqsteer", "lcdif", "pai", "pvi", "trng",
+                             "hdmi-tx", "hdmi-tx-phy";
+        #power-domain-cells = <1>;
+    };
-- 
2.30.2


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[PATCH v4 06/11] dt-bindings: soc: add binding for i.MX8MP HDMI blk-ctrl

[Lucas Stach]

Add the DT binding for the HDMI blk-ctrl found on the i.MX8MP SoC.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml     | 84 +++++++++++++++++++
 1 file changed, 84 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml

diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
new file mode 100644
index 000000000000..563e1d0e327f
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MP HDMI blk-ctrl
+
+maintainers:
+  - Lucas Stach <l.stach@pengutronix.de>
+
+description:
+  The i.MX8MP HDMMI blk-ctrl is a top-level peripheral providing access to
+  the NoC and ensuring proper power sequencing of the display pipeline
+  peripherals located in the HDMI domain of the SoC.
+
+properties:
+  compatible:
+    items:
+      - const: fsl,imx8mp-hdmi-blk-ctrl
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  power-domains:
+    minItems: 8
+    maxItems: 8
+
+  power-domain-names:
+    items:
+      - const: bus
+      - const: irqsteer
+      - const: lcdif
+      - const: pai
+      - const: pvi
+      - const: trng
+      - const: hdmi-tx
+      - const: hdmi-tx-phy
+
+  clocks:
+    minItems: 4
+    maxItems: 4
+
+  clock-names:
+    items:
+      - const: apb
+      - const: axi
+      - const: ref_266m
+      - const: ref_24m
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - power-domain-names
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mp-clock.h>
+    #include <dt-bindings/power/imx8mp-power.h>
+
+    blk-ctrl@32fc0000 {
+        compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";
+        reg = <0x32fc0000 0x23c>;
+        clocks = <&clk IMX8MP_CLK_HDMI_APB>,
+                 <&clk IMX8MP_CLK_HDMI_ROOT>,
+                 <&clk IMX8MP_CLK_HDMI_REF_266M>,
+                 <&clk IMX8MP_CLK_HDMI_24M>;
+        clock-names = "apb", "axi", "ref_266m", "ref_24m";
+        power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>,
+                        <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>,
+                        <&pgc_hdmimix>, <&pgc_hdmi_phy>;
+        power-domain-names = "bus", "irqsteer", "lcdif", "pai", "pvi", "trng",
+                             "hdmi-tx", "hdmi-tx-phy";
+        #power-domain-cells = <1>;
+    };
-- 
2.30.2

[PATCH v4 07/11] soc: imx: add i.MX8MP HDMI blk-ctrl

[Lucas Stach]

This adds driver support for the HDMI blk-ctrl found on the
i.MX8MP SoC.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/imx8mp-blk-ctrl.c | 193 ++++++++++++++++++++++++++++++
 1 file changed, 193 insertions(+)

diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
index 97cc8f08911e..f5692782bbdf 100644
--- a/drivers/soc/imx/imx8mp-blk-ctrl.c
+++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
@@ -174,6 +174,196 @@ static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = {
 	.num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data),
 };
 
+#define HDMI_RTX_RESET_CTL0	0x20
+#define HDMI_RTX_CLK_CTL0	0x40
+#define HDMI_RTX_CLK_CTL1	0x50
+#define HDMI_RTX_CLK_CTL2	0x60
+#define HDMI_RTX_CLK_CTL3	0x70
+#define HDMI_RTX_CLK_CTL4	0x80
+#define HDMI_TX_CONTROL0	0x200
+
+static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
+					  struct imx8mp_blk_ctrl_domain *domain)
+{
+	switch (domain->id) {
+	case IMX8MP_HDMIBLK_PD_IRQSTEER:
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9));
+		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));
+		break;
+	case IMX8MP_HDMIBLK_PD_LCDIF:
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
+				BIT(7) | BIT(16) | BIT(17) | BIT(18) |
+				BIT(19) | BIT(20));
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
+		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
+				BIT(4) | BIT(5) | BIT(6));
+		break;
+	case IMX8MP_HDMIBLK_PD_PAI:
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17));
+		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18));
+		break;
+	case IMX8MP_HDMIBLK_PD_PVI:
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28));
+		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22));
+		break;
+	case IMX8MP_HDMIBLK_PD_TRNG:
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30));
+		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20));
+		break;
+	case IMX8MP_HDMIBLK_PD_HDMI_TX:
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
+				BIT(2) | BIT(4) | BIT(5));
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
+				BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
+				BIT(18) | BIT(19) | BIT(20) | BIT(21));
+		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
+				BIT(7) | BIT(10) | BIT(11));
+		regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
+		break;
+	case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
+		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
+		regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
+		break;
+	default:
+		break;
+	}
+}
+
+static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
+					   struct imx8mp_blk_ctrl_domain *domain)
+{
+	switch (domain->id) {
+	case IMX8MP_HDMIBLK_PD_IRQSTEER:
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));
+		break;
+	case IMX8MP_HDMIBLK_PD_LCDIF:
+		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
+				  BIT(4) | BIT(5) | BIT(6));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
+				  BIT(7) | BIT(16) | BIT(17) | BIT(18) |
+				  BIT(19) | BIT(20));
+		break;
+	case IMX8MP_HDMIBLK_PD_PAI:
+		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17));
+		break;
+	case IMX8MP_HDMIBLK_PD_PVI:
+		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28));
+		break;
+	case IMX8MP_HDMIBLK_PD_TRNG:
+		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30));
+		break;
+	case IMX8MP_HDMIBLK_PD_HDMI_TX:
+		regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
+				  BIT(7) | BIT(10) | BIT(11));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
+				  BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
+				  BIT(18) | BIT(19) | BIT(20) | BIT(21));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
+				  BIT(2) | BIT(4) | BIT(5));
+		break;
+	case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
+		regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
+		break;
+	default:
+		break;
+	}
+}
+
+static int imx8mp_hdmi_power_notifier(struct notifier_block *nb,
+				      unsigned long action, void *data)
+{
+	struct imx8mp_blk_ctrl *bc = container_of(nb, struct imx8mp_blk_ctrl,
+						 power_nb);
+
+	if (action != GENPD_NOTIFY_ON)
+		return NOTIFY_OK;
+
+	/*
+	 * Contrary to other blk-ctrls the reset and clock don't clear when the
+	 * power domain is powered down. To ensure the proper reset pulsing,
+	 * first clear them all to asserted state, then enable the bus clocks
+	 * and then release the ADB reset.
+	 */
+	regmap_write(bc->regmap, HDMI_RTX_RESET_CTL0, 0x0);
+	regmap_write(bc->regmap, HDMI_RTX_CLK_CTL0, 0x0);
+	regmap_write(bc->regmap, HDMI_RTX_CLK_CTL1, 0x0);
+	regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
+			BIT(0) | BIT(1) | BIT(10));
+	regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(0));
+
+	/*
+	 * On power up we have no software backchannel to the GPC to
+	 * wait for the ADB handshake to happen, so we just delay for a
+	 * bit. On power down the GPC driver waits for the handshake.
+	 */
+	udelay(5);
+
+	return NOTIFY_OK;
+}
+
+static const struct imx8mp_blk_ctrl_domain_data imx8mp_hdmi_domain_data[] = {
+	[IMX8MP_HDMIBLK_PD_IRQSTEER] = {
+		.name = "hdmiblk-irqsteer",
+		.clk_names = (const char *[]){ "apb" },
+		.num_clks = 1,
+		.gpc_name = "irqsteer",
+	},
+	[IMX8MP_HDMIBLK_PD_LCDIF] = {
+		.name = "hdmiblk-lcdif",
+		.clk_names = (const char *[]){ "axi", "apb" },
+		.num_clks = 2,
+		.gpc_name = "lcdif",
+	},
+	[IMX8MP_HDMIBLK_PD_PAI] = {
+		.name = "hdmiblk-pai",
+		.clk_names = (const char *[]){ "apb" },
+		.num_clks = 1,
+		.gpc_name = "pai",
+	},
+	[IMX8MP_HDMIBLK_PD_PVI] = {
+		.name = "hdmiblk-pvi",
+		.clk_names = (const char *[]){ "apb" },
+		.num_clks = 1,
+		.gpc_name = "pvi",
+	},
+	[IMX8MP_HDMIBLK_PD_TRNG] = {
+		.name = "hdmiblk-trng",
+		.clk_names = (const char *[]){ "apb" },
+		.num_clks = 1,
+		.gpc_name = "trng",
+	},
+	[IMX8MP_HDMIBLK_PD_HDMI_TX] = {
+		.name = "hdmiblk-hdmi-tx",
+		.clk_names = (const char *[]){ "apb", "ref_266m" },
+		.num_clks = 2,
+		.gpc_name = "hdmi-tx",
+	},
+	[IMX8MP_HDMIBLK_PD_HDMI_TX_PHY] = {
+		.name = "hdmiblk-hdmi-tx-phy",
+		.clk_names = (const char *[]){ "apb", "ref_24m" },
+		.num_clks = 2,
+		.gpc_name = "hdmi-tx-phy",
+	},
+};
+
+static const struct imx8mp_blk_ctrl_data imx8mp_hdmi_blk_ctl_dev_data = {
+	.max_reg = 0x23c,
+	.power_on = imx8mp_hdmi_blk_ctrl_power_on,
+	.power_off = imx8mp_hdmi_blk_ctrl_power_off,
+	.power_notifier_fn = imx8mp_hdmi_power_notifier,
+	.domains = imx8mp_hdmi_domain_data,
+	.num_domains = ARRAY_SIZE(imx8mp_hdmi_domain_data),
+};
+
 static int imx8mp_blk_ctrl_power_on(struct generic_pm_domain *genpd)
 {
 	struct imx8mp_blk_ctrl_domain *domain = to_imx8mp_blk_ctrl_domain(genpd);
@@ -485,6 +675,9 @@ static const struct of_device_id imx8mp_blk_ctrl_of_match[] = {
 	{
 		.compatible = "fsl,imx8mp-hsio-blk-ctrl",
 		.data = &imx8mp_hsio_blk_ctl_dev_data,
+	}, {
+		.compatible = "fsl,imx8mp-hdmi-blk-ctrl",
+		.data = &imx8mp_hdmi_blk_ctl_dev_data,
 	}, {
 		/* Sentinel */
 	}
-- 
2.30.2


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 07/11] soc: imx: add i.MX8MP HDMI blk-ctrl

[Lucas Stach]

This adds driver support for the HDMI blk-ctrl found on the
i.MX8MP SoC.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/soc/imx/imx8mp-blk-ctrl.c | 193 ++++++++++++++++++++++++++++++
 1 file changed, 193 insertions(+)

diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
index 97cc8f08911e..f5692782bbdf 100644
--- a/drivers/soc/imx/imx8mp-blk-ctrl.c
+++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
@@ -174,6 +174,196 @@ static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = {
 	.num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data),
 };
 
+#define HDMI_RTX_RESET_CTL0	0x20
+#define HDMI_RTX_CLK_CTL0	0x40
+#define HDMI_RTX_CLK_CTL1	0x50
+#define HDMI_RTX_CLK_CTL2	0x60
+#define HDMI_RTX_CLK_CTL3	0x70
+#define HDMI_RTX_CLK_CTL4	0x80
+#define HDMI_TX_CONTROL0	0x200
+
+static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
+					  struct imx8mp_blk_ctrl_domain *domain)
+{
+	switch (domain->id) {
+	case IMX8MP_HDMIBLK_PD_IRQSTEER:
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9));
+		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));
+		break;
+	case IMX8MP_HDMIBLK_PD_LCDIF:
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
+				BIT(7) | BIT(16) | BIT(17) | BIT(18) |
+				BIT(19) | BIT(20));
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
+		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
+				BIT(4) | BIT(5) | BIT(6));
+		break;
+	case IMX8MP_HDMIBLK_PD_PAI:
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17));
+		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18));
+		break;
+	case IMX8MP_HDMIBLK_PD_PVI:
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28));
+		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22));
+		break;
+	case IMX8MP_HDMIBLK_PD_TRNG:
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30));
+		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20));
+		break;
+	case IMX8MP_HDMIBLK_PD_HDMI_TX:
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
+				BIT(2) | BIT(4) | BIT(5));
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
+				BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
+				BIT(18) | BIT(19) | BIT(20) | BIT(21));
+		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
+				BIT(7) | BIT(10) | BIT(11));
+		regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
+		break;
+	case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
+		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
+		regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
+		break;
+	default:
+		break;
+	}
+}
+
+static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
+					   struct imx8mp_blk_ctrl_domain *domain)
+{
+	switch (domain->id) {
+	case IMX8MP_HDMIBLK_PD_IRQSTEER:
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));
+		break;
+	case IMX8MP_HDMIBLK_PD_LCDIF:
+		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
+				  BIT(4) | BIT(5) | BIT(6));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
+				  BIT(7) | BIT(16) | BIT(17) | BIT(18) |
+				  BIT(19) | BIT(20));
+		break;
+	case IMX8MP_HDMIBLK_PD_PAI:
+		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17));
+		break;
+	case IMX8MP_HDMIBLK_PD_PVI:
+		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28));
+		break;
+	case IMX8MP_HDMIBLK_PD_TRNG:
+		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30));
+		break;
+	case IMX8MP_HDMIBLK_PD_HDMI_TX:
+		regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
+				  BIT(7) | BIT(10) | BIT(11));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1,
+				  BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
+				  BIT(18) | BIT(19) | BIT(20) | BIT(21));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
+				  BIT(2) | BIT(4) | BIT(5));
+		break;
+	case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
+		regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
+		break;
+	default:
+		break;
+	}
+}
+
+static int imx8mp_hdmi_power_notifier(struct notifier_block *nb,
+				      unsigned long action, void *data)
+{
+	struct imx8mp_blk_ctrl *bc = container_of(nb, struct imx8mp_blk_ctrl,
+						 power_nb);
+
+	if (action != GENPD_NOTIFY_ON)
+		return NOTIFY_OK;
+
+	/*
+	 * Contrary to other blk-ctrls the reset and clock don't clear when the
+	 * power domain is powered down. To ensure the proper reset pulsing,
+	 * first clear them all to asserted state, then enable the bus clocks
+	 * and then release the ADB reset.
+	 */
+	regmap_write(bc->regmap, HDMI_RTX_RESET_CTL0, 0x0);
+	regmap_write(bc->regmap, HDMI_RTX_CLK_CTL0, 0x0);
+	regmap_write(bc->regmap, HDMI_RTX_CLK_CTL1, 0x0);
+	regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
+			BIT(0) | BIT(1) | BIT(10));
+	regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(0));
+
+	/*
+	 * On power up we have no software backchannel to the GPC to
+	 * wait for the ADB handshake to happen, so we just delay for a
+	 * bit. On power down the GPC driver waits for the handshake.
+	 */
+	udelay(5);
+
+	return NOTIFY_OK;
+}
+
+static const struct imx8mp_blk_ctrl_domain_data imx8mp_hdmi_domain_data[] = {
+	[IMX8MP_HDMIBLK_PD_IRQSTEER] = {
+		.name = "hdmiblk-irqsteer",
+		.clk_names = (const char *[]){ "apb" },
+		.num_clks = 1,
+		.gpc_name = "irqsteer",
+	},
+	[IMX8MP_HDMIBLK_PD_LCDIF] = {
+		.name = "hdmiblk-lcdif",
+		.clk_names = (const char *[]){ "axi", "apb" },
+		.num_clks = 2,
+		.gpc_name = "lcdif",
+	},
+	[IMX8MP_HDMIBLK_PD_PAI] = {
+		.name = "hdmiblk-pai",
+		.clk_names = (const char *[]){ "apb" },
+		.num_clks = 1,
+		.gpc_name = "pai",
+	},
+	[IMX8MP_HDMIBLK_PD_PVI] = {
+		.name = "hdmiblk-pvi",
+		.clk_names = (const char *[]){ "apb" },
+		.num_clks = 1,
+		.gpc_name = "pvi",
+	},
+	[IMX8MP_HDMIBLK_PD_TRNG] = {
+		.name = "hdmiblk-trng",
+		.clk_names = (const char *[]){ "apb" },
+		.num_clks = 1,
+		.gpc_name = "trng",
+	},
+	[IMX8MP_HDMIBLK_PD_HDMI_TX] = {
+		.name = "hdmiblk-hdmi-tx",
+		.clk_names = (const char *[]){ "apb", "ref_266m" },
+		.num_clks = 2,
+		.gpc_name = "hdmi-tx",
+	},
+	[IMX8MP_HDMIBLK_PD_HDMI_TX_PHY] = {
+		.name = "hdmiblk-hdmi-tx-phy",
+		.clk_names = (const char *[]){ "apb", "ref_24m" },
+		.num_clks = 2,
+		.gpc_name = "hdmi-tx-phy",
+	},
+};
+
+static const struct imx8mp_blk_ctrl_data imx8mp_hdmi_blk_ctl_dev_data = {
+	.max_reg = 0x23c,
+	.power_on = imx8mp_hdmi_blk_ctrl_power_on,
+	.power_off = imx8mp_hdmi_blk_ctrl_power_off,
+	.power_notifier_fn = imx8mp_hdmi_power_notifier,
+	.domains = imx8mp_hdmi_domain_data,
+	.num_domains = ARRAY_SIZE(imx8mp_hdmi_domain_data),
+};
+
 static int imx8mp_blk_ctrl_power_on(struct generic_pm_domain *genpd)
 {
 	struct imx8mp_blk_ctrl_domain *domain = to_imx8mp_blk_ctrl_domain(genpd);
@@ -485,6 +675,9 @@ static const struct of_device_id imx8mp_blk_ctrl_of_match[] = {
 	{
 		.compatible = "fsl,imx8mp-hsio-blk-ctrl",
 		.data = &imx8mp_hsio_blk_ctl_dev_data,
+	}, {
+		.compatible = "fsl,imx8mp-hdmi-blk-ctrl",
+		.data = &imx8mp_hdmi_blk_ctl_dev_data,
 	}, {
 		/* Sentinel */
 	}
-- 
2.30.2

[PATCH v4 08/11] arm64: dts: imx8mp: add HSIO power-domains

[Lucas Stach]

This adds the GPC and HSIO blk-ctrl nodes providing power control for
the high-speed (USB and PCIe) IOs.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 57 ++++++++++++++++++++---
 1 file changed, 51 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index afd36374dccb..edf2d8f5e22e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -488,6 +488,21 @@ pgc {
 					#address-cells = <1>;
 					#size-cells = <0>;
 
+					pgc_pcie_phy: power-domain@1 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
+					};
+
+					pgc_usb1_phy: power-domain@2 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
+					};
+
+					pgc_usb2_phy: power-domain@3 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
+					};
+
 					pgc_gpu2d: power-domain@6 {
 						#power-domain-cells = <0>;
 						reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
@@ -514,6 +529,16 @@ pgc_gpu3d: power-domain@9 {
 							 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
 						power-domains = <&pgc_gpumix>;
 					};
+
+					pgc_hsiomix: power-domains@17 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
+						clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+							 <&clk IMX8MP_CLK_HSIO_ROOT>;
+						assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+						assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+						assigned-clock-rates = <500000000>;
+					};
 				};
 			};
 		};
@@ -933,6 +958,28 @@ eqos: ethernet@30bf0000 {
 			};
 		};
 
+		aips4: bus@32c00000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			reg = <0x32c00000 0x400000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			hsio_blk_ctrl: blk-ctrl@32f10000 {
+				compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
+				reg = <0x32f10000 0x24>;
+				clocks = <&clk IMX8MP_CLK_USB_ROOT>,
+					 <&clk IMX8MP_CLK_PCIE_ROOT>;
+				clock-names = "usb", "pcie";
+				power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
+						<&pgc_usb1_phy>, <&pgc_usb2_phy>,
+						<&pgc_hsiomix>, <&pgc_pcie_phy>;
+				power-domain-names = "bus", "usb", "usb-phy1",
+						     "usb-phy2", "pcie", "pcie-phy";
+				#power-domain-cells = <1>;
+			};
+		};
+
 		gpu3d: gpu@38000000 {
 			compatible = "vivante,gc";
 			reg = <0x38000000 0x8000>;
@@ -987,6 +1034,7 @@ usb3_phy0: usb-phy@381f0040 {
 			clock-names = "phy";
 			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
 			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
 			#phy-cells = <0>;
 			status = "disabled";
 		};
@@ -999,6 +1047,7 @@ usb3_0: usb@32f10100 {
 				 <&clk IMX8MP_CLK_USB_ROOT>;
 			clock-names = "hsio", "suspend";
 			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			dma-ranges = <0x40000000 0x40000000 0xc0000000>;
@@ -1012,9 +1061,6 @@ usb_dwc3_0: usb@38100000 {
 					 <&clk IMX8MP_CLK_USB_CORE_REF>,
 					 <&clk IMX8MP_CLK_USB_ROOT>;
 				clock-names = "bus_early", "ref", "suspend";
-				assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
-				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
-				assigned-clock-rates = <500000000>;
 				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 				phys = <&usb3_phy0>, <&usb3_phy0>;
 				phy-names = "usb2-phy", "usb3-phy";
@@ -1030,6 +1076,7 @@ usb3_phy1: usb-phy@382f0040 {
 			clock-names = "phy";
 			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
 			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
 			#phy-cells = <0>;
 			status = "disabled";
 		};
@@ -1042,6 +1089,7 @@ usb3_1: usb@32f10108 {
 				 <&clk IMX8MP_CLK_USB_ROOT>;
 			clock-names = "hsio", "suspend";
 			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			dma-ranges = <0x40000000 0x40000000 0xc0000000>;
@@ -1055,9 +1103,6 @@ usb_dwc3_1: usb@38200000 {
 					 <&clk IMX8MP_CLK_USB_CORE_REF>,
 					 <&clk IMX8MP_CLK_USB_ROOT>;
 				clock-names = "bus_early", "ref", "suspend";
-				assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
-				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
-				assigned-clock-rates = <500000000>;
 				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 				phys = <&usb3_phy1>, <&usb3_phy1>;
 				phy-names = "usb2-phy", "usb3-phy";
-- 
2.30.2


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[PATCH v4 08/11] arm64: dts: imx8mp: add HSIO power-domains

[Lucas Stach]

This adds the GPC and HSIO blk-ctrl nodes providing power control for
the high-speed (USB and PCIe) IOs.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 57 ++++++++++++++++++++---
 1 file changed, 51 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index afd36374dccb..edf2d8f5e22e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -488,6 +488,21 @@ pgc {
 					#address-cells = <1>;
 					#size-cells = <0>;
 
+					pgc_pcie_phy: power-domain@1 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
+					};
+
+					pgc_usb1_phy: power-domain@2 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
+					};
+
+					pgc_usb2_phy: power-domain@3 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
+					};
+
 					pgc_gpu2d: power-domain@6 {
 						#power-domain-cells = <0>;
 						reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
@@ -514,6 +529,16 @@ pgc_gpu3d: power-domain@9 {
 							 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
 						power-domains = <&pgc_gpumix>;
 					};
+
+					pgc_hsiomix: power-domains@17 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
+						clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+							 <&clk IMX8MP_CLK_HSIO_ROOT>;
+						assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+						assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+						assigned-clock-rates = <500000000>;
+					};
 				};
 			};
 		};
@@ -933,6 +958,28 @@ eqos: ethernet@30bf0000 {
 			};
 		};
 
+		aips4: bus@32c00000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			reg = <0x32c00000 0x400000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			hsio_blk_ctrl: blk-ctrl@32f10000 {
+				compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
+				reg = <0x32f10000 0x24>;
+				clocks = <&clk IMX8MP_CLK_USB_ROOT>,
+					 <&clk IMX8MP_CLK_PCIE_ROOT>;
+				clock-names = "usb", "pcie";
+				power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
+						<&pgc_usb1_phy>, <&pgc_usb2_phy>,
+						<&pgc_hsiomix>, <&pgc_pcie_phy>;
+				power-domain-names = "bus", "usb", "usb-phy1",
+						     "usb-phy2", "pcie", "pcie-phy";
+				#power-domain-cells = <1>;
+			};
+		};
+
 		gpu3d: gpu@38000000 {
 			compatible = "vivante,gc";
 			reg = <0x38000000 0x8000>;
@@ -987,6 +1034,7 @@ usb3_phy0: usb-phy@381f0040 {
 			clock-names = "phy";
 			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
 			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
 			#phy-cells = <0>;
 			status = "disabled";
 		};
@@ -999,6 +1047,7 @@ usb3_0: usb@32f10100 {
 				 <&clk IMX8MP_CLK_USB_ROOT>;
 			clock-names = "hsio", "suspend";
 			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			dma-ranges = <0x40000000 0x40000000 0xc0000000>;
@@ -1012,9 +1061,6 @@ usb_dwc3_0: usb@38100000 {
 					 <&clk IMX8MP_CLK_USB_CORE_REF>,
 					 <&clk IMX8MP_CLK_USB_ROOT>;
 				clock-names = "bus_early", "ref", "suspend";
-				assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
-				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
-				assigned-clock-rates = <500000000>;
 				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 				phys = <&usb3_phy0>, <&usb3_phy0>;
 				phy-names = "usb2-phy", "usb3-phy";
@@ -1030,6 +1076,7 @@ usb3_phy1: usb-phy@382f0040 {
 			clock-names = "phy";
 			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
 			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
 			#phy-cells = <0>;
 			status = "disabled";
 		};
@@ -1042,6 +1089,7 @@ usb3_1: usb@32f10108 {
 				 <&clk IMX8MP_CLK_USB_ROOT>;
 			clock-names = "hsio", "suspend";
 			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			dma-ranges = <0x40000000 0x40000000 0xc0000000>;
@@ -1055,9 +1103,6 @@ usb_dwc3_1: usb@38200000 {
 					 <&clk IMX8MP_CLK_USB_CORE_REF>,
 					 <&clk IMX8MP_CLK_USB_ROOT>;
 				clock-names = "bus_early", "ref", "suspend";
-				assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
-				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
-				assigned-clock-rates = <500000000>;
 				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 				phys = <&usb3_phy1>, <&usb3_phy1>;
 				phy-names = "usb2-phy", "usb3-phy";
-- 
2.30.2

[PATCH v4 09/11] arm64: dts: imx8mp: Add MEDIAMIX power domains

[Lucas Stach]

From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

Add the power domains related to the MEDIAMIX to the GPC.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index edf2d8f5e22e..e94c88a2fda8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -488,6 +488,11 @@ pgc {
 					#address-cells = <1>;
 					#size-cells = <0>;
 
+					pgc_mipi_phy1: power-domain@0 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
+					};
+
 					pgc_pcie_phy: power-domain@1 {
 						#power-domain-cells = <0>;
 						reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
@@ -530,6 +535,18 @@ pgc_gpu3d: power-domain@9 {
 						power-domains = <&pgc_gpumix>;
 					};
 
+					pgc_mediamix: power-domain@10 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
+						clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+							 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+					};
+
+					pgc_mipi_phy2: power-domain@16 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
+					};
+
 					pgc_hsiomix: power-domains@17 {
 						#power-domain-cells = <0>;
 						reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
@@ -539,6 +556,12 @@ pgc_hsiomix: power-domains@17 {
 						assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
 						assigned-clock-rates = <500000000>;
 					};
+
+					pgc_ispdwp: power-domain@18 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
+						clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>;
+					};
 				};
 			};
 		};
-- 
2.30.2


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[PATCH v4 09/11] arm64: dts: imx8mp: Add MEDIAMIX power domains

[Lucas Stach]

From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

Add the power domains related to the MEDIAMIX to the GPC.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index edf2d8f5e22e..e94c88a2fda8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -488,6 +488,11 @@ pgc {
 					#address-cells = <1>;
 					#size-cells = <0>;
 
+					pgc_mipi_phy1: power-domain@0 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
+					};
+
 					pgc_pcie_phy: power-domain@1 {
 						#power-domain-cells = <0>;
 						reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
@@ -530,6 +535,18 @@ pgc_gpu3d: power-domain@9 {
 						power-domains = <&pgc_gpumix>;
 					};
 
+					pgc_mediamix: power-domain@10 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
+						clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+							 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+					};
+
+					pgc_mipi_phy2: power-domain@16 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
+					};
+
 					pgc_hsiomix: power-domains@17 {
 						#power-domain-cells = <0>;
 						reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
@@ -539,6 +556,12 @@ pgc_hsiomix: power-domains@17 {
 						assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
 						assigned-clock-rates = <500000000>;
 					};
+
+					pgc_ispdwp: power-domain@18 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
+						clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>;
+					};
 				};
 			};
 		};
-- 
2.30.2

[PATCH v4 10/11] arm64: dts: imx8mp: Add MEDIA_BLK_CTRL

[Lucas Stach]

From: Paul Elder <paul.elder@ideasonboard.com>

Add a DT node for the MEDIA_BLK_CTRL, which provides power domains for
the camera and display devices.

Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 38 +++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index e94c88a2fda8..627846434901 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -988,6 +988,44 @@ aips4: bus@32c00000 {
 			#size-cells = <1>;
 			ranges;
 
+			media_blk_ctrl: blk-ctrl@32ec0000 {
+				compatible = "fsl,imx8mp-media-blk-ctrl",
+					     "syscon";
+				reg = <0x32ec0000 0x10000>;
+				power-domains = <&pgc_mediamix>,
+						<&pgc_mipi_phy1>,
+						<&pgc_mipi_phy1>,
+						<&pgc_mediamix>,
+						<&pgc_mediamix>,
+						<&pgc_mipi_phy2>,
+						<&pgc_mediamix>,
+						<&pgc_ispdwp>,
+						<&pgc_ispdwp>,
+						<&pgc_mipi_phy2>;
+				power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
+						     "lcdif1", "isi", "mipi-csi2",
+						     "lcdif2", "isp", "dwe",
+						     "mipi-dsi2";
+				clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
+				clock-names = "apb", "axi", "cam1", "cam2",
+					      "disp1", "disp2", "isp", "phy";
+
+				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
+						  <&clk IMX8MP_CLK_MEDIA_APB>;
+				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
+							 <&clk IMX8MP_SYS_PLL1_800M>;
+				assigned-clock-rates = <500000000>, <200000000>;
+
+				#power-domain-cells = <1>;
+			};
+
 			hsio_blk_ctrl: blk-ctrl@32f10000 {
 				compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
 				reg = <0x32f10000 0x24>;
-- 
2.30.2


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[PATCH v4 10/11] arm64: dts: imx8mp: Add MEDIA_BLK_CTRL

[Lucas Stach]

From: Paul Elder <paul.elder@ideasonboard.com>

Add a DT node for the MEDIA_BLK_CTRL, which provides power domains for
the camera and display devices.

Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 38 +++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index e94c88a2fda8..627846434901 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -988,6 +988,44 @@ aips4: bus@32c00000 {
 			#size-cells = <1>;
 			ranges;
 
+			media_blk_ctrl: blk-ctrl@32ec0000 {
+				compatible = "fsl,imx8mp-media-blk-ctrl",
+					     "syscon";
+				reg = <0x32ec0000 0x10000>;
+				power-domains = <&pgc_mediamix>,
+						<&pgc_mipi_phy1>,
+						<&pgc_mipi_phy1>,
+						<&pgc_mediamix>,
+						<&pgc_mediamix>,
+						<&pgc_mipi_phy2>,
+						<&pgc_mediamix>,
+						<&pgc_ispdwp>,
+						<&pgc_ispdwp>,
+						<&pgc_mipi_phy2>;
+				power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
+						     "lcdif1", "isi", "mipi-csi2",
+						     "lcdif2", "isp", "dwe",
+						     "mipi-dsi2";
+				clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
+				clock-names = "apb", "axi", "cam1", "cam2",
+					      "disp1", "disp2", "isp", "phy";
+
+				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
+						  <&clk IMX8MP_CLK_MEDIA_APB>;
+				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
+							 <&clk IMX8MP_SYS_PLL1_800M>;
+				assigned-clock-rates = <500000000>, <200000000>;
+
+				#power-domain-cells = <1>;
+			};
+
 			hsio_blk_ctrl: blk-ctrl@32f10000 {
 				compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
 				reg = <0x32f10000 0x24>;
-- 
2.30.2

[PATCH v4 11/11] arm64: dts: imx8mp: add HDMI power-domains

[Lucas Stach]

This adds the PGC and HDMI blk-ctrl nodes providing power control for
HDMI subsystem peripherals.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 35 +++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 627846434901..cbe75b816b43 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -542,6 +542,23 @@ pgc_mediamix: power-domain@10 {
 							 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
 					};
 
+					pgc_hdmimix: power-domains@14 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>;
+						clocks = <&clk IMX8MP_CLK_HDMI_ROOT>,
+							 <&clk IMX8MP_CLK_HDMI_APB>;
+						assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
+								  <&clk IMX8MP_CLK_HDMI_APB>;
+						assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
+									 <&clk IMX8MP_SYS_PLL1_133M>;
+						assigned-clock-rates = <500000000>, <133000000>;
+					};
+
+					pgc_hdmi_phy: power-domains@15 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>;
+					};
+
 					pgc_mipi_phy2: power-domain@16 {
 						#power-domain-cells = <0>;
 						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
@@ -1039,6 +1056,24 @@ hsio_blk_ctrl: blk-ctrl@32f10000 {
 						     "usb-phy2", "pcie", "pcie-phy";
 				#power-domain-cells = <1>;
 			};
+
+			hdmi_blk_ctrl: blk-ctrl@32fc0000 {
+				compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";
+				reg = <0x32fc0000 0x23c>;
+				clocks = <&clk IMX8MP_CLK_HDMI_APB>,
+					 <&clk IMX8MP_CLK_HDMI_ROOT>,
+					 <&clk IMX8MP_CLK_HDMI_REF_266M>,
+					 <&clk IMX8MP_CLK_HDMI_24M>;
+				clock-names = "apb", "axi", "ref_266m", "ref_24m";
+				power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>,
+						<&pgc_hdmimix>, <&pgc_hdmimix>,
+						<&pgc_hdmimix>, <&pgc_hdmimix>,
+						<&pgc_hdmimix>, <&pgc_hdmi_phy>;
+				power-domain-names = "bus", "irqsteer", "lcdif",
+						     "pai", "pvi", "trng",
+						     "hdmi-tx", "hdmi-tx-phy";
+				#power-domain-cells = <1>;
+			};
 		};
 
 		gpu3d: gpu@38000000 {
-- 
2.30.2


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[PATCH v4 11/11] arm64: dts: imx8mp: add HDMI power-domains

[Lucas Stach]

This adds the PGC and HDMI blk-ctrl nodes providing power control for
HDMI subsystem peripherals.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 35 +++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 627846434901..cbe75b816b43 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -542,6 +542,23 @@ pgc_mediamix: power-domain@10 {
 							 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
 					};
 
+					pgc_hdmimix: power-domains@14 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>;
+						clocks = <&clk IMX8MP_CLK_HDMI_ROOT>,
+							 <&clk IMX8MP_CLK_HDMI_APB>;
+						assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
+								  <&clk IMX8MP_CLK_HDMI_APB>;
+						assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
+									 <&clk IMX8MP_SYS_PLL1_133M>;
+						assigned-clock-rates = <500000000>, <133000000>;
+					};
+
+					pgc_hdmi_phy: power-domains@15 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>;
+					};
+
 					pgc_mipi_phy2: power-domain@16 {
 						#power-domain-cells = <0>;
 						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
@@ -1039,6 +1056,24 @@ hsio_blk_ctrl: blk-ctrl@32f10000 {
 						     "usb-phy2", "pcie", "pcie-phy";
 				#power-domain-cells = <1>;
 			};
+
+			hdmi_blk_ctrl: blk-ctrl@32fc0000 {
+				compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";
+				reg = <0x32fc0000 0x23c>;
+				clocks = <&clk IMX8MP_CLK_HDMI_APB>,
+					 <&clk IMX8MP_CLK_HDMI_ROOT>,
+					 <&clk IMX8MP_CLK_HDMI_REF_266M>,
+					 <&clk IMX8MP_CLK_HDMI_24M>;
+				clock-names = "apb", "axi", "ref_266m", "ref_24m";
+				power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>,
+						<&pgc_hdmimix>, <&pgc_hdmimix>,
+						<&pgc_hdmimix>, <&pgc_hdmimix>,
+						<&pgc_hdmimix>, <&pgc_hdmi_phy>;
+				power-domain-names = "bus", "irqsteer", "lcdif",
+						     "pai", "pvi", "trng",
+						     "hdmi-tx", "hdmi-tx-phy";
+				#power-domain-cells = <1>;
+			};
 		};
 
 		gpu3d: gpu@38000000 {
-- 
2.30.2

Re: [PATCH v4 02/11] soc: imx: add i.MX8MP HSIO blk-ctrl

[Marek Vasut]

On 4/6/22 17:33, Lucas Stach wrote:

[...]

> +static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = {
> +	.max_reg = 0x24,

Doesn't the HSIO_BLK_CTL go up to 0x10c ?

> +	.power_on = imx8mp_hsio_blk_ctrl_power_on,
> +	.power_off = imx8mp_hsio_blk_ctrl_power_off,
> +	.power_notifier_fn = imx8mp_hsio_power_notifier,
> +	.domains = imx8mp_hsio_domain_data,
> +	.num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data),
> +};
> +
> +static int imx8mp_blk_ctrl_power_on(struct generic_pm_domain *genpd)
> +{
> +	struct imx8mp_blk_ctrl_domain *domain = to_imx8mp_blk_ctrl_domain(genpd);
> +	const struct imx8mp_blk_ctrl_domain_data *data = domain->data;
> +	struct imx8mp_blk_ctrl *bc = domain->bc;
> +	int ret;
> +
> +	/* make sure bus domain is awake */
> +	ret = pm_runtime_resume_and_get(bc->bus_power_dev);
> +	if (ret < 0) {
> +		dev_err(bc->dev, "failed to power up bus domain\n");
> +		return ret;
> +	}
> +
> +	/* enable upstream clocks */
> +	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);;
> +	if (ret) {
> +		dev_err(bc->dev, "failed to enable clocks\n");
> +		goto bus_put;
> +	}
> +
> +	/* domain specific blk-ctrl manipulation */
> +	bc->power_on(bc, domain);

Would it make sense to add error checking ?

> +	/* power up upstream GPC domain */
> +	ret = pm_runtime_resume_and_get(domain->power_dev);
> +	if (ret < 0) {
> +		dev_err(bc->dev, "failed to power up peripheral domain\n");
> +		goto clk_disable;
> +	}
> +
> +	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
> +
> +	return 0;
> +
> +clk_disable:
> +	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
> +bus_put:
> +	pm_runtime_put(bc->bus_power_dev);
> +
> +	return ret;
> +}

[...]

Re: [PATCH v4 02/11] soc: imx: add i.MX8MP HSIO blk-ctrl

[Marek Vasut]

On 4/6/22 17:33, Lucas Stach wrote:

[...]

> +static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = {
> +	.max_reg = 0x24,

Doesn't the HSIO_BLK_CTL go up to 0x10c ?

> +	.power_on = imx8mp_hsio_blk_ctrl_power_on,
> +	.power_off = imx8mp_hsio_blk_ctrl_power_off,
> +	.power_notifier_fn = imx8mp_hsio_power_notifier,
> +	.domains = imx8mp_hsio_domain_data,
> +	.num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data),
> +};
> +
> +static int imx8mp_blk_ctrl_power_on(struct generic_pm_domain *genpd)
> +{
> +	struct imx8mp_blk_ctrl_domain *domain = to_imx8mp_blk_ctrl_domain(genpd);
> +	const struct imx8mp_blk_ctrl_domain_data *data = domain->data;
> +	struct imx8mp_blk_ctrl *bc = domain->bc;
> +	int ret;
> +
> +	/* make sure bus domain is awake */
> +	ret = pm_runtime_resume_and_get(bc->bus_power_dev);
> +	if (ret < 0) {
> +		dev_err(bc->dev, "failed to power up bus domain\n");
> +		return ret;
> +	}
> +
> +	/* enable upstream clocks */
> +	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);;
> +	if (ret) {
> +		dev_err(bc->dev, "failed to enable clocks\n");
> +		goto bus_put;
> +	}
> +
> +	/* domain specific blk-ctrl manipulation */
> +	bc->power_on(bc, domain);

Would it make sense to add error checking ?

> +	/* power up upstream GPC domain */
> +	ret = pm_runtime_resume_and_get(domain->power_dev);
> +	if (ret < 0) {
> +		dev_err(bc->dev, "failed to power up peripheral domain\n");
> +		goto clk_disable;
> +	}
> +
> +	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
> +
> +	return 0;
> +
> +clk_disable:
> +	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
> +bus_put:
> +	pm_runtime_put(bc->bus_power_dev);
> +
> +	return ret;
> +}

[...]

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Re: [PATCH v4 07/11] soc: imx: add i.MX8MP HDMI blk-ctrl

[Marek Vasut]

On 4/6/22 17:33, Lucas Stach wrote:

[...]

> +static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
> +					  struct imx8mp_blk_ctrl_domain *domain)
> +{
> +	switch (domain->id) {
> +	case IMX8MP_HDMIBLK_PD_IRQSTEER:
> +		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9));
> +		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));
> +		break;
> +	case IMX8MP_HDMIBLK_PD_LCDIF:
> +		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
> +				BIT(7) | BIT(16) | BIT(17) | BIT(18) |
> +				BIT(19) | BIT(20));
> +		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
> +		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
> +				BIT(4) | BIT(5) | BIT(6));

Macros which define all those ad-hoc bits might be nice.

[...]

Re: [PATCH v4 07/11] soc: imx: add i.MX8MP HDMI blk-ctrl

[Marek Vasut]

On 4/6/22 17:33, Lucas Stach wrote:

[...]

> +static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
> +					  struct imx8mp_blk_ctrl_domain *domain)
> +{
> +	switch (domain->id) {
> +	case IMX8MP_HDMIBLK_PD_IRQSTEER:
> +		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9));
> +		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));
> +		break;
> +	case IMX8MP_HDMIBLK_PD_LCDIF:
> +		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
> +				BIT(7) | BIT(16) | BIT(17) | BIT(18) |
> +				BIT(19) | BIT(20));
> +		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
> +		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
> +				BIT(4) | BIT(5) | BIT(6));

Macros which define all those ad-hoc bits might be nice.

[...]

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Re: [PATCH v4 02/11] soc: imx: add i.MX8MP HSIO blk-ctrl

[Lucas Stach]

Am Donnerstag, dem 07.04.2022 um 01:43 +0200 schrieb Marek Vasut:
> On 4/6/22 17:33, Lucas Stach wrote:
> 
> [...]
> 
> > +static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = {
> > +	.max_reg = 0x24,
> 
> Doesn't the HSIO_BLK_CTL go up to 0x10c ?

Technically yes, but there is already a driver for the USB glue
(fsl,imx8mp-dwc3) that occupies the USB registers at and above 0x100.
 
> 
> > +	.power_on = imx8mp_hsio_blk_ctrl_power_on,
> > +	.power_off = imx8mp_hsio_blk_ctrl_power_off,
> > +	.power_notifier_fn = imx8mp_hsio_power_notifier,
> > +	.domains = imx8mp_hsio_domain_data,
> > +	.num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data),
> > +};
> > +
> > +static int imx8mp_blk_ctrl_power_on(struct generic_pm_domain *genpd)
> > +{
> > +	struct imx8mp_blk_ctrl_domain *domain = to_imx8mp_blk_ctrl_domain(genpd);
> > +	const struct imx8mp_blk_ctrl_domain_data *data = domain->data;
> > +	struct imx8mp_blk_ctrl *bc = domain->bc;
> > +	int ret;
> > +
> > +	/* make sure bus domain is awake */
> > +	ret = pm_runtime_resume_and_get(bc->bus_power_dev);
> > +	if (ret < 0) {
> > +		dev_err(bc->dev, "failed to power up bus domain\n");
> > +		return ret;
> > +	}
> > +
> > +	/* enable upstream clocks */
> > +	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);;
> > +	if (ret) {
> > +		dev_err(bc->dev, "failed to enable clocks\n");
> > +		goto bus_put;
> > +	}
> > +
> > +	/* domain specific blk-ctrl manipulation */
> > +	bc->power_on(bc, domain);
> 
> Would it make sense to add error checking ?
> 
I don't expect those functions to do any more than a bit of blk-ctrl
MMIO register poking. If that fails you are in much more trouble than
what you can reasonably fix with some error checking.

Regards,
Lucas

> > +	/* power up upstream GPC domain */
> > +	ret = pm_runtime_resume_and_get(domain->power_dev);
> > +	if (ret < 0) {
> > +		dev_err(bc->dev, "failed to power up peripheral domain\n");
> > +		goto clk_disable;
> > +	}
> > +
> > +	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
> > +
> > +	return 0;
> > +
> > +clk_disable:
> > +	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
> > +bus_put:
> > +	pm_runtime_put(bc->bus_power_dev);
> > +
> > +	return ret;
> > +}
> 
> [...]

Re: [PATCH v4 02/11] soc: imx: add i.MX8MP HSIO blk-ctrl

[Lucas Stach]

Am Donnerstag, dem 07.04.2022 um 01:43 +0200 schrieb Marek Vasut:
> On 4/6/22 17:33, Lucas Stach wrote:
> 
> [...]
> 
> > +static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = {
> > +	.max_reg = 0x24,
> 
> Doesn't the HSIO_BLK_CTL go up to 0x10c ?

Technically yes, but there is already a driver for the USB glue
(fsl,imx8mp-dwc3) that occupies the USB registers at and above 0x100.
 
> 
> > +	.power_on = imx8mp_hsio_blk_ctrl_power_on,
> > +	.power_off = imx8mp_hsio_blk_ctrl_power_off,
> > +	.power_notifier_fn = imx8mp_hsio_power_notifier,
> > +	.domains = imx8mp_hsio_domain_data,
> > +	.num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data),
> > +};
> > +
> > +static int imx8mp_blk_ctrl_power_on(struct generic_pm_domain *genpd)
> > +{
> > +	struct imx8mp_blk_ctrl_domain *domain = to_imx8mp_blk_ctrl_domain(genpd);
> > +	const struct imx8mp_blk_ctrl_domain_data *data = domain->data;
> > +	struct imx8mp_blk_ctrl *bc = domain->bc;
> > +	int ret;
> > +
> > +	/* make sure bus domain is awake */
> > +	ret = pm_runtime_resume_and_get(bc->bus_power_dev);
> > +	if (ret < 0) {
> > +		dev_err(bc->dev, "failed to power up bus domain\n");
> > +		return ret;
> > +	}
> > +
> > +	/* enable upstream clocks */
> > +	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);;
> > +	if (ret) {
> > +		dev_err(bc->dev, "failed to enable clocks\n");
> > +		goto bus_put;
> > +	}
> > +
> > +	/* domain specific blk-ctrl manipulation */
> > +	bc->power_on(bc, domain);
> 
> Would it make sense to add error checking ?
> 
I don't expect those functions to do any more than a bit of blk-ctrl
MMIO register poking. If that fails you are in much more trouble than
what you can reasonably fix with some error checking.

Regards,
Lucas

> > +	/* power up upstream GPC domain */
> > +	ret = pm_runtime_resume_and_get(domain->power_dev);
> > +	if (ret < 0) {
> > +		dev_err(bc->dev, "failed to power up peripheral domain\n");
> > +		goto clk_disable;
> > +	}
> > +
> > +	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
> > +
> > +	return 0;
> > +
> > +clk_disable:
> > +	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
> > +bus_put:
> > +	pm_runtime_put(bc->bus_power_dev);
> > +
> > +	return ret;
> > +}
> 
> [...]



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Re: [PATCH v4 02/11] soc: imx: add i.MX8MP HSIO blk-ctrl

[Marek Vasut]

On 4/7/22 11:12, Lucas Stach wrote:
> Am Donnerstag, dem 07.04.2022 um 01:43 +0200 schrieb Marek Vasut:
>> On 4/6/22 17:33, Lucas Stach wrote:
>>
>> [...]
>>
>>> +static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = {
>>> +	.max_reg = 0x24,
>>
>> Doesn't the HSIO_BLK_CTL go up to 0x10c ?
> 
> Technically yes, but there is already a driver for the USB glue
> (fsl,imx8mp-dwc3) that occupies the USB registers at and above 0x100.

Shouldn't that imx8mp-dwc3 glue code be switched to syscon and access 
the registers through this driver then ?

>>> +	.power_on = imx8mp_hsio_blk_ctrl_power_on,
>>> +	.power_off = imx8mp_hsio_blk_ctrl_power_off,
>>> +	.power_notifier_fn = imx8mp_hsio_power_notifier,
>>> +	.domains = imx8mp_hsio_domain_data,
>>> +	.num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data),
>>> +};
>>> +
>>> +static int imx8mp_blk_ctrl_power_on(struct generic_pm_domain *genpd)
>>> +{
>>> +	struct imx8mp_blk_ctrl_domain *domain = to_imx8mp_blk_ctrl_domain(genpd);
>>> +	const struct imx8mp_blk_ctrl_domain_data *data = domain->data;
>>> +	struct imx8mp_blk_ctrl *bc = domain->bc;
>>> +	int ret;
>>> +
>>> +	/* make sure bus domain is awake */
>>> +	ret = pm_runtime_resume_and_get(bc->bus_power_dev);
>>> +	if (ret < 0) {
>>> +		dev_err(bc->dev, "failed to power up bus domain\n");
>>> +		return ret;
>>> +	}
>>> +
>>> +	/* enable upstream clocks */
>>> +	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);;
>>> +	if (ret) {
>>> +		dev_err(bc->dev, "failed to enable clocks\n");
>>> +		goto bus_put;
>>> +	}
>>> +
>>> +	/* domain specific blk-ctrl manipulation */
>>> +	bc->power_on(bc, domain);
>>
>> Would it make sense to add error checking ?
>>
> I don't expect those functions to do any more than a bit of blk-ctrl
> MMIO register poking. If that fails you are in much more trouble than
> what you can reasonably fix with some error checking.

All right.

Re: [PATCH v4 02/11] soc: imx: add i.MX8MP HSIO blk-ctrl

[Marek Vasut]

On 4/7/22 11:12, Lucas Stach wrote:
> Am Donnerstag, dem 07.04.2022 um 01:43 +0200 schrieb Marek Vasut:
>> On 4/6/22 17:33, Lucas Stach wrote:
>>
>> [...]
>>
>>> +static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = {
>>> +	.max_reg = 0x24,
>>
>> Doesn't the HSIO_BLK_CTL go up to 0x10c ?
> 
> Technically yes, but there is already a driver for the USB glue
> (fsl,imx8mp-dwc3) that occupies the USB registers at and above 0x100.

Shouldn't that imx8mp-dwc3 glue code be switched to syscon and access 
the registers through this driver then ?

>>> +	.power_on = imx8mp_hsio_blk_ctrl_power_on,
>>> +	.power_off = imx8mp_hsio_blk_ctrl_power_off,
>>> +	.power_notifier_fn = imx8mp_hsio_power_notifier,
>>> +	.domains = imx8mp_hsio_domain_data,
>>> +	.num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data),
>>> +};
>>> +
>>> +static int imx8mp_blk_ctrl_power_on(struct generic_pm_domain *genpd)
>>> +{
>>> +	struct imx8mp_blk_ctrl_domain *domain = to_imx8mp_blk_ctrl_domain(genpd);
>>> +	const struct imx8mp_blk_ctrl_domain_data *data = domain->data;
>>> +	struct imx8mp_blk_ctrl *bc = domain->bc;
>>> +	int ret;
>>> +
>>> +	/* make sure bus domain is awake */
>>> +	ret = pm_runtime_resume_and_get(bc->bus_power_dev);
>>> +	if (ret < 0) {
>>> +		dev_err(bc->dev, "failed to power up bus domain\n");
>>> +		return ret;
>>> +	}
>>> +
>>> +	/* enable upstream clocks */
>>> +	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);;
>>> +	if (ret) {
>>> +		dev_err(bc->dev, "failed to enable clocks\n");
>>> +		goto bus_put;
>>> +	}
>>> +
>>> +	/* domain specific blk-ctrl manipulation */
>>> +	bc->power_on(bc, domain);
>>
>> Would it make sense to add error checking ?
>>
> I don't expect those functions to do any more than a bit of blk-ctrl
> MMIO register poking. If that fails you are in much more trouble than
> what you can reasonably fix with some error checking.

All right.

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Re: [PATCH v4 02/11] soc: imx: add i.MX8MP HSIO blk-ctrl

[Lucas Stach]

Am Montag, dem 11.04.2022 um 00:11 +0200 schrieb Marek Vasut:
> On 4/7/22 11:12, Lucas Stach wrote:
> > Am Donnerstag, dem 07.04.2022 um 01:43 +0200 schrieb Marek Vasut:
> > > On 4/6/22 17:33, Lucas Stach wrote:
> > > 
> > > [...]
> > > 
> > > > +static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = {
> > > > +	.max_reg = 0x24,
> > > 
> > > Doesn't the HSIO_BLK_CTL go up to 0x10c ?
> > 
> > Technically yes, but there is already a driver for the USB glue
> > (fsl,imx8mp-dwc3) that occupies the USB registers at and above 0x100.
> 
> Shouldn't that imx8mp-dwc3 glue code be switched to syscon and access 
> the registers through this driver then ?

I don't see why this would be needed. Registers up to 0x24 are a mixed
bag of blk-ctrls, but the registers above 0x100 are only USB wakeup
related, I don't see the blk-ctrl ever wanting to touch them.

I think the current split is fine. Just because the RM lumps those
register regions together into the HSIO blk-ctrl description doesn't
mean we need to cover them all in a single syscon.

Regards,
Lucas

> 
> > > > +	.power_on = imx8mp_hsio_blk_ctrl_power_on,
> > > > +	.power_off = imx8mp_hsio_blk_ctrl_power_off,
> > > > +	.power_notifier_fn = imx8mp_hsio_power_notifier,
> > > > +	.domains = imx8mp_hsio_domain_data,
> > > > +	.num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data),
> > > > +};
> > > > +
> > > > +static int imx8mp_blk_ctrl_power_on(struct generic_pm_domain *genpd)
> > > > +{
> > > > +	struct imx8mp_blk_ctrl_domain *domain = to_imx8mp_blk_ctrl_domain(genpd);
> > > > +	const struct imx8mp_blk_ctrl_domain_data *data = domain->data;
> > > > +	struct imx8mp_blk_ctrl *bc = domain->bc;
> > > > +	int ret;
> > > > +
> > > > +	/* make sure bus domain is awake */
> > > > +	ret = pm_runtime_resume_and_get(bc->bus_power_dev);
> > > > +	if (ret < 0) {
> > > > +		dev_err(bc->dev, "failed to power up bus domain\n");
> > > > +		return ret;
> > > > +	}
> > > > +
> > > > +	/* enable upstream clocks */
> > > > +	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);;
> > > > +	if (ret) {
> > > > +		dev_err(bc->dev, "failed to enable clocks\n");
> > > > +		goto bus_put;
> > > > +	}
> > > > +
> > > > +	/* domain specific blk-ctrl manipulation */
> > > > +	bc->power_on(bc, domain);
> > > 
> > > Would it make sense to add error checking ?
> > > 
> > I don't expect those functions to do any more than a bit of blk-ctrl
> > MMIO register poking. If that fails you are in much more trouble than
> > what you can reasonably fix with some error checking.
> 
> All right.

Re: [PATCH v4 02/11] soc: imx: add i.MX8MP HSIO blk-ctrl

[Lucas Stach]

Am Montag, dem 11.04.2022 um 00:11 +0200 schrieb Marek Vasut:
> On 4/7/22 11:12, Lucas Stach wrote:
> > Am Donnerstag, dem 07.04.2022 um 01:43 +0200 schrieb Marek Vasut:
> > > On 4/6/22 17:33, Lucas Stach wrote:
> > > 
> > > [...]
> > > 
> > > > +static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = {
> > > > +	.max_reg = 0x24,
> > > 
> > > Doesn't the HSIO_BLK_CTL go up to 0x10c ?
> > 
> > Technically yes, but there is already a driver for the USB glue
> > (fsl,imx8mp-dwc3) that occupies the USB registers at and above 0x100.
> 
> Shouldn't that imx8mp-dwc3 glue code be switched to syscon and access 
> the registers through this driver then ?

I don't see why this would be needed. Registers up to 0x24 are a mixed
bag of blk-ctrls, but the registers above 0x100 are only USB wakeup
related, I don't see the blk-ctrl ever wanting to touch them.

I think the current split is fine. Just because the RM lumps those
register regions together into the HSIO blk-ctrl description doesn't
mean we need to cover them all in a single syscon.

Regards,
Lucas

> 
> > > > +	.power_on = imx8mp_hsio_blk_ctrl_power_on,
> > > > +	.power_off = imx8mp_hsio_blk_ctrl_power_off,
> > > > +	.power_notifier_fn = imx8mp_hsio_power_notifier,
> > > > +	.domains = imx8mp_hsio_domain_data,
> > > > +	.num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data),
> > > > +};
> > > > +
> > > > +static int imx8mp_blk_ctrl_power_on(struct generic_pm_domain *genpd)
> > > > +{
> > > > +	struct imx8mp_blk_ctrl_domain *domain = to_imx8mp_blk_ctrl_domain(genpd);
> > > > +	const struct imx8mp_blk_ctrl_domain_data *data = domain->data;
> > > > +	struct imx8mp_blk_ctrl *bc = domain->bc;
> > > > +	int ret;
> > > > +
> > > > +	/* make sure bus domain is awake */
> > > > +	ret = pm_runtime_resume_and_get(bc->bus_power_dev);
> > > > +	if (ret < 0) {
> > > > +		dev_err(bc->dev, "failed to power up bus domain\n");
> > > > +		return ret;
> > > > +	}
> > > > +
> > > > +	/* enable upstream clocks */
> > > > +	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);;
> > > > +	if (ret) {
> > > > +		dev_err(bc->dev, "failed to enable clocks\n");
> > > > +		goto bus_put;
> > > > +	}
> > > > +
> > > > +	/* domain specific blk-ctrl manipulation */
> > > > +	bc->power_on(bc, domain);
> > > 
> > > Would it make sense to add error checking ?
> > > 
> > I don't expect those functions to do any more than a bit of blk-ctrl
> > MMIO register poking. If that fails you are in much more trouble than
> > what you can reasonably fix with some error checking.
> 
> All right.



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Re: [PATCH v4 02/11] soc: imx: add i.MX8MP HSIO blk-ctrl

[Marek Vasut]

On 4/11/22 18:46, Lucas Stach wrote:
> Am Montag, dem 11.04.2022 um 00:11 +0200 schrieb Marek Vasut:
>> On 4/7/22 11:12, Lucas Stach wrote:
>>> Am Donnerstag, dem 07.04.2022 um 01:43 +0200 schrieb Marek Vasut:
>>>> On 4/6/22 17:33, Lucas Stach wrote:
>>>>
>>>> [...]
>>>>
>>>>> +static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = {
>>>>> +	.max_reg = 0x24,
>>>>
>>>> Doesn't the HSIO_BLK_CTL go up to 0x10c ?
>>>
>>> Technically yes, but there is already a driver for the USB glue
>>> (fsl,imx8mp-dwc3) that occupies the USB registers at and above 0x100.
>>
>> Shouldn't that imx8mp-dwc3 glue code be switched to syscon and access
>> the registers through this driver then ?
> 
> I don't see why this would be needed. Registers up to 0x24 are a mixed
> bag of blk-ctrls, but the registers above 0x100 are only USB wakeup
> related, I don't see the blk-ctrl ever wanting to touch them.
> 
> I think the current split is fine. Just because the RM lumps those
> register regions together into the HSIO blk-ctrl description doesn't
> mean we need to cover them all in a single syscon.

I guess we can also always fix this up later, OK.

Re: [PATCH v4 02/11] soc: imx: add i.MX8MP HSIO blk-ctrl

[Marek Vasut]

On 4/11/22 18:46, Lucas Stach wrote:
> Am Montag, dem 11.04.2022 um 00:11 +0200 schrieb Marek Vasut:
>> On 4/7/22 11:12, Lucas Stach wrote:
>>> Am Donnerstag, dem 07.04.2022 um 01:43 +0200 schrieb Marek Vasut:
>>>> On 4/6/22 17:33, Lucas Stach wrote:
>>>>
>>>> [...]
>>>>
>>>>> +static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = {
>>>>> +	.max_reg = 0x24,
>>>>
>>>> Doesn't the HSIO_BLK_CTL go up to 0x10c ?
>>>
>>> Technically yes, but there is already a driver for the USB glue
>>> (fsl,imx8mp-dwc3) that occupies the USB registers at and above 0x100.
>>
>> Shouldn't that imx8mp-dwc3 glue code be switched to syscon and access
>> the registers through this driver then ?
> 
> I don't see why this would be needed. Registers up to 0x24 are a mixed
> bag of blk-ctrls, but the registers above 0x100 are only USB wakeup
> related, I don't see the blk-ctrl ever wanting to touch them.
> 
> I think the current split is fine. Just because the RM lumps those
> register regions together into the HSIO blk-ctrl description doesn't
> mean we need to cover them all in a single syscon.

I guess we can also always fix this up later, OK.

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Re: [PATCH v4 05/11] dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains

[Rob Herring]

On Wed, 06 Apr 2022 17:33:56 +0200, Lucas Stach wrote:
> This adds the defines for the power domains provided by the HDMI
> blk-ctrl on the i.MX8MP.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  include/dt-bindings/power/imx8mp-power.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v4 05/11] dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains

[Rob Herring]

On Wed, 06 Apr 2022 17:33:56 +0200, Lucas Stach wrote:
> This adds the defines for the power domains provided by the HDMI
> blk-ctrl on the i.MX8MP.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  include/dt-bindings/power/imx8mp-power.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

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Re: [PATCH v4 06/11] dt-bindings: soc: add binding for i.MX8MP HDMI blk-ctrl

[Rob Herring]

On Wed, 06 Apr 2022 17:33:57 +0200, Lucas Stach wrote:
> Add the DT binding for the HDMI blk-ctrl found on the i.MX8MP SoC.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml     | 84 +++++++++++++++++++
>  1 file changed, 84 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v4 06/11] dt-bindings: soc: add binding for i.MX8MP HDMI blk-ctrl

[Rob Herring]

On Wed, 06 Apr 2022 17:33:57 +0200, Lucas Stach wrote:
> Add the DT binding for the HDMI blk-ctrl found on the i.MX8MP SoC.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml     | 84 +++++++++++++++++++
>  1 file changed, 84 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

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Re: [PATCH v4 01/11] soc: imx: imx8m-blk-ctrl: set power device name

[Laurent Pinchart]

Hi Lucas,

Thank you for the patch.

On Wed, Apr 06, 2022 at 05:33:52PM +0200, Lucas Stach wrote:
> Set the name for the virtual power device to the name of the attached
> blk-ctrl domain. Makes the debug output for the power domains a lot
> more pleasant to read.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  drivers/soc/imx/imx8m-blk-ctrl.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
> index 122f9c884b38..3071a8eca8ef 100644
> --- a/drivers/soc/imx/imx8m-blk-ctrl.c
> +++ b/drivers/soc/imx/imx8m-blk-ctrl.c
> @@ -241,6 +241,7 @@ static int imx8m_blk_ctrl_probe(struct platform_device *pdev)
>  			ret = PTR_ERR(domain->power_dev);
>  			goto cleanup_pds;
>  		}
> +		dev_set_name(domain->power_dev, "%s", data->name);

Would it make sense to keep "genpd" in the name ? Maybe "genpd:%s" ?

With or without that,

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

>  
>  		domain->genpd.name = data->name;
>  		domain->genpd.power_on = imx8m_blk_ctrl_power_on;

-- 
Regards,

Laurent Pinchart

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Re: [PATCH v4 01/11] soc: imx: imx8m-blk-ctrl: set power device name

[Laurent Pinchart]

Hi Lucas,

Thank you for the patch.

On Wed, Apr 06, 2022 at 05:33:52PM +0200, Lucas Stach wrote:
> Set the name for the virtual power device to the name of the attached
> blk-ctrl domain. Makes the debug output for the power domains a lot
> more pleasant to read.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  drivers/soc/imx/imx8m-blk-ctrl.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
> index 122f9c884b38..3071a8eca8ef 100644
> --- a/drivers/soc/imx/imx8m-blk-ctrl.c
> +++ b/drivers/soc/imx/imx8m-blk-ctrl.c
> @@ -241,6 +241,7 @@ static int imx8m_blk_ctrl_probe(struct platform_device *pdev)
>  			ret = PTR_ERR(domain->power_dev);
>  			goto cleanup_pds;
>  		}
> +		dev_set_name(domain->power_dev, "%s", data->name);

Would it make sense to keep "genpd" in the name ? Maybe "genpd:%s" ?

With or without that,

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

>  
>  		domain->genpd.name = data->name;
>  		domain->genpd.power_on = imx8m_blk_ctrl_power_on;

-- 
Regards,

Laurent Pinchart

Re: [PATCH v4 00/11] consolidated i.MX8MP HSIO/MEDIA/HDMI blk-ctrl series

[Lucas Stach]

Hi Shawn,

there were some comments about the implementation of the HDMI blk-ctrl,
which I don't know in which way to resolve, yet. In the meantime it
would be very helpful if you could take all but the last patch of this
series into your tree. They are all reviewed and tested and starting to
block further work on some parts of the i.MX8MP bringup.

Regards,
Lucas

Am Mittwoch, dem 06.04.2022 um 17:33 +0200 schrieb Lucas Stach:
> Hi all,
> 
> this series adds a bunch more power domains that integrate with the blk-ctrls
> to the i.MX8MP. It depends on the i.MX8MP GPCv2 support series posted in [1].
> 
> The HSIO blk-ctrl bindings are already applied upstream, so they are not part
> of this series anymore. The DT description hasn't changed, but the
> implementation of the HSIO blk-ctrl driver is reworked quite a bit from the
> last round of patches, so I've dropped the review/tested-by tags.
> 
> I've also picked up the pretty thoroughly reviewed and tested MEDIA blk-ctrl
> patches from Paul and Laurent into this series, as they would conflict with
> other patches from this series when applied separately. This should hopefully
> make it easier for Shawn to pick things up.
> 
> Finally this now also adds the HDMI blk-ctrl, not part of any previous series.
> This one is pretty complex and the documentation in the reference manual
> appears to be inaccurate. I found at least the following issues:
> 
> 1. GLOBAL_XTAL24M_CLK_EN does not actually gate the 24MHz reference clock,
> the PHY PLL happily locks and provides correct clocks without this clock being
> ungated. It seems to gate some clock input of the HDMI TX controller instead,
> register access to this controller fails without this clock.
> 
> 2. HDMI_RTX_RESET_CTL0 bits 6 and 7 are marked as "reserved" in the manual,
> but they are actually required to be configured. Bit 6 seems to keep something
> in the display pixel clock path in inactive state and Bit 7 seems to reset
> the HDMI TX i2c controller.
> 
> The HDMI blk-ctrl part is tested quite extensively with a PoC HDMI support
> patchset, which I will send out in a bit, so I'm pretty sure that the
> support as implemented is working. I've put the patches last in the series
> in case that this turns out to be controversial, so the other patches can
> be applied independent from the HDMI support.
> 
> Regards,
> Lucas
> 
> [1] https://lore.kernel.org/all/20220330104620.3600159-1-l.stach@pengutronix.de/
> 
> 
> Laurent Pinchart (1):
>   arm64: dts: imx8mp: Add MEDIAMIX power domains
> 
> Lucas Stach (7):
>   soc: imx: imx8m-blk-ctrl: set power device name
>   soc: imx: add i.MX8MP HSIO blk-ctrl
>   dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains
>   dt-bindings: soc: add binding for i.MX8MP HDMI blk-ctrl
>   soc: imx: add i.MX8MP HDMI blk-ctrl
>   arm64: dts: imx8mp: add HSIO power-domains
>   arm64: dts: imx8mp: add HDMI power-domains
> 
> Paul Elder (3):
>   dt-bindings: soc: Add i.MX8MP media block control DT bindings
>   soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
>   arm64: dts: imx8mp: Add MEDIA_BLK_CTRL
> 
>  .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml     |  84 +++
>  .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 104 +++
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi     | 153 +++-
>  drivers/soc/imx/Makefile                      |   1 +
>  drivers/soc/imx/imx8m-blk-ctrl.c              | 124 +++-
>  drivers/soc/imx/imx8mp-blk-ctrl.c             | 696 ++++++++++++++++++
>  include/dt-bindings/power/imx8mp-power.h      |  18 +
>  7 files changed, 1172 insertions(+), 8 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
>  create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c
> 

Re: [PATCH v4 00/11] consolidated i.MX8MP HSIO/MEDIA/HDMI blk-ctrl series

[Lucas Stach]

Hi Shawn,

there were some comments about the implementation of the HDMI blk-ctrl,
which I don't know in which way to resolve, yet. In the meantime it
would be very helpful if you could take all but the last patch of this
series into your tree. They are all reviewed and tested and starting to
block further work on some parts of the i.MX8MP bringup.

Regards,
Lucas

Am Mittwoch, dem 06.04.2022 um 17:33 +0200 schrieb Lucas Stach:
> Hi all,
> 
> this series adds a bunch more power domains that integrate with the blk-ctrls
> to the i.MX8MP. It depends on the i.MX8MP GPCv2 support series posted in [1].
> 
> The HSIO blk-ctrl bindings are already applied upstream, so they are not part
> of this series anymore. The DT description hasn't changed, but the
> implementation of the HSIO blk-ctrl driver is reworked quite a bit from the
> last round of patches, so I've dropped the review/tested-by tags.
> 
> I've also picked up the pretty thoroughly reviewed and tested MEDIA blk-ctrl
> patches from Paul and Laurent into this series, as they would conflict with
> other patches from this series when applied separately. This should hopefully
> make it easier for Shawn to pick things up.
> 
> Finally this now also adds the HDMI blk-ctrl, not part of any previous series.
> This one is pretty complex and the documentation in the reference manual
> appears to be inaccurate. I found at least the following issues:
> 
> 1. GLOBAL_XTAL24M_CLK_EN does not actually gate the 24MHz reference clock,
> the PHY PLL happily locks and provides correct clocks without this clock being
> ungated. It seems to gate some clock input of the HDMI TX controller instead,
> register access to this controller fails without this clock.
> 
> 2. HDMI_RTX_RESET_CTL0 bits 6 and 7 are marked as "reserved" in the manual,
> but they are actually required to be configured. Bit 6 seems to keep something
> in the display pixel clock path in inactive state and Bit 7 seems to reset
> the HDMI TX i2c controller.
> 
> The HDMI blk-ctrl part is tested quite extensively with a PoC HDMI support
> patchset, which I will send out in a bit, so I'm pretty sure that the
> support as implemented is working. I've put the patches last in the series
> in case that this turns out to be controversial, so the other patches can
> be applied independent from the HDMI support.
> 
> Regards,
> Lucas
> 
> [1] https://lore.kernel.org/all/20220330104620.3600159-1-l.stach@pengutronix.de/
> 
> 
> Laurent Pinchart (1):
>   arm64: dts: imx8mp: Add MEDIAMIX power domains
> 
> Lucas Stach (7):
>   soc: imx: imx8m-blk-ctrl: set power device name
>   soc: imx: add i.MX8MP HSIO blk-ctrl
>   dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains
>   dt-bindings: soc: add binding for i.MX8MP HDMI blk-ctrl
>   soc: imx: add i.MX8MP HDMI blk-ctrl
>   arm64: dts: imx8mp: add HSIO power-domains
>   arm64: dts: imx8mp: add HDMI power-domains
> 
> Paul Elder (3):
>   dt-bindings: soc: Add i.MX8MP media block control DT bindings
>   soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
>   arm64: dts: imx8mp: Add MEDIA_BLK_CTRL
> 
>  .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml     |  84 +++
>  .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 104 +++
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi     | 153 +++-
>  drivers/soc/imx/Makefile                      |   1 +
>  drivers/soc/imx/imx8m-blk-ctrl.c              | 124 +++-
>  drivers/soc/imx/imx8mp-blk-ctrl.c             | 696 ++++++++++++++++++
>  include/dt-bindings/power/imx8mp-power.h      |  18 +
>  7 files changed, 1172 insertions(+), 8 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
>  create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c
> 



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Re: [PATCH v4 00/11] consolidated i.MX8MP HSIO/MEDIA/HDMI blk-ctrl series

[Laurent Pinchart]

Hi Lucas,

On Wed, May 04, 2022 at 10:27:01AM +0200, Lucas Stach wrote:
> Hi Shawn,
> 
> there were some comments about the implementation of the HDMI blk-ctrl,
> which I don't know in which way to resolve, yet. In the meantime it
> would be very helpful if you could take all but the last patch of this
> series into your tree. They are all reviewed and tested and starting to
> block further work on some parts of the i.MX8MP bringup.

Can we decouple the HDMI blk-ctrl from the rest, to at least upstream
the MEDIA blk-ctrl ? That part is ready.

> Am Mittwoch, dem 06.04.2022 um 17:33 +0200 schrieb Lucas Stach:
> > Hi all,
> > 
> > this series adds a bunch more power domains that integrate with the blk-ctrls
> > to the i.MX8MP. It depends on the i.MX8MP GPCv2 support series posted in [1].
> > 
> > The HSIO blk-ctrl bindings are already applied upstream, so they are not part
> > of this series anymore. The DT description hasn't changed, but the
> > implementation of the HSIO blk-ctrl driver is reworked quite a bit from the
> > last round of patches, so I've dropped the review/tested-by tags.
> > 
> > I've also picked up the pretty thoroughly reviewed and tested MEDIA blk-ctrl
> > patches from Paul and Laurent into this series, as they would conflict with
> > other patches from this series when applied separately. This should hopefully
> > make it easier for Shawn to pick things up.
> > 
> > Finally this now also adds the HDMI blk-ctrl, not part of any previous series.
> > This one is pretty complex and the documentation in the reference manual
> > appears to be inaccurate. I found at least the following issues:
> > 
> > 1. GLOBAL_XTAL24M_CLK_EN does not actually gate the 24MHz reference clock,
> > the PHY PLL happily locks and provides correct clocks without this clock being
> > ungated. It seems to gate some clock input of the HDMI TX controller instead,
> > register access to this controller fails without this clock.
> > 
> > 2. HDMI_RTX_RESET_CTL0 bits 6 and 7 are marked as "reserved" in the manual,
> > but they are actually required to be configured. Bit 6 seems to keep something
> > in the display pixel clock path in inactive state and Bit 7 seems to reset
> > the HDMI TX i2c controller.
> > 
> > The HDMI blk-ctrl part is tested quite extensively with a PoC HDMI support
> > patchset, which I will send out in a bit, so I'm pretty sure that the
> > support as implemented is working. I've put the patches last in the series
> > in case that this turns out to be controversial, so the other patches can
> > be applied independent from the HDMI support.
> > 
> > Regards,
> > Lucas
> > 
> > [1] https://lore.kernel.org/all/20220330104620.3600159-1-l.stach@pengutronix.de/
> > 
> > 
> > Laurent Pinchart (1):
> >   arm64: dts: imx8mp: Add MEDIAMIX power domains
> > 
> > Lucas Stach (7):
> >   soc: imx: imx8m-blk-ctrl: set power device name
> >   soc: imx: add i.MX8MP HSIO blk-ctrl
> >   dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains
> >   dt-bindings: soc: add binding for i.MX8MP HDMI blk-ctrl
> >   soc: imx: add i.MX8MP HDMI blk-ctrl
> >   arm64: dts: imx8mp: add HSIO power-domains
> >   arm64: dts: imx8mp: add HDMI power-domains
> > 
> > Paul Elder (3):
> >   dt-bindings: soc: Add i.MX8MP media block control DT bindings
> >   soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
> >   arm64: dts: imx8mp: Add MEDIA_BLK_CTRL
> > 
> >  .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml     |  84 +++
> >  .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 104 +++
> >  arch/arm64/boot/dts/freescale/imx8mp.dtsi     | 153 +++-
> >  drivers/soc/imx/Makefile                      |   1 +
> >  drivers/soc/imx/imx8m-blk-ctrl.c              | 124 +++-
> >  drivers/soc/imx/imx8mp-blk-ctrl.c             | 696 ++++++++++++++++++
> >  include/dt-bindings/power/imx8mp-power.h      |  18 +
> >  7 files changed, 1172 insertions(+), 8 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
> >  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
> >  create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c

-- 
Regards,

Laurent Pinchart

Re: [PATCH v4 00/11] consolidated i.MX8MP HSIO/MEDIA/HDMI blk-ctrl series

[Laurent Pinchart]

Hi Lucas,

On Wed, May 04, 2022 at 10:27:01AM +0200, Lucas Stach wrote:
> Hi Shawn,
> 
> there were some comments about the implementation of the HDMI blk-ctrl,
> which I don't know in which way to resolve, yet. In the meantime it
> would be very helpful if you could take all but the last patch of this
> series into your tree. They are all reviewed and tested and starting to
> block further work on some parts of the i.MX8MP bringup.

Can we decouple the HDMI blk-ctrl from the rest, to at least upstream
the MEDIA blk-ctrl ? That part is ready.

> Am Mittwoch, dem 06.04.2022 um 17:33 +0200 schrieb Lucas Stach:
> > Hi all,
> > 
> > this series adds a bunch more power domains that integrate with the blk-ctrls
> > to the i.MX8MP. It depends on the i.MX8MP GPCv2 support series posted in [1].
> > 
> > The HSIO blk-ctrl bindings are already applied upstream, so they are not part
> > of this series anymore. The DT description hasn't changed, but the
> > implementation of the HSIO blk-ctrl driver is reworked quite a bit from the
> > last round of patches, so I've dropped the review/tested-by tags.
> > 
> > I've also picked up the pretty thoroughly reviewed and tested MEDIA blk-ctrl
> > patches from Paul and Laurent into this series, as they would conflict with
> > other patches from this series when applied separately. This should hopefully
> > make it easier for Shawn to pick things up.
> > 
> > Finally this now also adds the HDMI blk-ctrl, not part of any previous series.
> > This one is pretty complex and the documentation in the reference manual
> > appears to be inaccurate. I found at least the following issues:
> > 
> > 1. GLOBAL_XTAL24M_CLK_EN does not actually gate the 24MHz reference clock,
> > the PHY PLL happily locks and provides correct clocks without this clock being
> > ungated. It seems to gate some clock input of the HDMI TX controller instead,
> > register access to this controller fails without this clock.
> > 
> > 2. HDMI_RTX_RESET_CTL0 bits 6 and 7 are marked as "reserved" in the manual,
> > but they are actually required to be configured. Bit 6 seems to keep something
> > in the display pixel clock path in inactive state and Bit 7 seems to reset
> > the HDMI TX i2c controller.
> > 
> > The HDMI blk-ctrl part is tested quite extensively with a PoC HDMI support
> > patchset, which I will send out in a bit, so I'm pretty sure that the
> > support as implemented is working. I've put the patches last in the series
> > in case that this turns out to be controversial, so the other patches can
> > be applied independent from the HDMI support.
> > 
> > Regards,
> > Lucas
> > 
> > [1] https://lore.kernel.org/all/20220330104620.3600159-1-l.stach@pengutronix.de/
> > 
> > 
> > Laurent Pinchart (1):
> >   arm64: dts: imx8mp: Add MEDIAMIX power domains
> > 
> > Lucas Stach (7):
> >   soc: imx: imx8m-blk-ctrl: set power device name
> >   soc: imx: add i.MX8MP HSIO blk-ctrl
> >   dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains
> >   dt-bindings: soc: add binding for i.MX8MP HDMI blk-ctrl
> >   soc: imx: add i.MX8MP HDMI blk-ctrl
> >   arm64: dts: imx8mp: add HSIO power-domains
> >   arm64: dts: imx8mp: add HDMI power-domains
> > 
> > Paul Elder (3):
> >   dt-bindings: soc: Add i.MX8MP media block control DT bindings
> >   soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
> >   arm64: dts: imx8mp: Add MEDIA_BLK_CTRL
> > 
> >  .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml     |  84 +++
> >  .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 104 +++
> >  arch/arm64/boot/dts/freescale/imx8mp.dtsi     | 153 +++-
> >  drivers/soc/imx/Makefile                      |   1 +
> >  drivers/soc/imx/imx8m-blk-ctrl.c              | 124 +++-
> >  drivers/soc/imx/imx8mp-blk-ctrl.c             | 696 ++++++++++++++++++
> >  include/dt-bindings/power/imx8mp-power.h      |  18 +
> >  7 files changed, 1172 insertions(+), 8 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
> >  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
> >  create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c

-- 
Regards,

Laurent Pinchart

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Re: [PATCH v4 00/11] consolidated i.MX8MP HSIO/MEDIA/HDMI blk-ctrl series

[Lucas Stach]

Am Mittwoch, dem 04.05.2022 um 11:48 +0300 schrieb Laurent Pinchart:
> Hi Lucas,
> 
> On Wed, May 04, 2022 at 10:27:01AM +0200, Lucas Stach wrote:
> > Hi Shawn,
> > 
> > there were some comments about the implementation of the HDMI blk-ctrl,
> > which I don't know in which way to resolve, yet. In the meantime it
> > would be very helpful if you could take all but the last patch of this
> > series into your tree. They are all reviewed and tested and starting to
> > block further work on some parts of the i.MX8MP bringup.
> 
> Can we decouple the HDMI blk-ctrl from the rest, to at least upstream
> the MEDIA blk-ctrl ? That part is ready.
> 
I've structured the series in such a way that the HDMI part is
decoupled already. All that needs to be done is dropping the last
patch.

Regards,
Lucas

> > Am Mittwoch, dem 06.04.2022 um 17:33 +0200 schrieb Lucas Stach:
> > > Hi all,
> > > 
> > > this series adds a bunch more power domains that integrate with the blk-ctrls
> > > to the i.MX8MP. It depends on the i.MX8MP GPCv2 support series posted in [1].
> > > 
> > > The HSIO blk-ctrl bindings are already applied upstream, so they are not part
> > > of this series anymore. The DT description hasn't changed, but the
> > > implementation of the HSIO blk-ctrl driver is reworked quite a bit from the
> > > last round of patches, so I've dropped the review/tested-by tags.
> > > 
> > > I've also picked up the pretty thoroughly reviewed and tested MEDIA blk-ctrl
> > > patches from Paul and Laurent into this series, as they would conflict with
> > > other patches from this series when applied separately. This should hopefully
> > > make it easier for Shawn to pick things up.
> > > 
> > > Finally this now also adds the HDMI blk-ctrl, not part of any previous series.
> > > This one is pretty complex and the documentation in the reference manual
> > > appears to be inaccurate. I found at least the following issues:
> > > 
> > > 1. GLOBAL_XTAL24M_CLK_EN does not actually gate the 24MHz reference clock,
> > > the PHY PLL happily locks and provides correct clocks without this clock being
> > > ungated. It seems to gate some clock input of the HDMI TX controller instead,
> > > register access to this controller fails without this clock.
> > > 
> > > 2. HDMI_RTX_RESET_CTL0 bits 6 and 7 are marked as "reserved" in the manual,
> > > but they are actually required to be configured. Bit 6 seems to keep something
> > > in the display pixel clock path in inactive state and Bit 7 seems to reset
> > > the HDMI TX i2c controller.
> > > 
> > > The HDMI blk-ctrl part is tested quite extensively with a PoC HDMI support
> > > patchset, which I will send out in a bit, so I'm pretty sure that the
> > > support as implemented is working. I've put the patches last in the series
> > > in case that this turns out to be controversial, so the other patches can
> > > be applied independent from the HDMI support.
> > > 
> > > Regards,
> > > Lucas
> > > 
> > > [1] https://lore.kernel.org/all/20220330104620.3600159-1-l.stach@pengutronix.de/
> > > 
> > > 
> > > Laurent Pinchart (1):
> > >   arm64: dts: imx8mp: Add MEDIAMIX power domains
> > > 
> > > Lucas Stach (7):
> > >   soc: imx: imx8m-blk-ctrl: set power device name
> > >   soc: imx: add i.MX8MP HSIO blk-ctrl
> > >   dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains
> > >   dt-bindings: soc: add binding for i.MX8MP HDMI blk-ctrl
> > >   soc: imx: add i.MX8MP HDMI blk-ctrl
> > >   arm64: dts: imx8mp: add HSIO power-domains
> > >   arm64: dts: imx8mp: add HDMI power-domains
> > > 
> > > Paul Elder (3):
> > >   dt-bindings: soc: Add i.MX8MP media block control DT bindings
> > >   soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
> > >   arm64: dts: imx8mp: Add MEDIA_BLK_CTRL
> > > 
> > >  .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml     |  84 +++
> > >  .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 104 +++
> > >  arch/arm64/boot/dts/freescale/imx8mp.dtsi     | 153 +++-
> > >  drivers/soc/imx/Makefile                      |   1 +
> > >  drivers/soc/imx/imx8m-blk-ctrl.c              | 124 +++-
> > >  drivers/soc/imx/imx8mp-blk-ctrl.c             | 696 ++++++++++++++++++
> > >  include/dt-bindings/power/imx8mp-power.h      |  18 +
> > >  7 files changed, 1172 insertions(+), 8 deletions(-)
> > >  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
> > >  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
> > >  create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c
> 



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Re: [PATCH v4 00/11] consolidated i.MX8MP HSIO/MEDIA/HDMI blk-ctrl series

[Lucas Stach]

Am Mittwoch, dem 04.05.2022 um 11:48 +0300 schrieb Laurent Pinchart:
> Hi Lucas,
> 
> On Wed, May 04, 2022 at 10:27:01AM +0200, Lucas Stach wrote:
> > Hi Shawn,
> > 
> > there were some comments about the implementation of the HDMI blk-ctrl,
> > which I don't know in which way to resolve, yet. In the meantime it
> > would be very helpful if you could take all but the last patch of this
> > series into your tree. They are all reviewed and tested and starting to
> > block further work on some parts of the i.MX8MP bringup.
> 
> Can we decouple the HDMI blk-ctrl from the rest, to at least upstream
> the MEDIA blk-ctrl ? That part is ready.
> 
I've structured the series in such a way that the HDMI part is
decoupled already. All that needs to be done is dropping the last
patch.

Regards,
Lucas

> > Am Mittwoch, dem 06.04.2022 um 17:33 +0200 schrieb Lucas Stach:
> > > Hi all,
> > > 
> > > this series adds a bunch more power domains that integrate with the blk-ctrls
> > > to the i.MX8MP. It depends on the i.MX8MP GPCv2 support series posted in [1].
> > > 
> > > The HSIO blk-ctrl bindings are already applied upstream, so they are not part
> > > of this series anymore. The DT description hasn't changed, but the
> > > implementation of the HSIO blk-ctrl driver is reworked quite a bit from the
> > > last round of patches, so I've dropped the review/tested-by tags.
> > > 
> > > I've also picked up the pretty thoroughly reviewed and tested MEDIA blk-ctrl
> > > patches from Paul and Laurent into this series, as they would conflict with
> > > other patches from this series when applied separately. This should hopefully
> > > make it easier for Shawn to pick things up.
> > > 
> > > Finally this now also adds the HDMI blk-ctrl, not part of any previous series.
> > > This one is pretty complex and the documentation in the reference manual
> > > appears to be inaccurate. I found at least the following issues:
> > > 
> > > 1. GLOBAL_XTAL24M_CLK_EN does not actually gate the 24MHz reference clock,
> > > the PHY PLL happily locks and provides correct clocks without this clock being
> > > ungated. It seems to gate some clock input of the HDMI TX controller instead,
> > > register access to this controller fails without this clock.
> > > 
> > > 2. HDMI_RTX_RESET_CTL0 bits 6 and 7 are marked as "reserved" in the manual,
> > > but they are actually required to be configured. Bit 6 seems to keep something
> > > in the display pixel clock path in inactive state and Bit 7 seems to reset
> > > the HDMI TX i2c controller.
> > > 
> > > The HDMI blk-ctrl part is tested quite extensively with a PoC HDMI support
> > > patchset, which I will send out in a bit, so I'm pretty sure that the
> > > support as implemented is working. I've put the patches last in the series
> > > in case that this turns out to be controversial, so the other patches can
> > > be applied independent from the HDMI support.
> > > 
> > > Regards,
> > > Lucas
> > > 
> > > [1] https://lore.kernel.org/all/20220330104620.3600159-1-l.stach@pengutronix.de/
> > > 
> > > 
> > > Laurent Pinchart (1):
> > >   arm64: dts: imx8mp: Add MEDIAMIX power domains
> > > 
> > > Lucas Stach (7):
> > >   soc: imx: imx8m-blk-ctrl: set power device name
> > >   soc: imx: add i.MX8MP HSIO blk-ctrl
> > >   dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains
> > >   dt-bindings: soc: add binding for i.MX8MP HDMI blk-ctrl
> > >   soc: imx: add i.MX8MP HDMI blk-ctrl
> > >   arm64: dts: imx8mp: add HSIO power-domains
> > >   arm64: dts: imx8mp: add HDMI power-domains
> > > 
> > > Paul Elder (3):
> > >   dt-bindings: soc: Add i.MX8MP media block control DT bindings
> > >   soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
> > >   arm64: dts: imx8mp: Add MEDIA_BLK_CTRL
> > > 
> > >  .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml     |  84 +++
> > >  .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 104 +++
> > >  arch/arm64/boot/dts/freescale/imx8mp.dtsi     | 153 +++-
> > >  drivers/soc/imx/Makefile                      |   1 +
> > >  drivers/soc/imx/imx8m-blk-ctrl.c              | 124 +++-
> > >  drivers/soc/imx/imx8mp-blk-ctrl.c             | 696 ++++++++++++++++++
> > >  include/dt-bindings/power/imx8mp-power.h      |  18 +
> > >  7 files changed, 1172 insertions(+), 8 deletions(-)
> > >  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
> > >  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
> > >  create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c
> 

Re: [PATCH v4 00/11] consolidated i.MX8MP HSIO/MEDIA/HDMI blk-ctrl series

[Laurent Pinchart]

Hi Lucas,

On Wed, May 04, 2022 at 10:56:05AM +0200, Lucas Stach wrote:
> Am Mittwoch, dem 04.05.2022 um 11:48 +0300 schrieb Laurent Pinchart:
> > On Wed, May 04, 2022 at 10:27:01AM +0200, Lucas Stach wrote:
> > > Hi Shawn,
> > > 
> > > there were some comments about the implementation of the HDMI blk-ctrl,
> > > which I don't know in which way to resolve, yet. In the meantime it
> > > would be very helpful if you could take all but the last patch of this
> > > series into your tree. They are all reviewed and tested and starting to
> > > block further work on some parts of the i.MX8MP bringup.
> > 
> > Can we decouple the HDMI blk-ctrl from the rest, to at least upstream
> > the MEDIA blk-ctrl ? That part is ready.
> 
> I've structured the series in such a way that the HDMI part is
> decoupled already. All that needs to be done is dropping the last
> patch.

I had misread you and thought you asked Shawn to only apply the last
patch. Indeed, I second the request to get the series applied without
the last patch.

> > > Am Mittwoch, dem 06.04.2022 um 17:33 +0200 schrieb Lucas Stach:
> > > > Hi all,
> > > > 
> > > > this series adds a bunch more power domains that integrate with the blk-ctrls
> > > > to the i.MX8MP. It depends on the i.MX8MP GPCv2 support series posted in [1].
> > > > 
> > > > The HSIO blk-ctrl bindings are already applied upstream, so they are not part
> > > > of this series anymore. The DT description hasn't changed, but the
> > > > implementation of the HSIO blk-ctrl driver is reworked quite a bit from the
> > > > last round of patches, so I've dropped the review/tested-by tags.
> > > > 
> > > > I've also picked up the pretty thoroughly reviewed and tested MEDIA blk-ctrl
> > > > patches from Paul and Laurent into this series, as they would conflict with
> > > > other patches from this series when applied separately. This should hopefully
> > > > make it easier for Shawn to pick things up.
> > > > 
> > > > Finally this now also adds the HDMI blk-ctrl, not part of any previous series.
> > > > This one is pretty complex and the documentation in the reference manual
> > > > appears to be inaccurate. I found at least the following issues:
> > > > 
> > > > 1. GLOBAL_XTAL24M_CLK_EN does not actually gate the 24MHz reference clock,
> > > > the PHY PLL happily locks and provides correct clocks without this clock being
> > > > ungated. It seems to gate some clock input of the HDMI TX controller instead,
> > > > register access to this controller fails without this clock.
> > > > 
> > > > 2. HDMI_RTX_RESET_CTL0 bits 6 and 7 are marked as "reserved" in the manual,
> > > > but they are actually required to be configured. Bit 6 seems to keep something
> > > > in the display pixel clock path in inactive state and Bit 7 seems to reset
> > > > the HDMI TX i2c controller.
> > > > 
> > > > The HDMI blk-ctrl part is tested quite extensively with a PoC HDMI support
> > > > patchset, which I will send out in a bit, so I'm pretty sure that the
> > > > support as implemented is working. I've put the patches last in the series
> > > > in case that this turns out to be controversial, so the other patches can
> > > > be applied independent from the HDMI support.
> > > > 
> > > > Regards,
> > > > Lucas
> > > > 
> > > > [1] https://lore.kernel.org/all/20220330104620.3600159-1-l.stach@pengutronix.de/
> > > > 
> > > > 
> > > > Laurent Pinchart (1):
> > > >   arm64: dts: imx8mp: Add MEDIAMIX power domains
> > > > 
> > > > Lucas Stach (7):
> > > >   soc: imx: imx8m-blk-ctrl: set power device name
> > > >   soc: imx: add i.MX8MP HSIO blk-ctrl
> > > >   dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains
> > > >   dt-bindings: soc: add binding for i.MX8MP HDMI blk-ctrl
> > > >   soc: imx: add i.MX8MP HDMI blk-ctrl
> > > >   arm64: dts: imx8mp: add HSIO power-domains
> > > >   arm64: dts: imx8mp: add HDMI power-domains
> > > > 
> > > > Paul Elder (3):
> > > >   dt-bindings: soc: Add i.MX8MP media block control DT bindings
> > > >   soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
> > > >   arm64: dts: imx8mp: Add MEDIA_BLK_CTRL
> > > > 
> > > >  .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml     |  84 +++
> > > >  .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 104 +++
> > > >  arch/arm64/boot/dts/freescale/imx8mp.dtsi     | 153 +++-
> > > >  drivers/soc/imx/Makefile                      |   1 +
> > > >  drivers/soc/imx/imx8m-blk-ctrl.c              | 124 +++-
> > > >  drivers/soc/imx/imx8mp-blk-ctrl.c             | 696 ++++++++++++++++++
> > > >  include/dt-bindings/power/imx8mp-power.h      |  18 +
> > > >  7 files changed, 1172 insertions(+), 8 deletions(-)
> > > >  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
> > > >  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
> > > >  create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c

-- 
Regards,

Laurent Pinchart

Re: [PATCH v4 00/11] consolidated i.MX8MP HSIO/MEDIA/HDMI blk-ctrl series

[Laurent Pinchart]

Hi Lucas,

On Wed, May 04, 2022 at 10:56:05AM +0200, Lucas Stach wrote:
> Am Mittwoch, dem 04.05.2022 um 11:48 +0300 schrieb Laurent Pinchart:
> > On Wed, May 04, 2022 at 10:27:01AM +0200, Lucas Stach wrote:
> > > Hi Shawn,
> > > 
> > > there were some comments about the implementation of the HDMI blk-ctrl,
> > > which I don't know in which way to resolve, yet. In the meantime it
> > > would be very helpful if you could take all but the last patch of this
> > > series into your tree. They are all reviewed and tested and starting to
> > > block further work on some parts of the i.MX8MP bringup.
> > 
> > Can we decouple the HDMI blk-ctrl from the rest, to at least upstream
> > the MEDIA blk-ctrl ? That part is ready.
> 
> I've structured the series in such a way that the HDMI part is
> decoupled already. All that needs to be done is dropping the last
> patch.

I had misread you and thought you asked Shawn to only apply the last
patch. Indeed, I second the request to get the series applied without
the last patch.

> > > Am Mittwoch, dem 06.04.2022 um 17:33 +0200 schrieb Lucas Stach:
> > > > Hi all,
> > > > 
> > > > this series adds a bunch more power domains that integrate with the blk-ctrls
> > > > to the i.MX8MP. It depends on the i.MX8MP GPCv2 support series posted in [1].
> > > > 
> > > > The HSIO blk-ctrl bindings are already applied upstream, so they are not part
> > > > of this series anymore. The DT description hasn't changed, but the
> > > > implementation of the HSIO blk-ctrl driver is reworked quite a bit from the
> > > > last round of patches, so I've dropped the review/tested-by tags.
> > > > 
> > > > I've also picked up the pretty thoroughly reviewed and tested MEDIA blk-ctrl
> > > > patches from Paul and Laurent into this series, as they would conflict with
> > > > other patches from this series when applied separately. This should hopefully
> > > > make it easier for Shawn to pick things up.
> > > > 
> > > > Finally this now also adds the HDMI blk-ctrl, not part of any previous series.
> > > > This one is pretty complex and the documentation in the reference manual
> > > > appears to be inaccurate. I found at least the following issues:
> > > > 
> > > > 1. GLOBAL_XTAL24M_CLK_EN does not actually gate the 24MHz reference clock,
> > > > the PHY PLL happily locks and provides correct clocks without this clock being
> > > > ungated. It seems to gate some clock input of the HDMI TX controller instead,
> > > > register access to this controller fails without this clock.
> > > > 
> > > > 2. HDMI_RTX_RESET_CTL0 bits 6 and 7 are marked as "reserved" in the manual,
> > > > but they are actually required to be configured. Bit 6 seems to keep something
> > > > in the display pixel clock path in inactive state and Bit 7 seems to reset
> > > > the HDMI TX i2c controller.
> > > > 
> > > > The HDMI blk-ctrl part is tested quite extensively with a PoC HDMI support
> > > > patchset, which I will send out in a bit, so I'm pretty sure that the
> > > > support as implemented is working. I've put the patches last in the series
> > > > in case that this turns out to be controversial, so the other patches can
> > > > be applied independent from the HDMI support.
> > > > 
> > > > Regards,
> > > > Lucas
> > > > 
> > > > [1] https://lore.kernel.org/all/20220330104620.3600159-1-l.stach@pengutronix.de/
> > > > 
> > > > 
> > > > Laurent Pinchart (1):
> > > >   arm64: dts: imx8mp: Add MEDIAMIX power domains
> > > > 
> > > > Lucas Stach (7):
> > > >   soc: imx: imx8m-blk-ctrl: set power device name
> > > >   soc: imx: add i.MX8MP HSIO blk-ctrl
> > > >   dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains
> > > >   dt-bindings: soc: add binding for i.MX8MP HDMI blk-ctrl
> > > >   soc: imx: add i.MX8MP HDMI blk-ctrl
> > > >   arm64: dts: imx8mp: add HSIO power-domains
> > > >   arm64: dts: imx8mp: add HDMI power-domains
> > > > 
> > > > Paul Elder (3):
> > > >   dt-bindings: soc: Add i.MX8MP media block control DT bindings
> > > >   soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
> > > >   arm64: dts: imx8mp: Add MEDIA_BLK_CTRL
> > > > 
> > > >  .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml     |  84 +++
> > > >  .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 104 +++
> > > >  arch/arm64/boot/dts/freescale/imx8mp.dtsi     | 153 +++-
> > > >  drivers/soc/imx/Makefile                      |   1 +
> > > >  drivers/soc/imx/imx8m-blk-ctrl.c              | 124 +++-
> > > >  drivers/soc/imx/imx8mp-blk-ctrl.c             | 696 ++++++++++++++++++
> > > >  include/dt-bindings/power/imx8mp-power.h      |  18 +
> > > >  7 files changed, 1172 insertions(+), 8 deletions(-)
> > > >  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
> > > >  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
> > > >  create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c

-- 
Regards,

Laurent Pinchart

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Re: [PATCH v4 00/11] consolidated i.MX8MP HSIO/MEDIA/HDMI blk-ctrl series

[Marek Vasut]

On 5/4/22 12:08, Laurent Pinchart wrote:
> Hi Lucas,

Hello all,

> On Wed, May 04, 2022 at 10:56:05AM +0200, Lucas Stach wrote:
>> Am Mittwoch, dem 04.05.2022 um 11:48 +0300 schrieb Laurent Pinchart:
>>> On Wed, May 04, 2022 at 10:27:01AM +0200, Lucas Stach wrote:
>>>> Hi Shawn,
>>>>
>>>> there were some comments about the implementation of the HDMI blk-ctrl,
>>>> which I don't know in which way to resolve, yet. In the meantime it
>>>> would be very helpful if you could take all but the last patch of this
>>>> series into your tree. They are all reviewed and tested and starting to
>>>> block further work on some parts of the i.MX8MP bringup.
>>>
>>> Can we decouple the HDMI blk-ctrl from the rest, to at least upstream
>>> the MEDIA blk-ctrl ? That part is ready.
>>
>> I've structured the series in such a way that the HDMI part is
>> decoupled already. All that needs to be done is dropping the last
>> patch.
> 
> I had misread you and thought you asked Shawn to only apply the last
> patch. Indeed, I second the request to get the series applied without
> the last patch.

I agree with Lucas and you too, getting the first 10 patches in would be 
most helpful.

Re: [PATCH v4 00/11] consolidated i.MX8MP HSIO/MEDIA/HDMI blk-ctrl series

[Marek Vasut]

On 5/4/22 12:08, Laurent Pinchart wrote:
> Hi Lucas,

Hello all,

> On Wed, May 04, 2022 at 10:56:05AM +0200, Lucas Stach wrote:
>> Am Mittwoch, dem 04.05.2022 um 11:48 +0300 schrieb Laurent Pinchart:
>>> On Wed, May 04, 2022 at 10:27:01AM +0200, Lucas Stach wrote:
>>>> Hi Shawn,
>>>>
>>>> there were some comments about the implementation of the HDMI blk-ctrl,
>>>> which I don't know in which way to resolve, yet. In the meantime it
>>>> would be very helpful if you could take all but the last patch of this
>>>> series into your tree. They are all reviewed and tested and starting to
>>>> block further work on some parts of the i.MX8MP bringup.
>>>
>>> Can we decouple the HDMI blk-ctrl from the rest, to at least upstream
>>> the MEDIA blk-ctrl ? That part is ready.
>>
>> I've structured the series in such a way that the HDMI part is
>> decoupled already. All that needs to be done is dropping the last
>> patch.
> 
> I had misread you and thought you asked Shawn to only apply the last
> patch. Indeed, I second the request to get the series applied without
> the last patch.

I agree with Lucas and you too, getting the first 10 patches in would be 
most helpful.

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Re: [PATCH v4 00/11] consolidated i.MX8MP HSIO/MEDIA/HDMI blk-ctrl series

[Shawn Guo]

On Wed, Apr 06, 2022 at 05:33:51PM +0200, Lucas Stach wrote:
> Hi all,
> 
> this series adds a bunch more power domains that integrate with the blk-ctrls
> to the i.MX8MP. It depends on the i.MX8MP GPCv2 support series posted in [1].
> 
> The HSIO blk-ctrl bindings are already applied upstream, so they are not part
> of this series anymore. The DT description hasn't changed, but the
> implementation of the HSIO blk-ctrl driver is reworked quite a bit from the
> last round of patches, so I've dropped the review/tested-by tags.
> 
> I've also picked up the pretty thoroughly reviewed and tested MEDIA blk-ctrl
> patches from Paul and Laurent into this series, as they would conflict with
> other patches from this series when applied separately. This should hopefully
> make it easier for Shawn to pick things up.
> 
> Finally this now also adds the HDMI blk-ctrl, not part of any previous series.
> This one is pretty complex and the documentation in the reference manual
> appears to be inaccurate. I found at least the following issues:
> 
> 1. GLOBAL_XTAL24M_CLK_EN does not actually gate the 24MHz reference clock,
> the PHY PLL happily locks and provides correct clocks without this clock being
> ungated. It seems to gate some clock input of the HDMI TX controller instead,
> register access to this controller fails without this clock.
> 
> 2. HDMI_RTX_RESET_CTL0 bits 6 and 7 are marked as "reserved" in the manual,
> but they are actually required to be configured. Bit 6 seems to keep something
> in the display pixel clock path in inactive state and Bit 7 seems to reset
> the HDMI TX i2c controller.
> 
> The HDMI blk-ctrl part is tested quite extensively with a PoC HDMI support
> patchset, which I will send out in a bit, so I'm pretty sure that the
> support as implemented is working. I've put the patches last in the series
> in case that this turns out to be controversial, so the other patches can
> be applied independent from the HDMI support.
> 
> Regards,
> Lucas
> 
> [1] https://lore.kernel.org/all/20220330104620.3600159-1-l.stach@pengutronix.de/
> 
> 
> Laurent Pinchart (1):
>   arm64: dts: imx8mp: Add MEDIAMIX power domains
> 
> Lucas Stach (7):
>   soc: imx: imx8m-blk-ctrl: set power device name
>   soc: imx: add i.MX8MP HSIO blk-ctrl
>   dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains
>   dt-bindings: soc: add binding for i.MX8MP HDMI blk-ctrl
>   soc: imx: add i.MX8MP HDMI blk-ctrl
>   arm64: dts: imx8mp: add HSIO power-domains

>   arm64: dts: imx8mp: add HDMI power-domains

Applied all except this one.

Shawn

> 
> Paul Elder (3):
>   dt-bindings: soc: Add i.MX8MP media block control DT bindings
>   soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
>   arm64: dts: imx8mp: Add MEDIA_BLK_CTRL
> 
>  .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml     |  84 +++
>  .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 104 +++
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi     | 153 +++-
>  drivers/soc/imx/Makefile                      |   1 +
>  drivers/soc/imx/imx8m-blk-ctrl.c              | 124 +++-
>  drivers/soc/imx/imx8mp-blk-ctrl.c             | 696 ++++++++++++++++++
>  include/dt-bindings/power/imx8mp-power.h      |  18 +
>  7 files changed, 1172 insertions(+), 8 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
>  create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c
> 
> -- 
> 2.30.2
> 

Re: [PATCH v4 00/11] consolidated i.MX8MP HSIO/MEDIA/HDMI blk-ctrl series

[Shawn Guo]

On Wed, Apr 06, 2022 at 05:33:51PM +0200, Lucas Stach wrote:
> Hi all,
> 
> this series adds a bunch more power domains that integrate with the blk-ctrls
> to the i.MX8MP. It depends on the i.MX8MP GPCv2 support series posted in [1].
> 
> The HSIO blk-ctrl bindings are already applied upstream, so they are not part
> of this series anymore. The DT description hasn't changed, but the
> implementation of the HSIO blk-ctrl driver is reworked quite a bit from the
> last round of patches, so I've dropped the review/tested-by tags.
> 
> I've also picked up the pretty thoroughly reviewed and tested MEDIA blk-ctrl
> patches from Paul and Laurent into this series, as they would conflict with
> other patches from this series when applied separately. This should hopefully
> make it easier for Shawn to pick things up.
> 
> Finally this now also adds the HDMI blk-ctrl, not part of any previous series.
> This one is pretty complex and the documentation in the reference manual
> appears to be inaccurate. I found at least the following issues:
> 
> 1. GLOBAL_XTAL24M_CLK_EN does not actually gate the 24MHz reference clock,
> the PHY PLL happily locks and provides correct clocks without this clock being
> ungated. It seems to gate some clock input of the HDMI TX controller instead,
> register access to this controller fails without this clock.
> 
> 2. HDMI_RTX_RESET_CTL0 bits 6 and 7 are marked as "reserved" in the manual,
> but they are actually required to be configured. Bit 6 seems to keep something
> in the display pixel clock path in inactive state and Bit 7 seems to reset
> the HDMI TX i2c controller.
> 
> The HDMI blk-ctrl part is tested quite extensively with a PoC HDMI support
> patchset, which I will send out in a bit, so I'm pretty sure that the
> support as implemented is working. I've put the patches last in the series
> in case that this turns out to be controversial, so the other patches can
> be applied independent from the HDMI support.
> 
> Regards,
> Lucas
> 
> [1] https://lore.kernel.org/all/20220330104620.3600159-1-l.stach@pengutronix.de/
> 
> 
> Laurent Pinchart (1):
>   arm64: dts: imx8mp: Add MEDIAMIX power domains
> 
> Lucas Stach (7):
>   soc: imx: imx8m-blk-ctrl: set power device name
>   soc: imx: add i.MX8MP HSIO blk-ctrl
>   dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains
>   dt-bindings: soc: add binding for i.MX8MP HDMI blk-ctrl
>   soc: imx: add i.MX8MP HDMI blk-ctrl
>   arm64: dts: imx8mp: add HSIO power-domains

>   arm64: dts: imx8mp: add HDMI power-domains

Applied all except this one.

Shawn

> 
> Paul Elder (3):
>   dt-bindings: soc: Add i.MX8MP media block control DT bindings
>   soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
>   arm64: dts: imx8mp: Add MEDIA_BLK_CTRL
> 
>  .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml     |  84 +++
>  .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 104 +++
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi     | 153 +++-
>  drivers/soc/imx/Makefile                      |   1 +
>  drivers/soc/imx/imx8m-blk-ctrl.c              | 124 +++-
>  drivers/soc/imx/imx8mp-blk-ctrl.c             | 696 ++++++++++++++++++
>  include/dt-bindings/power/imx8mp-power.h      |  18 +
>  7 files changed, 1172 insertions(+), 8 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
>  create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c
> 
> -- 
> 2.30.2
> 

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Re: [PATCH v4 03/11] dt-bindings: soc: Add i.MX8MP media block control DT bindings

[Rob Herring]

On Wed, Apr 6, 2022 at 10:34 AM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> From: Paul Elder <paul.elder@ideasonboard.com>
>
> The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level
> peripheral providing access to the NoC and ensuring proper power
> sequencing of the peripherals within the MEDIAMIX domain. Add DT
> bindings for it.
>
> There is already a driver for block controls of other SoCs in the i.MX8M
> family, so these bindings will expand upon that.
>
> Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Reviewed-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 104 ++++++++++++++++++
>  include/dt-bindings/power/imx8mp-power.h      |  10 ++
>  2 files changed, 114 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml

This is now failing in linux-next:

/builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.example.dtb:
blk-ctl@32ec0000: power-domain-names:7: 'isp' was expected
 From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml

Rob

Re: [PATCH v4 03/11] dt-bindings: soc: Add i.MX8MP media block control DT bindings

[Rob Herring]

On Wed, Apr 6, 2022 at 10:34 AM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> From: Paul Elder <paul.elder@ideasonboard.com>
>
> The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level
> peripheral providing access to the NoC and ensuring proper power
> sequencing of the peripherals within the MEDIAMIX domain. Add DT
> bindings for it.
>
> There is already a driver for block controls of other SoCs in the i.MX8M
> family, so these bindings will expand upon that.
>
> Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Reviewed-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 104 ++++++++++++++++++
>  include/dt-bindings/power/imx8mp-power.h      |  10 ++
>  2 files changed, 114 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml

This is now failing in linux-next:

/builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.example.dtb:
blk-ctl@32ec0000: power-domain-names:7: 'isp' was expected
 From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml

Rob

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Re: [PATCH v4 03/11] dt-bindings: soc: Add i.MX8MP media block control DT bindings

[Laurent Pinchart]

On Mon, May 09, 2022 at 07:39:22AM -0500, Rob Herring wrote:
> On Wed, Apr 6, 2022 at 10:34 AM Lucas Stach <l.stach@pengutronix.de> wrote:
> >
> > From: Paul Elder <paul.elder@ideasonboard.com>
> >
> > The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level
> > peripheral providing access to the NoC and ensuring proper power
> > sequencing of the peripherals within the MEDIAMIX domain. Add DT
> > bindings for it.
> >
> > There is already a driver for block controls of other SoCs in the i.MX8M
> > family, so these bindings will expand upon that.
> >
> > Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > Reviewed-by: Marek Vasut <marex@denx.de>
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> >  .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 104 ++++++++++++++++++
> >  include/dt-bindings/power/imx8mp-power.h      |  10 ++
> >  2 files changed, 114 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
> 
> This is now failing in linux-next:
> 
> /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.example.dtb:
> blk-ctl@32ec0000: power-domain-names:7: 'isp' was expected
>  From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml

I'm not sure how that went past my tests :-S Sorry about it, I'll submit
a fix shortly.

-- 
Regards,

Laurent Pinchart

Re: [PATCH v4 03/11] dt-bindings: soc: Add i.MX8MP media block control DT bindings

[Laurent Pinchart]

On Mon, May 09, 2022 at 07:39:22AM -0500, Rob Herring wrote:
> On Wed, Apr 6, 2022 at 10:34 AM Lucas Stach <l.stach@pengutronix.de> wrote:
> >
> > From: Paul Elder <paul.elder@ideasonboard.com>
> >
> > The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level
> > peripheral providing access to the NoC and ensuring proper power
> > sequencing of the peripherals within the MEDIAMIX domain. Add DT
> > bindings for it.
> >
> > There is already a driver for block controls of other SoCs in the i.MX8M
> > family, so these bindings will expand upon that.
> >
> > Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > Reviewed-by: Marek Vasut <marex@denx.de>
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> >  .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 104 ++++++++++++++++++
> >  include/dt-bindings/power/imx8mp-power.h      |  10 ++
> >  2 files changed, 114 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
> 
> This is now failing in linux-next:
> 
> /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.example.dtb:
> blk-ctl@32ec0000: power-domain-names:7: 'isp' was expected
>  From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml

I'm not sure how that went past my tests :-S Sorry about it, I'll submit
a fix shortly.

-- 
Regards,

Laurent Pinchart

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