* [PATCH v2 1/4] arm64: dts: qcom: sdm660: move device nodes to sdm636
2022-05-21 20:35 [PATCH v2 0/4] arm64: dts: qcom: enable CDSP and MSS on ifc6560 board Dmitry Baryshkov
@ 2022-05-21 20:35 ` Dmitry Baryshkov
2022-06-29 18:48 ` Konrad Dybcio
2022-05-21 20:35 ` [PATCH v2 2/4] arm64: dts: qcom: sdm660: add device node for the compute PAS Dmitry Baryshkov
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Dmitry Baryshkov @ 2022-05-21 20:35 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, Konrad Dybcio, Marijn Suijten
The sdm636 is a lighter version of sdm660. It lacks Turing DSP (cdsp)
and has slightly different CPU speed and Adreno version.
Reflect this by moving all common device nodes from sdm660.dtsi to
sdm636.dtsi and including the later file from the former one. Currently
this is implemented in the opposite direction, sdm636 includes sdm660,
thus adding cdsp support would require adding delete-node statements to
sdm636.dtsi.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm636.dtsi | 253 +++++++++++++++++++++++++--
arch/arm64/boot/dts/qcom/sdm660.dtsi | 250 +-------------------------
2 files changed, 250 insertions(+), 253 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm636.dtsi b/arch/arm64/boot/dts/qcom/sdm636.dtsi
index ae15d81fa3f9..0cf72f0def38 100644
--- a/arch/arm64/boot/dts/qcom/sdm636.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm636.dtsi
@@ -5,19 +5,248 @@
* Copyright (c) 2020, Martin Botka <martin.botka1@gmail.com>
*/
-#include "sdm660.dtsi"
-
-/*
- * According to the downstream DTS,
- * 636 is basically a 660 except for
- * different CPU frequencies, Adreno
- * 509 instead of 512 and lack of
- * turing IP. These differences will
- * be addressed when the aforementioned
- * peripherals will be enabled upstream.
- */
+#include "sdm630.dtsi"
&adreno_gpu {
compatible = "qcom,adreno-509.0", "qcom,adreno";
- /* Adreno 509 shares the frequency table with 512 */
+ operating-points-v2 = <&gpu_sdm660_opp_table>;
+
+ gpu_sdm660_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /*
+ * 775MHz is only available on the highest speed bin
+ * Though it cannot be used for now due to interconnect
+ * framework not supporting multiple frequencies
+ * at the same opp-level
+
+ opp-750000000 {
+ opp-hz = /bits/ 64 <750000000>;
+ opp-level = <RPM_SMD_LEVEL_TURBO>;
+ opp-peak-kBps = <5412000>;
+ opp-supported-hw = <0xCHECKME>;
+ };
+
+ * These OPPs are correct, but we are lacking support for the
+ * GPU regulator. Hence, disable them for now to prevent the
+ * platform from hanging on high graphics loads.
+
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-level = <RPM_SMD_LEVEL_TURBO>;
+ opp-peak-kBps = <5184000>;
+ opp-supported-hw = <0xFF>;
+ };
+
+ opp-647000000 {
+ opp-hz = /bits/ 64 <647000000>;
+ opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
+ opp-peak-kBps = <4068000>;
+ opp-supported-hw = <0xFF>;
+ };
+
+ opp-588000000 {
+ opp-hz = /bits/ 64 <588000000>;
+ opp-level = <RPM_SMD_LEVEL_NOM>;
+ opp-peak-kBps = <3072000>;
+ opp-supported-hw = <0xFF>;
+ };
+
+ opp-465000000 {
+ opp-hz = /bits/ 64 <465000000>;
+ opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
+ opp-peak-kBps = <2724000>;
+ opp-supported-hw = <0xFF>;
+ };
+
+ opp-370000000 {
+ opp-hz = /bits/ 64 <370000000>;
+ opp-level = <RPM_SMD_LEVEL_SVS>;
+ opp-peak-kBps = <2188000>;
+ opp-supported-hw = <0xFF>;
+ };
+ */
+
+ opp-266000000 {
+ opp-hz = /bits/ 64 <266000000>;
+ opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <1648000>;
+ opp-supported-hw = <0xFF>;
+ };
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
+ opp-peak-kBps = <1200000>;
+ opp-supported-hw = <0xFF>;
+ };
+ };
+};
+
+&CPU0 {
+ compatible = "qcom,kryo260";
+ capacity-dmips-mhz = <1024>;
+ /delete-property/ operating-points-v2;
+};
+
+&CPU1 {
+ compatible = "qcom,kryo260";
+ capacity-dmips-mhz = <1024>;
+ /delete-property/ operating-points-v2;
+};
+
+&CPU2 {
+ compatible = "qcom,kryo260";
+ capacity-dmips-mhz = <1024>;
+ /delete-property/ operating-points-v2;
+};
+
+&CPU3 {
+ compatible = "qcom,kryo260";
+ capacity-dmips-mhz = <1024>;
+ /delete-property/ operating-points-v2;
+};
+
+&CPU4 {
+ compatible = "qcom,kryo260";
+ capacity-dmips-mhz = <640>;
+ /delete-property/ operating-points-v2;
+};
+
+&CPU5 {
+ compatible = "qcom,kryo260";
+ capacity-dmips-mhz = <640>;
+ /delete-property/ operating-points-v2;
+};
+
+&CPU6 {
+ compatible = "qcom,kryo260";
+ capacity-dmips-mhz = <640>;
+ /delete-property/ operating-points-v2;
+};
+
+&CPU7 {
+ compatible = "qcom,kryo260";
+ capacity-dmips-mhz = <640>;
+ /delete-property/ operating-points-v2;
+};
+
+&gcc {
+ compatible = "qcom,gcc-sdm660";
+};
+
+&gpucc {
+ compatible = "qcom,gpucc-sdm660";
+};
+
+&mdp {
+ ports {
+ port@1 {
+ reg = <1>;
+ mdp5_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+};
+
+&mdss {
+ dsi1: dsi@c996000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0x0c996000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ /* DSI1 shares the OPP table with DSI0 */
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmpd SDM660_VDDCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <5>;
+
+ assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
+ <&mmcc PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&dsi1_phy 0>,
+ <&dsi1_phy 1>;
+
+ clocks = <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_BYTE1_CLK>,
+ <&mmcc MDSS_BYTE1_INTF_CLK>,
+ <&mmcc MNOC_AHB_CLK>,
+ <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MISC_AHB_CLK>,
+ <&mmcc MDSS_PCLK1_CLK>,
+ <&mmcc MDSS_ESC1_CLK>;
+ clock-names = "mdp_core",
+ "byte",
+ "byte_intf",
+ "mnoc",
+ "iface",
+ "bus",
+ "core_mmss",
+ "pixel",
+ "core";
+
+ phys = <&dsi1_phy>;
+ phy-names = "dsi";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi1_in: endpoint {
+ remote-endpoint = <&mdp5_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi1_phy: dsi-phy@c996400 {
+ compatible = "qcom,dsi-phy-14nm-660";
+ reg = <0x0c996400 0x100>,
+ <0x0c996500 0x300>,
+ <0x0c996800 0x188>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "ref";
+ status = "disabled";
+ };
+};
+
+&mmcc {
+ compatible = "qcom,mmcc-sdm660";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&sleep_clk>,
+ <&gcc GCC_MMSS_GPLL0_CLK>,
+ <&gcc GCC_MMSS_GPLL0_DIV_CLK>,
+ <&dsi0_phy 1>,
+ <&dsi0_phy 0>,
+ <&dsi1_phy 1>,
+ <&dsi1_phy 0>,
+ <0>,
+ <0>;
+};
+
+&tlmm {
+ compatible = "qcom,sdm660-pinctrl";
+};
+
+&tsens {
+ #qcom,sensors = <14>;
};
diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi
index c92f1cef3d3c..f51f5b27819f 100644
--- a/arch/arm64/boot/dts/qcom/sdm660.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi
@@ -7,248 +7,16 @@
* Copyright (c) 2020, Martin Botka <martin.botka1@gmail.com>
*/
-#include "sdm630.dtsi"
+#include "sdm636.dtsi"
+
+/*
+ * According to the downstream DTS, 660 is basically a 660 except for different
+ * CPU frequencies, Adreno 512 instead of 509 and presens of turing IP. These
+ * differences will be addressed when the aforementioned peripherals will be
+ * enabled upstream.
+ */
&adreno_gpu {
compatible = "qcom,adreno-512.0", "qcom,adreno";
- operating-points-v2 = <&gpu_sdm660_opp_table>;
-
- gpu_sdm660_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- /*
- * 775MHz is only available on the highest speed bin
- * Though it cannot be used for now due to interconnect
- * framework not supporting multiple frequencies
- * at the same opp-level
-
- opp-750000000 {
- opp-hz = /bits/ 64 <750000000>;
- opp-level = <RPM_SMD_LEVEL_TURBO>;
- opp-peak-kBps = <5412000>;
- opp-supported-hw = <0xCHECKME>;
- };
-
- * These OPPs are correct, but we are lacking support for the
- * GPU regulator. Hence, disable them for now to prevent the
- * platform from hanging on high graphics loads.
-
- opp-700000000 {
- opp-hz = /bits/ 64 <700000000>;
- opp-level = <RPM_SMD_LEVEL_TURBO>;
- opp-peak-kBps = <5184000>;
- opp-supported-hw = <0xFF>;
- };
-
- opp-647000000 {
- opp-hz = /bits/ 64 <647000000>;
- opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
- opp-peak-kBps = <4068000>;
- opp-supported-hw = <0xFF>;
- };
-
- opp-588000000 {
- opp-hz = /bits/ 64 <588000000>;
- opp-level = <RPM_SMD_LEVEL_NOM>;
- opp-peak-kBps = <3072000>;
- opp-supported-hw = <0xFF>;
- };
-
- opp-465000000 {
- opp-hz = /bits/ 64 <465000000>;
- opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
- opp-peak-kBps = <2724000>;
- opp-supported-hw = <0xFF>;
- };
-
- opp-370000000 {
- opp-hz = /bits/ 64 <370000000>;
- opp-level = <RPM_SMD_LEVEL_SVS>;
- opp-peak-kBps = <2188000>;
- opp-supported-hw = <0xFF>;
- };
- */
-
- opp-266000000 {
- opp-hz = /bits/ 64 <266000000>;
- opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
- opp-peak-kBps = <1648000>;
- opp-supported-hw = <0xFF>;
- };
-
- opp-160000000 {
- opp-hz = /bits/ 64 <160000000>;
- opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
- opp-peak-kBps = <1200000>;
- opp-supported-hw = <0xFF>;
- };
- };
-};
-
-&CPU0 {
- compatible = "qcom,kryo260";
- capacity-dmips-mhz = <1024>;
- /delete-property/ operating-points-v2;
-};
-
-&CPU1 {
- compatible = "qcom,kryo260";
- capacity-dmips-mhz = <1024>;
- /delete-property/ operating-points-v2;
-};
-
-&CPU2 {
- compatible = "qcom,kryo260";
- capacity-dmips-mhz = <1024>;
- /delete-property/ operating-points-v2;
-};
-
-&CPU3 {
- compatible = "qcom,kryo260";
- capacity-dmips-mhz = <1024>;
- /delete-property/ operating-points-v2;
-};
-
-&CPU4 {
- compatible = "qcom,kryo260";
- capacity-dmips-mhz = <640>;
- /delete-property/ operating-points-v2;
-};
-
-&CPU5 {
- compatible = "qcom,kryo260";
- capacity-dmips-mhz = <640>;
- /delete-property/ operating-points-v2;
-};
-
-&CPU6 {
- compatible = "qcom,kryo260";
- capacity-dmips-mhz = <640>;
- /delete-property/ operating-points-v2;
-};
-
-&CPU7 {
- compatible = "qcom,kryo260";
- capacity-dmips-mhz = <640>;
- /delete-property/ operating-points-v2;
-};
-
-&gcc {
- compatible = "qcom,gcc-sdm660";
-};
-
-&gpucc {
- compatible = "qcom,gpucc-sdm660";
-};
-
-&mdp {
- ports {
- port@1 {
- reg = <1>;
- mdp5_intf2_out: endpoint {
- remote-endpoint = <&dsi1_in>;
- };
- };
- };
-};
-
-&mdss {
- dsi1: dsi@c996000 {
- compatible = "qcom,mdss-dsi-ctrl";
- reg = <0x0c996000 0x400>;
- reg-names = "dsi_ctrl";
-
- /* DSI1 shares the OPP table with DSI0 */
- operating-points-v2 = <&dsi_opp_table>;
- power-domains = <&rpmpd SDM660_VDDCX>;
-
- interrupt-parent = <&mdss>;
- interrupts = <5>;
-
- assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
- <&mmcc PCLK1_CLK_SRC>;
- assigned-clock-parents = <&dsi1_phy 0>,
- <&dsi1_phy 1>;
-
- clocks = <&mmcc MDSS_MDP_CLK>,
- <&mmcc MDSS_BYTE1_CLK>,
- <&mmcc MDSS_BYTE1_INTF_CLK>,
- <&mmcc MNOC_AHB_CLK>,
- <&mmcc MDSS_AHB_CLK>,
- <&mmcc MDSS_AXI_CLK>,
- <&mmcc MISC_AHB_CLK>,
- <&mmcc MDSS_PCLK1_CLK>,
- <&mmcc MDSS_ESC1_CLK>;
- clock-names = "mdp_core",
- "byte",
- "byte_intf",
- "mnoc",
- "iface",
- "bus",
- "core_mmss",
- "pixel",
- "core";
-
- phys = <&dsi1_phy>;
- phy-names = "dsi";
-
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dsi1_in: endpoint {
- remote-endpoint = <&mdp5_intf2_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- dsi1_out: endpoint {
- };
- };
- };
- };
-
- dsi1_phy: dsi-phy@c996400 {
- compatible = "qcom,dsi-phy-14nm-660";
- reg = <0x0c996400 0x100>,
- <0x0c996500 0x300>,
- <0x0c996800 0x188>;
- reg-names = "dsi_phy",
- "dsi_phy_lane",
- "dsi_pll";
-
- #clock-cells = <1>;
- #phy-cells = <0>;
-
- clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
- clock-names = "iface", "ref";
- status = "disabled";
- };
-};
-
-&mmcc {
- compatible = "qcom,mmcc-sdm660";
- clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
- <&sleep_clk>,
- <&gcc GCC_MMSS_GPLL0_CLK>,
- <&gcc GCC_MMSS_GPLL0_DIV_CLK>,
- <&dsi0_phy 1>,
- <&dsi0_phy 0>,
- <&dsi1_phy 1>,
- <&dsi1_phy 0>,
- <0>,
- <0>;
-};
-
-&tlmm {
- compatible = "qcom,sdm660-pinctrl";
-};
-
-&tsens {
- #qcom,sensors = <14>;
+ /* Adreno 512 shares the frequency table with 509 */
};
--
2.35.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 2/4] arm64: dts: qcom: sdm660: add device node for the compute PAS
2022-05-21 20:35 [PATCH v2 0/4] arm64: dts: qcom: enable CDSP and MSS on ifc6560 board Dmitry Baryshkov
2022-05-21 20:35 ` [PATCH v2 1/4] arm64: dts: qcom: sdm660: move device nodes to sdm636 Dmitry Baryshkov
@ 2022-05-21 20:35 ` Dmitry Baryshkov
2022-06-29 18:50 ` Konrad Dybcio
2022-05-21 20:35 ` [PATCH v2 3/4] arm64: dts: qcom: sdm630: add device node for the modem PAS Dmitry Baryshkov
2022-05-21 20:35 ` [PATCH v2 4/4] arm64: dts: qcom: sda660-inforce-ifc6560: enable cdsp and modem Dmitry Baryshkov
3 siblings, 1 reply; 9+ messages in thread
From: Dmitry Baryshkov @ 2022-05-21 20:35 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, Konrad Dybcio, Marijn Suijten
Add device tree node describing CDSP device found on the SDM660 (but not
on SDM630) platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm660.dtsi | 68 ++++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi
index f51f5b27819f..1869eeaff066 100644
--- a/arch/arm64/boot/dts/qcom/sdm660.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi
@@ -16,6 +16,74 @@
* enabled upstream.
*/
+/ {
+ reserved-memory {
+ /delete-node/ tzbuffer@94a00000;
+
+ cdsp_region: cdsp@94a00000 {
+ reg = <0x0 0x94a00000 0x0 0x600000>;
+ no-map;
+ };
+
+ };
+
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+ interrupts = <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs_glb 30>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ cdsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ cdsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ soc {
+ cdsp_pil: remoteproc@1a300000 {
+ compatible = "qcom,sdm660-cdsp-pas";
+ reg = <0x1a300000 0x4040>;
+
+ interrupts-extended =
+ <&intc GIC_SPI 518 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready",
+ "handover", "stop-ack";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+
+ memory-region = <&cdsp_region>;
+ power-domains = <&rpmpd SDM660_VDDCX>;
+ power-domain-names = "cx";
+
+ qcom,smem-states = <&cdsp_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ glink-edge {
+ interrupts = <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>;
+
+ label = "turing";
+ mboxes = <&apcs_glb 29>;
+ qcom,remote-pid = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+};
+
&adreno_gpu {
compatible = "qcom,adreno-512.0", "qcom,adreno";
/* Adreno 512 shares the frequency table with 509 */
--
2.35.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 3/4] arm64: dts: qcom: sdm630: add device node for the modem PAS
2022-05-21 20:35 [PATCH v2 0/4] arm64: dts: qcom: enable CDSP and MSS on ifc6560 board Dmitry Baryshkov
2022-05-21 20:35 ` [PATCH v2 1/4] arm64: dts: qcom: sdm660: move device nodes to sdm636 Dmitry Baryshkov
2022-05-21 20:35 ` [PATCH v2 2/4] arm64: dts: qcom: sdm660: add device node for the compute PAS Dmitry Baryshkov
@ 2022-05-21 20:35 ` Dmitry Baryshkov
2022-06-29 18:56 ` Konrad Dybcio
2022-05-21 20:35 ` [PATCH v2 4/4] arm64: dts: qcom: sda660-inforce-ifc6560: enable cdsp and modem Dmitry Baryshkov
3 siblings, 1 reply; 9+ messages in thread
From: Dmitry Baryshkov @ 2022-05-21 20:35 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, Konrad Dybcio, Marijn Suijten
Add device tree node describing modem device found on the SDM630/SDM660
devices.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm630.dtsi | 59 ++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index 55de345895e6..25b0067a93af 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1006,6 +1006,65 @@ data {
};
};
+ mss_pil: remoteproc@4080000 {
+ compatible = "qcom,sdm660-mss-pil";
+ reg = <0x04080000 0x408>, <0x04180000 0x48>;
+ reg-names = "qdsp6", "rmb";
+
+ interrupts-extended =
+ <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready",
+ "handover", "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
+ <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
+ <&gcc GCC_BOOT_ROM_AHB_CLK>,
+ <&gcc GCC_MSS_GPLL0_DIV_CLK>,
+ <&gcc GCC_MSS_SNOC_AXI_CLK>,
+ <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "iface", "bus", "mem", "gpll0_mss",
+ "snoc_axi", "mnoc_axi", "xo", "qdss";
+
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ resets = <&gcc GCC_MSS_RESTART>;
+ reset-names = "mss_restart";
+
+ qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
+
+ power-domains = <&rpmpd SDM660_VDDCX>,
+ <&rpmpd SDM660_VDDMX>;
+ power-domain-names = "cx", "mx";
+
+ status = "disabled";
+
+ mba {
+ memory-region = <&mba_region>;
+ };
+
+ mpss {
+ memory-region = <&mpss_region>;
+ };
+
+ glink-edge {
+ interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
+ label = "modem";
+ qcom,remote-pid = <1>;
+ mboxes = <&apcs_glb 15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
adreno_gpu: gpu@5000000 {
compatible = "qcom,adreno-508.0", "qcom,adreno";
--
2.35.1
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