* [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions
@ 2021-01-04 22:11 Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 01/15] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment Philippe Mathieu-Daudé
` (15 more replies)
0 siblings, 16 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-04 22:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
v3: Replace ISA_MIPS3 by ISA_MIPS64 (Richard)
v2: Do not use MIPS3 for 64R1 (Jiaxun)
Missing review: 1, 3, 4, 5
As we don't need to duplicate 32/64-bit ISA defititions,
this series remove the duplicated 64-bit variants,
simplifying the overall.
Regards,
Phil.
$ git backport-diff -u v2 -r ..v3
Key:
[----] : patches are identical
[####] : number of functional differences between upstream/downstream patch
[down] : patch is downstream-only
The flags [FC] indicate (F)unctional and (C)ontextual differences, respective=
ly
001/15:[down] 'target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment'
002/15:[----] [--] 'target/mips/mips-defs: Reorder CPU_MIPS5 definition'
003/15:[down] 'target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPS=
xxR1'
004/15:[down] 'target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64=
bit()'
005/15:[down] 'hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()'
006/15:[0004] [FC] 'target/mips/mips-defs: Use ISA_MIPS32 definition to check=
Release 1'
007/15:[0004] [FC] 'target/mips/mips-defs: Use ISA_MIPS32R2 definition to che=
ck Release 2'
008/15:[----] [--] 'target/mips/mips-defs: Use ISA_MIPS32R3 definition to che=
ck Release 3'
009/15:[----] [--] 'target/mips/mips-defs: Use ISA_MIPS32R5 definition to che=
ck Release 5'
010/15:[0002] [FC] 'target/mips/mips-defs: Use ISA_MIPS32R6 definition to che=
ck Release 6'
011/15:[0004] [FC] 'target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1'
012/15:[0006] [FC] 'target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2'
013/15:[----] [-C] 'target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3'
014/15:[----] [--] 'target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5'
015/15:[0018] [FC] 'target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6'
Philippe Mathieu-Daud=C3=A9 (15):
target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment
target/mips/mips-defs: Reorder CPU_MIPS5 definition
target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1
target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()
target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1
target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2
target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3
target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5
target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6
target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1
target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2
target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3
target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5
target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6
target/mips/cpu.h | 5 +
target/mips/internal.h | 8 +-
target/mips/mips-defs.h | 46 +--
hw/mips/boston.c | 6 +-
linux-user/mips/cpu_loop.c | 6 +-
target/mips/cp0_helper.c | 18 +-
target/mips/cp0_timer.c | 4 +-
target/mips/cpu.c | 6 +-
target/mips/fpu_helper.c | 4 +-
target/mips/helper.c | 12 +-
target/mips/translate.c | 620 +++++++++++++++----------------
target/mips/translate_init.c.inc | 14 +-
12 files changed, 370 insertions(+), 379 deletions(-)
--=20
2.26.2
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 01/15] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment
2021-01-04 22:11 [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
@ 2021-01-04 22:11 ` Philippe Mathieu-Daudé
2021-01-04 23:24 ` Richard Henderson
2021-01-04 22:11 ` [PATCH v3 02/15] target/mips/mips-defs: Reorder CPU_MIPS5 definition Philippe Mathieu-Daudé
` (14 subsequent siblings)
15 siblings, 1 reply; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-04 22:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
Remove a comment added 12 years ago but never used (commit
b6d96beda3a: "Use temporary registers for the MIPS FPU emulation").
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/mips-defs.h | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index ed6a7a9e545..555e165fb01 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -1,12 +1,6 @@
#ifndef QEMU_MIPS_DEFS_H
#define QEMU_MIPS_DEFS_H
-/*
- * If we want to use host float regs...
- *
- * #define USE_HOST_FLOAT_REGS
- */
-
/* Real pages are variable size... */
#define MIPS_TLB_MAX 128
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 02/15] target/mips/mips-defs: Reorder CPU_MIPS5 definition
2021-01-04 22:11 [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 01/15] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment Philippe Mathieu-Daudé
@ 2021-01-04 22:11 ` Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 03/15] target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 Philippe Mathieu-Daudé
` (13 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-04 22:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
Move CPU_MIPS5 after CPU_MIPS4 :)
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/mips-defs.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 555e165fb01..48544ba73b4 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -65,13 +65,12 @@
#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2)
#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
+#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
#define CPU_R5900 (CPU_MIPS3 | INSN_R5900)
#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
-#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
-
/* MIPS Technologies "Release 1" */
#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 03/15] target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1
2021-01-04 22:11 [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 01/15] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 02/15] target/mips/mips-defs: Reorder CPU_MIPS5 definition Philippe Mathieu-Daudé
@ 2021-01-04 22:11 ` Philippe Mathieu-Daudé
2021-01-04 23:25 ` Richard Henderson
2021-01-04 22:11 ` [PATCH v3 04/15] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() Philippe Mathieu-Daudé
` (12 subsequent siblings)
15 siblings, 1 reply; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-04 22:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing
the "Release 1" ISA. Rename it with the 'R1' suffix, as the other
CPU definitions do.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/mips-defs.h | 8 ++++----
target/mips/translate_init.c.inc | 14 +++++++-------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 48544ba73b4..1630ae20d59 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -72,12 +72,12 @@
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
/* MIPS Technologies "Release 1" */
-#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
-#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
+#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32)
+#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64)
/* MIPS Technologies "Release 2" */
-#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
-#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
+#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2)
+#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2 | ISA_MIPS64R2)
/* MIPS Technologies "Release 3" */
#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index f72fee3b40a..427da84768b 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -72,7 +72,7 @@ const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x1278FF17,
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_MIPS32,
+ .insn_flags = CPU_MIPS32R1,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -94,7 +94,7 @@ const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x1258FF17,
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_MIPS32 | ASE_MIPS16,
+ .insn_flags = CPU_MIPS32R1 | ASE_MIPS16,
.mmu_type = MMU_TYPE_FMT,
},
{
@@ -114,7 +114,7 @@ const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x1278FF17,
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_MIPS32,
+ .insn_flags = CPU_MIPS32R1,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -134,7 +134,7 @@ const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x1258FF17,
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_MIPS32 | ASE_MIPS16,
+ .insn_flags = CPU_MIPS32R1 | ASE_MIPS16,
.mmu_type = MMU_TYPE_FMT,
},
{
@@ -550,7 +550,7 @@ const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x12F8FFFF,
.SEGBITS = 42,
.PABITS = 36,
- .insn_flags = CPU_MIPS64,
+ .insn_flags = CPU_MIPS64R1,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -576,7 +576,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 42,
.PABITS = 36,
- .insn_flags = CPU_MIPS64,
+ .insn_flags = CPU_MIPS64R1,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -605,7 +605,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 40,
.PABITS = 36,
- .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
+ .insn_flags = CPU_MIPS64R1 | ASE_MIPS3D,
.mmu_type = MMU_TYPE_R4000,
},
{
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 04/15] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
2021-01-04 22:11 [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2021-01-04 22:11 ` [PATCH v3 03/15] target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 Philippe Mathieu-Daudé
@ 2021-01-04 22:11 ` Philippe Mathieu-Daudé
2021-01-04 23:30 ` Richard Henderson
2021-01-04 22:11 ` [PATCH v3 05/15] hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() Philippe Mathieu-Daudé
` (11 subsequent siblings)
15 siblings, 1 reply; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-04 22:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
MIPS 64-bit ISA is introduced with MIPS3.
Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA,
and the cpu_type_is_64bit() method to check if a CPU supports
this ISA (thus is 64-bit).
Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu.h | 5 +++++
target/mips/mips-defs.h | 4 +++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 4cbc31c3e8d..7c60a335f97 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1297,6 +1297,11 @@ static inline bool ase_mt_available(CPUMIPSState *env)
return env->CP0_Config3 & (1 << CP0C3_MT);
}
+static inline bool cpu_type_is_64bit(const char *cpu_type)
+{
+ return cpu_type_supports_isa(cpu_type, CPU_MIPS64);
+}
+
void cpu_set_exception_base(int vp_index, target_ulong address);
/* addr.c */
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 1630ae20d59..89a9a4dda31 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -13,7 +13,7 @@
*/
#define ISA_MIPS1 0x0000000000000001ULL
#define ISA_MIPS2 0x0000000000000002ULL
-#define ISA_MIPS3 0x0000000000000004ULL
+#define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */
#define ISA_MIPS4 0x0000000000000008ULL
#define ISA_MIPS5 0x0000000000000010ULL
#define ISA_MIPS32 0x0000000000000020ULL
@@ -71,6 +71,8 @@
#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
+#define CPU_MIPS64 (ISA_MIPS3)
+
/* MIPS Technologies "Release 1" */
#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32)
#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64)
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 05/15] hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()
2021-01-04 22:11 [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2021-01-04 22:11 ` [PATCH v3 04/15] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() Philippe Mathieu-Daudé
@ 2021-01-04 22:11 ` Philippe Mathieu-Daudé
2021-01-04 23:32 ` Richard Henderson
2021-01-04 22:11 ` [PATCH v3 06/15] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 Philippe Mathieu-Daudé
` (10 subsequent siblings)
15 siblings, 1 reply; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-04 22:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
Directly check if the CPU supports 64-bit with the recently
added cpu_type_is_64bit() helper (inlined).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/mips/boston.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index c3b94c68e1b..467fbc1c8be 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -444,7 +444,6 @@ static void boston_mach_init(MachineState *machine)
DriveInfo *hd[6];
Chardev *chr;
int fw_size, fit_err;
- bool is_64b;
if ((machine->ram_size % GiB) ||
(machine->ram_size > (2 * GiB))) {
@@ -463,8 +462,6 @@ static void boston_mach_init(MachineState *machine)
exit(1);
}
- is_64b = cpu_type_supports_isa(machine->cpu_type, ISA_MIPS64);
-
object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS);
object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type,
&error_fatal);
@@ -545,7 +542,8 @@ static void boston_mach_init(MachineState *machine)
}
gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000,
- s->kernel_entry, s->fdt_base, is_64b);
+ s->kernel_entry, s->fdt_base,
+ cpu_type_is_64bit(machine->cpu_type));
} else if (!qtest_enabled()) {
error_report("Please provide either a -kernel or -bios argument");
exit(1);
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 06/15] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1
2021-01-04 22:11 [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2021-01-04 22:11 ` [PATCH v3 05/15] hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() Philippe Mathieu-Daudé
@ 2021-01-04 22:11 ` Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 07/15] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 Philippe Mathieu-Daudé
` (9 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-04 22:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
Use the single ISA_MIPS32 definition to check if the Release 1
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R1 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/mips-defs.h | 3 +--
target/mips/translate.c | 10 +++++-----
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 89a9a4dda31..23ce8b8406f 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -18,7 +18,6 @@
#define ISA_MIPS5 0x0000000000000010ULL
#define ISA_MIPS32 0x0000000000000020ULL
#define ISA_MIPS32R2 0x0000000000000040ULL
-#define ISA_MIPS64 0x0000000000000080ULL
#define ISA_MIPS64R2 0x0000000000000100ULL
#define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS64R3 0x0000000000000400ULL
@@ -75,7 +74,7 @@
/* MIPS Technologies "Release 1" */
#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32)
-#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64)
+#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1)
/* MIPS Technologies "Release 2" */
#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 19933b7868c..172027f9d6e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -8943,7 +8943,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS32);
}
switch (reg) {
@@ -9669,7 +9669,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS32);
}
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
@@ -14907,12 +14907,12 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
break;
#if defined(TARGET_MIPS64)
case RR_RY_CNVT_ZEW:
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS32);
check_mips_64(ctx);
tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]);
break;
case RR_RY_CNVT_SEW:
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS32);
check_mips_64(ctx);
tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
break;
@@ -27612,7 +27612,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
#if defined(TARGET_MIPS64)
case OPC_DCLO:
case OPC_DCLZ:
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS32);
check_mips_64(ctx);
gen_cl(ctx, op1, rd, rs);
break;
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 07/15] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2
2021-01-04 22:11 [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2021-01-04 22:11 ` [PATCH v3 06/15] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 Philippe Mathieu-Daudé
@ 2021-01-04 22:11 ` Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 08/15] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 Philippe Mathieu-Daudé
` (8 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-04 22:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
Use the single ISA_MIPS32R2 definition to check if the Release 2
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R2 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/mips-defs.h | 3 +--
linux-user/mips/cpu_loop.c | 1 -
target/mips/translate.c | 4 ++--
3 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 23ce8b8406f..b36b59c12d3 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -18,7 +18,6 @@
#define ISA_MIPS5 0x0000000000000010ULL
#define ISA_MIPS32 0x0000000000000020ULL
#define ISA_MIPS32R2 0x0000000000000040ULL
-#define ISA_MIPS64R2 0x0000000000000100ULL
#define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS64R3 0x0000000000000400ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
@@ -78,7 +77,7 @@
/* MIPS Technologies "Release 2" */
#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2)
-#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2 | ISA_MIPS64R2)
+#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2)
/* MIPS Technologies "Release 3" */
#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index cfe7ba5c47d..f0831379cc4 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -385,7 +385,6 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
prog_req.fre &= interp_req.fre;
bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 ||
- env->insn_flags & ISA_MIPS64R2 ||
env->insn_flags & ISA_MIPS32R6 ||
env->insn_flags & ISA_MIPS64R6;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 172027f9d6e..9fc9dedf30d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28621,7 +28621,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
case OPC_DINSM:
case OPC_DINSU:
case OPC_DINS:
- check_insn(ctx, ISA_MIPS64R2);
+ check_insn(ctx, ISA_MIPS32R2);
check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
@@ -28641,7 +28641,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
decode_opc_special3_r6(env, ctx);
break;
default:
- check_insn(ctx, ISA_MIPS64R2);
+ check_insn(ctx, ISA_MIPS32R2);
check_mips_64(ctx);
op2 = MASK_DBSHFL(ctx->opcode);
gen_bshfl(ctx, op2, rt, rd);
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 08/15] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3
2021-01-04 22:11 [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2021-01-04 22:11 ` [PATCH v3 07/15] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 Philippe Mathieu-Daudé
@ 2021-01-04 22:11 ` Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 09/15] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 Philippe Mathieu-Daudé
` (7 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-04 22:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
Use the single ISA_MIPS32R3 definition to check if the Release 3
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R3 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/mips-defs.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index b36b59c12d3..ccdde0b4a43 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -19,7 +19,6 @@
#define ISA_MIPS32 0x0000000000000020ULL
#define ISA_MIPS32R2 0x0000000000000040ULL
#define ISA_MIPS32R3 0x0000000000000200ULL
-#define ISA_MIPS64R3 0x0000000000000400ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
#define ISA_MIPS64R5 0x0000000000001000ULL
#define ISA_MIPS32R6 0x0000000000002000ULL
@@ -81,7 +80,7 @@
/* MIPS Technologies "Release 3" */
#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
-#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
+#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3)
/* MIPS Technologies "Release 5" */
#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 09/15] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5
2021-01-04 22:11 [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2021-01-04 22:11 ` [PATCH v3 08/15] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 Philippe Mathieu-Daudé
@ 2021-01-04 22:11 ` Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 10/15] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 Philippe Mathieu-Daudé
` (6 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-04 22:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
Use the single ISA_MIPS32R5 definition to check if the Release 5
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R5 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/mips-defs.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index ccdde0b4a43..b71127ddd7c 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -20,7 +20,6 @@
#define ISA_MIPS32R2 0x0000000000000040ULL
#define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
-#define ISA_MIPS64R5 0x0000000000001000ULL
#define ISA_MIPS32R6 0x0000000000002000ULL
#define ISA_MIPS64R6 0x0000000000004000ULL
#define ISA_NANOMIPS32 0x0000000000008000ULL
@@ -84,7 +83,7 @@
/* MIPS Technologies "Release 5" */
#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
-#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
+#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5)
/* MIPS Technologies "Release 6" */
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 10/15] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6
2021-01-04 22:11 [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2021-01-04 22:11 ` [PATCH v3 09/15] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 Philippe Mathieu-Daudé
@ 2021-01-04 22:11 ` Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 11/15] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 Philippe Mathieu-Daudé
` (5 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-04 22:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
Use the single ISA_MIPS32R6 definition to check if the Release 6
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R6 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/internal.h | 2 +-
target/mips/mips-defs.h | 3 +--
linux-user/mips/cpu_loop.c | 3 +--
target/mips/helper.c | 6 +++---
target/mips/translate.c | 2 +-
5 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index e4d2d9f44f9..3466725b761 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -354,7 +354,7 @@ static inline void compute_hflags(CPUMIPSState *env)
} else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
!(env->CP0_Status & (1 << CP0St_UX))) {
env->hflags |= MIPS_HFLAG_AWRAP;
- } else if (env->insn_flags & ISA_MIPS64R6) {
+ } else if (env->insn_flags & ISA_MIPS32R6) {
/* Address wrapping for Supervisor and Kernel is specified in R6 */
if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
!(env->CP0_Status & (1 << CP0St_SX))) ||
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index b71127ddd7c..fea547508f0 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -21,7 +21,6 @@
#define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
#define ISA_MIPS32R6 0x0000000000002000ULL
-#define ISA_MIPS64R6 0x0000000000004000ULL
#define ISA_NANOMIPS32 0x0000000000008000ULL
/*
* bits 24-39: MIPS ASEs
@@ -87,7 +86,7 @@
/* MIPS Technologies "Release 6" */
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
-#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
+#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6)
/* Wave Computing: "nanoMIPS" */
#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index f0831379cc4..e400166c583 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -385,8 +385,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
prog_req.fre &= interp_req.fre;
bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 ||
- env->insn_flags & ISA_MIPS32R6 ||
- env->insn_flags & ISA_MIPS64R6;
+ env->insn_flags & ISA_MIPS32R6;
if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) {
env->CP0_Config5 |= (1 << CP0C5_FRE);
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 87296fbad69..5b74815beb0 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -1145,7 +1145,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
enter_debug_mode:
if (env->insn_flags & ISA_MIPS3) {
env->hflags |= MIPS_HFLAG_64;
- if (!(env->insn_flags & ISA_MIPS64R6) ||
+ if (!(env->insn_flags & ISA_MIPS32R6) ||
env->CP0_Status & (1 << CP0St_KX)) {
env->hflags &= ~MIPS_HFLAG_AWRAP;
}
@@ -1174,7 +1174,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
if (env->insn_flags & ISA_MIPS3) {
env->hflags |= MIPS_HFLAG_64;
- if (!(env->insn_flags & ISA_MIPS64R6) ||
+ if (!(env->insn_flags & ISA_MIPS32R6) ||
env->CP0_Status & (1 << CP0St_KX)) {
env->hflags &= ~MIPS_HFLAG_AWRAP;
}
@@ -1360,7 +1360,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->CP0_Status |= (1 << CP0St_EXL);
if (env->insn_flags & ISA_MIPS3) {
env->hflags |= MIPS_HFLAG_64;
- if (!(env->insn_flags & ISA_MIPS64R6) ||
+ if (!(env->insn_flags & ISA_MIPS32R6) ||
env->CP0_Status & (1 << CP0St_KX)) {
env->hflags &= ~MIPS_HFLAG_AWRAP;
}
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9fc9dedf30d..fc93b9da8eb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31438,7 +31438,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
#else
ctx->mem_idx = hflags_mmu_index(ctx->hflags);
#endif
- ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS32R6 | ISA_MIPS64R6 |
+ ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS32R6 |
INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 11/15] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1
2021-01-04 22:11 [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2021-01-04 22:11 ` [PATCH v3 10/15] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 Philippe Mathieu-Daudé
@ 2021-01-04 22:11 ` Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 12/15] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 Philippe Mathieu-Daudé
` (4 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-04 22:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
The MIPS ISA release '1' is common to 32/64-bit CPUs.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/internal.h | 2 +-
target/mips/mips-defs.h | 4 +--
target/mips/translate.c | 54 ++++++++++++++++++++---------------------
3 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 3466725b761..94910f75a61 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -411,7 +411,7 @@ static inline void compute_hflags(CPUMIPSState *env)
if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
env->hflags |= MIPS_HFLAG_COP1X;
}
- } else if (env->insn_flags & ISA_MIPS32) {
+ } else if (env->insn_flags & ISA_MIPS_R1) {
if (env->hflags & MIPS_HFLAG_64) {
env->hflags |= MIPS_HFLAG_COP1X;
}
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index fea547508f0..a7048ffaffe 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -16,7 +16,7 @@
#define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */
#define ISA_MIPS4 0x0000000000000008ULL
#define ISA_MIPS5 0x0000000000000010ULL
-#define ISA_MIPS32 0x0000000000000020ULL
+#define ISA_MIPS_R1 0x0000000000000020ULL
#define ISA_MIPS32R2 0x0000000000000040ULL
#define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
@@ -69,7 +69,7 @@
#define CPU_MIPS64 (ISA_MIPS3)
/* MIPS Technologies "Release 1" */
-#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32)
+#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS_R1)
#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1)
/* MIPS Technologies "Release 2" */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index fc93b9da8eb..a59fbd94bac 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7411,7 +7411,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
}
switch (reg) {
@@ -8179,7 +8179,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
}
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
@@ -8943,7 +8943,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
}
switch (reg) {
@@ -9669,7 +9669,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
}
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
@@ -11006,7 +11006,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
break;
case OPC_DERET:
opn = "deret";
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
if ((ctx->insn_flags & ISA_MIPS32R6) &&
(ctx->hflags & MIPS_HFLAG_BMASK)) {
goto die;
@@ -11021,7 +11021,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
break;
case OPC_WAIT:
opn = "wait";
- check_insn(ctx, ISA_MIPS3 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
if ((ctx->insn_flags & ISA_MIPS32R6) &&
(ctx->hflags & MIPS_HFLAG_BMASK)) {
goto die;
@@ -11056,7 +11056,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
}
if (cc != 0) {
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1);
}
btarget = ctx->base.pc_next + 4 + offset;
@@ -14425,7 +14425,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm);
break;
case I8_SVRS:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
{
int xsregs = (ctx->opcode >> 24) & 0x7;
int aregs = (ctx->opcode >> 16) & 0xf;
@@ -14675,7 +14675,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
((int8_t)ctx->opcode) << 3);
break;
case I8_SVRS:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
{
int do_ra = ctx->opcode & (1 << 6);
int do_s0 = ctx->opcode & (1 << 5);
@@ -14819,7 +14819,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
int ra = (ctx->opcode >> 5) & 0x1;
if (nd) {
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
}
if (link) {
@@ -14840,7 +14840,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
* XXX: not clear which exception should be raised
* when in debug mode...
*/
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
generate_exception_end(ctx, EXCP_DBp);
}
break;
@@ -14891,7 +14891,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
gen_HILO(ctx, OPC_MFHI, 0, rx);
break;
case RR_CNVT:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
switch (cnvt_op) {
case RR_RY_CNVT_ZEB:
tcg_gen_ext8u_tl(cpu_gpr[rx], cpu_gpr[rx]);
@@ -14907,12 +14907,12 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
break;
#if defined(TARGET_MIPS64)
case RR_RY_CNVT_ZEW:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
check_mips_64(ctx);
tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]);
break;
case RR_RY_CNVT_SEW:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
check_mips_64(ctx);
tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
break;
@@ -15831,7 +15831,7 @@ static void gen_pool16c_insn(DisasContext *ctx)
* XXX: not clear which exception should be raised
* when in debug mode...
*/
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
generate_exception_end(ctx, EXCP_DBp);
}
break;
@@ -16175,7 +16175,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
case CLZ:
mips32_op = OPC_CLZ;
do_cl:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
gen_cl(ctx, mips32_op, rt, rs);
break;
case RDHWR:
@@ -16202,7 +16202,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
mips32_op = OPC_DIVU;
goto do_div;
do_div:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
gen_muldiv(ctx, mips32_op, 0, rs, rt);
break;
case MADD:
@@ -16221,7 +16221,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_MSUBU;
do_mul:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
gen_muldiv(ctx, mips32_op, 0, rs, rt);
break;
default:
@@ -16369,7 +16369,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
if (is_uhi(extract32(ctx->opcode, 16, 10))) {
gen_helper_do_semihosting(cpu_env);
} else {
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
if (ctx->hflags & MIPS_HFLAG_SBRI) {
generate_exception_end(ctx, EXCP_RI);
} else {
@@ -24889,7 +24889,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
switch (op1) {
case OPC_MOVN: /* Conditional move */
case OPC_MOVZ:
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 |
INSN_LOONGSON2E | INSN_LOONGSON2F);
gen_cond_move(ctx, op1, rd, rs, rt);
break;
@@ -24902,7 +24902,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
gen_HILO(ctx, op1, rd & 3, rs);
break;
case OPC_MOVCI:
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1);
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
@@ -27577,7 +27577,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_MADDU:
case OPC_MSUB:
case OPC_MSUBU:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
gen_muldiv(ctx, op1, rd & 3, rs, rt);
break;
case OPC_MUL:
@@ -27594,7 +27594,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_CLO:
case OPC_CLZ:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
gen_cl(ctx, op1, rd, rs);
break;
case OPC_SDBBP:
@@ -27605,14 +27605,14 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
* XXX: not clear which exception should be raised
* when in debug mode...
*/
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
generate_exception_end(ctx, EXCP_DBp);
}
break;
#if defined(TARGET_MIPS64)
case OPC_DCLO:
case OPC_DCLZ:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
check_mips_64(ctx);
gen_cl(ctx, op1, rd, rs);
break;
@@ -31025,7 +31025,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_CACHE:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
check_cp0_enabled(ctx);
- check_insn(ctx, ISA_MIPS3 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
gen_cache_operation(ctx, rt, rs, imm);
}
@@ -31036,7 +31036,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
if (ctx->insn_flags & INSN_R5900) {
/* Treat as NOP. */
} else {
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1);
/* Treat as NOP. */
}
break;
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 12/15] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2
2021-01-04 22:11 [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2021-01-04 22:11 ` [PATCH v3 11/15] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 Philippe Mathieu-Daudé
@ 2021-01-04 22:11 ` Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 13/15] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 Philippe Mathieu-Daudé
` (3 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-04 22:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
The MIPS ISA release 2 is common to 32/64-bit CPUs.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/internal.h | 2 +-
target/mips/mips-defs.h | 4 +-
linux-user/mips/cpu_loop.c | 2 +-
target/mips/cp0_timer.c | 4 +-
target/mips/helper.c | 2 +-
target/mips/translate.c | 138 ++++++++++++++++++-------------------
6 files changed, 76 insertions(+), 76 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 94910f75a61..23ae31ef989 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -407,7 +407,7 @@ static inline void compute_hflags(CPUMIPSState *env)
}
}
- if (env->insn_flags & ISA_MIPS32R2) {
+ if (env->insn_flags & ISA_MIPS_R2) {
if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
env->hflags |= MIPS_HFLAG_COP1X;
}
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index a7048ffaffe..d1eeb69dfd7 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -17,7 +17,7 @@
#define ISA_MIPS4 0x0000000000000008ULL
#define ISA_MIPS5 0x0000000000000010ULL
#define ISA_MIPS_R1 0x0000000000000020ULL
-#define ISA_MIPS32R2 0x0000000000000040ULL
+#define ISA_MIPS_R2 0x0000000000000040ULL
#define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
#define ISA_MIPS32R6 0x0000000000002000ULL
@@ -73,7 +73,7 @@
#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1)
/* MIPS Technologies "Release 2" */
-#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2)
+#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS_R2)
#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2)
/* MIPS Technologies "Release 3" */
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index e400166c583..748e1c664f1 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -384,7 +384,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
prog_req.frdefault &= interp_req.frdefault;
prog_req.fre &= interp_req.fre;
- bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 ||
+ bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 ||
env->insn_flags & ISA_MIPS32R6;
if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) {
diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c
index 5ec0d6249e9..70de95d338f 100644
--- a/target/mips/cp0_timer.c
+++ b/target/mips/cp0_timer.c
@@ -44,7 +44,7 @@ static void cpu_mips_timer_update(CPUMIPSState *env)
static void cpu_mips_timer_expire(CPUMIPSState *env)
{
cpu_mips_timer_update(env);
- if (env->insn_flags & ISA_MIPS32R2) {
+ if (env->insn_flags & ISA_MIPS_R2) {
env->CP0_Cause |= 1 << CP0Ca_TI;
}
qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
@@ -93,7 +93,7 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value)
if (!(env->CP0_Cause & (1 << CP0Ca_DC))) {
cpu_mips_timer_update(env);
}
- if (env->insn_flags & ISA_MIPS32R2) {
+ if (env->insn_flags & ISA_MIPS_R2) {
env->CP0_Cause &= ~(1 << CP0Ca_TI);
}
qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 5b74815beb0..98d6ecaa65e 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -431,7 +431,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
uint32_t old = env->CP0_Cause;
int i;
- if (env->insn_flags & ISA_MIPS32R2) {
+ if (env->insn_flags & ISA_MIPS_R2) {
mask |= 1 << CP0Ca_DC;
}
if (env->insn_flags & ISA_MIPS32R6) {
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a59fbd94bac..9c71d306ee5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7612,7 +7612,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PageMask";
break;
case CP0_REG05__PAGEGRAIN:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain";
break;
@@ -7660,27 +7660,27 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Wired";
break;
case CP0_REG06__SRSCONF0:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0";
break;
case CP0_REG06__SRSCONF1:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1";
break;
case CP0_REG06__SRSCONF2:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2";
break;
case CP0_REG06__SRSCONF3:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3";
break;
case CP0_REG06__SRSCONF4:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4";
break;
@@ -7696,7 +7696,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_07:
switch (sel) {
case CP0_REG07__HWRENA:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
register_name = "HWREna";
break;
@@ -7791,17 +7791,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Status";
break;
case CP0_REG12__INTCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl";
break;
case CP0_REG12__SRSCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl";
break;
case CP0_REG12__SRSMAP:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap";
break;
@@ -7837,13 +7837,13 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PRid";
break;
case CP0_REG15__EBASE:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EBase";
break;
case CP0_REG15__CMGCRBASE:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
tcg_gen_ext32s_tl(arg, arg);
@@ -8357,7 +8357,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PageMask";
break;
case CP0_REG05__PAGEGRAIN:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain";
ctx->base.is_jmp = DISAS_STOP;
@@ -8403,27 +8403,27 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Wired";
break;
case CP0_REG06__SRSCONF0:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0";
break;
case CP0_REG06__SRSCONF1:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1";
break;
case CP0_REG06__SRSCONF2:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2";
break;
case CP0_REG06__SRSCONF3:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3";
break;
case CP0_REG06__SRSCONF4:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4";
break;
@@ -8439,7 +8439,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_07:
switch (sel) {
case CP0_REG07__HWRENA:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "HWREna";
@@ -8522,21 +8522,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Status";
break;
case CP0_REG12__INTCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
case CP0_REG12__SRSCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
break;
case CP0_REG12__SRSMAP:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
@@ -8581,7 +8581,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PRid";
break;
case CP0_REG15__EBASE:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
break;
@@ -9120,7 +9120,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PageMask";
break;
case CP0_REG05__PAGEGRAIN:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain";
break;
@@ -9165,27 +9165,27 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Wired";
break;
case CP0_REG06__SRSCONF0:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0";
break;
case CP0_REG06__SRSCONF1:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1";
break;
case CP0_REG06__SRSCONF2:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2";
break;
case CP0_REG06__SRSCONF3:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3";
break;
case CP0_REG06__SRSCONF4:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4";
break;
@@ -9201,7 +9201,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_07:
switch (sel) {
case CP0_REG07__HWRENA:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
register_name = "HWREna";
break;
@@ -9294,17 +9294,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Status";
break;
case CP0_REG12__INTCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl";
break;
case CP0_REG12__SRSCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl";
break;
case CP0_REG12__SRSMAP:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap";
break;
@@ -9339,12 +9339,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PRid";
break;
case CP0_REG15__EBASE:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
register_name = "EBase";
break;
case CP0_REG15__CMGCRBASE:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
register_name = "CMGCRBase";
@@ -9847,7 +9847,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PageMask";
break;
case CP0_REG05__PAGEGRAIN:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain";
break;
@@ -9892,27 +9892,27 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Wired";
break;
case CP0_REG06__SRSCONF0:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0";
break;
case CP0_REG06__SRSCONF1:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1";
break;
case CP0_REG06__SRSCONF2:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2";
break;
case CP0_REG06__SRSCONF3:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3";
break;
case CP0_REG06__SRSCONF4:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4";
break;
@@ -9928,7 +9928,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_07:
switch (sel) {
case CP0_REG07__HWRENA:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "HWREna";
@@ -10015,21 +10015,21 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Status";
break;
case CP0_REG12__INTCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
case CP0_REG12__SRSCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
break;
case CP0_REG12__SRSMAP:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
@@ -10074,7 +10074,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "PRid";
break;
case CP0_REG15__EBASE:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
break;
@@ -13453,7 +13453,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
* The Linux kernel will emulate rdhwr if it's not supported natively.
* Therefore only check the ISA in system mode.
*/
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
#endif
t0 = tcg_temp_new();
@@ -16269,12 +16269,12 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
switch (minor) {
case RDPGPR:
check_cp0_enabled(ctx);
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_load_srsgpr(rs, rt);
break;
case WRPGPR:
check_cp0_enabled(ctx);
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_store_srsgpr(rs, rt);
break;
default:
@@ -24984,7 +24984,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
switch ((ctx->opcode >> 21) & 0x1f) {
case 1:
/* rotr is decoded as srl on non-R2 CPUs */
- if (ctx->insn_flags & ISA_MIPS32R2) {
+ if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_ROTR;
}
/* Fallthrough */
@@ -25010,7 +25010,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
switch ((ctx->opcode >> 6) & 0x1f) {
case 1:
/* rotrv is decoded as srlv on non-R2 CPUs */
- if (ctx->insn_flags & ISA_MIPS32R2) {
+ if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_ROTRV;
}
/* Fallthrough */
@@ -25083,7 +25083,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
switch ((ctx->opcode >> 21) & 0x1f) {
case 1:
/* drotr is decoded as dsrl on non-R2 CPUs */
- if (ctx->insn_flags & ISA_MIPS32R2) {
+ if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_DROTR;
}
/* Fallthrough */
@@ -25101,7 +25101,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
switch ((ctx->opcode >> 21) & 0x1f) {
case 1:
/* drotr32 is decoded as dsrl32 on non-R2 CPUs */
- if (ctx->insn_flags & ISA_MIPS32R2) {
+ if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_DROTR32;
}
/* Fallthrough */
@@ -25133,7 +25133,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
switch ((ctx->opcode >> 6) & 0x1f) {
case 1:
/* drotrv is decoded as dsrlv on non-R2 CPUs */
- if (ctx->insn_flags & ISA_MIPS32R2) {
+ if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_DROTRV;
}
/* Fallthrough */
@@ -28594,7 +28594,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
switch (op1) {
case OPC_EXT:
case OPC_INS:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
case OPC_BSHFL:
@@ -28609,7 +28609,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
decode_opc_special3_r6(env, ctx);
break;
default:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_bshfl(ctx, op2, rt, rd);
break;
}
@@ -28621,7 +28621,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
case OPC_DINSM:
case OPC_DINSU:
case OPC_DINS:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
@@ -28641,7 +28641,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
decode_opc_special3_r6(env, ctx);
break;
default:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
check_mips_64(ctx);
op2 = MASK_DBSHFL(ctx->opcode);
gen_bshfl(ctx, op2, rt, rd);
@@ -30741,7 +30741,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
generate_exception_end(ctx, EXCP_RI);
break;
case OPC_SYNCI:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
/*
* Break the TB to be able to sync copied instructions
* immediately.
@@ -30858,7 +30858,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_DI:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
save_cpu_state(ctx, 1);
gen_helper_di(t0, cpu_env);
gen_store_gpr(t0, rt);
@@ -30869,7 +30869,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
ctx->base.is_jmp = DISAS_STOP;
break;
case OPC_EI:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
save_cpu_state(ctx, 1);
gen_helper_ei(t0, cpu_env);
gen_store_gpr(t0, rt);
@@ -30890,11 +30890,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
#endif /* !CONFIG_USER_ONLY */
break;
case OPC_RDPGPR:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_load_srsgpr(rt, rd);
break;
case OPC_WRPGPR:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_store_srsgpr(rt, rd);
break;
default:
@@ -31056,7 +31056,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_MFHC1:
case OPC_MTHC1:
check_cp1_enabled(ctx);
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
/* fall through */
case OPC_MFC1:
case OPC_CFC1:
@@ -31250,21 +31250,21 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
switch (op1) {
case OPC_LUXC1:
case OPC_SUXC1:
- check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2);
/* Fallthrough */
case OPC_LWXC1:
case OPC_LDXC1:
case OPC_SWXC1:
case OPC_SDXC1:
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);
break;
case OPC_PREFX:
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
/* Treat as NOP. */
break;
case OPC_ALNV_PS:
- check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2);
/* Fallthrough */
case OPC_MADD_S:
case OPC_MADD_D:
@@ -31278,7 +31278,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_NMSUB_S:
case OPC_NMSUB_D:
case OPC_NMSUB_PS:
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
break;
default:
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 13/15] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3
2021-01-04 22:11 [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2021-01-04 22:11 ` [PATCH v3 12/15] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 Philippe Mathieu-Daudé
@ 2021-01-04 22:11 ` Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 14/15] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 Philippe Mathieu-Daudé
` (2 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-04 22:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
The MIPS ISA release 3 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/mips-defs.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index d1eeb69dfd7..12ff2b3280c 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -18,7 +18,7 @@
#define ISA_MIPS5 0x0000000000000010ULL
#define ISA_MIPS_R1 0x0000000000000020ULL
#define ISA_MIPS_R2 0x0000000000000040ULL
-#define ISA_MIPS32R3 0x0000000000000200ULL
+#define ISA_MIPS_R3 0x0000000000000080ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
#define ISA_MIPS32R6 0x0000000000002000ULL
#define ISA_NANOMIPS32 0x0000000000008000ULL
@@ -77,7 +77,7 @@
#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2)
/* MIPS Technologies "Release 3" */
-#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS_R3)
#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3)
/* MIPS Technologies "Release 5" */
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 14/15] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5
2021-01-04 22:11 [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2021-01-04 22:11 ` [PATCH v3 13/15] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 Philippe Mathieu-Daudé
@ 2021-01-04 22:11 ` Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 15/15] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 Philippe Mathieu-Daudé
2021-01-06 17:56 ` [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
15 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-04 22:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
The MIPS ISA release 5 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/mips-defs.h | 4 ++--
target/mips/translate.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 12ff2b3280c..181f3715472 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -19,7 +19,7 @@
#define ISA_MIPS_R1 0x0000000000000020ULL
#define ISA_MIPS_R2 0x0000000000000040ULL
#define ISA_MIPS_R3 0x0000000000000080ULL
-#define ISA_MIPS32R5 0x0000000000000800ULL
+#define ISA_MIPS_R5 0x0000000000000100ULL
#define ISA_MIPS32R6 0x0000000000002000ULL
#define ISA_NANOMIPS32 0x0000000000008000ULL
/*
@@ -81,7 +81,7 @@
#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3)
/* MIPS Technologies "Release 5" */
-#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS_R5)
#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5)
/* MIPS Technologies "Release 6" */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9c71d306ee5..83fd6c473a5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -10993,7 +10993,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
if (ctx->opcode & (1 << bit_shift)) {
/* OPC_ERETNC */
opn = "eretnc";
- check_insn(ctx, ISA_MIPS32R5);
+ check_insn(ctx, ISA_MIPS_R5);
gen_helper_eretnc(cpu_env);
} else {
/* OPC_ERET */
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 15/15] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6
2021-01-04 22:11 [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2021-01-04 22:11 ` [PATCH v3 14/15] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 Philippe Mathieu-Daudé
@ 2021-01-04 22:11 ` Philippe Mathieu-Daudé
2021-01-06 17:56 ` [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
15 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-04 22:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
The MIPS ISA release 6 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/internal.h | 4 +-
target/mips/mips-defs.h | 4 +-
linux-user/mips/cpu_loop.c | 2 +-
target/mips/cp0_helper.c | 18 +-
target/mips/cpu.c | 6 +-
target/mips/fpu_helper.c | 4 +-
target/mips/helper.c | 10 +-
target/mips/translate.c | 426 ++++++++++++++++++-------------------
8 files changed, 237 insertions(+), 237 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 23ae31ef989..77a648bcf9c 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -354,7 +354,7 @@ static inline void compute_hflags(CPUMIPSState *env)
} else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
!(env->CP0_Status & (1 << CP0St_UX))) {
env->hflags |= MIPS_HFLAG_AWRAP;
- } else if (env->insn_flags & ISA_MIPS32R6) {
+ } else if (env->insn_flags & ISA_MIPS_R6) {
/* Address wrapping for Supervisor and Kernel is specified in R6 */
if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
!(env->CP0_Status & (1 << CP0St_SX))) ||
@@ -365,7 +365,7 @@ static inline void compute_hflags(CPUMIPSState *env)
}
#endif
if (((env->CP0_Status & (1 << CP0St_CU0)) &&
- !(env->insn_flags & ISA_MIPS32R6)) ||
+ !(env->insn_flags & ISA_MIPS_R6)) ||
!(env->hflags & MIPS_HFLAG_KSU)) {
env->hflags |= MIPS_HFLAG_CP0;
}
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 181f3715472..97866019a72 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -20,7 +20,7 @@
#define ISA_MIPS_R2 0x0000000000000040ULL
#define ISA_MIPS_R3 0x0000000000000080ULL
#define ISA_MIPS_R5 0x0000000000000100ULL
-#define ISA_MIPS32R6 0x0000000000002000ULL
+#define ISA_MIPS_R6 0x0000000000000200ULL
#define ISA_NANOMIPS32 0x0000000000008000ULL
/*
* bits 24-39: MIPS ASEs
@@ -85,7 +85,7 @@
#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5)
/* MIPS Technologies "Release 6" */
-#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
+#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6)
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6)
/* Wave Computing: "nanoMIPS" */
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index 748e1c664f1..19947448a25 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -385,7 +385,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
prog_req.fre &= interp_req.fre;
bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 ||
- env->insn_flags & ISA_MIPS32R6;
+ env->insn_flags & ISA_MIPS_R6;
if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) {
env->CP0_Config5 |= (1 << CP0C5_FRE);
diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
index 36a92857bfb..aae2af6eccc 100644
--- a/target/mips/cp0_helper.c
+++ b/target/mips/cp0_helper.c
@@ -527,7 +527,7 @@ void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
uint32_t index_p = env->CP0_Index & 0x80000000;
uint32_t tlb_index = arg1 & 0x7fffffff;
if (tlb_index < env->tlb->nb_tlb) {
- if (env->insn_flags & ISA_MIPS32R6) {
+ if (env->insn_flags & ISA_MIPS_R6) {
index_p |= arg1 & 0x80000000;
}
env->CP0_Index = index_p | tlb_index;
@@ -960,7 +960,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL;
uint32_t new_ptei = (arg1 >> CP0PF_PTEI) & 0x3FULL;
- if ((env->insn_flags & ISA_MIPS32R6)) {
+ if ((env->insn_flags & ISA_MIPS_R6)) {
if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) {
mask &= ~(0x3FULL << CP0PF_BDI);
}
@@ -980,7 +980,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
env->CP0_PWField = arg1 & mask;
if ((new_ptei >= 32) ||
- ((env->insn_flags & ISA_MIPS32R6) &&
+ ((env->insn_flags & ISA_MIPS_R6) &&
(new_ptei == 0 || new_ptei == 1))) {
env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) |
(old_ptei << CP0PF_PTEI);
@@ -990,7 +990,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
uint32_t new_ptew = (arg1 >> CP0PF_PTEW) & 0x3F;
- if ((env->insn_flags & ISA_MIPS32R6)) {
+ if ((env->insn_flags & ISA_MIPS_R6)) {
if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) {
mask &= ~(0x3F << CP0PF_GDW);
}
@@ -1007,7 +1007,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
env->CP0_PWField = arg1 & mask;
if ((new_ptew >= 32) ||
- ((env->insn_flags & ISA_MIPS32R6) &&
+ ((env->insn_flags & ISA_MIPS_R6) &&
(new_ptew == 0 || new_ptew == 1))) {
env->CP0_PWField = (env->CP0_PWField & ~0x3F) |
(old_ptew << CP0PF_PTEW);
@@ -1026,7 +1026,7 @@ void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
{
- if (env->insn_flags & ISA_MIPS32R6) {
+ if (env->insn_flags & ISA_MIPS_R6) {
if (arg1 < env->tlb->nb_tlb) {
env->CP0_Wired = arg1;
}
@@ -1075,10 +1075,10 @@ void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
uint32_t mask = 0x0000000F;
if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
- (env->insn_flags & ISA_MIPS32R6)) {
+ (env->insn_flags & ISA_MIPS_R6)) {
mask |= (1 << 4);
}
- if (env->insn_flags & ISA_MIPS32R6) {
+ if (env->insn_flags & ISA_MIPS_R6) {
mask |= (1 << 5);
}
if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
@@ -1149,7 +1149,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
/* 1k pages not implemented */
#if defined(TARGET_MIPS64)
- if (env->insn_flags & ISA_MIPS32R6) {
+ if (env->insn_flags & ISA_MIPS_R6) {
int entryhi_r = extract64(arg1, 62, 2);
int config0_at = extract32(env->CP0_Config0, 13, 2);
bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index b2cd69ff7f9..136db626456 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -71,7 +71,7 @@ static bool mips_cpu_has_work(CPUState *cs)
if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
cpu_mips_hw_interrupts_pending(env)) {
if (cpu_mips_hw_interrupts_enabled(env) ||
- (env->insn_flags & ISA_MIPS32R6)) {
+ (env->insn_flags & ISA_MIPS_R6)) {
has_work = true;
}
}
@@ -287,13 +287,13 @@ static void cpu_state_reset(CPUMIPSState *env)
/* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */
env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM);
#endif /* !CONFIG_USER_ONLY */
- if ((env->insn_flags & ISA_MIPS32R6) &&
+ if ((env->insn_flags & ISA_MIPS_R6) &&
(env->active_fpu.fcr0 & (1 << FCR0_F64))) {
/* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
env->CP0_Status |= (1 << CP0St_FR);
}
- if (env->insn_flags & ISA_MIPS32R6) {
+ if (env->insn_flags & ISA_MIPS_R6) {
/* PTW = 1 */
env->CP0_PWSize = 0x40;
/* GDI = 12 */
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index bdb65065ee7..91b6a2e11fc 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -145,7 +145,7 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
}
break;
case 25:
- if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
+ if ((env->insn_flags & ISA_MIPS_R6) || (arg1 & 0xffffff00)) {
return;
}
env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) |
@@ -172,7 +172,7 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
(env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
break;
default:
- if (env->insn_flags & ISA_MIPS32R6) {
+ if (env->insn_flags & ISA_MIPS_R6) {
do_raise_exception(env, EXCP_RI, GETPC());
}
return;
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 98d6ecaa65e..d1b6bb6fb23 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -397,7 +397,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
uint32_t mask = env->CP0_Status_rw_bitmask;
target_ulong old = env->CP0_Status;
- if (env->insn_flags & ISA_MIPS32R6) {
+ if (env->insn_flags & ISA_MIPS_R6) {
bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
#if defined(TARGET_MIPS64)
uint32_t ksux = (1 << CP0St_KX) & val;
@@ -434,7 +434,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
if (env->insn_flags & ISA_MIPS_R2) {
mask |= 1 << CP0Ca_DC;
}
- if (env->insn_flags & ISA_MIPS32R6) {
+ if (env->insn_flags & ISA_MIPS_R6) {
mask &= ~((1 << CP0Ca_WP) & val);
}
@@ -1145,7 +1145,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
enter_debug_mode:
if (env->insn_flags & ISA_MIPS3) {
env->hflags |= MIPS_HFLAG_64;
- if (!(env->insn_flags & ISA_MIPS32R6) ||
+ if (!(env->insn_flags & ISA_MIPS_R6) ||
env->CP0_Status & (1 << CP0St_KX)) {
env->hflags &= ~MIPS_HFLAG_AWRAP;
}
@@ -1174,7 +1174,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
if (env->insn_flags & ISA_MIPS3) {
env->hflags |= MIPS_HFLAG_64;
- if (!(env->insn_flags & ISA_MIPS32R6) ||
+ if (!(env->insn_flags & ISA_MIPS_R6) ||
env->CP0_Status & (1 << CP0St_KX)) {
env->hflags &= ~MIPS_HFLAG_AWRAP;
}
@@ -1360,7 +1360,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->CP0_Status |= (1 << CP0St_EXL);
if (env->insn_flags & ISA_MIPS3) {
env->hflags |= MIPS_HFLAG_64;
- if (!(env->insn_flags & ISA_MIPS32R6) ||
+ if (!(env->insn_flags & ISA_MIPS_R6) ||
env->CP0_Status & (1 << CP0St_KX)) {
env->hflags &= ~MIPS_HFLAG_AWRAP;
}
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 83fd6c473a5..e813add99c5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4014,7 +4014,7 @@ static void gen_logic_imm(DisasContext *ctx, uint32_t opc,
}
break;
case OPC_LUI:
- if (rs != 0 && (ctx->insn_flags & ISA_MIPS32R6)) {
+ if (rs != 0 && (ctx->insn_flags & ISA_MIPS_R6)) {
/* OPC_AUI */
tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm << 16);
tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
@@ -7399,7 +7399,7 @@ cp0_unimplemented:
static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg)
{
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
tcg_gen_movi_tl(arg, 0);
} else {
tcg_gen_movi_tl(arg, ~0);
@@ -7448,7 +7448,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_01:
switch (sel) {
case CP0_REG01__RANDOM:
- CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
+ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
gen_helper_mfc0_random(arg, cpu_env);
register_name = "Random";
break;
@@ -7964,7 +7964,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_21:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
- CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
+ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
@@ -8709,7 +8709,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_21:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
- CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
+ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
switch (sel) {
case 0:
gen_helper_mtc0_framemask(cpu_env, arg);
@@ -8980,7 +8980,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_01:
switch (sel) {
case CP0_REG01__RANDOM:
- CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
+ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
gen_helper_mfc0_random(arg, cpu_env);
register_name = "Random";
break;
@@ -9461,7 +9461,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_21:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
- CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
+ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
switch (sel) {
case 0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
@@ -10191,7 +10191,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_21:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
- CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
+ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
switch (sel) {
case 0:
gen_helper_mtc0_framemask(cpu_env, arg);
@@ -10985,7 +10985,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
gen_helper_tlbr(cpu_env);
break;
case OPC_ERET: /* OPC_ERETNC */
- if ((ctx->insn_flags & ISA_MIPS32R6) &&
+ if ((ctx->insn_flags & ISA_MIPS_R6) &&
(ctx->hflags & MIPS_HFLAG_BMASK)) {
goto die;
} else {
@@ -11007,7 +11007,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
case OPC_DERET:
opn = "deret";
check_insn(ctx, ISA_MIPS_R1);
- if ((ctx->insn_flags & ISA_MIPS32R6) &&
+ if ((ctx->insn_flags & ISA_MIPS_R6) &&
(ctx->hflags & MIPS_HFLAG_BMASK)) {
goto die;
}
@@ -11022,7 +11022,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
case OPC_WAIT:
opn = "wait";
check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
- if ((ctx->insn_flags & ISA_MIPS32R6) &&
+ if ((ctx->insn_flags & ISA_MIPS_R6) &&
(ctx->hflags & MIPS_HFLAG_BMASK)) {
goto die;
}
@@ -11050,7 +11050,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
target_ulong btarget;
TCGv_i32 t0 = tcg_temp_new_i32();
- if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) {
+ if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) {
generate_exception_end(ctx, EXCP_RI);
goto out;
}
@@ -11906,23 +11906,23 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_SEL_S:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_sel_s(ctx, op1, fd, ft, fs);
break;
case OPC_SELEQZ_S:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_sel_s(ctx, op1, fd, ft, fs);
break;
case OPC_SELNEZ_S:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_sel_s(ctx, op1, fd, ft, fs);
break;
case OPC_MOVCF_S:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_movcf_s(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
break;
case OPC_MOVZ_S:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
{
TCGLabel *l1 = gen_new_label();
TCGv_i32 fp0;
@@ -11938,7 +11938,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MOVN_S:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
{
TCGLabel *l1 = gen_new_label();
TCGv_i32 fp0;
@@ -11974,7 +11974,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MADDF_S:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
{
TCGv_i32 fp0 = tcg_temp_new_i32();
TCGv_i32 fp1 = tcg_temp_new_i32();
@@ -11990,7 +11990,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MSUBF_S:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
{
TCGv_i32 fp0 = tcg_temp_new_i32();
TCGv_i32 fp1 = tcg_temp_new_i32();
@@ -12006,7 +12006,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_RINT_S:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
{
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
@@ -12016,7 +12016,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_CLASS_S:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
{
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
@@ -12026,7 +12026,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MIN_S: /* OPC_RECIP2_S */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_MIN_S */
TCGv_i32 fp0 = tcg_temp_new_i32();
TCGv_i32 fp1 = tcg_temp_new_i32();
@@ -12055,7 +12055,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MINA_S: /* OPC_RECIP1_S */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_MINA_S */
TCGv_i32 fp0 = tcg_temp_new_i32();
TCGv_i32 fp1 = tcg_temp_new_i32();
@@ -12081,7 +12081,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MAX_S: /* OPC_RSQRT1_S */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_MAX_S */
TCGv_i32 fp0 = tcg_temp_new_i32();
TCGv_i32 fp1 = tcg_temp_new_i32();
@@ -12105,7 +12105,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MAXA_S: /* OPC_RSQRT2_S */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_MAXA_S */
TCGv_i32 fp0 = tcg_temp_new_i32();
TCGv_i32 fp1 = tcg_temp_new_i32();
@@ -12207,7 +12207,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
case OPC_CMP_NGE_S:
case OPC_CMP_LE_S:
case OPC_CMP_NGT_S:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
if (ctx->opcode & (1 << 6)) {
gen_cmpabs_s(ctx, func - 48, ft, fs, cc);
} else {
@@ -12450,23 +12450,23 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_SEL_D:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_sel_d(ctx, op1, fd, ft, fs);
break;
case OPC_SELEQZ_D:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_sel_d(ctx, op1, fd, ft, fs);
break;
case OPC_SELNEZ_D:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_sel_d(ctx, op1, fd, ft, fs);
break;
case OPC_MOVCF_D:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
break;
case OPC_MOVZ_D:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
{
TCGLabel *l1 = gen_new_label();
TCGv_i64 fp0;
@@ -12482,7 +12482,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MOVN_D:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
{
TCGLabel *l1 = gen_new_label();
TCGv_i64 fp0;
@@ -12520,7 +12520,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MADDF_D:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
{
TCGv_i64 fp0 = tcg_temp_new_i64();
TCGv_i64 fp1 = tcg_temp_new_i64();
@@ -12536,7 +12536,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MSUBF_D:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
{
TCGv_i64 fp0 = tcg_temp_new_i64();
TCGv_i64 fp1 = tcg_temp_new_i64();
@@ -12552,7 +12552,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_RINT_D:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
@@ -12562,7 +12562,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_CLASS_D:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
@@ -12572,7 +12572,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MIN_D: /* OPC_RECIP2_D */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_MIN_D */
TCGv_i64 fp0 = tcg_temp_new_i64();
TCGv_i64 fp1 = tcg_temp_new_i64();
@@ -12599,7 +12599,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MINA_D: /* OPC_RECIP1_D */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_MINA_D */
TCGv_i64 fp0 = tcg_temp_new_i64();
TCGv_i64 fp1 = tcg_temp_new_i64();
@@ -12623,7 +12623,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MAX_D: /* OPC_RSQRT1_D */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_MAX_D */
TCGv_i64 fp0 = tcg_temp_new_i64();
TCGv_i64 fp1 = tcg_temp_new_i64();
@@ -12647,7 +12647,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
}
break;
case OPC_MAXA_D: /* OPC_RSQRT2_D */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_MAXA_D */
TCGv_i64 fp0 = tcg_temp_new_i64();
TCGv_i64 fp1 = tcg_temp_new_i64();
@@ -12689,7 +12689,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
case OPC_CMP_NGE_D:
case OPC_CMP_LE_D:
case OPC_CMP_NGT_D:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
if (ctx->opcode & (1 << 6)) {
gen_cmpabs_d(ctx, func - 48, ft, fs, cc);
} else {
@@ -13485,7 +13485,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
gen_store_gpr(t0, rt);
break;
case 4:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
if (sel != 0) {
/*
* Performance counter registers are not implemented other than
@@ -13497,7 +13497,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
gen_store_gpr(t0, rt);
break;
case 5:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_helper_rdhwr_xnp(t0, cpu_env);
gen_store_gpr(t0, rt);
break;
@@ -16160,7 +16160,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
case 0x2c:
switch (minor) {
case BITSWAP:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_bitswap(ctx, OPC_BITSWAP, rs, rt);
break;
case SEB:
@@ -16179,26 +16179,26 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
gen_cl(ctx, mips32_op, rt, rs);
break;
case RDHWR:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_rdhwr(ctx, rt, rs, 0);
break;
case WSBH:
gen_bshfl(ctx, OPC_WSBH, rs, rt);
break;
case MULT:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MULT;
goto do_mul;
case MULTU:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MULTU;
goto do_mul;
case DIV:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_DIV;
goto do_div;
case DIVU:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_DIVU;
goto do_div;
do_div:
@@ -16206,19 +16206,19 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
gen_muldiv(ctx, mips32_op, 0, rs, rt);
break;
case MADD:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MADD;
goto do_mul;
case MADDU:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MADDU;
goto do_mul;
case MSUB:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MSUB;
goto do_mul;
case MSUBU:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MSUBU;
do_mul:
check_insn(ctx, ISA_MIPS_R1);
@@ -16246,7 +16246,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
switch (minor) {
case JALR: /* JALRC */
case JALR_HB: /* JALRC_HB */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* JALRC, JALRC_HB */
gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0);
} else {
@@ -16257,7 +16257,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
break;
case JALRS:
case JALRS_HB:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 2);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break;
@@ -16400,7 +16400,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
}
break;
case 0x35:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
switch (minor) {
case MFHI32:
gen_HILO(ctx, OPC_MFHI, 0, rs);
@@ -16674,7 +16674,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs)
case COND_FLOAT_MOV(MOVT, 5):
case COND_FLOAT_MOV(MOVT, 6):
case COND_FLOAT_MOV(MOVT, 7):
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 1);
break;
case COND_FLOAT_MOV(MOVF, 0):
@@ -16685,7 +16685,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs)
case COND_FLOAT_MOV(MOVF, 5):
case COND_FLOAT_MOV(MOVF, 6):
case COND_FLOAT_MOV(MOVF, 7):
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 0);
break;
default:
@@ -16736,15 +16736,15 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
gen_shift_imm(ctx, mips32_op, rt, rs, rd);
break;
case SELEQZ:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_cond_move(ctx, OPC_SELEQZ, rd, rs, rt);
break;
case SELNEZ:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_cond_move(ctx, OPC_SELNEZ, rd, rs, rt);
break;
case R6_RDHWR:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3));
break;
default:
@@ -16768,7 +16768,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
mips32_op = OPC_SUBU;
goto do_arith;
case MUL:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MUL;
do_arith:
gen_arith(ctx, mips32_op, rd, rs, rt);
@@ -16821,7 +16821,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
switch (minor) {
/* Conditional moves */
case MOVN: /* MUL */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* MUL */
gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt);
} else {
@@ -16830,7 +16830,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case MOVZ: /* MUH */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* MUH */
gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt);
} else {
@@ -16839,15 +16839,15 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case MULU:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt);
break;
case MUHU:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt);
break;
case LWXS: /* DIV */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* DIV */
gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt);
} else {
@@ -16856,15 +16856,15 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case MOD:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt);
break;
case R6_DIVU:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt);
break;
case MODU:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt);
break;
default:
@@ -16875,12 +16875,12 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
gen_bitops(ctx, OPC_INS, rt, rs, rr, rd);
return;
case LSA:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_lsa(ctx, OPC_LSA, rd, rs, rt,
extract32(ctx->opcode, 9, 2));
break;
case ALIGN:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2));
break;
case EXT:
@@ -16893,7 +16893,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
generate_exception_end(ctx, EXCP_BREAK);
break;
case SIGRIE:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
generate_exception_end(ctx, EXCP_RI);
break;
default:
@@ -16951,61 +16951,61 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
check_cp1_enabled(ctx);
switch (minor) {
case ALNV_PS:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_ALNV_PS;
goto do_madd;
case MADD_S:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MADD_S;
goto do_madd;
case MADD_D:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MADD_D;
goto do_madd;
case MADD_PS:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MADD_PS;
goto do_madd;
case MSUB_S:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MSUB_S;
goto do_madd;
case MSUB_D:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MSUB_D;
goto do_madd;
case MSUB_PS:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_MSUB_PS;
goto do_madd;
case NMADD_S:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_NMADD_S;
goto do_madd;
case NMADD_D:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_NMADD_D;
goto do_madd;
case NMADD_PS:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_NMADD_PS;
goto do_madd;
case NMSUB_S:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_NMSUB_S;
goto do_madd;
case NMSUB_D:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_NMSUB_D;
goto do_madd;
case NMSUB_PS:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_NMSUB_PS;
do_madd:
gen_flt3_arith(ctx, mips32_op, rd, rr, rs, rt);
break;
case CABS_COND_FMT:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
cond = (ctx->opcode >> 6) & 0xf;
cc = (ctx->opcode >> 13) & 0x7;
fmt = (ctx->opcode >> 10) & 0x3;
@@ -17024,7 +17024,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case C_COND_FMT:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
cond = (ctx->opcode >> 6) & 0xf;
cc = (ctx->opcode >> 13) & 0x7;
fmt = (ctx->opcode >> 10) & 0x3;
@@ -17043,11 +17043,11 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case CMP_CONDN_S:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
break;
case CMP_CONDN_D:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
break;
case POOL32FXF:
@@ -17069,7 +17069,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
mips32_op = OPC_PUU_PS;
goto do_ps;
case CVT_PS_S:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_CVT_PS_S;
do_ps:
gen_farith(ctx, mips32_op, rt, rs, rd, 0);
@@ -17079,7 +17079,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case MIN_FMT:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0);
@@ -17095,27 +17095,27 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
/* [LS][WDU]XC1 */
switch ((ctx->opcode >> 6) & 0x7) {
case LWXC1:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LWXC1;
goto do_ldst_cp1;
case SWXC1:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SWXC1;
goto do_ldst_cp1;
case LDXC1:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LDXC1;
goto do_ldst_cp1;
case SDXC1:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SDXC1;
goto do_ldst_cp1;
case LUXC1:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LUXC1;
goto do_ldst_cp1;
case SUXC1:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SUXC1;
do_ldst_cp1:
gen_flt3_ldst(ctx, mips32_op, rd, rd, rt, rs);
@@ -17125,7 +17125,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case MAX_FMT:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0);
@@ -17139,7 +17139,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case 0x18:
/* 3D insns */
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
fmt = (ctx->opcode >> 9) & 0x3;
switch ((ctx->opcode >> 6) & 0x7) {
case RSQRT2_FMT:
@@ -17190,7 +17190,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
fmt = (ctx->opcode >> 9) & 0x3;
switch ((ctx->opcode >> 6) & 0x7) {
case MOVF_FMT: /* RINT_FMT */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* RINT_FMT */
switch (fmt) {
case FMT_SDPS_S:
@@ -17221,7 +17221,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case MOVT_FMT: /* CLASS_FMT */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* CLASS_FMT */
switch (fmt) {
case FMT_SDPS_S:
@@ -17252,7 +17252,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case PREFX:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
break;
default:
goto pool32f_invalid;
@@ -17274,7 +17274,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
goto pool32f_invalid; \
}
case MINA_FMT:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0);
@@ -17287,7 +17287,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case MAXA_FMT:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0);
@@ -17329,7 +17329,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
/* cmovs */
switch ((ctx->opcode >> 6) & 0x7) {
case MOVN_FMT: /* SELEQZ_FMT */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* SELEQZ_FMT */
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
@@ -17347,11 +17347,11 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case MOVN_FMT_04:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
FINSN_3ARG_SDPS(MOVN);
break;
case MOVZ_FMT: /* SELNEZ_FMT */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* SELNEZ_FMT */
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
@@ -17369,11 +17369,11 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case MOVZ_FMT_05:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
FINSN_3ARG_SDPS(MOVZ);
break;
case SEL_FMT:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs);
@@ -17386,7 +17386,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case MADDF_FMT:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
mips32_op = OPC_MADDF_S;
@@ -17399,7 +17399,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case MSUBF_FMT:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
mips32_op = OPC_MSUBF_S;
@@ -17432,45 +17432,45 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
minor = (ctx->opcode >> 21) & 0x1f;
switch (minor) {
case BLTZ:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BLTZ, 4, rs, -1, imm << 1, 4);
break;
case BLTZAL:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 4);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break;
case BLTZALS:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 2);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break;
case BGEZ:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BGEZ, 4, rs, -1, imm << 1, 4);
break;
case BGEZAL:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 4);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break;
case BGEZALS:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 2);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break;
case BLEZ:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BLEZ, 4, rs, -1, imm << 1, 4);
break;
case BGTZ:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, OPC_BGTZ, 4, rs, -1, imm << 1, 4);
break;
/* Traps */
case TLTI: /* BC1EQZC */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* BC1EQZC */
check_cp1_enabled(ctx);
gen_compute_branch1_r6(ctx, OPC_BC1EQZ, rs, imm << 1, 0);
@@ -17481,7 +17481,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case TGEI: /* BC1NEZC */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* BC1NEZC */
check_cp1_enabled(ctx);
gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rs, imm << 1, 0);
@@ -17492,15 +17492,15 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case TLTIU:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_TLTIU;
goto do_trapi;
case TGEIU:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_TGEIU;
goto do_trapi;
case TNEI: /* SYNCI */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* SYNCI */
/*
* Break the TB to be able to sync copied instructions
@@ -17514,7 +17514,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case TEQI:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_TEQI;
do_trapi:
gen_trap(ctx, mips32_op, rs, -1, imm);
@@ -17522,7 +17522,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
case BNEZC:
case BEQZC:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch(ctx, minor == BNEZC ? OPC_BNE : OPC_BEQ,
4, rs, 0, imm << 1, 0);
/*
@@ -17532,11 +17532,11 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
*/
break;
case LUI:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_logic_imm(ctx, OPC_LUI, rs, 0, imm);
break;
case SYNCI:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/*
* Break the TB to be able to sync copied instructions
* immediately.
@@ -17545,24 +17545,24 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case BC2F:
case BC2T:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* COP2: Not implemented. */
generate_exception_err(ctx, EXCP_CpU, 2);
break;
case BC1F:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1FANY2 : OPC_BC1F;
goto do_cp1branch;
case BC1T:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1TANY2 : OPC_BC1T;
goto do_cp1branch;
case BC1ANY4F:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_BC1FANY4;
goto do_cp1mips3d;
case BC1ANY4T:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_BC1TANY4;
do_cp1mips3d:
check_cop1x(ctx);
@@ -17590,47 +17590,47 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
case POOL32C:
minor = (ctx->opcode >> 12) & 0xf;
offset = sextract32(ctx->opcode, 0,
- (ctx->insn_flags & ISA_MIPS32R6) ? 9 : 12);
+ (ctx->insn_flags & ISA_MIPS_R6) ? 9 : 12);
switch (minor) {
case LWL:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LWL;
goto do_ld_lr;
case SWL:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SWL;
goto do_st_lr;
case LWR:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LWR;
goto do_ld_lr;
case SWR:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SWR;
goto do_st_lr;
#if defined(TARGET_MIPS64)
case LDL:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LDL;
goto do_ld_lr;
case SDL:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SDL;
goto do_st_lr;
case LDR:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LDR;
goto do_ld_lr;
case SDR:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SDR;
goto do_st_lr;
case LWU:
@@ -17681,11 +17681,11 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
mips32_op = OPC_LHUE;
goto do_ld_lr;
case LWLE:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LWLE;
goto do_ld_lr;
case LWRE:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_LWRE;
goto do_ld_lr;
case LBE:
@@ -17714,16 +17714,16 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
offset = sextract32(ctx->opcode, 0, 9);
switch (minor2) {
case SWLE:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SWLE;
goto do_st_lr;
case SWRE:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
mips32_op = OPC_SWRE;
goto do_st_lr;
case PREFE:
/* Treat as no-op */
- if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >= 24)) {
+ if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >= 24)) {
/* hint codes 24-31 are reserved and signal RI */
generate_exception(ctx, EXCP_RI);
}
@@ -17750,7 +17750,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case PREF:
/* Treat as no-op */
- if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >= 24)) {
+ if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >= 24)) {
/* hint codes 24-31 are reserved and signal RI */
generate_exception(ctx, EXCP_RI);
}
@@ -17762,7 +17762,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case ADDI32: /* AUI, LUI */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* AUI, LUI */
gen_logic_imm(ctx, OPC_LUI, rt, rs, imm);
} else {
@@ -17800,13 +17800,13 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
gen_slt_imm(ctx, mips32_op, rt, rs, imm);
break;
case JALX32:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
gen_compute_branch(ctx, OPC_JALX, 4, rt, rs, offset, 4);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break;
case JALS32: /* BOVC, BEQC, BEQZALC */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
if (rs >= rt) {
/* BOVC */
mips32_op = OPC_BOVC;
@@ -17826,7 +17826,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case BEQ32: /* BC */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* BC */
gen_compute_compact_branch(ctx, OPC_BC, 0, 0,
sextract32(ctx->opcode << 1, 0, 27));
@@ -17836,7 +17836,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case BNE32: /* BALC */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* BALC */
gen_compute_compact_branch(ctx, OPC_BALC, 0, 0,
sextract32(ctx->opcode << 1, 0, 27));
@@ -17846,7 +17846,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case J32: /* BGTZC, BLTZC, BLTC */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
if (rs == 0 && rt != 0) {
/* BGTZC */
mips32_op = OPC_BGTZC;
@@ -17865,7 +17865,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case JAL32: /* BLEZC, BGEZC, BGEC */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
if (rs == 0 && rt != 0) {
/* BLEZC */
mips32_op = OPC_BLEZC;
@@ -17900,7 +17900,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
gen_cop1_ldst(ctx, mips32_op, rt, rs, imm);
break;
case ADDIUPC: /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
switch ((ctx->opcode >> 16) & 0x1f) {
case ADDIUPC_00:
@@ -17942,7 +17942,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case BNVC: /* BNEC, BNEZALC */
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
if (rs >= rt) {
/* BNVC */
mips32_op = OPC_BNVC;
@@ -17956,7 +17956,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
break;
case R6_BNEZC: /* JIALC */
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
if (rt != 0) {
/* BNEZC */
gen_compute_compact_branch(ctx, OPC_BNEZC, rt, 0,
@@ -17967,7 +17967,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case R6_BEQZC: /* JIC */
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
if (rt != 0) {
/* BEQZC */
gen_compute_compact_branch(ctx, OPC_BEQZC, rt, 0,
@@ -17978,7 +17978,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case BLEZALC: /* BGEZALC, BGEUC */
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
if (rs == 0 && rt != 0) {
/* BLEZALC */
mips32_op = OPC_BLEZALC;
@@ -17992,7 +17992,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
break;
case BGTZALC: /* BLTZALC, BLTUC */
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
if (rs == 0 && rt != 0) {
/* BGTZALC */
mips32_op = OPC_BGTZALC;
@@ -18114,7 +18114,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx)
opc = OPC_SUBU;
break;
}
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/*
* In the Release 6, the register number location in
* the instruction encoding has changed.
@@ -18146,7 +18146,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case POOL16C:
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
gen_pool16c_r6_insn(ctx);
} else {
gen_pool16c_insn(ctx);
@@ -18162,7 +18162,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case POOL16F:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
if (ctx->opcode & 1) {
generate_exception_end(ctx, EXCP_RI);
} else {
@@ -18280,14 +18280,14 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx)
case B16: /* BC16 */
gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0,
sextract32(ctx->opcode, 0, 10) << 1,
- (ctx->insn_flags & ISA_MIPS32R6) ? 0 : 4);
+ (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4);
break;
case BNEZ16: /* BNEZC16 */
case BEQZ16: /* BEQZC16 */
gen_compute_branch(ctx, op == BNEZ16 ? OPC_BNE : OPC_BEQ, 2,
mmreg(uMIPS_RD(ctx->opcode)),
0, sextract32(ctx->opcode, 0, 7) << 1,
- (ctx->insn_flags & ISA_MIPS32R6) ? 0 : 4);
+ (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4);
break;
case LI16:
@@ -24970,7 +24970,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
case OPC_SLL: /* Shift with immediate */
if (sa == 5 && rd == 0 &&
rs == 0 && rt == 0) { /* PAUSE */
- if ((ctx->insn_flags & ISA_MIPS32R6) &&
+ if ((ctx->insn_flags & ISA_MIPS_R6) &&
(ctx->hflags & MIPS_HFLAG_BMASK)) {
generate_exception_end(ctx, EXCP_RI);
break;
@@ -25045,7 +25045,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
gen_trap(ctx, op1, rs, rt, -1);
break;
case OPC_LSA: /* OPC_PMON */
- if ((ctx->insn_flags & ISA_MIPS32R6) ||
+ if ((ctx->insn_flags & ISA_MIPS_R6) ||
(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
decode_opc_special_r6(env, ctx);
} else {
@@ -25148,14 +25148,14 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_DLSA:
- if ((ctx->insn_flags & ISA_MIPS32R6) ||
+ if ((ctx->insn_flags & ISA_MIPS_R6) ||
(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
decode_opc_special_r6(env, ctx);
}
break;
#endif
default:
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
decode_opc_special_r6(env, ctx);
} else if (ctx->insn_flags & INSN_R5900) {
decode_opc_special_tx79(env, ctx);
@@ -27565,7 +27565,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
int rs, rt, rd;
uint32_t op1;
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
@@ -28552,7 +28552,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
switch (op1) {
case OPC_LWLE:
case OPC_LWRE:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* fall through */
case OPC_LBUE:
case OPC_LHUE:
@@ -28565,7 +28565,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
return;
case OPC_SWLE:
case OPC_SWRE:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* fall through */
case OPC_SBE:
case OPC_SHE:
@@ -28605,7 +28605,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
case OPC_ALIGN_2:
case OPC_ALIGN_3:
case OPC_BITSWAP:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
decode_opc_special3_r6(env, ctx);
break;
default:
@@ -28637,7 +28637,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
case OPC_DALIGN_6:
case OPC_DALIGN_7:
case OPC_DBITSWAP:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
decode_opc_special3_r6(env, ctx);
break;
default:
@@ -28677,7 +28677,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
}
break;
default:
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
decode_opc_special3_r6(env, ctx);
} else {
decode_opc_special3_legacy(env, ctx);
@@ -30706,7 +30706,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_BLTZALL:
case OPC_BGEZALL:
check_insn(ctx, ISA_MIPS2);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* Fallthrough */
case OPC_BLTZ:
case OPC_BGEZ:
@@ -30714,7 +30714,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_BLTZAL:
case OPC_BGEZAL:
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
if (rs == 0) {
/* OPC_NAL, OPC_BAL */
gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4);
@@ -30733,11 +30733,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_TNEI:
check_insn(ctx, ISA_MIPS2);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_trap(ctx, op1, rs, -1, imm);
break;
case OPC_SIGRIE:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
generate_exception_end(ctx, EXCP_RI);
break;
case OPC_SYNCI:
@@ -30757,14 +30757,14 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
#if defined(TARGET_MIPS64)
case OPC_DAHI:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
check_mips_64(ctx);
if (rs != 0) {
tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 32);
}
break;
case OPC_DATI:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
check_mips_64(ctx);
if (rs != 0) {
tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 48);
@@ -30844,14 +30844,14 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_store_gpr(t0, rt);
break;
case OPC_DVP:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
if (ctx->vp) {
gen_helper_dvp(t0, cpu_env);
gen_store_gpr(t0, rt);
}
break;
case OPC_EVP:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
if (ctx->vp) {
gen_helper_evp(t0, cpu_env);
gen_store_gpr(t0, rt);
@@ -30904,7 +30904,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
} else {
@@ -30933,7 +30933,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
/* Branch */
case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
if (rt == 0) {
generate_exception_end(ctx, EXCP_RI);
break;
@@ -30946,7 +30946,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
if (rt == 0) {
generate_exception_end(ctx, EXCP_RI);
break;
@@ -30963,7 +30963,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* OPC_BLEZ */
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
} else {
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
/* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
}
@@ -30973,7 +30973,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* OPC_BGTZ */
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
} else {
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
/* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
}
@@ -30981,7 +30981,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_BEQL:
case OPC_BNEL:
check_insn(ctx, ISA_MIPS2);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* Fallthrough */
case OPC_BEQ:
case OPC_BNE:
@@ -30995,7 +30995,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* Fallthrough */
case OPC_LWL:
case OPC_LWR:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* Fallthrough */
case OPC_LB:
case OPC_LH:
@@ -31007,7 +31007,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SWL:
case OPC_SWR:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* fall through */
case OPC_SB:
case OPC_SH:
@@ -31016,14 +31016,14 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SC:
check_insn(ctx, ISA_MIPS2);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
gen_st_cond(ctx, rt, rs, imm, MO_TESL, false);
break;
case OPC_CACHE:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
check_cp0_enabled(ctx);
check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
@@ -31032,7 +31032,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* Treat as NOP. */
break;
case OPC_PREF:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
if (ctx->insn_flags & INSN_R5900) {
/* Treat as NOP. */
} else {
@@ -31076,7 +31076,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
#endif
case OPC_BC1EQZ: /* OPC_BC1ANY2 */
check_cp1_enabled(ctx);
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_BC1EQZ */
gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode),
rt, imm << 2, 4);
@@ -31090,19 +31090,19 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_BC1NEZ:
check_cp1_enabled(ctx);
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode),
rt, imm << 2, 4);
break;
case OPC_BC1ANY4:
check_cp1_enabled(ctx);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
check_cop1x(ctx);
check_insn(ctx, ASE_MIPS3D);
/* fall through */
case OPC_BC1:
check_cp1_enabled(ctx);
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
(rt >> 2) & 0x7, imm << 2);
break;
@@ -31120,7 +31120,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
{
int r6_op = ctx->opcode & FOP(0x3f, 0x1f);
check_cp1_enabled(ctx);
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
switch (r6_op) {
case R6_OPC_CMP_AF_S:
case R6_OPC_CMP_UN_S:
@@ -31205,7 +31205,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* Compact branches [R6] and COP2 [non-R6] */
case OPC_BC: /* OPC_LWC2 */
case OPC_BALC: /* OPC_SWC2 */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_BC, OPC_BALC */
gen_compute_compact_branch(ctx, op, 0, 0,
sextract32(ctx->opcode << 2, 0, 28));
@@ -31219,7 +31219,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_BEQZC: /* OPC_JIC, OPC_LDC2 */
case OPC_BNEZC: /* OPC_JIALC, OPC_SDC2 */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
if (rs != 0) {
/* OPC_BEQZC, OPC_BNEZC */
gen_compute_compact_branch(ctx, op, rs, 0,
@@ -31243,7 +31243,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_CP3:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
op1 = MASK_CP3(ctx->opcode);
@@ -31300,7 +31300,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* fall through */
case OPC_LDL:
case OPC_LDR:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* fall through */
case OPC_LWU:
case OPC_LD:
@@ -31310,7 +31310,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SDL:
case OPC_SDR:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* fall through */
case OPC_SD:
check_insn(ctx, ISA_MIPS3);
@@ -31318,7 +31318,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_st(ctx, op, rt, rs, imm);
break;
case OPC_SCD:
- check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
check_insn(ctx, ISA_MIPS3);
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
@@ -31327,7 +31327,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_st_cond(ctx, rt, rs, imm, MO_TEQ, false);
break;
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
/* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
} else {
@@ -31344,7 +31344,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
#else
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
} else {
MIPS_INVAL("major opcode");
@@ -31353,7 +31353,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
#endif
case OPC_DAUI: /* OPC_JALX */
- if (ctx->insn_flags & ISA_MIPS32R6) {
+ if (ctx->insn_flags & ISA_MIPS_R6) {
#if defined(TARGET_MIPS64)
/* OPC_DAUI */
check_mips_64(ctx);
@@ -31387,7 +31387,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_PCREL:
- check_insn(ctx, ISA_MIPS32R6);
+ check_insn(ctx, ISA_MIPS_R6);
gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs);
break;
default: /* Invalid */
@@ -31438,7 +31438,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
#else
ctx->mem_idx = hflags_mmu_index(ctx->hflags);
#endif
- ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS32R6 |
+ ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 |
INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v3 01/15] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment
2021-01-04 22:11 ` [PATCH v3 01/15] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment Philippe Mathieu-Daudé
@ 2021-01-04 23:24 ` Richard Henderson
0 siblings, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2021-01-04 23:24 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Aurelien Jarno
On 1/4/21 12:11 PM, Philippe Mathieu-Daudé wrote:
> Remove a comment added 12 years ago but never used (commit
> b6d96beda3a: "Use temporary registers for the MIPS FPU emulation").
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/mips-defs.h | 6 ------
> 1 file changed, 6 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 03/15] target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1
2021-01-04 22:11 ` [PATCH v3 03/15] target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 Philippe Mathieu-Daudé
@ 2021-01-04 23:25 ` Richard Henderson
0 siblings, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2021-01-04 23:25 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Aurelien Jarno
On 1/4/21 12:11 PM, Philippe Mathieu-Daudé wrote:
> 'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing
> the "Release 1" ISA. Rename it with the 'R1' suffix, as the other
> CPU definitions do.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/mips-defs.h | 8 ++++----
> target/mips/translate_init.c.inc | 14 +++++++-------
> 2 files changed, 11 insertions(+), 11 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 04/15] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
2021-01-04 22:11 ` [PATCH v3 04/15] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() Philippe Mathieu-Daudé
@ 2021-01-04 23:30 ` Richard Henderson
2021-01-05 8:34 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 27+ messages in thread
From: Richard Henderson @ 2021-01-04 23:30 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Aurelien Jarno
On 1/4/21 12:11 PM, Philippe Mathieu-Daudé wrote:
> MIPS 64-bit ISA is introduced with MIPS3.
>
> Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA,
> and the cpu_type_is_64bit() method to check if a CPU supports
> this ISA (thus is 64-bit).
>
> Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/cpu.h | 5 +++++
> target/mips/mips-defs.h | 4 +++-
> 2 files changed, 8 insertions(+), 1 deletion(-)
I still don't understand this as an alias, as opposed to a separate bit.
(ISA_MIPS3 | CPU_MIPS64R6) does not make sense, because R6 removes instructions.
But if this is an intermediate step,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 05/15] hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()
2021-01-04 22:11 ` [PATCH v3 05/15] hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() Philippe Mathieu-Daudé
@ 2021-01-04 23:32 ` Richard Henderson
0 siblings, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2021-01-04 23:32 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Aurelien Jarno
On 1/4/21 12:11 PM, Philippe Mathieu-Daudé wrote:
> Directly check if the CPU supports 64-bit with the recently
> added cpu_type_is_64bit() helper (inlined).
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/mips/boston.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 04/15] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
2021-01-04 23:30 ` Richard Henderson
@ 2021-01-05 8:34 ` Philippe Mathieu-Daudé
2021-01-05 10:05 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-05 8:34 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Aleksandar Rikalo, Aurelien Jarno, Paul Burton
On 1/5/21 12:30 AM, Richard Henderson wrote:
> On 1/4/21 12:11 PM, Philippe Mathieu-Daudé wrote:
>> MIPS 64-bit ISA is introduced with MIPS3.
>>
>> Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA,
>> and the cpu_type_is_64bit() method to check if a CPU supports
>> this ISA (thus is 64-bit).
>>
>> Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> target/mips/cpu.h | 5 +++++
>> target/mips/mips-defs.h | 4 +++-
>> 2 files changed, 8 insertions(+), 1 deletion(-)
>
> I still don't understand this as an alias, as opposed to a separate bit.
> (ISA_MIPS3 | CPU_MIPS64R6) does not make sense, because R6 removes instructions.
I now understand your concern.
I based the decodetree logic on the R6 ISA manual, decoding the
bits from the more recent feature (a leaf) to the root, following
this tree:
https://images.anandtech.com/doci/8457/MIPS%20ISA%20Evolution.JPG
(2.3 Evolution of the Architecture).
Also "2.1 Historical Perspective":
In the MIPS IIITM ISA, 64-bit integers and addresses were added
to the instruction set. [...]
The MIPS32 Release 6 ISA maintains backward-compatibility, with
the exception of a few rarely used instructions, though the use
of trap-and-emulate or trap-and-patch; all pre-Release 6 binaries
can execute under binary translation. [...]
The MIPS64 Architecture is based on the MIPS V ISA and is backward
compatible with the MIPS32 Architecture.
> But if this is an intermediate step,
As this isn't planned as intermediate step, I'll try to keep
CPU_MIPS64 as a separate bit and post the result.
Thanks for reviewing!
Phil.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 04/15] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
2021-01-05 8:34 ` Philippe Mathieu-Daudé
@ 2021-01-05 10:05 ` Philippe Mathieu-Daudé
2021-01-05 16:01 ` Richard Henderson
2021-01-06 4:23 ` Jiaxun Yang
0 siblings, 2 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-05 10:05 UTC (permalink / raw)
To: Richard Henderson, qemu-devel, Jiaxun Yang
Cc: Aleksandar Rikalo, Paul Burton, Aurelien Jarno
Hi Richard,
On 1/5/21 9:34 AM, Philippe Mathieu-Daudé wrote:
> On 1/5/21 12:30 AM, Richard Henderson wrote:
>> On 1/4/21 12:11 PM, Philippe Mathieu-Daudé wrote:
>>> MIPS 64-bit ISA is introduced with MIPS3.
>>>
>>> Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA,
>>> and the cpu_type_is_64bit() method to check if a CPU supports
>>> this ISA (thus is 64-bit).
>>>
>>> Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>> ---
>>> target/mips/cpu.h | 5 +++++
>>> target/mips/mips-defs.h | 4 +++-
>>> 2 files changed, 8 insertions(+), 1 deletion(-)
>>
>> I still don't understand this as an alias, as opposed to a separate bit.
>> (ISA_MIPS3 | CPU_MIPS64R6) does not make sense, because R6 removes instructions.
Well, FWIW (ISA_MIPS3 | CPU_MIPS64R6) is what we currently have:
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
So CPU_MIPS64R6 -> CPU_MIPS64R5 -> CPU_MIPS64R3 -> CPU_MIPS64R2
-> CPU_MIPS64 -> CPU_MIPS5 -> CPU_MIPS4 -> CPU_MIPS3 -> ISA_MIPS3
This patch doesn't make it worst :)
> I now understand your concern.
>
> I based the decodetree logic on the R6 ISA manual, decoding the
> bits from the more recent feature (a leaf) to the root, following
> this tree:
> https://images.anandtech.com/doci/8457/MIPS%20ISA%20Evolution.JPG
> (2.3 Evolution of the Architecture).
>
> Also "2.1 Historical Perspective":
>
> In the MIPS IIITM ISA, 64-bit integers and addresses were added
> to the instruction set. [...]
> The MIPS32 Release 6 ISA maintains backward-compatibility, with
> the exception of a few rarely used instructions, though the use
> of trap-and-emulate or trap-and-patch; all pre-Release 6 binaries
> can execute under binary translation. [...]
> The MIPS64 Architecture is based on the MIPS V ISA and is backward
> compatible with the MIPS32 Architecture.
>
>> But if this is an intermediate step,
>
> As this isn't planned as intermediate step, I'll try to keep
> CPU_MIPS64 as a separate bit and post the result.
I'm not sure it is worth the effort, as I plan to check each ISA /
ASE bit from the CP0_ConfigX bits (similarly target/arm/ does), so
these definitions should disappear eventually.
I.e. for the MSA ASE see:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg767523.html
/* Check presence of MSA implementation */
static inline bool ase_msa_available(CPUMIPSState *env)
{
return env->CP0_Config3 & (1 << CP0C3_MSAP);
}
Might I keep your R-b tag for this patch (eventually improving the
commit description with some of the info added in this mail) and
keep going?
Thanks,
Phil.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 04/15] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
2021-01-05 10:05 ` Philippe Mathieu-Daudé
@ 2021-01-05 16:01 ` Richard Henderson
2021-01-06 17:55 ` Philippe Mathieu-Daudé
2021-01-06 4:23 ` Jiaxun Yang
1 sibling, 1 reply; 27+ messages in thread
From: Richard Henderson @ 2021-01-05 16:01 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel, Jiaxun Yang
Cc: Aleksandar Rikalo, Paul Burton, Aurelien Jarno
On 1/5/21 12:05 AM, Philippe Mathieu-Daudé wrote:
> I'm not sure it is worth the effort, as I plan to check each ISA /
> ASE bit from the CP0_ConfigX bits (similarly target/arm/ does), so
> these definitions should disappear eventually.
Excellent.
> Might I keep your R-b tag for this patch (eventually improving the
> commit description with some of the info added in this mail) and
> keep going?
Yes.
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 04/15] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
2021-01-05 10:05 ` Philippe Mathieu-Daudé
2021-01-05 16:01 ` Richard Henderson
@ 2021-01-06 4:23 ` Jiaxun Yang
2021-01-06 5:22 ` Philippe Mathieu-Daudé
1 sibling, 1 reply; 27+ messages in thread
From: Jiaxun Yang @ 2021-01-06 4:23 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel
Cc: Aleksandar Rikalo, Paul Burton, Aurelien Jarno
在 2021/1/5 下午6:05, Philippe Mathieu-Daudé 写道:
> Hi Richard,
>
> On 1/5/21 9:34 AM, Philippe Mathieu-Daudé wrote:
>> On 1/5/21 12:30 AM, Richard Henderson wrote:
>>> On 1/4/21 12:11 PM, Philippe Mathieu-Daudé wrote:
>>>> MIPS 64-bit ISA is introduced with MIPS3.
>>>>
>>>> Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA,
>>>> and the cpu_type_is_64bit() method to check if a CPU supports
>>>> this ISA (thus is 64-bit).
>>>>
>>>> Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>>> ---
>>>> target/mips/cpu.h | 5 +++++
>>>> target/mips/mips-defs.h | 4 +++-
>>>> 2 files changed, 8 insertions(+), 1 deletion(-)
>>> I still don't understand this as an alias, as opposed to a separate bit.
>>> (ISA_MIPS3 | CPU_MIPS64R6) does not make sense, because R6 removes instructions.
> Well, FWIW (ISA_MIPS3 | CPU_MIPS64R6) is what we currently have:
>
> #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
>
> #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
>
> #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
>
> #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
>
> #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
>
> #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
>
> #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
>
> #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
>
> So CPU_MIPS64R6 -> CPU_MIPS64R5 -> CPU_MIPS64R3 -> CPU_MIPS64R2
> -> CPU_MIPS64 -> CPU_MIPS5 -> CPU_MIPS4 -> CPU_MIPS3 -> ISA_MIPS3
>
> This patch doesn't make it worst :)
>
>> I now understand your concern.
>>
>> I based the decodetree logic on the R6 ISA manual, decoding the
>> bits from the more recent feature (a leaf) to the root, following
>> this tree:
>> https://images.anandtech.com/doci/8457/MIPS%20ISA%20Evolution.JPG
>> (2.3 Evolution of the Architecture).
>>
>> Also "2.1 Historical Perspective":
>>
>> In the MIPS IIITM ISA, 64-bit integers and addresses were added
>> to the instruction set. [...]
>> The MIPS32 Release 6 ISA maintains backward-compatibility, with
>> the exception of a few rarely used instructions, though the use
>> of trap-and-emulate or trap-and-patch; all pre-Release 6 binaries
>> can execute under binary translation. [...]
>> The MIPS64 Architecture is based on the MIPS V ISA and is backward
>> compatible with the MIPS32 Architecture.
Hi all,
Well I don't think it's worthy to keep R6 backward compatible with previous
Release. Opcodes existed in pre-R6 but removed in R6 will be reused in
future Releases (e.g. R6.1) for different functions.
And the statement here about trap-and-emul, trap-and-patch is false. It
never
happens in the real world. R2-to-R6 emul in kernel never goes into
production
quality, not to mention IEEE754-2008 (NAN2008) issue.
Based on documents we have, I'd prefer to treat MIPS ISA into three eras
Classic (I, II, III, IV), Modern (R1, R2, R3, R5), R6+(R6 and afterwards).
The difference inside each era is well-documented in manuals, it can prevent
us from get into a long-term hide and seek game of finding difference
between
ISA levels.
>>
>>> But if this is an intermediate step,
>> As this isn't planned as intermediate step, I'll try to keep
>> CPU_MIPS64 as a separate bit and post the result.
> I'm not sure it is worth the effort, as I plan to check each ISA /
> ASE bit from the CP0_ConfigX bits (similarly target/arm/ does), so
> these definitions should disappear eventually.
>
> I.e. for the MSA ASE see:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg767523.html
>
> /* Check presence of MSA implementation */
> static inline bool ase_msa_available(CPUMIPSState *env)
> {
> return env->CP0_Config3 & (1 << CP0C3_MSAP);
> }
Unfortunately MIPS has a bad manner that allows vendors to have random
extensions without unique identification.
ASEs flag can never go...... But identify ASEs from registers is surely
a good
idea though. At least removing MIPS defined ASEs from ASE flag can make
life easier.
AFAIK Loongson has a CPUID instruction for 3A4000 and we may
implement that to identify Loongson extensions, Ingenic is also marking
MXU support in CP0. There could be some PRID based match to further
reduce ASEs flag.
Thanks.
- Jiaxun
>
> Might I keep your R-b tag for this patch (eventually improving the
> commit description with some of the info added in this mail) and
> keep going?
>
> Thanks,
>
> Phil.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 04/15] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
2021-01-06 4:23 ` Jiaxun Yang
@ 2021-01-06 5:22 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-06 5:22 UTC (permalink / raw)
To: Jiaxun Yang, Richard Henderson, qemu-devel
Cc: Aleksandar Rikalo, Aurelien Jarno, Paul Burton
On 1/6/21 5:23 AM, Jiaxun Yang wrote:
> 在 2021/1/5 下午6:05, Philippe Mathieu-Daudé 写道:
[...]
>>> I based the decodetree logic on the R6 ISA manual, decoding the
>>> bits from the more recent feature (a leaf) to the root, following
>>> this tree:
>>> https://images.anandtech.com/doci/8457/MIPS%20ISA%20Evolution.JPG
>>> (2.3 Evolution of the Architecture).
>>>
>>> Also "2.1 Historical Perspective":
>>>
>>> In the MIPS IIITM ISA, 64-bit integers and addresses were added
>>> to the instruction set. [...]
>>> The MIPS32 Release 6 ISA maintains backward-compatibility, with
>>> the exception of a few rarely used instructions, though the use
>>> of trap-and-emulate or trap-and-patch; all pre-Release 6 binaries
>>> can execute under binary translation. [...]
>>> The MIPS64 Architecture is based on the MIPS V ISA and is backward
>>> compatible with the MIPS32 Architecture.
>
> Hi all,
>
> Well I don't think it's worthy to keep R6 backward compatible with previous
> Release. Opcodes existed in pre-R6 but removed in R6 will be reused in
> future Releases (e.g. R6.1) for different functions.
>
> And the statement here about trap-and-emul, trap-and-patch is false. It
> never
> happens in the real world. R2-to-R6 emul in kernel never goes into
> production
> quality, not to mention IEEE754-2008 (NAN2008) issue.
>
> Based on documents we have, I'd prefer to treat MIPS ISA into three eras
> Classic (I, II, III, IV), Modern (R1, R2, R3, R5), R6+(R6 and afterwards).
Sounds good to me!
> The difference inside each era is well-documented in manuals, it can
> prevent
> us from get into a long-term hide and seek game of finding difference
> between
> ISA levels.
Which is easier when you have access to the manuals ;)
>>>
>>>> But if this is an intermediate step,
>>> As this isn't planned as intermediate step, I'll try to keep
>>> CPU_MIPS64 as a separate bit and post the result.
>> I'm not sure it is worth the effort, as I plan to check each ISA /
>> ASE bit from the CP0_ConfigX bits (similarly target/arm/ does), so
>> these definitions should disappear eventually.
>>
>> I.e. for the MSA ASE see:
>> https://www.mail-archive.com/qemu-devel@nongnu.org/msg767523.html
>>
>> /* Check presence of MSA implementation */
>> static inline bool ase_msa_available(CPUMIPSState *env)
>> {
>> return env->CP0_Config3 & (1 << CP0C3_MSAP);
>> }
> Unfortunately MIPS has a bad manner that allows vendors to have random
> extensions without unique identification.
> ASEs flag can never go...... But identify ASEs from registers is surely
> a good
> idea though. At least removing MIPS defined ASEs from ASE flag can make
> life easier.
>
> AFAIK Loongson has a CPUID instruction for 3A4000 and we may
> implement that to identify Loongson extensions, Ingenic is also marking
> MXU support in CP0. There could be some PRID based match to further
> reduce ASEs flag.
Yes. I'd like to have check_$FEAT() opaque from the TCG helpers
perspective. Then how the check is implemented is a different
story and can involve CPU specific code (as your 3A4000 example).
Regards,
Phil.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 04/15] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
2021-01-05 16:01 ` Richard Henderson
@ 2021-01-06 17:55 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-06 17:55 UTC (permalink / raw)
To: Richard Henderson, qemu-devel, Jiaxun Yang
Cc: Aleksandar Rikalo, Aurelien Jarno, Paul Burton
On 1/5/21 5:01 PM, Richard Henderson wrote:
> On 1/5/21 12:05 AM, Philippe Mathieu-Daudé wrote:
>> I'm not sure it is worth the effort, as I plan to check each ISA /
>> ASE bit from the CP0_ConfigX bits (similarly target/arm/ does), so
>> these definitions should disappear eventually.
>
> Excellent.
>
>> Might I keep your R-b tag for this patch (eventually improving the
>> commit description with some of the info added in this mail) and
>> keep going?
>
> Yes.
Thanks :)
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions
2021-01-04 22:11 [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2021-01-04 22:11 ` [PATCH v3 15/15] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 Philippe Mathieu-Daudé
@ 2021-01-06 17:56 ` Philippe Mathieu-Daudé
15 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-06 17:56 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Aurelien Jarno, Paul Burton
On 1/4/21 11:11 PM, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daud=C3=A9 (15):
> target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment
> target/mips/mips-defs: Reorder CPU_MIPS5 definition
> target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1
> target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
> hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()
> target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1
> target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2
> target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3
> target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5
> target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6
> target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1
> target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2
> target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3
> target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5
> target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6
>
> target/mips/cpu.h | 5 +
> target/mips/internal.h | 8 +-
> target/mips/mips-defs.h | 46 +--
> hw/mips/boston.c | 6 +-
> linux-user/mips/cpu_loop.c | 6 +-
> target/mips/cp0_helper.c | 18 +-
> target/mips/cp0_timer.c | 4 +-
> target/mips/cpu.c | 6 +-
> target/mips/fpu_helper.c | 4 +-
> target/mips/helper.c | 12 +-
> target/mips/translate.c | 620 +++++++++++++++----------------
> target/mips/translate_init.c.inc | 14 +-
> 12 files changed, 370 insertions(+), 379 deletions(-)
Series queued to mips-next.
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2021-01-06 17:59 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-01-04 22:11 [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 01/15] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment Philippe Mathieu-Daudé
2021-01-04 23:24 ` Richard Henderson
2021-01-04 22:11 ` [PATCH v3 02/15] target/mips/mips-defs: Reorder CPU_MIPS5 definition Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 03/15] target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 Philippe Mathieu-Daudé
2021-01-04 23:25 ` Richard Henderson
2021-01-04 22:11 ` [PATCH v3 04/15] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() Philippe Mathieu-Daudé
2021-01-04 23:30 ` Richard Henderson
2021-01-05 8:34 ` Philippe Mathieu-Daudé
2021-01-05 10:05 ` Philippe Mathieu-Daudé
2021-01-05 16:01 ` Richard Henderson
2021-01-06 17:55 ` Philippe Mathieu-Daudé
2021-01-06 4:23 ` Jiaxun Yang
2021-01-06 5:22 ` Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 05/15] hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() Philippe Mathieu-Daudé
2021-01-04 23:32 ` Richard Henderson
2021-01-04 22:11 ` [PATCH v3 06/15] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 07/15] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 08/15] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 09/15] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 10/15] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 11/15] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 12/15] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 13/15] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 14/15] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 Philippe Mathieu-Daudé
2021-01-04 22:11 ` [PATCH v3 15/15] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 Philippe Mathieu-Daudé
2021-01-06 17:56 ` [PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
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