* [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-27 3:25 ` Chris Packham
0 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-27 3:25 UTC (permalink / raw)
To: linux-arm-kernel
The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
integrated CPUs. They CPU block is common within these product lines and
(as far as I can tell/have been told) is based on the Armada XP. There
are a few differences due to the fact they have to squeeze the CPU into
the same package as the switch.
I've rebased this series against linux-pinctrl/devel to get access to
mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to v4.10.0-rc5.
Chris Packham (4):
clk: mvebu: support for 98DX3236 SoC
Changes in v2:
- Update devicetree binding documentation for new compatible string
Changes in v3:
- Add 98dx3236 support to mvebu/clk-corediv.c rather than creating a new
driver.
- Document mv98dx3236-corediv-clock binding
Changes in v4:
- None
Changes in v5:
- Collect ack from Rob
- Remove explicit initialisation of fields to 0 in mv98dx3236_coreclks
- Register dummy clock provider for marvell,mv98dx3236-cpu-clock
arm: mvebu: support for SMP on 98DX3336 SoC
Changes in v2:
- Document new enable-method value
- Correct some references from 98DX4521 to 98DX3236
Changes in v3:
- Simplify mv98dx3236_resume_init by using of_io_request_and_map()
Changes in v4:
- integrate changes into platsmp.c instead of new init call
- avoid duplicated code.
- fix error return
- Collect ack from Rob
Changes in v5:
- Remove useless casts (thanks to Stephen Boyd)
arm: mvebu: Add device tree for 98DX3236 SoCs
Changes in v2:
- Update devicetree binding documentation to reflect that 98DX3336 and
984251 are supersets of 98DX3236.
- disable crypto block
- disable sdio for 98DX3236, enable for 98DX4251
Changes in v3:
- fix typo 4521 -> 4251
- document prestera bindings
- rework corediv-clock binding
- add label to packet processor node
- add new compatible string for DFX server
Changes in v4:
- Collect ack from Rob
Changes in v5:
- Fixup license text. Add labels to nodes.
arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
Changes in v5:
- update license text
- use node labels
Kalyan Kinthada (1):
pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
Changes in v2:
- include sdio support for the 98DX4251
Changes in v3:
- None
Changes in v4:
- Correct some discrepencies between binding and driver.
- Collect acks from Rob and Sebastian
Changes in v5:
- Update bindings to reflect "gpo" pins
- Use mvebu_mmio_mpp_ctrl instead of armada_xp_mpp_ctrl (note this is reliant
on changes queued in linux-pinctrl)
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
.../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 16 ++
.../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ++
.../bindings/clock/mvebu-corediv-clock.txt | 1 +
.../devicetree/bindings/clock/mvebu-cpu-clock.txt | 1 +
.../devicetree/bindings/net/marvell,prestera.txt | 50 ++++
.../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++
arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 254 +++++++++++++++++++++
arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 76 ++++++
arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 90 ++++++++
arch/arm/boot/dts/db-dxbc2.dts | 151 ++++++++++++
arch/arm/boot/dts/db-xc3-24g4xg.dts | 142 ++++++++++++
arch/arm/mach-mvebu/platsmp.c | 86 +++++++
drivers/clk/mvebu/armada-xp.c | 39 ++++
drivers/clk/mvebu/clk-corediv.c | 23 ++
drivers/clk/mvebu/clk-cpu.c | 8 +
drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 156 +++++++++++++
17 files changed, 1163 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
create mode 100644 Documentation/devicetree/bindings/net/marvell,prestera.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
interdiff to v4:
diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
index 520562a7dc2a..c7b4e3a6b2c6 100644
@@ -85,7 +86,7 @@
by address and length of the PMU DFS registers
- #clock-cells : should be set to 1.
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
-index b3094315a3c0..0413bf8284e0 100644
+index b3094315a3c0..890a863ae0d0 100644
--- a/drivers/clk/mvebu/armada-xp.c
+++ b/drivers/clk/mvebu/armada-xp.c
return 250000000;
@@ -118,9 +119,6 @@
+static const struct coreclk_soc_desc mv98dx3236_coreclks = {
+ .get_tclk_freq = mv98dx3236_get_tclk_freq,
+ .get_cpu_freq = mv98dx3236_get_cpu_freq,
-+ .get_clk_ratio = NULL,
-+ .ratios = NULL,
-+ .num_ratios = 0,
+};
+
/*
@@ -200,53 +198,16 @@
+CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock",
+ mv98dx3236_corediv_clk_init);
diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
-index 5837eb8a212f..3b8f0e14fa01 100644
+index 5837eb8a212f..044892b6534d 100644
--- a/drivers/clk/mvebu/clk-cpu.c
+++ b/drivers/clk/mvebu/clk-cpu.c
- .set_rate = clk_cpu_set_rate,
- };
-
--static void __init of_cpu_clk_setup(struct device_node *node)
-+/* Add parameter to allow this to support different clock operations. */
-+static void __init _of_cpu_clk_setup(struct device_node *node,
-+ const struct clk_ops *cpu_clk_ops)
- {
- struct cpu_clk *cpuclk;
- void __iomem *clock_complex_base = of_iomap(node, 0);
- cpuclk[cpu].hw.init = &init;
- init.name = cpuclk[cpu].clk_name;
-- init.ops = &cpu_ops;
-+ init.ops = cpu_clk_ops;
- init.flags = 0;
- init.parent_names = &cpuclk[cpu].parent_name;
- init.num_parents = 1;
- iounmap(clock_complex_base);
- }
-
-+/* Use this function to call the generic setup with the correct
-+ * clock operation
-+ */
-+static void __init of_cpu_clk_setup(struct device_node *node)
-+{
-+ _of_cpu_clk_setup(node, &cpu_ops);
-+}
-+
CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
of_cpu_clk_setup);
+
-+/* Define the clock and operations for the mv98dx3236 - it cannot perform
-+ * any operations.
-+ */
-+static const struct clk_ops mv98dx3236_cpu_ops = {
-+ .recalc_rate = NULL,
-+ .round_rate = NULL,
-+ .set_rate = NULL,
-+};
-+
+static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
+{
-+ _of_cpu_clk_setup(node, &mv98dx3236_cpu_ops);
++ of_clk_add_provider(node, of_clk_src_simple_get, NULL);
+}
+
+CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
@@ -285,7 +247,7 @@
"qcom,gcc-msm8660"
diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
new file mode 100644
-index 000000000000..8082ba872edd
+index 000000000000..26eb9d3aa630
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
+Resume Control
@@ -304,10 +266,8 @@
+ compatible = "marvell,98dx3336-resume-ctrl";
+ reg = <0x20980 0x10>;
+};
-+
-+
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
-index 46c742d3bd41..59be3ca0464f 100644
+index 46c742d3bd41..a5b464497e1a 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -327,7 +287,7 @@
+static const struct of_device_id of_mv98dx3236_resume_table[] = {
+ {
+ .compatible = "marvell,98dx3336-resume-ctrl",
-+ .data = (void *)&mv98dx3336_resume_controller,
++ .data = &mv98dx3336_resume_controller,
+ },
+ { /* end of list */ },
+};
@@ -337,7 +297,7 @@
+ const struct of_device_id *match;
+ struct device_node *np;
+ void __iomem *base;
-+ struct resume_controller *rc;
++ const struct resume_controller *rc;
+
+ WARN_ON(hw_cpu != 1);
+
@@ -347,7 +307,7 @@
+ return -ENODEV;
+
+ base = of_io_request_and_map(np, 0, of_node_full_name(np));
-+ rc = (struct resume_controller *)match->data;
++ rc = match->data;
+ of_node_put(np);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
@@ -411,15 +371,17 @@
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
new file mode 100644
-index 000000000000..d4e6ecdfc853
+index 000000000000..97aef67ee769
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
+* Marvell 98dx3236 pinctrl driver for mpp
@@ -435,41 +397,41 @@
+
+name pins functions
+================================================================================
-+mpp0 0 gpio, spi0(mosi), dev(ad8)
++mpp0 0 gpo, spi0(mosi), dev(ad8)
+mpp1 1 gpio, spi0(miso), dev(ad9)
-+mpp2 2 gpio, spi0(sck), dev(ad10)
++mpp2 2 gpo, spi0(sck), dev(ad10)
+mpp3 3 gpio, spi0(cs0), dev(ad11)
+mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
+mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
-+mpp6 6 gpio, sd0(clk), dev(a2)
++mpp6 6 gpo, sd0(clk), dev(a2)
+mpp7 7 gpio, sd0(d0), dev(ale0)
+mpp8 8 gpio, sd0(d1), dev(ale1)
+mpp9 9 gpio, sd0(d2), dev(ready0)
+mpp10 10 gpio, sd0(d3), dev(ad12)
+mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13)
-+mpp12 12 gpio, uart1(txd), uart0(rts), dev(ad14)
++mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14)
+mpp13 13 gpio, intr(out), dev(ad15)
+mpp14 14 gpio, i2c0(sck)
+mpp15 15 gpio, i2c0(sda)
-+mpp16 16 gpio, dev(oe)
-+mpp17 17 gpio, dev(clk)
++mpp16 16 gpo, dev(oe)
++mpp17 17 gpo, dev(clkout)
+mpp18 18 gpio, uart1(txd)
+mpp19 19 gpio, uart1(rxd), dev(rb)
-+mpp20 20 gpio, dev(we)
-+mpp21 21 gpio, dev(ad0)
-+mpp22 22 gpio, dev(ad1)
-+mpp23 23 gpio, dev(ad2)
-+mpp24 24 gpio, dev(ad3)
-+mpp25 25 gpio, dev(ad4)
-+mpp26 26 gpio, dev(ad5)
-+mpp27 27 gpio, dev(ad6)
-+mpp28 28 gpio, dev(ad7)
-+mpp29 29 gpio, dev(a0)
-+mpp30 30 gpio, dev(a1)
++mpp20 20 gpo, dev(we0)
++mpp21 21 gpo, dev(ad0)
++mpp22 22 gpo, dev(ad1)
++mpp23 23 gpo, dev(ad2)
++mpp24 24 gpo, dev(ad3)
++mpp25 25 gpo, dev(ad4)
++mpp26 26 gpo, dev(ad5)
++mpp27 27 gpo, dev(ad6)
++mpp28 28 gpo, dev(ad7)
++mpp29 29 gpo, dev(a0)
++mpp30 30 gpo, dev(a1)
+mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
+mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
-index e4ea71a9d985..554eeae8cd21 100644
+index 63e1bd506983..61cbc138703e 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
V_MV78460 = BIT(2),
@@ -495,8 +457,8 @@
+ MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)),
+ MPP_MODE(2,
-+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
-+ MPP_VAR_FUNCTION(0x2, "spi0", "csk", V_98DX3236_PLUS),
++ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
++ MPP_VAR_FUNCTION(0x2, "spi0", "sck", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)),
+ MPP_MODE(3,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
@@ -511,7 +473,7 @@
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251),
-+ MPP_VAR_FUNCTION(0x4, "dev", "bootcs0", V_98DX3236_PLUS)),
++ MPP_VAR_FUNCTION(0x4, "dev", "bootcs", V_98DX3236_PLUS)),
+ MPP_MODE(6,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251),
@@ -563,7 +525,8 @@
+ MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)),
+ MPP_MODE(19,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
-+ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS)),
++ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS),
++ MPP_VAR_FUNCTION(0x4, "dev", "rb", V_98DX3236_PLUS)),
+ MPP_MODE(20,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)),
@@ -630,11 +593,11 @@
};
+static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = {
-+ MPP_FUNC_CTRL(0, 32, NULL, armada_xp_mpp_ctrl),
++ MPP_FUNC_CTRL(0, 32, NULL, mvebu_mmio_mpp_ctrl),
+};
+
+static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = {
-+ MPP_GPIO_RANGE(0, 0, 0, 32),
++ MPP_GPIO_RANGE(0, 0, 0, 32),
+};
+
static int armada_xp_pinctrl_suspend(struct platform_device *pdev,
@@ -767,7 +731,7 @@
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
new file mode 100644
-index 000000000000..4b7b2fe3b682
+index 000000000000..9461128fae24
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+/*
@@ -785,17 +749,17 @@
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
-+ * This file is distributed in the hope that it will be useful
++ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
-+ * Or, alternatively
++ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use
++ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
@@ -804,11 +768,11 @@
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
-+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
@@ -851,9 +815,9 @@
+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
+
+ /*
-+ * 98DX3236 has 1 x1 PCIe unit Gen2.0: One unit can be
++ * 98DX3236 has 1 x1 PCIe unit Gen2.0
+ */
-+ pcie-controller {
++ pciec: pcie-controller at 82000000 {
+ compatible = "marvell,armada-xp-pcie";
+ status = "disabled";
+ device_type = "pci";
@@ -870,7 +834,7 @@
+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
+ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;
+
-+ pcie at 1,0 {
++ pcie1: pcie at 1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
@@ -967,7 +931,7 @@
+ };
+ };
+
-+ dfx-registers {
++ dfxr: dfx-registers at ac000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
@@ -987,7 +951,7 @@
+ };
+ };
+
-+ switch {
++ switch: switch at a8000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
@@ -1026,7 +990,7 @@
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
new file mode 100644
-index 000000000000..a9b0f47f8df9
+index 000000000000..e1580afdc260
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
+/*
@@ -1044,17 +1008,17 @@
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
-+ * This file is distributed in the hope that it will be useful
++ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
-+ * Or, alternatively
++ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use
++ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
@@ -1063,16 +1027,16 @@
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
-+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
-+ * Contains definitions specific to the 98dx3336 SoC that are not
++ * Contains definitions specific to the 98dx3236 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
@@ -1107,7 +1071,7 @@
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
new file mode 100644
-index 000000000000..446e6e65ec59
+index 000000000000..4b0533a4ccb7
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
+/*
@@ -1125,17 +1089,17 @@
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
-+ * This file is distributed in the hope that it will be useful
++ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
-+ * Or, alternatively
++ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use
++ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
@@ -1144,11 +1108,11 @@
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
-+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
@@ -1213,15 +1177,15 @@
diff --git a/arch/arm/boot/dts/db-dxbc2.dts b/arch/arm/boot/dts/db-dxbc2.dts
new file mode 100644
-index 000000000000..f56786cea5f8
+index 000000000000..a8130805074e
--- /dev/null
+++ b/arch/arm/boot/dts/db-dxbc2.dts
+/*
@@ -1241,17 +1205,17 @@
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
-+ * This file is distributed in the hope that it will be useful
++ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
-+ * Or, alternatively
++ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use
++ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
@@ -1260,11 +1224,11 @@
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
-+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
@@ -1295,66 +1259,58 @@
+ reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
+ };
+
-+ soc {
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
-+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
-+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
-+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
-+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
++};
+
-+ devbus-bootcs {
-+ status = "okay";
++&devbus_bootcs {
++ status = "okay";
+
-+ /* Device Bus parameters are required */
++ /* Device Bus parameters are required */
+
-+ /* Read parameters */
-+ devbus,bus-width = <16>;
-+ devbus,turn-off-ps = <60000>;
-+ devbus,badr-skew-ps = <0>;
-+ devbus,acc-first-ps = <124000>;
-+ devbus,acc-next-ps = <248000>;
-+ devbus,rd-setup-ps = <0>;
-+ devbus,rd-hold-ps = <0>;
-+
-+ /* Write parameters */
-+ devbus,sync-enable = <0>;
-+ devbus,wr-high-ps = <60000>;
-+ devbus,wr-low-ps = <60000>;
-+ devbus,ale-wr-ps = <60000>;
-+ };
++ /* Read parameters */
++ devbus,bus-width = <16>;
++ devbus,turn-off-ps = <60000>;
++ devbus,badr-skew-ps = <0>;
++ devbus,acc-first-ps = <124000>;
++ devbus,acc-next-ps = <248000>;
++ devbus,rd-setup-ps = <0>;
++ devbus,rd-hold-ps = <0>;
++
++ /* Write parameters */
++ devbus,sync-enable = <0>;
++ devbus,wr-high-ps = <60000>;
++ devbus,wr-low-ps = <60000>;
++ devbus,ale-wr-ps = <60000>;
++};
+
-+ internal-regs {
-+ serial at 12000 {
-+ status = "okay";
-+ };
-+ serial at 12100 {
-+ status = "okay";
-+ };
++&i2c0 {
++ clock-frequency = <100000>;
++ status = "okay";
++};
+
-+ i2c at 11000 {
-+ clock-frequency = <100000>;
-+ status = "okay";
-+ };
++&uart0 {
++ status = "okay";
++};
+
-+ mvsdio at d4000 {
-+ pinctrl-0 = <&sdio_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+ /* No CD or WP GPIOs */
-+ broken-cd;
-+ };
++&uart1 {
++ status = "okay";
++};
+
-+ nand at d0000 {
-+ status = "okay";
-+ num-cs = <1>;
-+ marvell,nand-keep-config;
-+ marvell,nand-enable-arbiter;
-+ nand-on-flash-bbt;
-+ nand-ecc-strength = <4>;
-+ nand-ecc-step-size = <512>;
-+ };
-+ };
-+ };
++&nand {
++ status = "okay";
++ num-cs = <1>;
++ marvell,nand-keep-config;
++ marvell,nand-enable-arbiter;
++ nand-on-flash-bbt;
++ nand-ecc-strength = <4>;
++ nand-ecc-step-size = <512>;
++};
++
++&sdio {
++ pinctrl-0 = <&sdio_pins>;
++ pinctrl-names = "default";
++ status = "okay";
++ /* No CD or WP GPIOs */
++ broken-cd;
+};
+
+&spi0 {
@@ -1385,7 +1341,7 @@
+};
diff --git a/arch/arm/boot/dts/db-xc3-24g4xg.dts b/arch/arm/boot/dts/db-xc3-24g4xg.dts
new file mode 100644
-index 000000000000..5eb89ffb9a7d
+index 000000000000..4e07cb6ed800
--- /dev/null
+++ b/arch/arm/boot/dts/db-xc3-24g4xg.dts
+/*
@@ -1405,17 +1361,17 @@
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
-+ * This file is distributed in the hope that it will be useful
++ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
-+ * Or, alternatively
++ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use
++ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
@@ -1424,11 +1380,11 @@
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
-+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
@@ -1458,63 +1414,50 @@
+ device_type = "memory";
+ reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
+ };
++};
+
-+ soc {
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
-+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
-+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
-+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
-+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
-+
-+ devbus-bootcs {
-+ status = "okay";
++&devbus_bootcs {
++ status = "okay";
+
-+ /* Device Bus parameters are required */
++ /* Device Bus parameters are required */
+
-+ /* Read parameters */
-+ devbus,bus-width = <16>;
-+ devbus,turn-off-ps = <60000>;
-+ devbus,badr-skew-ps = <0>;
-+ devbus,acc-first-ps = <124000>;
-+ devbus,acc-next-ps = <248000>;
-+ devbus,rd-setup-ps = <0>;
-+ devbus,rd-hold-ps = <0>;
-+
-+ /* Write parameters */
-+ devbus,sync-enable = <0>;
-+ devbus,wr-high-ps = <60000>;
-+ devbus,wr-low-ps = <60000>;
-+ devbus,ale-wr-ps = <60000>;
-+ };
++ /* Read parameters */
++ devbus,bus-width = <16>;
++ devbus,turn-off-ps = <60000>;
++ devbus,badr-skew-ps = <0>;
++ devbus,acc-first-ps = <124000>;
++ devbus,acc-next-ps = <248000>;
++ devbus,rd-setup-ps = <0>;
++ devbus,rd-hold-ps = <0>;
++
++ /* Write parameters */
++ devbus,sync-enable = <0>;
++ devbus,wr-high-ps = <60000>;
++ devbus,wr-low-ps = <60000>;
++ devbus,ale-wr-ps = <60000>;
++};
+
-+ internal-regs {
-+ serial at 12000 {
-+ status = "okay";
-+ };
-+ serial at 12100 {
-+ status = "okay";
-+ };
++&uart0 {
++ status = "okay";
++};
+
-+ i2c at 11000 {
-+ clock-frequency = <100000>;
-+ status = "okay";
-+ };
++&uart1 {
++ status = "okay";
++};
+
-+ mvsdio at d4000 {
-+ status = "disabled";
-+ };
++&i2c0 {
++ clock-frequency = <100000>;
++ status = "okay";
++};
+
-+ nand at d0000 {
-+ status = "okay";
-+ num-cs = <1>;
-+ marvell,nand-keep-config;
-+ marvell,nand-enable-arbiter;
-+ nand-on-flash-bbt;
-+ nand-ecc-strength = <4>;
-+ nand-ecc-step-size = <512>;
-+ };
-+ };
-+ };
++&nand {
++ status = "okay";
++ num-cs = <1>;
++ marvell,nand-keep-config;
++ marvell,nand-enable-arbiter;
++ nand-on-flash-bbt;
++ nand-ecc-strength = <4>;
++ nand-ecc-step-size = <512>;
+};
+
+&spi0 {
--
2.11.0.24.ge6920cf
^ permalink raw reply [flat|nested] 49+ messages in thread* [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-27 3:25 ` Chris Packham
0 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-27 3:25 UTC (permalink / raw)
To: linux, linux-arm-kernel
Cc: Chris Packham, Rob Herring, Mark Rutland, Michael Turquette,
Stephen Boyd, Linus Walleij, Jason Cooper, Andrew Lunn,
Gregory Clement, Sebastian Hesselbarth, Geert Uytterhoeven,
Chris Brand, Florian Fainelli, Arnd Bergmann, Thierry Reding,
Sudeep Holla, Juri Lelli, Thomas Petazzoni, Laxman Dewangan,
Kalyan Kinthada, devicetree, linux-kernel, linux-clk, linux-gpio
The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
integrated CPUs. They CPU block is common within these product lines and
(as far as I can tell/have been told) is based on the Armada XP. There
are a few differences due to the fact they have to squeeze the CPU into
the same package as the switch.
I've rebased this series against linux-pinctrl/devel to get access to
mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to v4.10.0-rc5.
Chris Packham (4):
clk: mvebu: support for 98DX3236 SoC
Changes in v2:
- Update devicetree binding documentation for new compatible string
Changes in v3:
- Add 98dx3236 support to mvebu/clk-corediv.c rather than creating a new
driver.
- Document mv98dx3236-corediv-clock binding
Changes in v4:
- None
Changes in v5:
- Collect ack from Rob
- Remove explicit initialisation of fields to 0 in mv98dx3236_coreclks
- Register dummy clock provider for marvell,mv98dx3236-cpu-clock
arm: mvebu: support for SMP on 98DX3336 SoC
Changes in v2:
- Document new enable-method value
- Correct some references from 98DX4521 to 98DX3236
Changes in v3:
- Simplify mv98dx3236_resume_init by using of_io_request_and_map()
Changes in v4:
- integrate changes into platsmp.c instead of new init call
- avoid duplicated code.
- fix error return
- Collect ack from Rob
Changes in v5:
- Remove useless casts (thanks to Stephen Boyd)
arm: mvebu: Add device tree for 98DX3236 SoCs
Changes in v2:
- Update devicetree binding documentation to reflect that 98DX3336 and
984251 are supersets of 98DX3236.
- disable crypto block
- disable sdio for 98DX3236, enable for 98DX4251
Changes in v3:
- fix typo 4521 -> 4251
- document prestera bindings
- rework corediv-clock binding
- add label to packet processor node
- add new compatible string for DFX server
Changes in v4:
- Collect ack from Rob
Changes in v5:
- Fixup license text. Add labels to nodes.
arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
Changes in v5:
- update license text
- use node labels
Kalyan Kinthada (1):
pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
Changes in v2:
- include sdio support for the 98DX4251
Changes in v3:
- None
Changes in v4:
- Correct some discrepencies between binding and driver.
- Collect acks from Rob and Sebastian
Changes in v5:
- Update bindings to reflect "gpo" pins
- Use mvebu_mmio_mpp_ctrl instead of armada_xp_mpp_ctrl (note this is reliant
on changes queued in linux-pinctrl)
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
.../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 16 ++
.../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ++
.../bindings/clock/mvebu-corediv-clock.txt | 1 +
.../devicetree/bindings/clock/mvebu-cpu-clock.txt | 1 +
.../devicetree/bindings/net/marvell,prestera.txt | 50 ++++
.../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++
arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 254 +++++++++++++++++++++
arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 76 ++++++
arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 90 ++++++++
arch/arm/boot/dts/db-dxbc2.dts | 151 ++++++++++++
arch/arm/boot/dts/db-xc3-24g4xg.dts | 142 ++++++++++++
arch/arm/mach-mvebu/platsmp.c | 86 +++++++
drivers/clk/mvebu/armada-xp.c | 39 ++++
drivers/clk/mvebu/clk-corediv.c | 23 ++
drivers/clk/mvebu/clk-cpu.c | 8 +
drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 156 +++++++++++++
17 files changed, 1163 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
create mode 100644 Documentation/devicetree/bindings/net/marvell,prestera.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
interdiff to v4:
diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
index 520562a7dc2a..c7b4e3a6b2c6 100644
@@ -85,7 +86,7 @@
by address and length of the PMU DFS registers
- #clock-cells : should be set to 1.
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
-index b3094315a3c0..0413bf8284e0 100644
+index b3094315a3c0..890a863ae0d0 100644
--- a/drivers/clk/mvebu/armada-xp.c
+++ b/drivers/clk/mvebu/armada-xp.c
return 250000000;
@@ -118,9 +119,6 @@
+static const struct coreclk_soc_desc mv98dx3236_coreclks = {
+ .get_tclk_freq = mv98dx3236_get_tclk_freq,
+ .get_cpu_freq = mv98dx3236_get_cpu_freq,
-+ .get_clk_ratio = NULL,
-+ .ratios = NULL,
-+ .num_ratios = 0,
+};
+
/*
@@ -200,53 +198,16 @@
+CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock",
+ mv98dx3236_corediv_clk_init);
diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
-index 5837eb8a212f..3b8f0e14fa01 100644
+index 5837eb8a212f..044892b6534d 100644
--- a/drivers/clk/mvebu/clk-cpu.c
+++ b/drivers/clk/mvebu/clk-cpu.c
- .set_rate = clk_cpu_set_rate,
- };
-
--static void __init of_cpu_clk_setup(struct device_node *node)
-+/* Add parameter to allow this to support different clock operations. */
-+static void __init _of_cpu_clk_setup(struct device_node *node,
-+ const struct clk_ops *cpu_clk_ops)
- {
- struct cpu_clk *cpuclk;
- void __iomem *clock_complex_base = of_iomap(node, 0);
- cpuclk[cpu].hw.init = &init;
- init.name = cpuclk[cpu].clk_name;
-- init.ops = &cpu_ops;
-+ init.ops = cpu_clk_ops;
- init.flags = 0;
- init.parent_names = &cpuclk[cpu].parent_name;
- init.num_parents = 1;
- iounmap(clock_complex_base);
- }
-
-+/* Use this function to call the generic setup with the correct
-+ * clock operation
-+ */
-+static void __init of_cpu_clk_setup(struct device_node *node)
-+{
-+ _of_cpu_clk_setup(node, &cpu_ops);
-+}
-+
CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
of_cpu_clk_setup);
+
-+/* Define the clock and operations for the mv98dx3236 - it cannot perform
-+ * any operations.
-+ */
-+static const struct clk_ops mv98dx3236_cpu_ops = {
-+ .recalc_rate = NULL,
-+ .round_rate = NULL,
-+ .set_rate = NULL,
-+};
-+
+static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
+{
-+ _of_cpu_clk_setup(node, &mv98dx3236_cpu_ops);
++ of_clk_add_provider(node, of_clk_src_simple_get, NULL);
+}
+
+CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
@@ -285,7 +247,7 @@
"qcom,gcc-msm8660"
diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
new file mode 100644
-index 000000000000..8082ba872edd
+index 000000000000..26eb9d3aa630
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
+Resume Control
@@ -304,10 +266,8 @@
+ compatible = "marvell,98dx3336-resume-ctrl";
+ reg = <0x20980 0x10>;
+};
-+
-+
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
-index 46c742d3bd41..59be3ca0464f 100644
+index 46c742d3bd41..a5b464497e1a 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -327,7 +287,7 @@
+static const struct of_device_id of_mv98dx3236_resume_table[] = {
+ {
+ .compatible = "marvell,98dx3336-resume-ctrl",
-+ .data = (void *)&mv98dx3336_resume_controller,
++ .data = &mv98dx3336_resume_controller,
+ },
+ { /* end of list */ },
+};
@@ -337,7 +297,7 @@
+ const struct of_device_id *match;
+ struct device_node *np;
+ void __iomem *base;
-+ struct resume_controller *rc;
++ const struct resume_controller *rc;
+
+ WARN_ON(hw_cpu != 1);
+
@@ -347,7 +307,7 @@
+ return -ENODEV;
+
+ base = of_io_request_and_map(np, 0, of_node_full_name(np));
-+ rc = (struct resume_controller *)match->data;
++ rc = match->data;
+ of_node_put(np);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
@@ -411,15 +371,17 @@
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
new file mode 100644
-index 000000000000..d4e6ecdfc853
+index 000000000000..97aef67ee769
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
+* Marvell 98dx3236 pinctrl driver for mpp
@@ -435,41 +397,41 @@
+
+name pins functions
+================================================================================
-+mpp0 0 gpio, spi0(mosi), dev(ad8)
++mpp0 0 gpo, spi0(mosi), dev(ad8)
+mpp1 1 gpio, spi0(miso), dev(ad9)
-+mpp2 2 gpio, spi0(sck), dev(ad10)
++mpp2 2 gpo, spi0(sck), dev(ad10)
+mpp3 3 gpio, spi0(cs0), dev(ad11)
+mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
+mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
-+mpp6 6 gpio, sd0(clk), dev(a2)
++mpp6 6 gpo, sd0(clk), dev(a2)
+mpp7 7 gpio, sd0(d0), dev(ale0)
+mpp8 8 gpio, sd0(d1), dev(ale1)
+mpp9 9 gpio, sd0(d2), dev(ready0)
+mpp10 10 gpio, sd0(d3), dev(ad12)
+mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13)
-+mpp12 12 gpio, uart1(txd), uart0(rts), dev(ad14)
++mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14)
+mpp13 13 gpio, intr(out), dev(ad15)
+mpp14 14 gpio, i2c0(sck)
+mpp15 15 gpio, i2c0(sda)
-+mpp16 16 gpio, dev(oe)
-+mpp17 17 gpio, dev(clk)
++mpp16 16 gpo, dev(oe)
++mpp17 17 gpo, dev(clkout)
+mpp18 18 gpio, uart1(txd)
+mpp19 19 gpio, uart1(rxd), dev(rb)
-+mpp20 20 gpio, dev(we)
-+mpp21 21 gpio, dev(ad0)
-+mpp22 22 gpio, dev(ad1)
-+mpp23 23 gpio, dev(ad2)
-+mpp24 24 gpio, dev(ad3)
-+mpp25 25 gpio, dev(ad4)
-+mpp26 26 gpio, dev(ad5)
-+mpp27 27 gpio, dev(ad6)
-+mpp28 28 gpio, dev(ad7)
-+mpp29 29 gpio, dev(a0)
-+mpp30 30 gpio, dev(a1)
++mpp20 20 gpo, dev(we0)
++mpp21 21 gpo, dev(ad0)
++mpp22 22 gpo, dev(ad1)
++mpp23 23 gpo, dev(ad2)
++mpp24 24 gpo, dev(ad3)
++mpp25 25 gpo, dev(ad4)
++mpp26 26 gpo, dev(ad5)
++mpp27 27 gpo, dev(ad6)
++mpp28 28 gpo, dev(ad7)
++mpp29 29 gpo, dev(a0)
++mpp30 30 gpo, dev(a1)
+mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
+mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
-index e4ea71a9d985..554eeae8cd21 100644
+index 63e1bd506983..61cbc138703e 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
V_MV78460 = BIT(2),
@@ -495,8 +457,8 @@
+ MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)),
+ MPP_MODE(2,
-+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
-+ MPP_VAR_FUNCTION(0x2, "spi0", "csk", V_98DX3236_PLUS),
++ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
++ MPP_VAR_FUNCTION(0x2, "spi0", "sck", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)),
+ MPP_MODE(3,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
@@ -511,7 +473,7 @@
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251),
-+ MPP_VAR_FUNCTION(0x4, "dev", "bootcs0", V_98DX3236_PLUS)),
++ MPP_VAR_FUNCTION(0x4, "dev", "bootcs", V_98DX3236_PLUS)),
+ MPP_MODE(6,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251),
@@ -563,7 +525,8 @@
+ MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)),
+ MPP_MODE(19,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
-+ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS)),
++ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS),
++ MPP_VAR_FUNCTION(0x4, "dev", "rb", V_98DX3236_PLUS)),
+ MPP_MODE(20,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)),
@@ -630,11 +593,11 @@
};
+static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = {
-+ MPP_FUNC_CTRL(0, 32, NULL, armada_xp_mpp_ctrl),
++ MPP_FUNC_CTRL(0, 32, NULL, mvebu_mmio_mpp_ctrl),
+};
+
+static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = {
-+ MPP_GPIO_RANGE(0, 0, 0, 32),
++ MPP_GPIO_RANGE(0, 0, 0, 32),
+};
+
static int armada_xp_pinctrl_suspend(struct platform_device *pdev,
@@ -767,7 +731,7 @@
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
new file mode 100644
-index 000000000000..4b7b2fe3b682
+index 000000000000..9461128fae24
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+/*
@@ -785,17 +749,17 @@
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
-+ * This file is distributed in the hope that it will be useful
++ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
-+ * Or, alternatively
++ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use
++ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
@@ -804,11 +768,11 @@
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
-+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
@@ -851,9 +815,9 @@
+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
+
+ /*
-+ * 98DX3236 has 1 x1 PCIe unit Gen2.0: One unit can be
++ * 98DX3236 has 1 x1 PCIe unit Gen2.0
+ */
-+ pcie-controller {
++ pciec: pcie-controller@82000000 {
+ compatible = "marvell,armada-xp-pcie";
+ status = "disabled";
+ device_type = "pci";
@@ -870,7 +834,7 @@
+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
+ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;
+
-+ pcie@1,0 {
++ pcie1: pcie@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
@@ -967,7 +931,7 @@
+ };
+ };
+
-+ dfx-registers {
++ dfxr: dfx-registers@ac000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
@@ -987,7 +951,7 @@
+ };
+ };
+
-+ switch {
++ switch: switch@a8000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
@@ -1026,7 +990,7 @@
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
new file mode 100644
-index 000000000000..a9b0f47f8df9
+index 000000000000..e1580afdc260
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
+/*
@@ -1044,17 +1008,17 @@
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
-+ * This file is distributed in the hope that it will be useful
++ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
-+ * Or, alternatively
++ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use
++ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
@@ -1063,16 +1027,16 @@
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
-+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
-+ * Contains definitions specific to the 98dx3336 SoC that are not
++ * Contains definitions specific to the 98dx3236 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
@@ -1107,7 +1071,7 @@
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
new file mode 100644
-index 000000000000..446e6e65ec59
+index 000000000000..4b0533a4ccb7
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
+/*
@@ -1125,17 +1089,17 @@
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
-+ * This file is distributed in the hope that it will be useful
++ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
-+ * Or, alternatively
++ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use
++ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
@@ -1144,11 +1108,11 @@
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
-+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
@@ -1213,15 +1177,15 @@
diff --git a/arch/arm/boot/dts/db-dxbc2.dts b/arch/arm/boot/dts/db-dxbc2.dts
new file mode 100644
-index 000000000000..f56786cea5f8
+index 000000000000..a8130805074e
--- /dev/null
+++ b/arch/arm/boot/dts/db-dxbc2.dts
+/*
@@ -1241,17 +1205,17 @@
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
-+ * This file is distributed in the hope that it will be useful
++ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
-+ * Or, alternatively
++ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use
++ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
@@ -1260,11 +1224,11 @@
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
-+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
@@ -1295,66 +1259,58 @@
+ reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
+ };
+
-+ soc {
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
-+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
-+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
-+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
-+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
++};
+
-+ devbus-bootcs {
-+ status = "okay";
++&devbus_bootcs {
++ status = "okay";
+
-+ /* Device Bus parameters are required */
++ /* Device Bus parameters are required */
+
-+ /* Read parameters */
-+ devbus,bus-width = <16>;
-+ devbus,turn-off-ps = <60000>;
-+ devbus,badr-skew-ps = <0>;
-+ devbus,acc-first-ps = <124000>;
-+ devbus,acc-next-ps = <248000>;
-+ devbus,rd-setup-ps = <0>;
-+ devbus,rd-hold-ps = <0>;
-+
-+ /* Write parameters */
-+ devbus,sync-enable = <0>;
-+ devbus,wr-high-ps = <60000>;
-+ devbus,wr-low-ps = <60000>;
-+ devbus,ale-wr-ps = <60000>;
-+ };
++ /* Read parameters */
++ devbus,bus-width = <16>;
++ devbus,turn-off-ps = <60000>;
++ devbus,badr-skew-ps = <0>;
++ devbus,acc-first-ps = <124000>;
++ devbus,acc-next-ps = <248000>;
++ devbus,rd-setup-ps = <0>;
++ devbus,rd-hold-ps = <0>;
++
++ /* Write parameters */
++ devbus,sync-enable = <0>;
++ devbus,wr-high-ps = <60000>;
++ devbus,wr-low-ps = <60000>;
++ devbus,ale-wr-ps = <60000>;
++};
+
-+ internal-regs {
-+ serial@12000 {
-+ status = "okay";
-+ };
-+ serial@12100 {
-+ status = "okay";
-+ };
++&i2c0 {
++ clock-frequency = <100000>;
++ status = "okay";
++};
+
-+ i2c@11000 {
-+ clock-frequency = <100000>;
-+ status = "okay";
-+ };
++&uart0 {
++ status = "okay";
++};
+
-+ mvsdio@d4000 {
-+ pinctrl-0 = <&sdio_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+ /* No CD or WP GPIOs */
-+ broken-cd;
-+ };
++&uart1 {
++ status = "okay";
++};
+
-+ nand@d0000 {
-+ status = "okay";
-+ num-cs = <1>;
-+ marvell,nand-keep-config;
-+ marvell,nand-enable-arbiter;
-+ nand-on-flash-bbt;
-+ nand-ecc-strength = <4>;
-+ nand-ecc-step-size = <512>;
-+ };
-+ };
-+ };
++&nand {
++ status = "okay";
++ num-cs = <1>;
++ marvell,nand-keep-config;
++ marvell,nand-enable-arbiter;
++ nand-on-flash-bbt;
++ nand-ecc-strength = <4>;
++ nand-ecc-step-size = <512>;
++};
++
++&sdio {
++ pinctrl-0 = <&sdio_pins>;
++ pinctrl-names = "default";
++ status = "okay";
++ /* No CD or WP GPIOs */
++ broken-cd;
+};
+
+&spi0 {
@@ -1385,7 +1341,7 @@
+};
diff --git a/arch/arm/boot/dts/db-xc3-24g4xg.dts b/arch/arm/boot/dts/db-xc3-24g4xg.dts
new file mode 100644
-index 000000000000..5eb89ffb9a7d
+index 000000000000..4e07cb6ed800
--- /dev/null
+++ b/arch/arm/boot/dts/db-xc3-24g4xg.dts
+/*
@@ -1405,17 +1361,17 @@
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
-+ * This file is distributed in the hope that it will be useful
++ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
-+ * Or, alternatively
++ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use
++ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
@@ -1424,11 +1380,11 @@
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
-+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
@@ -1458,63 +1414,50 @@
+ device_type = "memory";
+ reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
+ };
++};
+
-+ soc {
-+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
-+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
-+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
-+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
-+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
-+
-+ devbus-bootcs {
-+ status = "okay";
++&devbus_bootcs {
++ status = "okay";
+
-+ /* Device Bus parameters are required */
++ /* Device Bus parameters are required */
+
-+ /* Read parameters */
-+ devbus,bus-width = <16>;
-+ devbus,turn-off-ps = <60000>;
-+ devbus,badr-skew-ps = <0>;
-+ devbus,acc-first-ps = <124000>;
-+ devbus,acc-next-ps = <248000>;
-+ devbus,rd-setup-ps = <0>;
-+ devbus,rd-hold-ps = <0>;
-+
-+ /* Write parameters */
-+ devbus,sync-enable = <0>;
-+ devbus,wr-high-ps = <60000>;
-+ devbus,wr-low-ps = <60000>;
-+ devbus,ale-wr-ps = <60000>;
-+ };
++ /* Read parameters */
++ devbus,bus-width = <16>;
++ devbus,turn-off-ps = <60000>;
++ devbus,badr-skew-ps = <0>;
++ devbus,acc-first-ps = <124000>;
++ devbus,acc-next-ps = <248000>;
++ devbus,rd-setup-ps = <0>;
++ devbus,rd-hold-ps = <0>;
++
++ /* Write parameters */
++ devbus,sync-enable = <0>;
++ devbus,wr-high-ps = <60000>;
++ devbus,wr-low-ps = <60000>;
++ devbus,ale-wr-ps = <60000>;
++};
+
-+ internal-regs {
-+ serial@12000 {
-+ status = "okay";
-+ };
-+ serial@12100 {
-+ status = "okay";
-+ };
++&uart0 {
++ status = "okay";
++};
+
-+ i2c@11000 {
-+ clock-frequency = <100000>;
-+ status = "okay";
-+ };
++&uart1 {
++ status = "okay";
++};
+
-+ mvsdio@d4000 {
-+ status = "disabled";
-+ };
++&i2c0 {
++ clock-frequency = <100000>;
++ status = "okay";
++};
+
-+ nand@d0000 {
-+ status = "okay";
-+ num-cs = <1>;
-+ marvell,nand-keep-config;
-+ marvell,nand-enable-arbiter;
-+ nand-on-flash-bbt;
-+ nand-ecc-strength = <4>;
-+ nand-ecc-step-size = <512>;
-+ };
-+ };
-+ };
++&nand {
++ status = "okay";
++ num-cs = <1>;
++ marvell,nand-keep-config;
++ marvell,nand-enable-arbiter;
++ nand-on-flash-bbt;
++ nand-ecc-strength = <4>;
++ nand-ecc-step-size = <512>;
+};
+
+&spi0 {
--
2.11.0.24.ge6920cf
^ permalink raw reply [flat|nested] 49+ messages in thread* [PATCHv5 1/5] clk: mvebu: support for 98DX3236 SoC
2017-01-27 3:25 ` Chris Packham
@ 2017-01-27 3:25 ` Chris Packham
-1 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-27 3:25 UTC (permalink / raw)
To: linux, linux-arm-kernel
Cc: Chris Packham, Michael Turquette, Stephen Boyd, Rob Herring,
Mark Rutland, linux-clk, devicetree, linux-kernel
The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.
The clock gating options are a subset of those on the Armada XP.
The core clock divider is different to the Armada XP also.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
---
Notes:
Changes in v2:
- Update devicetree binding documentation for new compatible string
Changes in v3:
- Add 98dx3236 support to mvebu/clk-corediv.c rather than creating a new
driver.
- Document mv98dx3236-corediv-clock binding
Changes in v4:
- None
Changes in v5:
- Collect ack from Rob
- Remove explicit initialisation of fields to 0 in mv98dx3236_coreclks
- Register dummy clock provider for marvell,mv98dx3236-cpu-clock
.../bindings/clock/mvebu-corediv-clock.txt | 1 +
.../devicetree/bindings/clock/mvebu-cpu-clock.txt | 1 +
drivers/clk/mvebu/armada-xp.c | 39 ++++++++++++++++++++++
drivers/clk/mvebu/clk-corediv.c | 23 +++++++++++++
drivers/clk/mvebu/clk-cpu.c | 8 +++++
5 files changed, 72 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
index 520562a7dc2a..c7b4e3a6b2c6 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
@@ -7,6 +7,7 @@ Required properties:
- compatible : must be "marvell,armada-370-corediv-clock",
"marvell,armada-375-corediv-clock",
"marvell,armada-380-corediv-clock",
+ "marvell,mv98dx3236-corediv-clock",
- reg : must be the register address of Core Divider control register
- #clock-cells : from common clock binding; shall be set to 1
diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
index 99c214660bdc..7f28506eaee7 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
@@ -3,6 +3,7 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms
Required properties:
- compatible : shall be one of the following:
"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
+ "marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
- reg : Address and length of the clock complex register set, followed
by address and length of the PMU DFS registers
- #clock-cells : should be set to 1.
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
index b3094315a3c0..890a863ae0d0 100644
--- a/drivers/clk/mvebu/armada-xp.c
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -52,6 +52,12 @@ static u32 __init axp_get_tclk_freq(void __iomem *sar)
return 250000000;
}
+/* MV98DX3236 TCLK frequency is fixed to 200MHz */
+static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar)
+{
+ return 200000000;
+}
+
static const u32 axp_cpu_freqs[] __initconst = {
1000000000,
1066000000,
@@ -89,6 +95,12 @@ static u32 __init axp_get_cpu_freq(void __iomem *sar)
return cpu_freq;
}
+/* MV98DX3236 CLK frequency is fixed to 800MHz */
+static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar)
+{
+ return 800000000;
+}
+
static const int axp_nbclk_ratios[32][2] __initconst = {
{0, 1}, {1, 2}, {2, 2}, {2, 2},
{1, 2}, {1, 2}, {1, 1}, {2, 3},
@@ -158,6 +170,11 @@ static const struct coreclk_soc_desc axp_coreclks = {
.num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
};
+static const struct coreclk_soc_desc mv98dx3236_coreclks = {
+ .get_tclk_freq = mv98dx3236_get_tclk_freq,
+ .get_cpu_freq = mv98dx3236_get_cpu_freq,
+};
+
/*
* Clock Gating Control
*/
@@ -195,6 +212,15 @@ static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = {
{ }
};
+static const struct clk_gating_soc_desc mv98dx3236_gating_desc[] __initconst = {
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex00", NULL, 5, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "xor0", NULL, 22, 0 },
+ { }
+};
+
static void __init axp_clk_init(struct device_node *np)
{
struct device_node *cgnp =
@@ -206,3 +232,16 @@ static void __init axp_clk_init(struct device_node *np)
mvebu_clk_gating_setup(cgnp, axp_gating_desc);
}
CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init);
+
+static void __init mv98dx3236_clk_init(struct device_node *np)
+{
+ struct device_node *cgnp =
+ of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock");
+
+ mvebu_coreclk_setup(np, &mv98dx3236_coreclks);
+
+ if (cgnp)
+ mvebu_clk_gating_setup(cgnp, mv98dx3236_gating_desc);
+}
+CLK_OF_DECLARE(mv98dx3236_clk, "marvell,mv98dx3236-core-clock",
+ mv98dx3236_clk_init);
diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c
index d1e5863d3375..8491979f4096 100644
--- a/drivers/clk/mvebu/clk-corediv.c
+++ b/drivers/clk/mvebu/clk-corediv.c
@@ -71,6 +71,10 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] = {
{ .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */
};
+static const struct clk_corediv_desc mv98dx3236_corediv_desc[] = {
+ { .mask = 0x0f, .offset = 6, .fieldbit = 26 }, /* NAND clock */
+};
+
#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
static int clk_corediv_is_enabled(struct clk_hw *hwclk)
@@ -232,6 +236,18 @@ static const struct clk_corediv_soc_desc armada375_corediv_soc = {
.ratio_offset = 0x4,
};
+static const struct clk_corediv_soc_desc mv98dx3236_corediv_soc = {
+ .descs = mv98dx3236_corediv_desc,
+ .ndescs = ARRAY_SIZE(mv98dx3236_corediv_desc),
+ .ops = {
+ .recalc_rate = clk_corediv_recalc_rate,
+ .round_rate = clk_corediv_round_rate,
+ .set_rate = clk_corediv_set_rate,
+ },
+ .ratio_reload = BIT(10),
+ .ratio_offset = 0x8,
+};
+
static void __init
mvebu_corediv_clk_init(struct device_node *node,
const struct clk_corediv_soc_desc *soc_desc)
@@ -313,3 +329,10 @@ static void __init armada380_corediv_clk_init(struct device_node *node)
}
CLK_OF_DECLARE(armada380_corediv_clk, "marvell,armada-380-corediv-clock",
armada380_corediv_clk_init);
+
+static void __init mv98dx3236_corediv_clk_init(struct device_node *node)
+{
+ return mvebu_corediv_clk_init(node, &mv98dx3236_corediv_soc);
+}
+CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock",
+ mv98dx3236_corediv_clk_init);
diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
index 5837eb8a212f..044892b6534d 100644
--- a/drivers/clk/mvebu/clk-cpu.c
+++ b/drivers/clk/mvebu/clk-cpu.c
@@ -245,3 +245,11 @@ static void __init of_cpu_clk_setup(struct device_node *node)
CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
of_cpu_clk_setup);
+
+static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
+{
+ of_clk_add_provider(node, of_clk_src_simple_get, NULL);
+}
+
+CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
+ of_mv98dx3236_cpu_clk_setup);
--
2.11.0.24.ge6920cf
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCHv5 1/5] clk: mvebu: support for 98DX3236 SoC
@ 2017-01-27 3:25 ` Chris Packham
0 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-27 3:25 UTC (permalink / raw)
To: linux-arm-kernel
The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.
The clock gating options are a subset of those on the Armada XP.
The core clock divider is different to the Armada XP also.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
---
Notes:
Changes in v2:
- Update devicetree binding documentation for new compatible string
Changes in v3:
- Add 98dx3236 support to mvebu/clk-corediv.c rather than creating a new
driver.
- Document mv98dx3236-corediv-clock binding
Changes in v4:
- None
Changes in v5:
- Collect ack from Rob
- Remove explicit initialisation of fields to 0 in mv98dx3236_coreclks
- Register dummy clock provider for marvell,mv98dx3236-cpu-clock
.../bindings/clock/mvebu-corediv-clock.txt | 1 +
.../devicetree/bindings/clock/mvebu-cpu-clock.txt | 1 +
drivers/clk/mvebu/armada-xp.c | 39 ++++++++++++++++++++++
drivers/clk/mvebu/clk-corediv.c | 23 +++++++++++++
drivers/clk/mvebu/clk-cpu.c | 8 +++++
5 files changed, 72 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
index 520562a7dc2a..c7b4e3a6b2c6 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
@@ -7,6 +7,7 @@ Required properties:
- compatible : must be "marvell,armada-370-corediv-clock",
"marvell,armada-375-corediv-clock",
"marvell,armada-380-corediv-clock",
+ "marvell,mv98dx3236-corediv-clock",
- reg : must be the register address of Core Divider control register
- #clock-cells : from common clock binding; shall be set to 1
diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
index 99c214660bdc..7f28506eaee7 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
@@ -3,6 +3,7 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms
Required properties:
- compatible : shall be one of the following:
"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
+ "marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
- reg : Address and length of the clock complex register set, followed
by address and length of the PMU DFS registers
- #clock-cells : should be set to 1.
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
index b3094315a3c0..890a863ae0d0 100644
--- a/drivers/clk/mvebu/armada-xp.c
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -52,6 +52,12 @@ static u32 __init axp_get_tclk_freq(void __iomem *sar)
return 250000000;
}
+/* MV98DX3236 TCLK frequency is fixed to 200MHz */
+static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar)
+{
+ return 200000000;
+}
+
static const u32 axp_cpu_freqs[] __initconst = {
1000000000,
1066000000,
@@ -89,6 +95,12 @@ static u32 __init axp_get_cpu_freq(void __iomem *sar)
return cpu_freq;
}
+/* MV98DX3236 CLK frequency is fixed to 800MHz */
+static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar)
+{
+ return 800000000;
+}
+
static const int axp_nbclk_ratios[32][2] __initconst = {
{0, 1}, {1, 2}, {2, 2}, {2, 2},
{1, 2}, {1, 2}, {1, 1}, {2, 3},
@@ -158,6 +170,11 @@ static const struct coreclk_soc_desc axp_coreclks = {
.num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
};
+static const struct coreclk_soc_desc mv98dx3236_coreclks = {
+ .get_tclk_freq = mv98dx3236_get_tclk_freq,
+ .get_cpu_freq = mv98dx3236_get_cpu_freq,
+};
+
/*
* Clock Gating Control
*/
@@ -195,6 +212,15 @@ static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = {
{ }
};
+static const struct clk_gating_soc_desc mv98dx3236_gating_desc[] __initconst = {
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex00", NULL, 5, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "xor0", NULL, 22, 0 },
+ { }
+};
+
static void __init axp_clk_init(struct device_node *np)
{
struct device_node *cgnp =
@@ -206,3 +232,16 @@ static void __init axp_clk_init(struct device_node *np)
mvebu_clk_gating_setup(cgnp, axp_gating_desc);
}
CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init);
+
+static void __init mv98dx3236_clk_init(struct device_node *np)
+{
+ struct device_node *cgnp =
+ of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock");
+
+ mvebu_coreclk_setup(np, &mv98dx3236_coreclks);
+
+ if (cgnp)
+ mvebu_clk_gating_setup(cgnp, mv98dx3236_gating_desc);
+}
+CLK_OF_DECLARE(mv98dx3236_clk, "marvell,mv98dx3236-core-clock",
+ mv98dx3236_clk_init);
diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c
index d1e5863d3375..8491979f4096 100644
--- a/drivers/clk/mvebu/clk-corediv.c
+++ b/drivers/clk/mvebu/clk-corediv.c
@@ -71,6 +71,10 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] = {
{ .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */
};
+static const struct clk_corediv_desc mv98dx3236_corediv_desc[] = {
+ { .mask = 0x0f, .offset = 6, .fieldbit = 26 }, /* NAND clock */
+};
+
#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
static int clk_corediv_is_enabled(struct clk_hw *hwclk)
@@ -232,6 +236,18 @@ static const struct clk_corediv_soc_desc armada375_corediv_soc = {
.ratio_offset = 0x4,
};
+static const struct clk_corediv_soc_desc mv98dx3236_corediv_soc = {
+ .descs = mv98dx3236_corediv_desc,
+ .ndescs = ARRAY_SIZE(mv98dx3236_corediv_desc),
+ .ops = {
+ .recalc_rate = clk_corediv_recalc_rate,
+ .round_rate = clk_corediv_round_rate,
+ .set_rate = clk_corediv_set_rate,
+ },
+ .ratio_reload = BIT(10),
+ .ratio_offset = 0x8,
+};
+
static void __init
mvebu_corediv_clk_init(struct device_node *node,
const struct clk_corediv_soc_desc *soc_desc)
@@ -313,3 +329,10 @@ static void __init armada380_corediv_clk_init(struct device_node *node)
}
CLK_OF_DECLARE(armada380_corediv_clk, "marvell,armada-380-corediv-clock",
armada380_corediv_clk_init);
+
+static void __init mv98dx3236_corediv_clk_init(struct device_node *node)
+{
+ return mvebu_corediv_clk_init(node, &mv98dx3236_corediv_soc);
+}
+CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock",
+ mv98dx3236_corediv_clk_init);
diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
index 5837eb8a212f..044892b6534d 100644
--- a/drivers/clk/mvebu/clk-cpu.c
+++ b/drivers/clk/mvebu/clk-cpu.c
@@ -245,3 +245,11 @@ static void __init of_cpu_clk_setup(struct device_node *node)
CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
of_cpu_clk_setup);
+
+static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
+{
+ of_clk_add_provider(node, of_clk_src_simple_get, NULL);
+}
+
+CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
+ of_mv98dx3236_cpu_clk_setup);
--
2.11.0.24.ge6920cf
^ permalink raw reply related [flat|nested] 49+ messages in thread* Re: [PATCHv5 1/5] clk: mvebu: support for 98DX3236 SoC
2017-01-27 3:25 ` Chris Packham
(?)
@ 2017-01-27 18:48 ` Stephen Boyd
-1 siblings, 0 replies; 49+ messages in thread
From: Stephen Boyd @ 2017-01-27 18:48 UTC (permalink / raw)
To: Chris Packham
Cc: linux, linux-arm-kernel, Michael Turquette, Rob Herring,
Mark Rutland, linux-clk, devicetree, linux-kernel
On 01/27, Chris Packham wrote:
> The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
> the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.
>
> The clock gating options are a subset of those on the Armada XP.
>
> The core clock divider is different to the Armada XP also.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCHv5 1/5] clk: mvebu: support for 98DX3236 SoC
@ 2017-01-27 18:48 ` Stephen Boyd
0 siblings, 0 replies; 49+ messages in thread
From: Stephen Boyd @ 2017-01-27 18:48 UTC (permalink / raw)
To: linux-arm-kernel
On 01/27, Chris Packham wrote:
> The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
> the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.
>
> The clock gating options are a subset of those on the Armada XP.
>
> The core clock divider is different to the Armada XP also.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCHv5 1/5] clk: mvebu: support for 98DX3236 SoC
@ 2017-01-27 18:48 ` Stephen Boyd
0 siblings, 0 replies; 49+ messages in thread
From: Stephen Boyd @ 2017-01-27 18:48 UTC (permalink / raw)
To: Chris Packham
Cc: Mark Rutland, devicetree, Michael Turquette, linux, linux-kernel,
Rob Herring, linux-clk, linux-arm-kernel
On 01/27, Chris Packham wrote:
> The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
> the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.
>
> The clock gating options are a subset of those on the Armada XP.
>
> The core clock divider is different to the Armada XP also.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCHv5 2/5] arm: mvebu: support for SMP on 98DX3336 SoC
2017-01-27 3:25 ` Chris Packham
@ 2017-01-27 3:25 ` Chris Packham
-1 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-27 3:25 UTC (permalink / raw)
To: linux, linux-arm-kernel
Cc: Chris Packham, Rob Herring, Mark Rutland, Jason Cooper,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth, devicetree,
linux-kernel
Compared to the armada-xp the 98DX3336 uses different registers to set
the boot address for the secondary CPU so a new enable-method is needed.
This will only work if the machine definition doesn't define an overall
smp_ops because there is not currently a way of overriding this from the
device tree if it is set in the machine definition.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
---
Notes:
Changes in v2:
- Document new enable-method value
- Correct some references from 98DX4521 to 98DX3236
Changes in v3:
- Simplify mv98dx3236_resume_init by using of_io_request_and_map()
Changes in v4:
- integrate changes into platsmp.c instead of new init call
- avoid duplicated code.
- fix error return
- Collect ack from Rob
Changes in v5:
- Remove useless casts (thanks to Stephen Boyd)
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
.../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 16 ++++
arch/arm/mach-mvebu/platsmp.c | 86 ++++++++++++++++++++++
3 files changed, 103 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index a1bcfeed5f24..3c2fd72d0bf9 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -202,6 +202,7 @@ nodes to be present and contain the properties described below.
"marvell,armada-380-smp"
"marvell,armada-390-smp"
"marvell,armada-xp-smp"
+ "marvell,98dx3236-smp"
"mediatek,mt6589-smp"
"mediatek,mt81xx-tz-smp"
"qcom,gcc-msm8660"
diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
new file mode 100644
index 000000000000..26eb9d3aa630
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
@@ -0,0 +1,16 @@
+Resume Control
+--------------
+Available on Marvell SOCs: 98DX3336 and 98DX4251
+
+Required properties:
+
+- compatible: must be "marvell,98dx3336-resume-ctrl"
+
+- reg: Should contain resume control registers location and length
+
+Example:
+
+resume@20980 {
+ compatible = "marvell,98dx3336-resume-ctrl";
+ reg = <0x20980 0x10>;
+};
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index 46c742d3bd41..a5b464497e1a 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -184,3 +184,89 @@ const struct smp_operations armada_xp_smp_ops __initconst = {
CPU_METHOD_OF_DECLARE(armada_xp_smp, "marvell,armada-xp-smp",
&armada_xp_smp_ops);
+
+struct resume_controller {
+ u32 resume_control;
+ u32 resume_boot_addr;
+};
+
+static const struct resume_controller mv98dx3336_resume_controller = {
+ .resume_control = 0x08,
+ .resume_boot_addr = 0x04,
+};
+
+static const struct of_device_id of_mv98dx3236_resume_table[] = {
+ {
+ .compatible = "marvell,98dx3336-resume-ctrl",
+ .data = &mv98dx3336_resume_controller,
+ },
+ { /* end of list */ },
+};
+
+static int mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
+{
+ const struct of_device_id *match;
+ struct device_node *np;
+ void __iomem *base;
+ const struct resume_controller *rc;
+
+ WARN_ON(hw_cpu != 1);
+
+ np = of_find_matching_node_and_match(NULL, of_mv98dx3236_resume_table,
+ &match);
+ if (!np)
+ return -ENODEV;
+
+ base = of_io_request_and_map(np, 0, of_node_full_name(np));
+ rc = match->data;
+ of_node_put(np);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ writel(0, base + rc->resume_control);
+ writel(virt_to_phys(boot_addr), base + rc->resume_boot_addr);
+
+ return 0;
+}
+
+static int mv98dx3236_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ int ret, hw_cpu;
+
+ hw_cpu = cpu_logical_map(cpu);
+ set_secondary_cpu_clock(hw_cpu);
+ mv98dx3236_resume_set_cpu_boot_addr(hw_cpu,
+ armada_xp_secondary_startup);
+
+ /*
+ * This is needed to wake up CPUs in the offline state after
+ * using CPU hotplug.
+ */
+ arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+ /*
+ * This is needed to take secondary CPUs out of reset on the
+ * initial boot.
+ */
+ ret = mvebu_cpu_reset_deassert(hw_cpu);
+ if (ret) {
+ pr_warn("unable to boot CPU: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct smp_operations mv98dx3236_smp_ops __initconst = {
+ .smp_init_cpus = armada_xp_smp_init_cpus,
+ .smp_prepare_cpus = armada_xp_smp_prepare_cpus,
+ .smp_boot_secondary = mv98dx3236_boot_secondary,
+ .smp_secondary_init = armada_xp_secondary_init,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_die = armada_xp_cpu_die,
+ .cpu_kill = armada_xp_cpu_kill,
+#endif
+};
+
+CPU_METHOD_OF_DECLARE(mv98dx3236_smp, "marvell,98dx3236-smp",
+ &mv98dx3236_smp_ops);
--
2.11.0.24.ge6920cf
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCHv5 2/5] arm: mvebu: support for SMP on 98DX3336 SoC
@ 2017-01-27 3:25 ` Chris Packham
0 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-27 3:25 UTC (permalink / raw)
To: linux-arm-kernel
Compared to the armada-xp the 98DX3336 uses different registers to set
the boot address for the secondary CPU so a new enable-method is needed.
This will only work if the machine definition doesn't define an overall
smp_ops because there is not currently a way of overriding this from the
device tree if it is set in the machine definition.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
---
Notes:
Changes in v2:
- Document new enable-method value
- Correct some references from 98DX4521 to 98DX3236
Changes in v3:
- Simplify mv98dx3236_resume_init by using of_io_request_and_map()
Changes in v4:
- integrate changes into platsmp.c instead of new init call
- avoid duplicated code.
- fix error return
- Collect ack from Rob
Changes in v5:
- Remove useless casts (thanks to Stephen Boyd)
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
.../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 16 ++++
arch/arm/mach-mvebu/platsmp.c | 86 ++++++++++++++++++++++
3 files changed, 103 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index a1bcfeed5f24..3c2fd72d0bf9 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -202,6 +202,7 @@ nodes to be present and contain the properties described below.
"marvell,armada-380-smp"
"marvell,armada-390-smp"
"marvell,armada-xp-smp"
+ "marvell,98dx3236-smp"
"mediatek,mt6589-smp"
"mediatek,mt81xx-tz-smp"
"qcom,gcc-msm8660"
diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
new file mode 100644
index 000000000000..26eb9d3aa630
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
@@ -0,0 +1,16 @@
+Resume Control
+--------------
+Available on Marvell SOCs: 98DX3336 and 98DX4251
+
+Required properties:
+
+- compatible: must be "marvell,98dx3336-resume-ctrl"
+
+- reg: Should contain resume control registers location and length
+
+Example:
+
+resume at 20980 {
+ compatible = "marvell,98dx3336-resume-ctrl";
+ reg = <0x20980 0x10>;
+};
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index 46c742d3bd41..a5b464497e1a 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -184,3 +184,89 @@ const struct smp_operations armada_xp_smp_ops __initconst = {
CPU_METHOD_OF_DECLARE(armada_xp_smp, "marvell,armada-xp-smp",
&armada_xp_smp_ops);
+
+struct resume_controller {
+ u32 resume_control;
+ u32 resume_boot_addr;
+};
+
+static const struct resume_controller mv98dx3336_resume_controller = {
+ .resume_control = 0x08,
+ .resume_boot_addr = 0x04,
+};
+
+static const struct of_device_id of_mv98dx3236_resume_table[] = {
+ {
+ .compatible = "marvell,98dx3336-resume-ctrl",
+ .data = &mv98dx3336_resume_controller,
+ },
+ { /* end of list */ },
+};
+
+static int mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
+{
+ const struct of_device_id *match;
+ struct device_node *np;
+ void __iomem *base;
+ const struct resume_controller *rc;
+
+ WARN_ON(hw_cpu != 1);
+
+ np = of_find_matching_node_and_match(NULL, of_mv98dx3236_resume_table,
+ &match);
+ if (!np)
+ return -ENODEV;
+
+ base = of_io_request_and_map(np, 0, of_node_full_name(np));
+ rc = match->data;
+ of_node_put(np);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ writel(0, base + rc->resume_control);
+ writel(virt_to_phys(boot_addr), base + rc->resume_boot_addr);
+
+ return 0;
+}
+
+static int mv98dx3236_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ int ret, hw_cpu;
+
+ hw_cpu = cpu_logical_map(cpu);
+ set_secondary_cpu_clock(hw_cpu);
+ mv98dx3236_resume_set_cpu_boot_addr(hw_cpu,
+ armada_xp_secondary_startup);
+
+ /*
+ * This is needed to wake up CPUs in the offline state after
+ * using CPU hotplug.
+ */
+ arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+ /*
+ * This is needed to take secondary CPUs out of reset on the
+ * initial boot.
+ */
+ ret = mvebu_cpu_reset_deassert(hw_cpu);
+ if (ret) {
+ pr_warn("unable to boot CPU: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct smp_operations mv98dx3236_smp_ops __initconst = {
+ .smp_init_cpus = armada_xp_smp_init_cpus,
+ .smp_prepare_cpus = armada_xp_smp_prepare_cpus,
+ .smp_boot_secondary = mv98dx3236_boot_secondary,
+ .smp_secondary_init = armada_xp_secondary_init,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_die = armada_xp_cpu_die,
+ .cpu_kill = armada_xp_cpu_kill,
+#endif
+};
+
+CPU_METHOD_OF_DECLARE(mv98dx3236_smp, "marvell,98dx3236-smp",
+ &mv98dx3236_smp_ops);
--
2.11.0.24.ge6920cf
^ permalink raw reply related [flat|nested] 49+ messages in thread* Re: [PATCHv5 2/5] arm: mvebu: support for SMP on 98DX3336 SoC
2017-01-27 3:25 ` Chris Packham
(?)
@ 2017-01-27 14:06 ` Gregory CLEMENT
-1 siblings, 0 replies; 49+ messages in thread
From: Gregory CLEMENT @ 2017-01-27 14:06 UTC (permalink / raw)
To: Chris Packham
Cc: linux, linux-arm-kernel, Rob Herring, Mark Rutland, Jason Cooper,
Andrew Lunn, Sebastian Hesselbarth, devicetree, linux-kernel
Hi Chris,
On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
> Compared to the armada-xp the 98DX3336 uses different registers to set
> the boot address for the secondary CPU so a new enable-method is needed.
> This will only work if the machine definition doesn't define an overall
> smp_ops because there is not currently a way of overriding this from the
> device tree if it is set in the machine definition.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
>
> Notes:
> Changes in v2:
> - Document new enable-method value
> - Correct some references from 98DX4521 to 98DX3236
> Changes in v3:
> - Simplify mv98dx3236_resume_init by using of_io_request_and_map()
> Changes in v4:
> - integrate changes into platsmp.c instead of new init call
> - avoid duplicated code.
> - fix error return
> - Collect ack from Rob
> Changes in v5:
> - Remove useless casts (thanks to Stephen Boyd)
>
> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> .../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 16 ++++
> arch/arm/mach-mvebu/platsmp.c | 86 ++++++++++++++++++++++
> 3 files changed, 103 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index a1bcfeed5f24..3c2fd72d0bf9 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -202,6 +202,7 @@ nodes to be present and contain the properties described below.
> "marvell,armada-380-smp"
> "marvell,armada-390-smp"
> "marvell,armada-xp-smp"
> + "marvell,98dx3236-smp"
> "mediatek,mt6589-smp"
> "mediatek,mt81xx-tz-smp"
> "qcom,gcc-msm8660"
> diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> new file mode 100644
> index 000000000000..26eb9d3aa630
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> @@ -0,0 +1,16 @@
> +Resume Control
> +--------------
> +Available on Marvell SOCs: 98DX3336 and 98DX4251
> +
> +Required properties:
> +
> +- compatible: must be "marvell,98dx3336-resume-ctrl"
> +
> +- reg: Should contain resume control registers location and length
> +
> +Example:
> +
> +resume@20980 {
> + compatible = "marvell,98dx3336-resume-ctrl";
> + reg = <0x20980 0x10>;
> +};
> diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
> index 46c742d3bd41..a5b464497e1a 100644
> --- a/arch/arm/mach-mvebu/platsmp.c
> +++ b/arch/arm/mach-mvebu/platsmp.c
> @@ -184,3 +184,89 @@ const struct smp_operations armada_xp_smp_ops __initconst = {
>
> CPU_METHOD_OF_DECLARE(armada_xp_smp, "marvell,armada-xp-smp",
> &armada_xp_smp_ops);
> +
> +struct resume_controller {
> + u32 resume_control;
> + u32 resume_boot_addr;
> +};
> +
> +static const struct resume_controller mv98dx3336_resume_controller = {
> + .resume_control = 0x08,
> + .resume_boot_addr = 0x04,
> +};
> +
> +static const struct of_device_id of_mv98dx3236_resume_table[] = {
> + {
> + .compatible = "marvell,98dx3336-resume-ctrl",
> + .data = &mv98dx3336_resume_controller,
> + },
> + { /* end of list */ },
> +};
Do you expect to have other SoC which use the same logical but with
register at a different place?
Else you can just remove the resume_controller struct and use the address
(using define) directly in the mv98dx3236_resume_set_cpu_boot_addr
function.
> +
> +static int mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
> +{
> + const struct of_device_id *match;
> + struct device_node *np;
> + void __iomem *base;
> + const struct resume_controller *rc;
> +
> + WARN_ON(hw_cpu != 1);
> +
> + np = of_find_matching_node_and_match(NULL, of_mv98dx3236_resume_table,
> + &match);
> + if (!np)
> + return -ENODEV;
> +
> + base = of_io_request_and_map(np, 0, of_node_full_name(np));
> + rc = match->data;
> + of_node_put(np);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + writel(0, base + rc->resume_control);
> + writel(virt_to_phys(boot_addr), base + rc->resume_boot_addr);
> +
you should use iounmap() on base here, to free it.
Gregory
> + return 0;
> +}
> +
> +static int mv98dx3236_boot_secondary(unsigned int cpu, struct task_struct *idle)
> +{
> + int ret, hw_cpu;
> +
> + hw_cpu = cpu_logical_map(cpu);
> + set_secondary_cpu_clock(hw_cpu);
> + mv98dx3236_resume_set_cpu_boot_addr(hw_cpu,
> + armada_xp_secondary_startup);
> +
> + /*
> + * This is needed to wake up CPUs in the offline state after
> + * using CPU hotplug.
> + */
> + arch_send_wakeup_ipi_mask(cpumask_of(cpu));
> +
> + /*
> + * This is needed to take secondary CPUs out of reset on the
> + * initial boot.
> + */
> + ret = mvebu_cpu_reset_deassert(hw_cpu);
> + if (ret) {
> + pr_warn("unable to boot CPU: %d\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct smp_operations mv98dx3236_smp_ops __initconst = {
> + .smp_init_cpus = armada_xp_smp_init_cpus,
> + .smp_prepare_cpus = armada_xp_smp_prepare_cpus,
> + .smp_boot_secondary = mv98dx3236_boot_secondary,
> + .smp_secondary_init = armada_xp_secondary_init,
> +#ifdef CONFIG_HOTPLUG_CPU
> + .cpu_die = armada_xp_cpu_die,
> + .cpu_kill = armada_xp_cpu_kill,
> +#endif
> +};
> +
> +CPU_METHOD_OF_DECLARE(mv98dx3236_smp, "marvell,98dx3236-smp",
> + &mv98dx3236_smp_ops);
> --
> 2.11.0.24.ge6920cf
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 49+ messages in thread* [PATCHv5 2/5] arm: mvebu: support for SMP on 98DX3336 SoC
@ 2017-01-27 14:06 ` Gregory CLEMENT
0 siblings, 0 replies; 49+ messages in thread
From: Gregory CLEMENT @ 2017-01-27 14:06 UTC (permalink / raw)
To: linux-arm-kernel
Hi Chris,
On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
> Compared to the armada-xp the 98DX3336 uses different registers to set
> the boot address for the secondary CPU so a new enable-method is needed.
> This will only work if the machine definition doesn't define an overall
> smp_ops because there is not currently a way of overriding this from the
> device tree if it is set in the machine definition.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
>
> Notes:
> Changes in v2:
> - Document new enable-method value
> - Correct some references from 98DX4521 to 98DX3236
> Changes in v3:
> - Simplify mv98dx3236_resume_init by using of_io_request_and_map()
> Changes in v4:
> - integrate changes into platsmp.c instead of new init call
> - avoid duplicated code.
> - fix error return
> - Collect ack from Rob
> Changes in v5:
> - Remove useless casts (thanks to Stephen Boyd)
>
> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> .../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 16 ++++
> arch/arm/mach-mvebu/platsmp.c | 86 ++++++++++++++++++++++
> 3 files changed, 103 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index a1bcfeed5f24..3c2fd72d0bf9 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -202,6 +202,7 @@ nodes to be present and contain the properties described below.
> "marvell,armada-380-smp"
> "marvell,armada-390-smp"
> "marvell,armada-xp-smp"
> + "marvell,98dx3236-smp"
> "mediatek,mt6589-smp"
> "mediatek,mt81xx-tz-smp"
> "qcom,gcc-msm8660"
> diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> new file mode 100644
> index 000000000000..26eb9d3aa630
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> @@ -0,0 +1,16 @@
> +Resume Control
> +--------------
> +Available on Marvell SOCs: 98DX3336 and 98DX4251
> +
> +Required properties:
> +
> +- compatible: must be "marvell,98dx3336-resume-ctrl"
> +
> +- reg: Should contain resume control registers location and length
> +
> +Example:
> +
> +resume at 20980 {
> + compatible = "marvell,98dx3336-resume-ctrl";
> + reg = <0x20980 0x10>;
> +};
> diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
> index 46c742d3bd41..a5b464497e1a 100644
> --- a/arch/arm/mach-mvebu/platsmp.c
> +++ b/arch/arm/mach-mvebu/platsmp.c
> @@ -184,3 +184,89 @@ const struct smp_operations armada_xp_smp_ops __initconst = {
>
> CPU_METHOD_OF_DECLARE(armada_xp_smp, "marvell,armada-xp-smp",
> &armada_xp_smp_ops);
> +
> +struct resume_controller {
> + u32 resume_control;
> + u32 resume_boot_addr;
> +};
> +
> +static const struct resume_controller mv98dx3336_resume_controller = {
> + .resume_control = 0x08,
> + .resume_boot_addr = 0x04,
> +};
> +
> +static const struct of_device_id of_mv98dx3236_resume_table[] = {
> + {
> + .compatible = "marvell,98dx3336-resume-ctrl",
> + .data = &mv98dx3336_resume_controller,
> + },
> + { /* end of list */ },
> +};
Do you expect to have other SoC which use the same logical but with
register at a different place?
Else you can just remove the resume_controller struct and use the address
(using define) directly in the mv98dx3236_resume_set_cpu_boot_addr
function.
> +
> +static int mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
> +{
> + const struct of_device_id *match;
> + struct device_node *np;
> + void __iomem *base;
> + const struct resume_controller *rc;
> +
> + WARN_ON(hw_cpu != 1);
> +
> + np = of_find_matching_node_and_match(NULL, of_mv98dx3236_resume_table,
> + &match);
> + if (!np)
> + return -ENODEV;
> +
> + base = of_io_request_and_map(np, 0, of_node_full_name(np));
> + rc = match->data;
> + of_node_put(np);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + writel(0, base + rc->resume_control);
> + writel(virt_to_phys(boot_addr), base + rc->resume_boot_addr);
> +
you should use iounmap() on base here, to free it.
Gregory
> + return 0;
> +}
> +
> +static int mv98dx3236_boot_secondary(unsigned int cpu, struct task_struct *idle)
> +{
> + int ret, hw_cpu;
> +
> + hw_cpu = cpu_logical_map(cpu);
> + set_secondary_cpu_clock(hw_cpu);
> + mv98dx3236_resume_set_cpu_boot_addr(hw_cpu,
> + armada_xp_secondary_startup);
> +
> + /*
> + * This is needed to wake up CPUs in the offline state after
> + * using CPU hotplug.
> + */
> + arch_send_wakeup_ipi_mask(cpumask_of(cpu));
> +
> + /*
> + * This is needed to take secondary CPUs out of reset on the
> + * initial boot.
> + */
> + ret = mvebu_cpu_reset_deassert(hw_cpu);
> + if (ret) {
> + pr_warn("unable to boot CPU: %d\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct smp_operations mv98dx3236_smp_ops __initconst = {
> + .smp_init_cpus = armada_xp_smp_init_cpus,
> + .smp_prepare_cpus = armada_xp_smp_prepare_cpus,
> + .smp_boot_secondary = mv98dx3236_boot_secondary,
> + .smp_secondary_init = armada_xp_secondary_init,
> +#ifdef CONFIG_HOTPLUG_CPU
> + .cpu_die = armada_xp_cpu_die,
> + .cpu_kill = armada_xp_cpu_kill,
> +#endif
> +};
> +
> +CPU_METHOD_OF_DECLARE(mv98dx3236_smp, "marvell,98dx3236-smp",
> + &mv98dx3236_smp_ops);
> --
> 2.11.0.24.ge6920cf
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCHv5 2/5] arm: mvebu: support for SMP on 98DX3336 SoC
@ 2017-01-27 14:06 ` Gregory CLEMENT
0 siblings, 0 replies; 49+ messages in thread
From: Gregory CLEMENT @ 2017-01-27 14:06 UTC (permalink / raw)
To: Chris Packham
Cc: Mark Rutland, Andrew Lunn, Jason Cooper, devicetree, linux,
linux-kernel, Rob Herring, linux-arm-kernel,
Sebastian Hesselbarth
Hi Chris,
On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
> Compared to the armada-xp the 98DX3336 uses different registers to set
> the boot address for the secondary CPU so a new enable-method is needed.
> This will only work if the machine definition doesn't define an overall
> smp_ops because there is not currently a way of overriding this from the
> device tree if it is set in the machine definition.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
>
> Notes:
> Changes in v2:
> - Document new enable-method value
> - Correct some references from 98DX4521 to 98DX3236
> Changes in v3:
> - Simplify mv98dx3236_resume_init by using of_io_request_and_map()
> Changes in v4:
> - integrate changes into platsmp.c instead of new init call
> - avoid duplicated code.
> - fix error return
> - Collect ack from Rob
> Changes in v5:
> - Remove useless casts (thanks to Stephen Boyd)
>
> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> .../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 16 ++++
> arch/arm/mach-mvebu/platsmp.c | 86 ++++++++++++++++++++++
> 3 files changed, 103 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index a1bcfeed5f24..3c2fd72d0bf9 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -202,6 +202,7 @@ nodes to be present and contain the properties described below.
> "marvell,armada-380-smp"
> "marvell,armada-390-smp"
> "marvell,armada-xp-smp"
> + "marvell,98dx3236-smp"
> "mediatek,mt6589-smp"
> "mediatek,mt81xx-tz-smp"
> "qcom,gcc-msm8660"
> diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> new file mode 100644
> index 000000000000..26eb9d3aa630
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> @@ -0,0 +1,16 @@
> +Resume Control
> +--------------
> +Available on Marvell SOCs: 98DX3336 and 98DX4251
> +
> +Required properties:
> +
> +- compatible: must be "marvell,98dx3336-resume-ctrl"
> +
> +- reg: Should contain resume control registers location and length
> +
> +Example:
> +
> +resume@20980 {
> + compatible = "marvell,98dx3336-resume-ctrl";
> + reg = <0x20980 0x10>;
> +};
> diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
> index 46c742d3bd41..a5b464497e1a 100644
> --- a/arch/arm/mach-mvebu/platsmp.c
> +++ b/arch/arm/mach-mvebu/platsmp.c
> @@ -184,3 +184,89 @@ const struct smp_operations armada_xp_smp_ops __initconst = {
>
> CPU_METHOD_OF_DECLARE(armada_xp_smp, "marvell,armada-xp-smp",
> &armada_xp_smp_ops);
> +
> +struct resume_controller {
> + u32 resume_control;
> + u32 resume_boot_addr;
> +};
> +
> +static const struct resume_controller mv98dx3336_resume_controller = {
> + .resume_control = 0x08,
> + .resume_boot_addr = 0x04,
> +};
> +
> +static const struct of_device_id of_mv98dx3236_resume_table[] = {
> + {
> + .compatible = "marvell,98dx3336-resume-ctrl",
> + .data = &mv98dx3336_resume_controller,
> + },
> + { /* end of list */ },
> +};
Do you expect to have other SoC which use the same logical but with
register at a different place?
Else you can just remove the resume_controller struct and use the address
(using define) directly in the mv98dx3236_resume_set_cpu_boot_addr
function.
> +
> +static int mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
> +{
> + const struct of_device_id *match;
> + struct device_node *np;
> + void __iomem *base;
> + const struct resume_controller *rc;
> +
> + WARN_ON(hw_cpu != 1);
> +
> + np = of_find_matching_node_and_match(NULL, of_mv98dx3236_resume_table,
> + &match);
> + if (!np)
> + return -ENODEV;
> +
> + base = of_io_request_and_map(np, 0, of_node_full_name(np));
> + rc = match->data;
> + of_node_put(np);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + writel(0, base + rc->resume_control);
> + writel(virt_to_phys(boot_addr), base + rc->resume_boot_addr);
> +
you should use iounmap() on base here, to free it.
Gregory
> + return 0;
> +}
> +
> +static int mv98dx3236_boot_secondary(unsigned int cpu, struct task_struct *idle)
> +{
> + int ret, hw_cpu;
> +
> + hw_cpu = cpu_logical_map(cpu);
> + set_secondary_cpu_clock(hw_cpu);
> + mv98dx3236_resume_set_cpu_boot_addr(hw_cpu,
> + armada_xp_secondary_startup);
> +
> + /*
> + * This is needed to wake up CPUs in the offline state after
> + * using CPU hotplug.
> + */
> + arch_send_wakeup_ipi_mask(cpumask_of(cpu));
> +
> + /*
> + * This is needed to take secondary CPUs out of reset on the
> + * initial boot.
> + */
> + ret = mvebu_cpu_reset_deassert(hw_cpu);
> + if (ret) {
> + pr_warn("unable to boot CPU: %d\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct smp_operations mv98dx3236_smp_ops __initconst = {
> + .smp_init_cpus = armada_xp_smp_init_cpus,
> + .smp_prepare_cpus = armada_xp_smp_prepare_cpus,
> + .smp_boot_secondary = mv98dx3236_boot_secondary,
> + .smp_secondary_init = armada_xp_secondary_init,
> +#ifdef CONFIG_HOTPLUG_CPU
> + .cpu_die = armada_xp_cpu_die,
> + .cpu_kill = armada_xp_cpu_kill,
> +#endif
> +};
> +
> +CPU_METHOD_OF_DECLARE(mv98dx3236_smp, "marvell,98dx3236-smp",
> + &mv98dx3236_smp_ops);
> --
> 2.11.0.24.ge6920cf
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCHv5 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
2017-01-27 3:25 ` Chris Packham
@ 2017-01-27 3:25 ` Chris Packham
-1 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-27 3:25 UTC (permalink / raw)
To: linux, linux-arm-kernel
Cc: Kalyan Kinthada, Chris Packham, Linus Walleij, Rob Herring,
Mark Rutland, linux-gpio, devicetree, linux-kernel
From: Kalyan Kinthada <kalyan.kinthada@alliedtelesis.co.nz>
This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs
from Marvell.
Signed-off-by: Kalyan Kinthada <kalyan.kinthada@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Notes:
Changes in v2:
- include sdio support for the 98DX4251
Changes in v3:
- None
Changes in v4:
- Correct some discrepencies between binding and driver.
- Collect acks from Rob and Sebastian
Changes in v5:
- Update bindings to reflect "gpo" pins
- Use mvebu_mmio_mpp_ctrl instead of armada_xp_mpp_ctrl (note this is reliant
on changes queued in linux-pinctrl)
.../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++++
drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 156 +++++++++++++++++++++
2 files changed, 202 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
new file mode 100644
index 000000000000..97aef67ee769
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
@@ -0,0 +1,46 @@
+* Marvell 98dx3236 pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage
+
+Required properties:
+- compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
+- reg: register specifier of MPP registers
+
+This driver supports all 98dx3236, 98dx3336 and 98dx4251 variants
+
+name pins functions
+================================================================================
+mpp0 0 gpo, spi0(mosi), dev(ad8)
+mpp1 1 gpio, spi0(miso), dev(ad9)
+mpp2 2 gpo, spi0(sck), dev(ad10)
+mpp3 3 gpio, spi0(cs0), dev(ad11)
+mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
+mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
+mpp6 6 gpo, sd0(clk), dev(a2)
+mpp7 7 gpio, sd0(d0), dev(ale0)
+mpp8 8 gpio, sd0(d1), dev(ale1)
+mpp9 9 gpio, sd0(d2), dev(ready0)
+mpp10 10 gpio, sd0(d3), dev(ad12)
+mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13)
+mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14)
+mpp13 13 gpio, intr(out), dev(ad15)
+mpp14 14 gpio, i2c0(sck)
+mpp15 15 gpio, i2c0(sda)
+mpp16 16 gpo, dev(oe)
+mpp17 17 gpo, dev(clkout)
+mpp18 18 gpio, uart1(txd)
+mpp19 19 gpio, uart1(rxd), dev(rb)
+mpp20 20 gpo, dev(we0)
+mpp21 21 gpo, dev(ad0)
+mpp22 22 gpo, dev(ad1)
+mpp23 23 gpo, dev(ad2)
+mpp24 24 gpo, dev(ad3)
+mpp25 25 gpo, dev(ad4)
+mpp26 26 gpo, dev(ad5)
+mpp27 27 gpo, dev(ad6)
+mpp28 28 gpo, dev(ad7)
+mpp29 29 gpo, dev(a0)
+mpp30 30 gpo, dev(a1)
+mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
+mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
index 63e1bd506983..61cbc138703e 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
@@ -38,6 +38,10 @@ enum armada_xp_variant {
V_MV78460 = BIT(2),
V_MV78230_PLUS = (V_MV78230 | V_MV78260 | V_MV78460),
V_MV78260_PLUS = (V_MV78260 | V_MV78460),
+ V_98DX3236 = BIT(3),
+ V_98DX3336 = BIT(4),
+ V_98DX4251 = BIT(5),
+ V_98DX3236_PLUS = (V_98DX3236 | V_98DX3336 | V_98DX4251),
};
static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
@@ -349,6 +353,131 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
MPP_VAR_FUNCTION(0x1, "dev", "ad31", V_MV78260_PLUS)),
};
+static struct mvebu_mpp_mode mv98dx3236_mpp_modes[] = {
+ MPP_MODE(0,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "spi0", "mosi", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad8", V_98DX3236_PLUS)),
+ MPP_MODE(1,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)),
+ MPP_MODE(2,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "spi0", "sck", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)),
+ MPP_MODE(3,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "spi0", "cs0", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad11", V_98DX3236_PLUS)),
+ MPP_MODE(4,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "spi0", "cs1", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "cs0", V_98DX3236_PLUS)),
+ MPP_MODE(5,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251),
+ MPP_VAR_FUNCTION(0x4, "dev", "bootcs", V_98DX3236_PLUS)),
+ MPP_MODE(6,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251),
+ MPP_VAR_FUNCTION(0x4, "dev", "a2", V_98DX3236_PLUS)),
+ MPP_MODE(7,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "d0", V_98DX4251),
+ MPP_VAR_FUNCTION(0x4, "dev", "ale0", V_98DX3236_PLUS)),
+ MPP_MODE(8,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "d1", V_98DX4251),
+ MPP_VAR_FUNCTION(0x4, "dev", "ale1", V_98DX3236_PLUS)),
+ MPP_MODE(9,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "d2", V_98DX4251),
+ MPP_VAR_FUNCTION(0x4, "dev", "ready0", V_98DX3236_PLUS)),
+ MPP_MODE(10,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "d3", V_98DX4251),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad12", V_98DX3236_PLUS)),
+ MPP_MODE(11,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart1", "rxd", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x3, "uart0", "cts", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad13", V_98DX3236_PLUS)),
+ MPP_MODE(12,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart1", "txd", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x3, "uart0", "rts", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad14", V_98DX3236_PLUS)),
+ MPP_MODE(13,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "intr", "out", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad15", V_98DX3236_PLUS)),
+ MPP_MODE(14,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "i2c0", "sck", V_98DX3236_PLUS)),
+ MPP_MODE(15,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "i2c0", "sda", V_98DX3236_PLUS)),
+ MPP_MODE(16,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "oe", V_98DX3236_PLUS)),
+ MPP_MODE(17,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "clkout", V_98DX3236_PLUS)),
+ MPP_MODE(18,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)),
+ MPP_MODE(19,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "rb", V_98DX3236_PLUS)),
+ MPP_MODE(20,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)),
+ MPP_MODE(21,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad0", V_98DX3236_PLUS)),
+ MPP_MODE(22,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad1", V_98DX3236_PLUS)),
+ MPP_MODE(23,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad2", V_98DX3236_PLUS)),
+ MPP_MODE(24,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad3", V_98DX3236_PLUS)),
+ MPP_MODE(25,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad4", V_98DX3236_PLUS)),
+ MPP_MODE(26,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad5", V_98DX3236_PLUS)),
+ MPP_MODE(27,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad6", V_98DX3236_PLUS)),
+ MPP_MODE(28,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad7", V_98DX3236_PLUS)),
+ MPP_MODE(29,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "a0", V_98DX3236_PLUS)),
+ MPP_MODE(30,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "a1", V_98DX3236_PLUS)),
+ MPP_MODE(31,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "slv_smi", "mdc", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "we1", V_98DX3236_PLUS)),
+ MPP_MODE(32,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "slv_smi", "mdio", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x3, "smi", "mdio", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "cs1", V_98DX3236_PLUS)),
+};
+
static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info;
static const struct of_device_id armada_xp_pinctrl_of_match[] = {
@@ -364,6 +493,14 @@ static const struct of_device_id armada_xp_pinctrl_of_match[] = {
.compatible = "marvell,mv78460-pinctrl",
.data = (void *) V_MV78460,
},
+ {
+ .compatible = "marvell,98dx3236-pinctrl",
+ .data = (void *) V_98DX3236,
+ },
+ {
+ .compatible = "marvell,98dx4251-pinctrl",
+ .data = (void *) V_98DX4251,
+ },
{ },
};
@@ -396,6 +533,14 @@ static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = {
MPP_GPIO_RANGE(2, 64, 64, 3),
};
+static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = {
+ MPP_FUNC_CTRL(0, 32, NULL, mvebu_mmio_mpp_ctrl),
+};
+
+static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 32),
+};
+
static int armada_xp_pinctrl_suspend(struct platform_device *pdev,
pm_message_t state)
{
@@ -471,6 +616,17 @@ static int armada_xp_pinctrl_probe(struct platform_device *pdev)
soc->gpioranges = mv78460_mpp_gpio_ranges;
soc->ngpioranges = ARRAY_SIZE(mv78460_mpp_gpio_ranges);
break;
+ case V_98DX3236:
+ case V_98DX3336:
+ case V_98DX4251:
+ /* fall-through */
+ soc->controls = mv98dx3236_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv98dx3236_mpp_controls);
+ soc->modes = mv98dx3236_mpp_modes;
+ soc->nmodes = mv98dx3236_mpp_controls[0].npins;
+ soc->gpioranges = mv98dx3236_mpp_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv98dx3236_mpp_gpio_ranges);
+ break;
}
nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG);
--
2.11.0.24.ge6920cf
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCHv5 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
@ 2017-01-27 3:25 ` Chris Packham
0 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-27 3:25 UTC (permalink / raw)
To: linux-arm-kernel
From: Kalyan Kinthada <kalyan.kinthada@alliedtelesis.co.nz>
This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs
from Marvell.
Signed-off-by: Kalyan Kinthada <kalyan.kinthada@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Notes:
Changes in v2:
- include sdio support for the 98DX4251
Changes in v3:
- None
Changes in v4:
- Correct some discrepencies between binding and driver.
- Collect acks from Rob and Sebastian
Changes in v5:
- Update bindings to reflect "gpo" pins
- Use mvebu_mmio_mpp_ctrl instead of armada_xp_mpp_ctrl (note this is reliant
on changes queued in linux-pinctrl)
.../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++++
drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 156 +++++++++++++++++++++
2 files changed, 202 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
new file mode 100644
index 000000000000..97aef67ee769
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
@@ -0,0 +1,46 @@
+* Marvell 98dx3236 pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage
+
+Required properties:
+- compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
+- reg: register specifier of MPP registers
+
+This driver supports all 98dx3236, 98dx3336 and 98dx4251 variants
+
+name pins functions
+================================================================================
+mpp0 0 gpo, spi0(mosi), dev(ad8)
+mpp1 1 gpio, spi0(miso), dev(ad9)
+mpp2 2 gpo, spi0(sck), dev(ad10)
+mpp3 3 gpio, spi0(cs0), dev(ad11)
+mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
+mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
+mpp6 6 gpo, sd0(clk), dev(a2)
+mpp7 7 gpio, sd0(d0), dev(ale0)
+mpp8 8 gpio, sd0(d1), dev(ale1)
+mpp9 9 gpio, sd0(d2), dev(ready0)
+mpp10 10 gpio, sd0(d3), dev(ad12)
+mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13)
+mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14)
+mpp13 13 gpio, intr(out), dev(ad15)
+mpp14 14 gpio, i2c0(sck)
+mpp15 15 gpio, i2c0(sda)
+mpp16 16 gpo, dev(oe)
+mpp17 17 gpo, dev(clkout)
+mpp18 18 gpio, uart1(txd)
+mpp19 19 gpio, uart1(rxd), dev(rb)
+mpp20 20 gpo, dev(we0)
+mpp21 21 gpo, dev(ad0)
+mpp22 22 gpo, dev(ad1)
+mpp23 23 gpo, dev(ad2)
+mpp24 24 gpo, dev(ad3)
+mpp25 25 gpo, dev(ad4)
+mpp26 26 gpo, dev(ad5)
+mpp27 27 gpo, dev(ad6)
+mpp28 28 gpo, dev(ad7)
+mpp29 29 gpo, dev(a0)
+mpp30 30 gpo, dev(a1)
+mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
+mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
index 63e1bd506983..61cbc138703e 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
@@ -38,6 +38,10 @@ enum armada_xp_variant {
V_MV78460 = BIT(2),
V_MV78230_PLUS = (V_MV78230 | V_MV78260 | V_MV78460),
V_MV78260_PLUS = (V_MV78260 | V_MV78460),
+ V_98DX3236 = BIT(3),
+ V_98DX3336 = BIT(4),
+ V_98DX4251 = BIT(5),
+ V_98DX3236_PLUS = (V_98DX3236 | V_98DX3336 | V_98DX4251),
};
static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
@@ -349,6 +353,131 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
MPP_VAR_FUNCTION(0x1, "dev", "ad31", V_MV78260_PLUS)),
};
+static struct mvebu_mpp_mode mv98dx3236_mpp_modes[] = {
+ MPP_MODE(0,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "spi0", "mosi", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad8", V_98DX3236_PLUS)),
+ MPP_MODE(1,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)),
+ MPP_MODE(2,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "spi0", "sck", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)),
+ MPP_MODE(3,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "spi0", "cs0", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad11", V_98DX3236_PLUS)),
+ MPP_MODE(4,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "spi0", "cs1", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "cs0", V_98DX3236_PLUS)),
+ MPP_MODE(5,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251),
+ MPP_VAR_FUNCTION(0x4, "dev", "bootcs", V_98DX3236_PLUS)),
+ MPP_MODE(6,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251),
+ MPP_VAR_FUNCTION(0x4, "dev", "a2", V_98DX3236_PLUS)),
+ MPP_MODE(7,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "d0", V_98DX4251),
+ MPP_VAR_FUNCTION(0x4, "dev", "ale0", V_98DX3236_PLUS)),
+ MPP_MODE(8,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "d1", V_98DX4251),
+ MPP_VAR_FUNCTION(0x4, "dev", "ale1", V_98DX3236_PLUS)),
+ MPP_MODE(9,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "d2", V_98DX4251),
+ MPP_VAR_FUNCTION(0x4, "dev", "ready0", V_98DX3236_PLUS)),
+ MPP_MODE(10,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "sd0", "d3", V_98DX4251),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad12", V_98DX3236_PLUS)),
+ MPP_MODE(11,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart1", "rxd", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x3, "uart0", "cts", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad13", V_98DX3236_PLUS)),
+ MPP_MODE(12,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x2, "uart1", "txd", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x3, "uart0", "rts", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad14", V_98DX3236_PLUS)),
+ MPP_MODE(13,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "intr", "out", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "ad15", V_98DX3236_PLUS)),
+ MPP_MODE(14,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "i2c0", "sck", V_98DX3236_PLUS)),
+ MPP_MODE(15,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "i2c0", "sda", V_98DX3236_PLUS)),
+ MPP_MODE(16,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "oe", V_98DX3236_PLUS)),
+ MPP_MODE(17,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "clkout", V_98DX3236_PLUS)),
+ MPP_MODE(18,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)),
+ MPP_MODE(19,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "rb", V_98DX3236_PLUS)),
+ MPP_MODE(20,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)),
+ MPP_MODE(21,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad0", V_98DX3236_PLUS)),
+ MPP_MODE(22,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad1", V_98DX3236_PLUS)),
+ MPP_MODE(23,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad2", V_98DX3236_PLUS)),
+ MPP_MODE(24,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad3", V_98DX3236_PLUS)),
+ MPP_MODE(25,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad4", V_98DX3236_PLUS)),
+ MPP_MODE(26,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad5", V_98DX3236_PLUS)),
+ MPP_MODE(27,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad6", V_98DX3236_PLUS)),
+ MPP_MODE(28,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "ad7", V_98DX3236_PLUS)),
+ MPP_MODE(29,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "a0", V_98DX3236_PLUS)),
+ MPP_MODE(30,
+ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "dev", "a1", V_98DX3236_PLUS)),
+ MPP_MODE(31,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "slv_smi", "mdc", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "we1", V_98DX3236_PLUS)),
+ MPP_MODE(32,
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x1, "slv_smi", "mdio", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x3, "smi", "mdio", V_98DX3236_PLUS),
+ MPP_VAR_FUNCTION(0x4, "dev", "cs1", V_98DX3236_PLUS)),
+};
+
static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info;
static const struct of_device_id armada_xp_pinctrl_of_match[] = {
@@ -364,6 +493,14 @@ static const struct of_device_id armada_xp_pinctrl_of_match[] = {
.compatible = "marvell,mv78460-pinctrl",
.data = (void *) V_MV78460,
},
+ {
+ .compatible = "marvell,98dx3236-pinctrl",
+ .data = (void *) V_98DX3236,
+ },
+ {
+ .compatible = "marvell,98dx4251-pinctrl",
+ .data = (void *) V_98DX4251,
+ },
{ },
};
@@ -396,6 +533,14 @@ static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = {
MPP_GPIO_RANGE(2, 64, 64, 3),
};
+static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = {
+ MPP_FUNC_CTRL(0, 32, NULL, mvebu_mmio_mpp_ctrl),
+};
+
+static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 32),
+};
+
static int armada_xp_pinctrl_suspend(struct platform_device *pdev,
pm_message_t state)
{
@@ -471,6 +616,17 @@ static int armada_xp_pinctrl_probe(struct platform_device *pdev)
soc->gpioranges = mv78460_mpp_gpio_ranges;
soc->ngpioranges = ARRAY_SIZE(mv78460_mpp_gpio_ranges);
break;
+ case V_98DX3236:
+ case V_98DX3336:
+ case V_98DX4251:
+ /* fall-through */
+ soc->controls = mv98dx3236_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv98dx3236_mpp_controls);
+ soc->modes = mv98dx3236_mpp_modes;
+ soc->nmodes = mv98dx3236_mpp_controls[0].npins;
+ soc->gpioranges = mv98dx3236_mpp_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv98dx3236_mpp_gpio_ranges);
+ break;
}
nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG);
--
2.11.0.24.ge6920cf
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCHv5 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs
@ 2017-01-27 3:25 ` Chris Packham
0 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-27 3:25 UTC (permalink / raw)
To: linux, linux-arm-kernel
Cc: Chris Packham, Rob Herring, Mark Rutland, Jason Cooper,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth, devicetree,
linux-kernel, netdev
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
with integrated CPUs. They are similar to the Armada XP SoCs but have
different I/O interfaces.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
---
Notes:
Changes in v2:
- Update devicetree binding documentation to reflect that 98DX3336 and
984251 are supersets of 98DX3236.
- disable crypto block
- disable sdio for 98DX3236, enable for 98DX4251
Changes in v3:
- fix typo 4521 -> 4251
- document prestera bindings
- rework corediv-clock binding
- add label to packet processor node
- add new compatible string for DFX server
Changes in v4:
- Collect ack from Rob
Changes in v5:
- Fixup license text. Add labels to nodes.
.../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ++
.../devicetree/bindings/net/marvell,prestera.txt | 50 ++++
arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 254 +++++++++++++++++++++
arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 76 ++++++
arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 90 ++++++++
5 files changed, 493 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
create mode 100644 Documentation/devicetree/bindings/net/marvell,prestera.txt
create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
new file mode 100644
index 000000000000..64e8c73fc5ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
@@ -0,0 +1,23 @@
+Marvell 98DX3236, 98DX3336 and 98DX4251 Platforms Device Tree Bindings
+----------------------------------------------------------------------
+
+Boards with a SoC of the Marvell 98DX3236, 98DX3336 and 98DX4251 families
+shall have the following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp-98dx3236"
+
+In addition, boards using the Marvell 98DX3336 SoC shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp-98dx3336"
+
+In addition, boards using the Marvell 98DX4251 SoC shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp-98dx4251"
diff --git a/Documentation/devicetree/bindings/net/marvell,prestera.txt b/Documentation/devicetree/bindings/net/marvell,prestera.txt
new file mode 100644
index 000000000000..5fbab29718e8
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/marvell,prestera.txt
@@ -0,0 +1,50 @@
+Marvell Prestera Switch Chip bindings
+-------------------------------------
+
+Required properties:
+- compatible: one of the following
+ "marvell,prestera-98dx3236",
+ "marvell,prestera-98dx3336",
+ "marvell,prestera-98dx4251",
+- reg: address and length of the register set for the device.
+- interrupts: interrupt for the device
+
+Optional properties:
+- dfx: phandle reference to the "DFX Server" node
+
+Example:
+
+switch {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
+
+ packet-processor@0 {
+ compatible = "marvell,prestera-98dx3236";
+ reg = <0 0x4000000>;
+ interrupts = <33>, <34>, <35>;
+ dfx = <&dfx>;
+ };
+};
+
+DFX Server bindings
+-------------------
+
+Required properties:
+- compatible: must be "marvell,dfx-server"
+- reg: address and length of the register set for the device.
+
+Example:
+
+dfx-registers {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
+
+ dfx: dfx@0 {
+ compatible = "marvell,dfx-server";
+ reg = <0 0x100000>;
+ };
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
new file mode 100644
index 000000000000..9461128fae24
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -0,0 +1,254 @@
+/*
+ * Device Tree Include file for Marvell 98dx3236 family SoC
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Contains definitions specific to the 98dx3236 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+#include "armada-xp.dtsi"
+
+/ {
+ model = "Marvell 98DX3236 SoC";
+ compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "marvell,98dx3236-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <0>;
+ clocks = <&cpuclk 0>;
+ clock-latency = <1000000>;
+ };
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
+
+ /*
+ * 98DX3236 has 1 x1 PCIe unit Gen2.0
+ */
+ pciec: pcie-controller@82000000 {
+ compatible = "marvell,armada-xp-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ msi-parent = <&mpic>;
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
+ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;
+
+ pcie1: pcie@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 58>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+ };
+
+ internal-regs {
+ coreclk: mvebu-sar@18230 {
+ compatible = "marvell,mv98dx3236-core-clock";
+ };
+
+ cpuclk: clock-complex@18700 {
+ compatible = "marvell,mv98dx3236-cpu-clock";
+ };
+
+ corediv-clock@18740 {
+ status = "disabled";
+ };
+
+ xor@60900 {
+ status = "disabled";
+ };
+
+ crypto@90000 {
+ status = "disabled";
+ };
+
+ xor@f0900 {
+ status = "disabled";
+ };
+
+ xor@f0800 {
+ compatible = "marvell,orion-xor";
+ reg = <0xf0800 0x100
+ 0xf0a00 0x100>;
+ clocks = <&gateclk 22>;
+ status = "okay";
+
+ xor10 {
+ interrupts = <51>;
+ dmacap,memcpy;
+ dmacap,xor;
+ };
+ xor11 {
+ interrupts = <52>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
+ };
+ };
+
+ gpio0: gpio@18100 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18100 0x40>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <82>, <83>, <84>, <85>;
+ };
+
+ /* does not exist */
+ gpio1: gpio@18140 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18140 0x40>;
+ status = "disabled";
+ };
+
+ gpio2: gpio@18180 { /* rework some properties */
+ compatible = "marvell,orion-gpio";
+ reg = <0x18180 0x40>;
+ ngpios = <1>; /* only gpio #32 */
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <87>;
+ };
+
+ nand: nand@d0000 {
+ clocks = <&dfx_coredivclk 0>;
+ };
+ };
+
+ dfxr: dfx-registers@ac000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
+
+ dfx_coredivclk: corediv-clock@f8268 {
+ compatible = "marvell,mv98dx3236-corediv-clock";
+ reg = <0xf8268 0xc>;
+ #clock-cells = <1>;
+ clocks = <&mainpll>;
+ clock-output-names = "nand";
+ };
+
+ dfx: dfx@0 {
+ compatible = "marvell,dfx-server";
+ reg = <0 0x100000>;
+ };
+ };
+
+ switch: switch@a8000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
+
+ pp0: packet-processor@0 {
+ compatible = "marvell,prestera-98dx3236";
+ reg = <0 0x4000000>;
+ interrupts = <33>, <34>, <35>;
+ dfx = <&dfx>;
+ };
+ };
+ };
+};
+
+&pinctrl {
+ compatible = "marvell,98dx3236-pinctrl";
+
+ spi0_pins: spi0-pins {
+ marvell,pins = "mpp0", "mpp1",
+ "mpp2", "mpp3";
+ marvell,function = "spi0";
+ };
+};
+
+&sdio {
+ status = "disabled";
+};
+
+&crypto_sram0 {
+ status = "disabled";
+};
+
+&crypto_sram1 {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
new file mode 100644
index 000000000000..e1580afdc260
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
@@ -0,0 +1,76 @@
+/*
+ * Device Tree Include file for Marvell 98dx3336 family SoC
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Contains definitions specific to the 98dx3236 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+#include "armada-xp-98dx3236.dtsi"
+
+/ {
+ model = "Marvell 98DX3336 SoC";
+ compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ cpus {
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <1>;
+ clocks = <&cpuclk 1>;
+ clock-latency = <1000000>;
+ };
+ };
+
+ soc {
+ internal-regs {
+ resume@20980 {
+ compatible = "marvell,98dx3336-resume-ctrl";
+ reg = <0x20980 0x10>;
+ };
+ };
+ };
+};
+
+&pp0 {
+ compatible = "marvell,prestera-98dx3336";
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
new file mode 100644
index 000000000000..4b0533a4ccb7
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
@@ -0,0 +1,90 @@
+/*
+ * Device Tree Include file for Marvell 98dx4521 family SoC
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Contains definitions specific to the 98dx4521 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+#include "armada-xp-98dx3236.dtsi"
+
+/ {
+ model = "Marvell 98DX4251 SoC";
+ compatible = "marvell,armadaxp-98dx4521", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ cpus {
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <1>;
+ clocks = <&cpuclk 1>;
+ clock-latency = <1000000>;
+ };
+ };
+
+ soc {
+ internal-regs {
+ resume@20980 {
+ compatible = "marvell,98dx3336-resume-ctrl";
+ reg = <0x20980 0x10>;
+ };
+ };
+ };
+};
+
+&sdio {
+ status = "okay";
+};
+
+&pinctrl {
+ compatible = "marvell,98dx4251-pinctrl";
+
+ sdio_pins: sdio-pins {
+ marvell,pins = "mpp5", "mpp6", "mpp7",
+ "mpp8", "mpp9", "mpp10";
+ marvell,function = "sd0";
+ };
+};
+
+&pp0 {
+ compatible = "marvell,prestera-98dx4251";
+};
--
2.11.0.24.ge6920cf
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCHv5 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs
@ 2017-01-27 3:25 ` Chris Packham
0 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-27 3:25 UTC (permalink / raw)
To: linux-arm-kernel
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
with integrated CPUs. They are similar to the Armada XP SoCs but have
different I/O interfaces.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
---
Notes:
Changes in v2:
- Update devicetree binding documentation to reflect that 98DX3336 and
984251 are supersets of 98DX3236.
- disable crypto block
- disable sdio for 98DX3236, enable for 98DX4251
Changes in v3:
- fix typo 4521 -> 4251
- document prestera bindings
- rework corediv-clock binding
- add label to packet processor node
- add new compatible string for DFX server
Changes in v4:
- Collect ack from Rob
Changes in v5:
- Fixup license text. Add labels to nodes.
.../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ++
.../devicetree/bindings/net/marvell,prestera.txt | 50 ++++
arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 254 +++++++++++++++++++++
arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 76 ++++++
arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 90 ++++++++
5 files changed, 493 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
create mode 100644 Documentation/devicetree/bindings/net/marvell,prestera.txt
create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
new file mode 100644
index 000000000000..64e8c73fc5ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
@@ -0,0 +1,23 @@
+Marvell 98DX3236, 98DX3336 and 98DX4251 Platforms Device Tree Bindings
+----------------------------------------------------------------------
+
+Boards with a SoC of the Marvell 98DX3236, 98DX3336 and 98DX4251 families
+shall have the following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp-98dx3236"
+
+In addition, boards using the Marvell 98DX3336 SoC shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp-98dx3336"
+
+In addition, boards using the Marvell 98DX4251 SoC shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp-98dx4251"
diff --git a/Documentation/devicetree/bindings/net/marvell,prestera.txt b/Documentation/devicetree/bindings/net/marvell,prestera.txt
new file mode 100644
index 000000000000..5fbab29718e8
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/marvell,prestera.txt
@@ -0,0 +1,50 @@
+Marvell Prestera Switch Chip bindings
+-------------------------------------
+
+Required properties:
+- compatible: one of the following
+ "marvell,prestera-98dx3236",
+ "marvell,prestera-98dx3336",
+ "marvell,prestera-98dx4251",
+- reg: address and length of the register set for the device.
+- interrupts: interrupt for the device
+
+Optional properties:
+- dfx: phandle reference to the "DFX Server" node
+
+Example:
+
+switch {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
+
+ packet-processor at 0 {
+ compatible = "marvell,prestera-98dx3236";
+ reg = <0 0x4000000>;
+ interrupts = <33>, <34>, <35>;
+ dfx = <&dfx>;
+ };
+};
+
+DFX Server bindings
+-------------------
+
+Required properties:
+- compatible: must be "marvell,dfx-server"
+- reg: address and length of the register set for the device.
+
+Example:
+
+dfx-registers {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
+
+ dfx: dfx at 0 {
+ compatible = "marvell,dfx-server";
+ reg = <0 0x100000>;
+ };
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
new file mode 100644
index 000000000000..9461128fae24
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -0,0 +1,254 @@
+/*
+ * Device Tree Include file for Marvell 98dx3236 family SoC
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Contains definitions specific to the 98dx3236 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+#include "armada-xp.dtsi"
+
+/ {
+ model = "Marvell 98DX3236 SoC";
+ compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "marvell,98dx3236-smp";
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <0>;
+ clocks = <&cpuclk 0>;
+ clock-latency = <1000000>;
+ };
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
+
+ /*
+ * 98DX3236 has 1 x1 PCIe unit Gen2.0
+ */
+ pciec: pcie-controller at 82000000 {
+ compatible = "marvell,armada-xp-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ msi-parent = <&mpic>;
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
+ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;
+
+ pcie1: pcie at 1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 58>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+ };
+
+ internal-regs {
+ coreclk: mvebu-sar at 18230 {
+ compatible = "marvell,mv98dx3236-core-clock";
+ };
+
+ cpuclk: clock-complex at 18700 {
+ compatible = "marvell,mv98dx3236-cpu-clock";
+ };
+
+ corediv-clock at 18740 {
+ status = "disabled";
+ };
+
+ xor at 60900 {
+ status = "disabled";
+ };
+
+ crypto at 90000 {
+ status = "disabled";
+ };
+
+ xor at f0900 {
+ status = "disabled";
+ };
+
+ xor at f0800 {
+ compatible = "marvell,orion-xor";
+ reg = <0xf0800 0x100
+ 0xf0a00 0x100>;
+ clocks = <&gateclk 22>;
+ status = "okay";
+
+ xor10 {
+ interrupts = <51>;
+ dmacap,memcpy;
+ dmacap,xor;
+ };
+ xor11 {
+ interrupts = <52>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
+ };
+ };
+
+ gpio0: gpio at 18100 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18100 0x40>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <82>, <83>, <84>, <85>;
+ };
+
+ /* does not exist */
+ gpio1: gpio at 18140 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18140 0x40>;
+ status = "disabled";
+ };
+
+ gpio2: gpio at 18180 { /* rework some properties */
+ compatible = "marvell,orion-gpio";
+ reg = <0x18180 0x40>;
+ ngpios = <1>; /* only gpio #32 */
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <87>;
+ };
+
+ nand: nand at d0000 {
+ clocks = <&dfx_coredivclk 0>;
+ };
+ };
+
+ dfxr: dfx-registers at ac000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
+
+ dfx_coredivclk: corediv-clock at f8268 {
+ compatible = "marvell,mv98dx3236-corediv-clock";
+ reg = <0xf8268 0xc>;
+ #clock-cells = <1>;
+ clocks = <&mainpll>;
+ clock-output-names = "nand";
+ };
+
+ dfx: dfx at 0 {
+ compatible = "marvell,dfx-server";
+ reg = <0 0x100000>;
+ };
+ };
+
+ switch: switch at a8000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
+
+ pp0: packet-processor at 0 {
+ compatible = "marvell,prestera-98dx3236";
+ reg = <0 0x4000000>;
+ interrupts = <33>, <34>, <35>;
+ dfx = <&dfx>;
+ };
+ };
+ };
+};
+
+&pinctrl {
+ compatible = "marvell,98dx3236-pinctrl";
+
+ spi0_pins: spi0-pins {
+ marvell,pins = "mpp0", "mpp1",
+ "mpp2", "mpp3";
+ marvell,function = "spi0";
+ };
+};
+
+&sdio {
+ status = "disabled";
+};
+
+&crypto_sram0 {
+ status = "disabled";
+};
+
+&crypto_sram1 {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
new file mode 100644
index 000000000000..e1580afdc260
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
@@ -0,0 +1,76 @@
+/*
+ * Device Tree Include file for Marvell 98dx3336 family SoC
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Contains definitions specific to the 98dx3236 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+#include "armada-xp-98dx3236.dtsi"
+
+/ {
+ model = "Marvell 98DX3336 SoC";
+ compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ cpus {
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <1>;
+ clocks = <&cpuclk 1>;
+ clock-latency = <1000000>;
+ };
+ };
+
+ soc {
+ internal-regs {
+ resume at 20980 {
+ compatible = "marvell,98dx3336-resume-ctrl";
+ reg = <0x20980 0x10>;
+ };
+ };
+ };
+};
+
+&pp0 {
+ compatible = "marvell,prestera-98dx3336";
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
new file mode 100644
index 000000000000..4b0533a4ccb7
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
@@ -0,0 +1,90 @@
+/*
+ * Device Tree Include file for Marvell 98dx4521 family SoC
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Contains definitions specific to the 98dx4521 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+#include "armada-xp-98dx3236.dtsi"
+
+/ {
+ model = "Marvell 98DX4251 SoC";
+ compatible = "marvell,armadaxp-98dx4521", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ cpus {
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <1>;
+ clocks = <&cpuclk 1>;
+ clock-latency = <1000000>;
+ };
+ };
+
+ soc {
+ internal-regs {
+ resume at 20980 {
+ compatible = "marvell,98dx3336-resume-ctrl";
+ reg = <0x20980 0x10>;
+ };
+ };
+ };
+};
+
+&sdio {
+ status = "okay";
+};
+
+&pinctrl {
+ compatible = "marvell,98dx4251-pinctrl";
+
+ sdio_pins: sdio-pins {
+ marvell,pins = "mpp5", "mpp6", "mpp7",
+ "mpp8", "mpp9", "mpp10";
+ marvell,function = "sd0";
+ };
+};
+
+&pp0 {
+ compatible = "marvell,prestera-98dx4251";
+};
--
2.11.0.24.ge6920cf
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCHv5 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs
@ 2017-01-27 3:25 ` Chris Packham
0 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-27 3:25 UTC (permalink / raw)
To: linux-I+IVW8TIWO2tmTQ+vhA3Yw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Chris Packham, Rob Herring, Mark Rutland, Jason Cooper,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
netdev-u79uwXL29TY76Z2rM5mHXA
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
with integrated CPUs. They are similar to the Armada XP SoCs but have
different I/O interfaces.
Signed-off-by: Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
Notes:
Changes in v2:
- Update devicetree binding documentation to reflect that 98DX3336 and
984251 are supersets of 98DX3236.
- disable crypto block
- disable sdio for 98DX3236, enable for 98DX4251
Changes in v3:
- fix typo 4521 -> 4251
- document prestera bindings
- rework corediv-clock binding
- add label to packet processor node
- add new compatible string for DFX server
Changes in v4:
- Collect ack from Rob
Changes in v5:
- Fixup license text. Add labels to nodes.
.../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ++
.../devicetree/bindings/net/marvell,prestera.txt | 50 ++++
arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 254 +++++++++++++++++++++
arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 76 ++++++
arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 90 ++++++++
5 files changed, 493 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
create mode 100644 Documentation/devicetree/bindings/net/marvell,prestera.txt
create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
new file mode 100644
index 000000000000..64e8c73fc5ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
@@ -0,0 +1,23 @@
+Marvell 98DX3236, 98DX3336 and 98DX4251 Platforms Device Tree Bindings
+----------------------------------------------------------------------
+
+Boards with a SoC of the Marvell 98DX3236, 98DX3336 and 98DX4251 families
+shall have the following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp-98dx3236"
+
+In addition, boards using the Marvell 98DX3336 SoC shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp-98dx3336"
+
+In addition, boards using the Marvell 98DX4251 SoC shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp-98dx4251"
diff --git a/Documentation/devicetree/bindings/net/marvell,prestera.txt b/Documentation/devicetree/bindings/net/marvell,prestera.txt
new file mode 100644
index 000000000000..5fbab29718e8
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/marvell,prestera.txt
@@ -0,0 +1,50 @@
+Marvell Prestera Switch Chip bindings
+-------------------------------------
+
+Required properties:
+- compatible: one of the following
+ "marvell,prestera-98dx3236",
+ "marvell,prestera-98dx3336",
+ "marvell,prestera-98dx4251",
+- reg: address and length of the register set for the device.
+- interrupts: interrupt for the device
+
+Optional properties:
+- dfx: phandle reference to the "DFX Server" node
+
+Example:
+
+switch {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
+
+ packet-processor@0 {
+ compatible = "marvell,prestera-98dx3236";
+ reg = <0 0x4000000>;
+ interrupts = <33>, <34>, <35>;
+ dfx = <&dfx>;
+ };
+};
+
+DFX Server bindings
+-------------------
+
+Required properties:
+- compatible: must be "marvell,dfx-server"
+- reg: address and length of the register set for the device.
+
+Example:
+
+dfx-registers {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
+
+ dfx: dfx@0 {
+ compatible = "marvell,dfx-server";
+ reg = <0 0x100000>;
+ };
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
new file mode 100644
index 000000000000..9461128fae24
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -0,0 +1,254 @@
+/*
+ * Device Tree Include file for Marvell 98dx3236 family SoC
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Contains definitions specific to the 98dx3236 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+#include "armada-xp.dtsi"
+
+/ {
+ model = "Marvell 98DX3236 SoC";
+ compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "marvell,98dx3236-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <0>;
+ clocks = <&cpuclk 0>;
+ clock-latency = <1000000>;
+ };
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
+
+ /*
+ * 98DX3236 has 1 x1 PCIe unit Gen2.0
+ */
+ pciec: pcie-controller@82000000 {
+ compatible = "marvell,armada-xp-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ msi-parent = <&mpic>;
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
+ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;
+
+ pcie1: pcie@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 58>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+ };
+
+ internal-regs {
+ coreclk: mvebu-sar@18230 {
+ compatible = "marvell,mv98dx3236-core-clock";
+ };
+
+ cpuclk: clock-complex@18700 {
+ compatible = "marvell,mv98dx3236-cpu-clock";
+ };
+
+ corediv-clock@18740 {
+ status = "disabled";
+ };
+
+ xor@60900 {
+ status = "disabled";
+ };
+
+ crypto@90000 {
+ status = "disabled";
+ };
+
+ xor@f0900 {
+ status = "disabled";
+ };
+
+ xor@f0800 {
+ compatible = "marvell,orion-xor";
+ reg = <0xf0800 0x100
+ 0xf0a00 0x100>;
+ clocks = <&gateclk 22>;
+ status = "okay";
+
+ xor10 {
+ interrupts = <51>;
+ dmacap,memcpy;
+ dmacap,xor;
+ };
+ xor11 {
+ interrupts = <52>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
+ };
+ };
+
+ gpio0: gpio@18100 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18100 0x40>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <82>, <83>, <84>, <85>;
+ };
+
+ /* does not exist */
+ gpio1: gpio@18140 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18140 0x40>;
+ status = "disabled";
+ };
+
+ gpio2: gpio@18180 { /* rework some properties */
+ compatible = "marvell,orion-gpio";
+ reg = <0x18180 0x40>;
+ ngpios = <1>; /* only gpio #32 */
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <87>;
+ };
+
+ nand: nand@d0000 {
+ clocks = <&dfx_coredivclk 0>;
+ };
+ };
+
+ dfxr: dfx-registers@ac000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
+
+ dfx_coredivclk: corediv-clock@f8268 {
+ compatible = "marvell,mv98dx3236-corediv-clock";
+ reg = <0xf8268 0xc>;
+ #clock-cells = <1>;
+ clocks = <&mainpll>;
+ clock-output-names = "nand";
+ };
+
+ dfx: dfx@0 {
+ compatible = "marvell,dfx-server";
+ reg = <0 0x100000>;
+ };
+ };
+
+ switch: switch@a8000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
+
+ pp0: packet-processor@0 {
+ compatible = "marvell,prestera-98dx3236";
+ reg = <0 0x4000000>;
+ interrupts = <33>, <34>, <35>;
+ dfx = <&dfx>;
+ };
+ };
+ };
+};
+
+&pinctrl {
+ compatible = "marvell,98dx3236-pinctrl";
+
+ spi0_pins: spi0-pins {
+ marvell,pins = "mpp0", "mpp1",
+ "mpp2", "mpp3";
+ marvell,function = "spi0";
+ };
+};
+
+&sdio {
+ status = "disabled";
+};
+
+&crypto_sram0 {
+ status = "disabled";
+};
+
+&crypto_sram1 {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
new file mode 100644
index 000000000000..e1580afdc260
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
@@ -0,0 +1,76 @@
+/*
+ * Device Tree Include file for Marvell 98dx3336 family SoC
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Contains definitions specific to the 98dx3236 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+#include "armada-xp-98dx3236.dtsi"
+
+/ {
+ model = "Marvell 98DX3336 SoC";
+ compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ cpus {
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <1>;
+ clocks = <&cpuclk 1>;
+ clock-latency = <1000000>;
+ };
+ };
+
+ soc {
+ internal-regs {
+ resume@20980 {
+ compatible = "marvell,98dx3336-resume-ctrl";
+ reg = <0x20980 0x10>;
+ };
+ };
+ };
+};
+
+&pp0 {
+ compatible = "marvell,prestera-98dx3336";
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
new file mode 100644
index 000000000000..4b0533a4ccb7
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
@@ -0,0 +1,90 @@
+/*
+ * Device Tree Include file for Marvell 98dx4521 family SoC
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Contains definitions specific to the 98dx4521 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+#include "armada-xp-98dx3236.dtsi"
+
+/ {
+ model = "Marvell 98DX4251 SoC";
+ compatible = "marvell,armadaxp-98dx4521", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ cpus {
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <1>;
+ clocks = <&cpuclk 1>;
+ clock-latency = <1000000>;
+ };
+ };
+
+ soc {
+ internal-regs {
+ resume@20980 {
+ compatible = "marvell,98dx3336-resume-ctrl";
+ reg = <0x20980 0x10>;
+ };
+ };
+ };
+};
+
+&sdio {
+ status = "okay";
+};
+
+&pinctrl {
+ compatible = "marvell,98dx4251-pinctrl";
+
+ sdio_pins: sdio-pins {
+ marvell,pins = "mpp5", "mpp6", "mpp7",
+ "mpp8", "mpp9", "mpp10";
+ marvell,function = "sd0";
+ };
+};
+
+&pp0 {
+ compatible = "marvell,prestera-98dx4251";
+};
--
2.11.0.24.ge6920cf
--
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^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCHv5 5/5] arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
@ 2017-01-27 3:25 ` Chris Packham
0 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-27 3:25 UTC (permalink / raw)
To: linux, linux-arm-kernel
Cc: Chris Packham, Rob Herring, Mark Rutland, devicetree, linux-kernel
These boards are Marvell's evaluation boards for the 98DX4251 and
98DX3336 SoCs.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
Notes:
Changes in v5:
- update license text
- use node labels
arch/arm/boot/dts/db-dxbc2.dts | 151 ++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/db-xc3-24g4xg.dts | 142 +++++++++++++++++++++++++++++++++
2 files changed, 293 insertions(+)
create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
diff --git a/arch/arm/boot/dts/db-dxbc2.dts b/arch/arm/boot/dts/db-dxbc2.dts
new file mode 100644
index 000000000000..a8130805074e
--- /dev/null
+++ b/arch/arm/boot/dts/db-dxbc2.dts
@@ -0,0 +1,151 @@
+/*
+ * Device Tree file for DB-DXBC2 board
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * Based on armada-xp-db.dts
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
+ */
+
+/dts-v1/;
+#include "armada-xp-98dx4251.dtsi"
+
+/ {
+ model = "Marvell Bobcat2 Evaluation Board";
+ compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
+ };
+
+};
+
+&devbus_bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width = <16>;
+ devbus,turn-off-ps = <60000>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters */
+ devbus,sync-enable = <0>;
+ devbus,wr-high-ps = <60000>;
+ devbus,wr-low-ps = <60000>;
+ devbus,ale-wr-ps = <60000>;
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&nand {
+ status = "okay";
+ num-cs = <1>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+};
+
+&sdio {
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ /* No CD or WP GPIOs */
+ broken-cd;
+};
+
+&spi0 {
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p64";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <20000000>;
+ m25p,fast-read;
+
+ partition@u-boot {
+ reg = <0x00000000 0x00100000>;
+ label = "u-boot";
+ };
+ partition@u-boot-env {
+ reg = <0x00100000 0x00040000>;
+ label = "u-boot-env";
+ };
+ partition@unused {
+ reg = <0x00140000 0x00ec0000>;
+ label = "unused";
+ };
+
+ };
+};
diff --git a/arch/arm/boot/dts/db-xc3-24g4xg.dts b/arch/arm/boot/dts/db-xc3-24g4xg.dts
new file mode 100644
index 000000000000..4e07cb6ed800
--- /dev/null
+++ b/arch/arm/boot/dts/db-xc3-24g4xg.dts
@@ -0,0 +1,142 @@
+/*
+ * Device Tree file for DB-XC3-24G4XG board
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * Based on armada-xp-db.dts
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
+ */
+
+/dts-v1/;
+#include "armada-xp-98dx3336.dtsi"
+
+/ {
+ model = "DB-XC3-24G4XG";
+ compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
+ };
+};
+
+&devbus_bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width = <16>;
+ devbus,turn-off-ps = <60000>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters */
+ devbus,sync-enable = <0>;
+ devbus,wr-high-ps = <60000>;
+ devbus,wr-low-ps = <60000>;
+ devbus,ale-wr-ps = <60000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&nand {
+ status = "okay";
+ num-cs = <1>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+};
+
+&spi0 {
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p64";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <20000000>;
+ m25p,fast-read;
+
+ partition@u-boot {
+ reg = <0x00000000 0x00100000>;
+ label = "u-boot";
+ };
+ partition@u-boot-env {
+ reg = <0x00100000 0x00040000>;
+ label = "u-boot-env";
+ };
+ partition@unused {
+ reg = <0x00140000 0x00ec0000>;
+ label = "unused";
+ };
+
+ };
+};
--
2.11.0.24.ge6920cf
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCHv5 5/5] arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
@ 2017-01-27 3:25 ` Chris Packham
0 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-27 3:25 UTC (permalink / raw)
To: linux-arm-kernel
These boards are Marvell's evaluation boards for the 98DX4251 and
98DX3336 SoCs.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
Notes:
Changes in v5:
- update license text
- use node labels
arch/arm/boot/dts/db-dxbc2.dts | 151 ++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/db-xc3-24g4xg.dts | 142 +++++++++++++++++++++++++++++++++
2 files changed, 293 insertions(+)
create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
diff --git a/arch/arm/boot/dts/db-dxbc2.dts b/arch/arm/boot/dts/db-dxbc2.dts
new file mode 100644
index 000000000000..a8130805074e
--- /dev/null
+++ b/arch/arm/boot/dts/db-dxbc2.dts
@@ -0,0 +1,151 @@
+/*
+ * Device Tree file for DB-DXBC2 board
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * Based on armada-xp-db.dts
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
+ */
+
+/dts-v1/;
+#include "armada-xp-98dx4251.dtsi"
+
+/ {
+ model = "Marvell Bobcat2 Evaluation Board";
+ compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
+ };
+
+};
+
+&devbus_bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width = <16>;
+ devbus,turn-off-ps = <60000>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters */
+ devbus,sync-enable = <0>;
+ devbus,wr-high-ps = <60000>;
+ devbus,wr-low-ps = <60000>;
+ devbus,ale-wr-ps = <60000>;
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&nand {
+ status = "okay";
+ num-cs = <1>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+};
+
+&sdio {
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ /* No CD or WP GPIOs */
+ broken-cd;
+};
+
+&spi0 {
+ status = "okay";
+
+ spi-flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p64";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <20000000>;
+ m25p,fast-read;
+
+ partition at u-boot {
+ reg = <0x00000000 0x00100000>;
+ label = "u-boot";
+ };
+ partition at u-boot-env {
+ reg = <0x00100000 0x00040000>;
+ label = "u-boot-env";
+ };
+ partition at unused {
+ reg = <0x00140000 0x00ec0000>;
+ label = "unused";
+ };
+
+ };
+};
diff --git a/arch/arm/boot/dts/db-xc3-24g4xg.dts b/arch/arm/boot/dts/db-xc3-24g4xg.dts
new file mode 100644
index 000000000000..4e07cb6ed800
--- /dev/null
+++ b/arch/arm/boot/dts/db-xc3-24g4xg.dts
@@ -0,0 +1,142 @@
+/*
+ * Device Tree file for DB-XC3-24G4XG board
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * Based on armada-xp-db.dts
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
+ */
+
+/dts-v1/;
+#include "armada-xp-98dx3336.dtsi"
+
+/ {
+ model = "DB-XC3-24G4XG";
+ compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
+ };
+};
+
+&devbus_bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width = <16>;
+ devbus,turn-off-ps = <60000>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters */
+ devbus,sync-enable = <0>;
+ devbus,wr-high-ps = <60000>;
+ devbus,wr-low-ps = <60000>;
+ devbus,ale-wr-ps = <60000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&nand {
+ status = "okay";
+ num-cs = <1>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+};
+
+&spi0 {
+ status = "okay";
+
+ spi-flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p64";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <20000000>;
+ m25p,fast-read;
+
+ partition at u-boot {
+ reg = <0x00000000 0x00100000>;
+ label = "u-boot";
+ };
+ partition at u-boot-env {
+ reg = <0x00100000 0x00040000>;
+ label = "u-boot-env";
+ };
+ partition at unused {
+ reg = <0x00140000 0x00ec0000>;
+ label = "unused";
+ };
+
+ };
+};
--
2.11.0.24.ge6920cf
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCHv5 5/5] arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
@ 2017-01-27 3:25 ` Chris Packham
0 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-27 3:25 UTC (permalink / raw)
To: linux-I+IVW8TIWO2tmTQ+vhA3Yw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Chris Packham, Rob Herring, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
These boards are Marvell's evaluation boards for the 98DX4251 and
98DX3336 SoCs.
Signed-off-by: Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>
---
Notes:
Changes in v5:
- update license text
- use node labels
arch/arm/boot/dts/db-dxbc2.dts | 151 ++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/db-xc3-24g4xg.dts | 142 +++++++++++++++++++++++++++++++++
2 files changed, 293 insertions(+)
create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
diff --git a/arch/arm/boot/dts/db-dxbc2.dts b/arch/arm/boot/dts/db-dxbc2.dts
new file mode 100644
index 000000000000..a8130805074e
--- /dev/null
+++ b/arch/arm/boot/dts/db-dxbc2.dts
@@ -0,0 +1,151 @@
+/*
+ * Device Tree file for DB-DXBC2 board
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * Based on armada-xp-db.dts
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
+ */
+
+/dts-v1/;
+#include "armada-xp-98dx4251.dtsi"
+
+/ {
+ model = "Marvell Bobcat2 Evaluation Board";
+ compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
+ };
+
+};
+
+&devbus_bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width = <16>;
+ devbus,turn-off-ps = <60000>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters */
+ devbus,sync-enable = <0>;
+ devbus,wr-high-ps = <60000>;
+ devbus,wr-low-ps = <60000>;
+ devbus,ale-wr-ps = <60000>;
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&nand {
+ status = "okay";
+ num-cs = <1>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+};
+
+&sdio {
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ /* No CD or WP GPIOs */
+ broken-cd;
+};
+
+&spi0 {
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p64";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <20000000>;
+ m25p,fast-read;
+
+ partition@u-boot {
+ reg = <0x00000000 0x00100000>;
+ label = "u-boot";
+ };
+ partition@u-boot-env {
+ reg = <0x00100000 0x00040000>;
+ label = "u-boot-env";
+ };
+ partition@unused {
+ reg = <0x00140000 0x00ec0000>;
+ label = "unused";
+ };
+
+ };
+};
diff --git a/arch/arm/boot/dts/db-xc3-24g4xg.dts b/arch/arm/boot/dts/db-xc3-24g4xg.dts
new file mode 100644
index 000000000000..4e07cb6ed800
--- /dev/null
+++ b/arch/arm/boot/dts/db-xc3-24g4xg.dts
@@ -0,0 +1,142 @@
+/*
+ * Device Tree file for DB-XC3-24G4XG board
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * Based on armada-xp-db.dts
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
+ */
+
+/dts-v1/;
+#include "armada-xp-98dx3336.dtsi"
+
+/ {
+ model = "DB-XC3-24G4XG";
+ compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
+ };
+};
+
+&devbus_bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width = <16>;
+ devbus,turn-off-ps = <60000>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters */
+ devbus,sync-enable = <0>;
+ devbus,wr-high-ps = <60000>;
+ devbus,wr-low-ps = <60000>;
+ devbus,ale-wr-ps = <60000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&nand {
+ status = "okay";
+ num-cs = <1>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+};
+
+&spi0 {
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p64";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <20000000>;
+ m25p,fast-read;
+
+ partition@u-boot {
+ reg = <0x00000000 0x00100000>;
+ label = "u-boot";
+ };
+ partition@u-boot-env {
+ reg = <0x00100000 0x00040000>;
+ label = "u-boot-env";
+ };
+ partition@unused {
+ reg = <0x00140000 0x00ec0000>;
+ label = "unused";
+ };
+
+ };
+};
--
2.11.0.24.ge6920cf
--
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^ permalink raw reply related [flat|nested] 49+ messages in thread* Re: [PATCHv5 5/5] arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
2017-01-27 3:25 ` Chris Packham
@ 2017-01-27 16:48 ` Gregory CLEMENT
-1 siblings, 0 replies; 49+ messages in thread
From: Gregory CLEMENT @ 2017-01-27 16:48 UTC (permalink / raw)
To: Chris Packham
Cc: linux, linux-arm-kernel, Mark Rutland, devicetree, linux-kernel,
Rob Herring
Hi Chris,
On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
> These boards are Marvell's evaluation boards for the 98DX4251 and
> 98DX3336 SoCs.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
>
> Notes:
> Changes in v5:
> - update license text
> - use node labels
>
> arch/arm/boot/dts/db-dxbc2.dts | 151 ++++++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/db-xc3-24g4xg.dts | 142 +++++++++++++++++++++++++++++++++
> 2 files changed, 293 insertions(+)
> create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
> create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
I only noticed it when I applied your patch: could you rename them by
adding the prefix armada-xp-. The rule we use for naming the dts is to
start by the SoC it belongs. The main benefit is when we try to have all
the device tree file of the same SoC we just have to parse the name of
the files.
Thanks,
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCHv5 5/5] arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
@ 2017-01-27 16:48 ` Gregory CLEMENT
0 siblings, 0 replies; 49+ messages in thread
From: Gregory CLEMENT @ 2017-01-27 16:48 UTC (permalink / raw)
To: linux-arm-kernel
Hi Chris,
On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
> These boards are Marvell's evaluation boards for the 98DX4251 and
> 98DX3336 SoCs.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
>
> Notes:
> Changes in v5:
> - update license text
> - use node labels
>
> arch/arm/boot/dts/db-dxbc2.dts | 151 ++++++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/db-xc3-24g4xg.dts | 142 +++++++++++++++++++++++++++++++++
> 2 files changed, 293 insertions(+)
> create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
> create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
I only noticed it when I applied your patch: could you rename them by
adding the prefix armada-xp-. The rule we use for naming the dts is to
start by the SoC it belongs. The main benefit is when we try to have all
the device tree file of the same SoC we just have to parse the name of
the files.
Thanks,
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
2017-01-27 3:25 ` Chris Packham
(?)
(?)
@ 2017-01-27 16:39 ` Gregory CLEMENT
-1 siblings, 0 replies; 49+ messages in thread
From: Gregory CLEMENT @ 2017-01-27 16:39 UTC (permalink / raw)
To: Stephen Boyd, Linus Walleij, Chris Packham
Cc: Mark Rutland, Andrew Lunn, Geert Uytterhoeven, Michael Turquette,
Laxman Dewangan, linux-clk, Florian Fainelli, Juri Lelli, linux,
Thierry Reding, Sebastian Hesselbarth, devicetree, Jason Cooper,
Arnd Bergmann, linux-gpio, Rob Herring, Chris Brand,
linux-arm-kernel, Thomas Petazzoni, Kalyan Kinthada,
linux-kernel, Sudeep Holla
Hi all,
On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
> integrated CPUs. They CPU block is common within these product lines and
> (as far as I can tell/have been told) is based on the Armada XP. There
> are a few differences due to the fact they have to squeeze the CPU into
> the same package as the switch.
>
> I've rebased this series against linux-pinctrl/devel to get access to
> mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to
> v4.10.0-rc5.
Just to let you know that I plan to apply the 3 arm patch once Chris
will have sent the new series with the minor fixes I asked on patch 3.
I already applied them in the for-next branch to benefit of some build
test coverage.
Stephen,
you gave your Acked-by on the first patch, but don't you plan to apply
it on the clk branch?
If you really want I can apply on mvebu but there is no build
dependencies, so the order the patches will be merged is not important.
Linus,
I expect you will apply the pinctrl patch on your tree as it depend of
code already there.
Thanks,
Gregory
>
> Chris Packham (4):
> clk: mvebu: support for 98DX3236 SoC
> Changes in v2:
> - Update devicetree binding documentation for new compatible string
> Changes in v3:
> - Add 98dx3236 support to mvebu/clk-corediv.c rather than creating a new
> driver.
> - Document mv98dx3236-corediv-clock binding
> Changes in v4:
> - None
> Changes in v5:
> - Collect ack from Rob
> - Remove explicit initialisation of fields to 0 in mv98dx3236_coreclks
> - Register dummy clock provider for marvell,mv98dx3236-cpu-clock
> arm: mvebu: support for SMP on 98DX3336 SoC
> Changes in v2:
> - Document new enable-method value
> - Correct some references from 98DX4521 to 98DX3236
> Changes in v3:
> - Simplify mv98dx3236_resume_init by using of_io_request_and_map()
> Changes in v4:
> - integrate changes into platsmp.c instead of new init call
> - avoid duplicated code.
> - fix error return
> - Collect ack from Rob
> Changes in v5:
> - Remove useless casts (thanks to Stephen Boyd)
> arm: mvebu: Add device tree for 98DX3236 SoCs
> Changes in v2:
> - Update devicetree binding documentation to reflect that 98DX3336 and
> 984251 are supersets of 98DX3236.
> - disable crypto block
> - disable sdio for 98DX3236, enable for 98DX4251
> Changes in v3:
> - fix typo 4521 -> 4251
> - document prestera bindings
> - rework corediv-clock binding
> - add label to packet processor node
> - add new compatible string for DFX server
> Changes in v4:
> - Collect ack from Rob
> Changes in v5:
> - Fixup license text. Add labels to nodes.
> arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
> Changes in v5:
> - update license text
> - use node labels
>
> Kalyan Kinthada (1):
> pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
> Changes in v2:
> - include sdio support for the 98DX4251
> Changes in v3:
> - None
> Changes in v4:
> - Correct some discrepencies between binding and driver.
> - Collect acks from Rob and Sebastian
> Changes in v5:
> - Update bindings to reflect "gpo" pins
> - Use mvebu_mmio_mpp_ctrl instead of armada_xp_mpp_ctrl (note this is reliant
> on changes queued in linux-pinctrl)
>
> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> .../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 16 ++
> .../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ++
> .../bindings/clock/mvebu-corediv-clock.txt | 1 +
> .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 1 +
> .../devicetree/bindings/net/marvell,prestera.txt | 50 ++++
> .../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++
> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 254 +++++++++++++++++++++
> arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 76 ++++++
> arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 90 ++++++++
> arch/arm/boot/dts/db-dxbc2.dts | 151 ++++++++++++
> arch/arm/boot/dts/db-xc3-24g4xg.dts | 142 ++++++++++++
> arch/arm/mach-mvebu/platsmp.c | 86 +++++++
> drivers/clk/mvebu/armada-xp.c | 39 ++++
> drivers/clk/mvebu/clk-corediv.c | 23 ++
> drivers/clk/mvebu/clk-cpu.c | 8 +
> drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 156 +++++++++++++
> 17 files changed, 1163 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
> create mode 100644 Documentation/devicetree/bindings/net/marvell,prestera.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
> create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
> create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
> create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
>
> interdiff to v4:
>
> diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
> index 520562a7dc2a..c7b4e3a6b2c6 100644
> @@ -85,7 +86,7 @@
> by address and length of the PMU DFS registers
> - #clock-cells : should be set to 1.
> diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
> -index b3094315a3c0..0413bf8284e0 100644
> +index b3094315a3c0..890a863ae0d0 100644
> --- a/drivers/clk/mvebu/armada-xp.c
> +++ b/drivers/clk/mvebu/armada-xp.c
> return 250000000;
> @@ -118,9 +119,6 @@
> +static const struct coreclk_soc_desc mv98dx3236_coreclks = {
> + .get_tclk_freq = mv98dx3236_get_tclk_freq,
> + .get_cpu_freq = mv98dx3236_get_cpu_freq,
> -+ .get_clk_ratio = NULL,
> -+ .ratios = NULL,
> -+ .num_ratios = 0,
> +};
> +
> /*
> @@ -200,53 +198,16 @@
> +CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock",
> + mv98dx3236_corediv_clk_init);
> diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
> -index 5837eb8a212f..3b8f0e14fa01 100644
> +index 5837eb8a212f..044892b6534d 100644
> --- a/drivers/clk/mvebu/clk-cpu.c
> +++ b/drivers/clk/mvebu/clk-cpu.c
> - .set_rate = clk_cpu_set_rate,
> - };
> -
> --static void __init of_cpu_clk_setup(struct device_node *node)
> -+/* Add parameter to allow this to support different clock operations. */
> -+static void __init _of_cpu_clk_setup(struct device_node *node,
> -+ const struct clk_ops *cpu_clk_ops)
> - {
> - struct cpu_clk *cpuclk;
> - void __iomem *clock_complex_base = of_iomap(node, 0);
> - cpuclk[cpu].hw.init = &init;
>
> - init.name = cpuclk[cpu].clk_name;
> -- init.ops = &cpu_ops;
> -+ init.ops = cpu_clk_ops;
> - init.flags = 0;
> - init.parent_names = &cpuclk[cpu].parent_name;
> - init.num_parents = 1;
> - iounmap(clock_complex_base);
> - }
> -
> -+/* Use this function to call the generic setup with the correct
> -+ * clock operation
> -+ */
> -+static void __init of_cpu_clk_setup(struct device_node *node)
> -+{
> -+ _of_cpu_clk_setup(node, &cpu_ops);
> -+}
> -+
> CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
> of_cpu_clk_setup);
> +
> -+/* Define the clock and operations for the mv98dx3236 - it cannot perform
> -+ * any operations.
> -+ */
> -+static const struct clk_ops mv98dx3236_cpu_ops = {
> -+ .recalc_rate = NULL,
> -+ .round_rate = NULL,
> -+ .set_rate = NULL,
> -+};
> -+
> +static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
> +{
> -+ _of_cpu_clk_setup(node, &mv98dx3236_cpu_ops);
> ++ of_clk_add_provider(node, of_clk_src_simple_get, NULL);
> +}
> +
> +CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
> @@ -285,7 +247,7 @@
> "qcom,gcc-msm8660"
> diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> new file mode 100644
> -index 000000000000..8082ba872edd
> +index 000000000000..26eb9d3aa630
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> +Resume Control
> @@ -304,10 +266,8 @@
> + compatible = "marvell,98dx3336-resume-ctrl";
> + reg = <0x20980 0x10>;
> +};
> -+
> -+
> diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
> -index 46c742d3bd41..59be3ca0464f 100644
> +index 46c742d3bd41..a5b464497e1a 100644
> --- a/arch/arm/mach-mvebu/platsmp.c
> +++ b/arch/arm/mach-mvebu/platsmp.c
>
> @@ -327,7 +287,7 @@
> +static const struct of_device_id of_mv98dx3236_resume_table[] = {
> + {
> + .compatible = "marvell,98dx3336-resume-ctrl",
> -+ .data = (void *)&mv98dx3336_resume_controller,
> ++ .data = &mv98dx3336_resume_controller,
> + },
> + { /* end of list */ },
> +};
> @@ -337,7 +297,7 @@
> + const struct of_device_id *match;
> + struct device_node *np;
> + void __iomem *base;
> -+ struct resume_controller *rc;
> ++ const struct resume_controller *rc;
> +
> + WARN_ON(hw_cpu != 1);
> +
> @@ -347,7 +307,7 @@
> + return -ENODEV;
> +
> + base = of_io_request_and_map(np, 0, of_node_full_name(np));
> -+ rc = (struct resume_controller *)match->data;
> ++ rc = match->data;
> + of_node_put(np);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> @@ -411,15 +371,17 @@
> diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
> new file mode 100644
> -index 000000000000..d4e6ecdfc853
> +index 000000000000..97aef67ee769
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
> +* Marvell 98dx3236 pinctrl driver for mpp
> @@ -435,41 +397,41 @@
> +
> +name pins functions
> +================================================================================
> -+mpp0 0 gpio, spi0(mosi), dev(ad8)
> ++mpp0 0 gpo, spi0(mosi), dev(ad8)
> +mpp1 1 gpio, spi0(miso), dev(ad9)
> -+mpp2 2 gpio, spi0(sck), dev(ad10)
> ++mpp2 2 gpo, spi0(sck), dev(ad10)
> +mpp3 3 gpio, spi0(cs0), dev(ad11)
> +mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
> +mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
> -+mpp6 6 gpio, sd0(clk), dev(a2)
> ++mpp6 6 gpo, sd0(clk), dev(a2)
> +mpp7 7 gpio, sd0(d0), dev(ale0)
> +mpp8 8 gpio, sd0(d1), dev(ale1)
> +mpp9 9 gpio, sd0(d2), dev(ready0)
> +mpp10 10 gpio, sd0(d3), dev(ad12)
> +mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13)
> -+mpp12 12 gpio, uart1(txd), uart0(rts), dev(ad14)
> ++mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14)
> +mpp13 13 gpio, intr(out), dev(ad15)
> +mpp14 14 gpio, i2c0(sck)
> +mpp15 15 gpio, i2c0(sda)
> -+mpp16 16 gpio, dev(oe)
> -+mpp17 17 gpio, dev(clk)
> ++mpp16 16 gpo, dev(oe)
> ++mpp17 17 gpo, dev(clkout)
> +mpp18 18 gpio, uart1(txd)
> +mpp19 19 gpio, uart1(rxd), dev(rb)
> -+mpp20 20 gpio, dev(we)
> -+mpp21 21 gpio, dev(ad0)
> -+mpp22 22 gpio, dev(ad1)
> -+mpp23 23 gpio, dev(ad2)
> -+mpp24 24 gpio, dev(ad3)
> -+mpp25 25 gpio, dev(ad4)
> -+mpp26 26 gpio, dev(ad5)
> -+mpp27 27 gpio, dev(ad6)
> -+mpp28 28 gpio, dev(ad7)
> -+mpp29 29 gpio, dev(a0)
> -+mpp30 30 gpio, dev(a1)
> ++mpp20 20 gpo, dev(we0)
> ++mpp21 21 gpo, dev(ad0)
> ++mpp22 22 gpo, dev(ad1)
> ++mpp23 23 gpo, dev(ad2)
> ++mpp24 24 gpo, dev(ad3)
> ++mpp25 25 gpo, dev(ad4)
> ++mpp26 26 gpo, dev(ad5)
> ++mpp27 27 gpo, dev(ad6)
> ++mpp28 28 gpo, dev(ad7)
> ++mpp29 29 gpo, dev(a0)
> ++mpp30 30 gpo, dev(a1)
> +mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
> +mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
> diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
> -index e4ea71a9d985..554eeae8cd21 100644
> +index 63e1bd506983..61cbc138703e 100644
> --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
> +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
> V_MV78460 = BIT(2),
> @@ -495,8 +457,8 @@
> + MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)),
> + MPP_MODE(2,
> -+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
> -+ MPP_VAR_FUNCTION(0x2, "spi0", "csk", V_98DX3236_PLUS),
> ++ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
> ++ MPP_VAR_FUNCTION(0x2, "spi0", "sck", V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)),
> + MPP_MODE(3,
> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
> @@ -511,7 +473,7 @@
> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251),
> -+ MPP_VAR_FUNCTION(0x4, "dev", "bootcs0", V_98DX3236_PLUS)),
> ++ MPP_VAR_FUNCTION(0x4, "dev", "bootcs", V_98DX3236_PLUS)),
> + MPP_MODE(6,
> + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251),
> @@ -563,7 +525,8 @@
> + MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)),
> + MPP_MODE(19,
> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
> -+ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS)),
> ++ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS),
> ++ MPP_VAR_FUNCTION(0x4, "dev", "rb", V_98DX3236_PLUS)),
> + MPP_MODE(20,
> + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)),
> @@ -630,11 +593,11 @@
> };
>
> +static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = {
> -+ MPP_FUNC_CTRL(0, 32, NULL, armada_xp_mpp_ctrl),
> ++ MPP_FUNC_CTRL(0, 32, NULL, mvebu_mmio_mpp_ctrl),
> +};
> +
> +static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = {
> -+ MPP_GPIO_RANGE(0, 0, 0, 32),
> ++ MPP_GPIO_RANGE(0, 0, 0, 32),
> +};
> +
> static int armada_xp_pinctrl_suspend(struct platform_device *pdev,
> @@ -767,7 +731,7 @@
> +};
> diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
> new file mode 100644
> -index 000000000000..4b7b2fe3b682
> +index 000000000000..9461128fae24
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
> +/*
> @@ -785,17 +749,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -804,11 +768,11 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> @@ -851,9 +815,9 @@
> + MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
> +
> + /*
> -+ * 98DX3236 has 1 x1 PCIe unit Gen2.0: One unit can be
> ++ * 98DX3236 has 1 x1 PCIe unit Gen2.0
> + */
> -+ pcie-controller {
> ++ pciec: pcie-controller@82000000 {
> + compatible = "marvell,armada-xp-pcie";
> + status = "disabled";
> + device_type = "pci";
> @@ -870,7 +834,7 @@
> + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
> + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;
> +
> -+ pcie@1,0 {
> ++ pcie1: pcie@1,0 {
> + device_type = "pci";
> + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
> + reg = <0x0800 0 0 0 0>;
> @@ -967,7 +931,7 @@
> + };
> + };
> +
> -+ dfx-registers {
> ++ dfxr: dfx-registers@ac000000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> @@ -987,7 +951,7 @@
> + };
> + };
> +
> -+ switch {
> ++ switch: switch@a8000000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> @@ -1026,7 +990,7 @@
> +};
> diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
> new file mode 100644
> -index 000000000000..a9b0f47f8df9
> +index 000000000000..e1580afdc260
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
> +/*
> @@ -1044,17 +1008,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -1063,16 +1027,16 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> -+ * Contains definitions specific to the 98dx3336 SoC that are not
> ++ * Contains definitions specific to the 98dx3236 SoC that are not
> + * common to all Armada XP SoCs.
> + */
> +
> @@ -1107,7 +1071,7 @@
> +};
> diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
> new file mode 100644
> -index 000000000000..446e6e65ec59
> +index 000000000000..4b0533a4ccb7
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
> +/*
> @@ -1125,17 +1089,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -1144,11 +1108,11 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> @@ -1213,15 +1177,15 @@
> diff --git a/arch/arm/boot/dts/db-dxbc2.dts b/arch/arm/boot/dts/db-dxbc2.dts
> new file mode 100644
> -index 000000000000..f56786cea5f8
> +index 000000000000..a8130805074e
> --- /dev/null
> +++ b/arch/arm/boot/dts/db-dxbc2.dts
> +/*
> @@ -1241,17 +1205,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -1260,11 +1224,11 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> @@ -1295,66 +1259,58 @@
> + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
> + };
> +
> -+ soc {
> -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
> -+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
> -+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
> -+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
> -+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
> ++};
> +
> -+ devbus-bootcs {
> -+ status = "okay";
> ++&devbus_bootcs {
> ++ status = "okay";
> +
> -+ /* Device Bus parameters are required */
> ++ /* Device Bus parameters are required */
> +
> -+ /* Read parameters */
> -+ devbus,bus-width = <16>;
> -+ devbus,turn-off-ps = <60000>;
> -+ devbus,badr-skew-ps = <0>;
> -+ devbus,acc-first-ps = <124000>;
> -+ devbus,acc-next-ps = <248000>;
> -+ devbus,rd-setup-ps = <0>;
> -+ devbus,rd-hold-ps = <0>;
> -+
> -+ /* Write parameters */
> -+ devbus,sync-enable = <0>;
> -+ devbus,wr-high-ps = <60000>;
> -+ devbus,wr-low-ps = <60000>;
> -+ devbus,ale-wr-ps = <60000>;
> -+ };
> ++ /* Read parameters */
> ++ devbus,bus-width = <16>;
> ++ devbus,turn-off-ps = <60000>;
> ++ devbus,badr-skew-ps = <0>;
> ++ devbus,acc-first-ps = <124000>;
> ++ devbus,acc-next-ps = <248000>;
> ++ devbus,rd-setup-ps = <0>;
> ++ devbus,rd-hold-ps = <0>;
> ++
> ++ /* Write parameters */
> ++ devbus,sync-enable = <0>;
> ++ devbus,wr-high-ps = <60000>;
> ++ devbus,wr-low-ps = <60000>;
> ++ devbus,ale-wr-ps = <60000>;
> ++};
> +
> -+ internal-regs {
> -+ serial@12000 {
> -+ status = "okay";
> -+ };
> -+ serial@12100 {
> -+ status = "okay";
> -+ };
> ++&i2c0 {
> ++ clock-frequency = <100000>;
> ++ status = "okay";
> ++};
> +
> -+ i2c@11000 {
> -+ clock-frequency = <100000>;
> -+ status = "okay";
> -+ };
> ++&uart0 {
> ++ status = "okay";
> ++};
> +
> -+ mvsdio@d4000 {
> -+ pinctrl-0 = <&sdio_pins>;
> -+ pinctrl-names = "default";
> -+ status = "okay";
> -+ /* No CD or WP GPIOs */
> -+ broken-cd;
> -+ };
> ++&uart1 {
> ++ status = "okay";
> ++};
> +
> -+ nand@d0000 {
> -+ status = "okay";
> -+ num-cs = <1>;
> -+ marvell,nand-keep-config;
> -+ marvell,nand-enable-arbiter;
> -+ nand-on-flash-bbt;
> -+ nand-ecc-strength = <4>;
> -+ nand-ecc-step-size = <512>;
> -+ };
> -+ };
> -+ };
> ++&nand {
> ++ status = "okay";
> ++ num-cs = <1>;
> ++ marvell,nand-keep-config;
> ++ marvell,nand-enable-arbiter;
> ++ nand-on-flash-bbt;
> ++ nand-ecc-strength = <4>;
> ++ nand-ecc-step-size = <512>;
> ++};
> ++
> ++&sdio {
> ++ pinctrl-0 = <&sdio_pins>;
> ++ pinctrl-names = "default";
> ++ status = "okay";
> ++ /* No CD or WP GPIOs */
> ++ broken-cd;
> +};
> +
> +&spi0 {
> @@ -1385,7 +1341,7 @@
> +};
> diff --git a/arch/arm/boot/dts/db-xc3-24g4xg.dts b/arch/arm/boot/dts/db-xc3-24g4xg.dts
> new file mode 100644
> -index 000000000000..5eb89ffb9a7d
> +index 000000000000..4e07cb6ed800
> --- /dev/null
> +++ b/arch/arm/boot/dts/db-xc3-24g4xg.dts
> +/*
> @@ -1405,17 +1361,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -1424,11 +1380,11 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> @@ -1458,63 +1414,50 @@
> + device_type = "memory";
> + reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
> + };
> ++};
> +
> -+ soc {
> -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
> -+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
> -+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
> -+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
> -+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
> -+
> -+ devbus-bootcs {
> -+ status = "okay";
> ++&devbus_bootcs {
> ++ status = "okay";
> +
> -+ /* Device Bus parameters are required */
> ++ /* Device Bus parameters are required */
> +
> -+ /* Read parameters */
> -+ devbus,bus-width = <16>;
> -+ devbus,turn-off-ps = <60000>;
> -+ devbus,badr-skew-ps = <0>;
> -+ devbus,acc-first-ps = <124000>;
> -+ devbus,acc-next-ps = <248000>;
> -+ devbus,rd-setup-ps = <0>;
> -+ devbus,rd-hold-ps = <0>;
> -+
> -+ /* Write parameters */
> -+ devbus,sync-enable = <0>;
> -+ devbus,wr-high-ps = <60000>;
> -+ devbus,wr-low-ps = <60000>;
> -+ devbus,ale-wr-ps = <60000>;
> -+ };
> ++ /* Read parameters */
> ++ devbus,bus-width = <16>;
> ++ devbus,turn-off-ps = <60000>;
> ++ devbus,badr-skew-ps = <0>;
> ++ devbus,acc-first-ps = <124000>;
> ++ devbus,acc-next-ps = <248000>;
> ++ devbus,rd-setup-ps = <0>;
> ++ devbus,rd-hold-ps = <0>;
> ++
> ++ /* Write parameters */
> ++ devbus,sync-enable = <0>;
> ++ devbus,wr-high-ps = <60000>;
> ++ devbus,wr-low-ps = <60000>;
> ++ devbus,ale-wr-ps = <60000>;
> ++};
> +
> -+ internal-regs {
> -+ serial@12000 {
> -+ status = "okay";
> -+ };
> -+ serial@12100 {
> -+ status = "okay";
> -+ };
> ++&uart0 {
> ++ status = "okay";
> ++};
> +
> -+ i2c@11000 {
> -+ clock-frequency = <100000>;
> -+ status = "okay";
> -+ };
> ++&uart1 {
> ++ status = "okay";
> ++};
> +
> -+ mvsdio@d4000 {
> -+ status = "disabled";
> -+ };
> ++&i2c0 {
> ++ clock-frequency = <100000>;
> ++ status = "okay";
> ++};
> +
> -+ nand@d0000 {
> -+ status = "okay";
> -+ num-cs = <1>;
> -+ marvell,nand-keep-config;
> -+ marvell,nand-enable-arbiter;
> -+ nand-on-flash-bbt;
> -+ nand-ecc-strength = <4>;
> -+ nand-ecc-step-size = <512>;
> -+ };
> -+ };
> -+ };
> ++&nand {
> ++ status = "okay";
> ++ num-cs = <1>;
> ++ marvell,nand-keep-config;
> ++ marvell,nand-enable-arbiter;
> ++ nand-on-flash-bbt;
> ++ nand-ecc-strength = <4>;
> ++ nand-ecc-step-size = <512>;
> +};
> +
> +&spi0 {
>
> --
> 2.11.0.24.ge6920cf
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 49+ messages in thread* [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-27 16:39 ` Gregory CLEMENT
0 siblings, 0 replies; 49+ messages in thread
From: Gregory CLEMENT @ 2017-01-27 16:39 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
> integrated CPUs. They CPU block is common within these product lines and
> (as far as I can tell/have been told) is based on the Armada XP. There
> are a few differences due to the fact they have to squeeze the CPU into
> the same package as the switch.
>
> I've rebased this series against linux-pinctrl/devel to get access to
> mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to
> v4.10.0-rc5.
Just to let you know that I plan to apply the 3 arm patch once Chris
will have sent the new series with the minor fixes I asked on patch 3.
I already applied them in the for-next branch to benefit of some build
test coverage.
Stephen,
you gave your Acked-by on the first patch, but don't you plan to apply
it on the clk branch?
If you really want I can apply on mvebu but there is no build
dependencies, so the order the patches will be merged is not important.
Linus,
I expect you will apply the pinctrl patch on your tree as it depend of
code already there.
Thanks,
Gregory
>
> Chris Packham (4):
> clk: mvebu: support for 98DX3236 SoC
> Changes in v2:
> - Update devicetree binding documentation for new compatible string
> Changes in v3:
> - Add 98dx3236 support to mvebu/clk-corediv.c rather than creating a new
> driver.
> - Document mv98dx3236-corediv-clock binding
> Changes in v4:
> - None
> Changes in v5:
> - Collect ack from Rob
> - Remove explicit initialisation of fields to 0 in mv98dx3236_coreclks
> - Register dummy clock provider for marvell,mv98dx3236-cpu-clock
> arm: mvebu: support for SMP on 98DX3336 SoC
> Changes in v2:
> - Document new enable-method value
> - Correct some references from 98DX4521 to 98DX3236
> Changes in v3:
> - Simplify mv98dx3236_resume_init by using of_io_request_and_map()
> Changes in v4:
> - integrate changes into platsmp.c instead of new init call
> - avoid duplicated code.
> - fix error return
> - Collect ack from Rob
> Changes in v5:
> - Remove useless casts (thanks to Stephen Boyd)
> arm: mvebu: Add device tree for 98DX3236 SoCs
> Changes in v2:
> - Update devicetree binding documentation to reflect that 98DX3336 and
> 984251 are supersets of 98DX3236.
> - disable crypto block
> - disable sdio for 98DX3236, enable for 98DX4251
> Changes in v3:
> - fix typo 4521 -> 4251
> - document prestera bindings
> - rework corediv-clock binding
> - add label to packet processor node
> - add new compatible string for DFX server
> Changes in v4:
> - Collect ack from Rob
> Changes in v5:
> - Fixup license text. Add labels to nodes.
> arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
> Changes in v5:
> - update license text
> - use node labels
>
> Kalyan Kinthada (1):
> pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
> Changes in v2:
> - include sdio support for the 98DX4251
> Changes in v3:
> - None
> Changes in v4:
> - Correct some discrepencies between binding and driver.
> - Collect acks from Rob and Sebastian
> Changes in v5:
> - Update bindings to reflect "gpo" pins
> - Use mvebu_mmio_mpp_ctrl instead of armada_xp_mpp_ctrl (note this is reliant
> on changes queued in linux-pinctrl)
>
> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> .../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 16 ++
> .../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ++
> .../bindings/clock/mvebu-corediv-clock.txt | 1 +
> .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 1 +
> .../devicetree/bindings/net/marvell,prestera.txt | 50 ++++
> .../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++
> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 254 +++++++++++++++++++++
> arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 76 ++++++
> arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 90 ++++++++
> arch/arm/boot/dts/db-dxbc2.dts | 151 ++++++++++++
> arch/arm/boot/dts/db-xc3-24g4xg.dts | 142 ++++++++++++
> arch/arm/mach-mvebu/platsmp.c | 86 +++++++
> drivers/clk/mvebu/armada-xp.c | 39 ++++
> drivers/clk/mvebu/clk-corediv.c | 23 ++
> drivers/clk/mvebu/clk-cpu.c | 8 +
> drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 156 +++++++++++++
> 17 files changed, 1163 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
> create mode 100644 Documentation/devicetree/bindings/net/marvell,prestera.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
> create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
> create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
> create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
>
> interdiff to v4:
>
> diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
> index 520562a7dc2a..c7b4e3a6b2c6 100644
> @@ -85,7 +86,7 @@
> by address and length of the PMU DFS registers
> - #clock-cells : should be set to 1.
> diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
> -index b3094315a3c0..0413bf8284e0 100644
> +index b3094315a3c0..890a863ae0d0 100644
> --- a/drivers/clk/mvebu/armada-xp.c
> +++ b/drivers/clk/mvebu/armada-xp.c
> return 250000000;
> @@ -118,9 +119,6 @@
> +static const struct coreclk_soc_desc mv98dx3236_coreclks = {
> + .get_tclk_freq = mv98dx3236_get_tclk_freq,
> + .get_cpu_freq = mv98dx3236_get_cpu_freq,
> -+ .get_clk_ratio = NULL,
> -+ .ratios = NULL,
> -+ .num_ratios = 0,
> +};
> +
> /*
> @@ -200,53 +198,16 @@
> +CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock",
> + mv98dx3236_corediv_clk_init);
> diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
> -index 5837eb8a212f..3b8f0e14fa01 100644
> +index 5837eb8a212f..044892b6534d 100644
> --- a/drivers/clk/mvebu/clk-cpu.c
> +++ b/drivers/clk/mvebu/clk-cpu.c
> - .set_rate = clk_cpu_set_rate,
> - };
> -
> --static void __init of_cpu_clk_setup(struct device_node *node)
> -+/* Add parameter to allow this to support different clock operations. */
> -+static void __init _of_cpu_clk_setup(struct device_node *node,
> -+ const struct clk_ops *cpu_clk_ops)
> - {
> - struct cpu_clk *cpuclk;
> - void __iomem *clock_complex_base = of_iomap(node, 0);
> - cpuclk[cpu].hw.init = &init;
>
> - init.name = cpuclk[cpu].clk_name;
> -- init.ops = &cpu_ops;
> -+ init.ops = cpu_clk_ops;
> - init.flags = 0;
> - init.parent_names = &cpuclk[cpu].parent_name;
> - init.num_parents = 1;
> - iounmap(clock_complex_base);
> - }
> -
> -+/* Use this function to call the generic setup with the correct
> -+ * clock operation
> -+ */
> -+static void __init of_cpu_clk_setup(struct device_node *node)
> -+{
> -+ _of_cpu_clk_setup(node, &cpu_ops);
> -+}
> -+
> CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
> of_cpu_clk_setup);
> +
> -+/* Define the clock and operations for the mv98dx3236 - it cannot perform
> -+ * any operations.
> -+ */
> -+static const struct clk_ops mv98dx3236_cpu_ops = {
> -+ .recalc_rate = NULL,
> -+ .round_rate = NULL,
> -+ .set_rate = NULL,
> -+};
> -+
> +static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
> +{
> -+ _of_cpu_clk_setup(node, &mv98dx3236_cpu_ops);
> ++ of_clk_add_provider(node, of_clk_src_simple_get, NULL);
> +}
> +
> +CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
> @@ -285,7 +247,7 @@
> "qcom,gcc-msm8660"
> diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> new file mode 100644
> -index 000000000000..8082ba872edd
> +index 000000000000..26eb9d3aa630
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> +Resume Control
> @@ -304,10 +266,8 @@
> + compatible = "marvell,98dx3336-resume-ctrl";
> + reg = <0x20980 0x10>;
> +};
> -+
> -+
> diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
> -index 46c742d3bd41..59be3ca0464f 100644
> +index 46c742d3bd41..a5b464497e1a 100644
> --- a/arch/arm/mach-mvebu/platsmp.c
> +++ b/arch/arm/mach-mvebu/platsmp.c
>
> @@ -327,7 +287,7 @@
> +static const struct of_device_id of_mv98dx3236_resume_table[] = {
> + {
> + .compatible = "marvell,98dx3336-resume-ctrl",
> -+ .data = (void *)&mv98dx3336_resume_controller,
> ++ .data = &mv98dx3336_resume_controller,
> + },
> + { /* end of list */ },
> +};
> @@ -337,7 +297,7 @@
> + const struct of_device_id *match;
> + struct device_node *np;
> + void __iomem *base;
> -+ struct resume_controller *rc;
> ++ const struct resume_controller *rc;
> +
> + WARN_ON(hw_cpu != 1);
> +
> @@ -347,7 +307,7 @@
> + return -ENODEV;
> +
> + base = of_io_request_and_map(np, 0, of_node_full_name(np));
> -+ rc = (struct resume_controller *)match->data;
> ++ rc = match->data;
> + of_node_put(np);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> @@ -411,15 +371,17 @@
> diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
> new file mode 100644
> -index 000000000000..d4e6ecdfc853
> +index 000000000000..97aef67ee769
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
> +* Marvell 98dx3236 pinctrl driver for mpp
> @@ -435,41 +397,41 @@
> +
> +name pins functions
> +================================================================================
> -+mpp0 0 gpio, spi0(mosi), dev(ad8)
> ++mpp0 0 gpo, spi0(mosi), dev(ad8)
> +mpp1 1 gpio, spi0(miso), dev(ad9)
> -+mpp2 2 gpio, spi0(sck), dev(ad10)
> ++mpp2 2 gpo, spi0(sck), dev(ad10)
> +mpp3 3 gpio, spi0(cs0), dev(ad11)
> +mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
> +mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
> -+mpp6 6 gpio, sd0(clk), dev(a2)
> ++mpp6 6 gpo, sd0(clk), dev(a2)
> +mpp7 7 gpio, sd0(d0), dev(ale0)
> +mpp8 8 gpio, sd0(d1), dev(ale1)
> +mpp9 9 gpio, sd0(d2), dev(ready0)
> +mpp10 10 gpio, sd0(d3), dev(ad12)
> +mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13)
> -+mpp12 12 gpio, uart1(txd), uart0(rts), dev(ad14)
> ++mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14)
> +mpp13 13 gpio, intr(out), dev(ad15)
> +mpp14 14 gpio, i2c0(sck)
> +mpp15 15 gpio, i2c0(sda)
> -+mpp16 16 gpio, dev(oe)
> -+mpp17 17 gpio, dev(clk)
> ++mpp16 16 gpo, dev(oe)
> ++mpp17 17 gpo, dev(clkout)
> +mpp18 18 gpio, uart1(txd)
> +mpp19 19 gpio, uart1(rxd), dev(rb)
> -+mpp20 20 gpio, dev(we)
> -+mpp21 21 gpio, dev(ad0)
> -+mpp22 22 gpio, dev(ad1)
> -+mpp23 23 gpio, dev(ad2)
> -+mpp24 24 gpio, dev(ad3)
> -+mpp25 25 gpio, dev(ad4)
> -+mpp26 26 gpio, dev(ad5)
> -+mpp27 27 gpio, dev(ad6)
> -+mpp28 28 gpio, dev(ad7)
> -+mpp29 29 gpio, dev(a0)
> -+mpp30 30 gpio, dev(a1)
> ++mpp20 20 gpo, dev(we0)
> ++mpp21 21 gpo, dev(ad0)
> ++mpp22 22 gpo, dev(ad1)
> ++mpp23 23 gpo, dev(ad2)
> ++mpp24 24 gpo, dev(ad3)
> ++mpp25 25 gpo, dev(ad4)
> ++mpp26 26 gpo, dev(ad5)
> ++mpp27 27 gpo, dev(ad6)
> ++mpp28 28 gpo, dev(ad7)
> ++mpp29 29 gpo, dev(a0)
> ++mpp30 30 gpo, dev(a1)
> +mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
> +mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
> diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
> -index e4ea71a9d985..554eeae8cd21 100644
> +index 63e1bd506983..61cbc138703e 100644
> --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
> +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
> V_MV78460 = BIT(2),
> @@ -495,8 +457,8 @@
> + MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)),
> + MPP_MODE(2,
> -+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
> -+ MPP_VAR_FUNCTION(0x2, "spi0", "csk", V_98DX3236_PLUS),
> ++ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
> ++ MPP_VAR_FUNCTION(0x2, "spi0", "sck", V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)),
> + MPP_MODE(3,
> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
> @@ -511,7 +473,7 @@
> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251),
> -+ MPP_VAR_FUNCTION(0x4, "dev", "bootcs0", V_98DX3236_PLUS)),
> ++ MPP_VAR_FUNCTION(0x4, "dev", "bootcs", V_98DX3236_PLUS)),
> + MPP_MODE(6,
> + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251),
> @@ -563,7 +525,8 @@
> + MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)),
> + MPP_MODE(19,
> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
> -+ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS)),
> ++ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS),
> ++ MPP_VAR_FUNCTION(0x4, "dev", "rb", V_98DX3236_PLUS)),
> + MPP_MODE(20,
> + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)),
> @@ -630,11 +593,11 @@
> };
>
> +static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = {
> -+ MPP_FUNC_CTRL(0, 32, NULL, armada_xp_mpp_ctrl),
> ++ MPP_FUNC_CTRL(0, 32, NULL, mvebu_mmio_mpp_ctrl),
> +};
> +
> +static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = {
> -+ MPP_GPIO_RANGE(0, 0, 0, 32),
> ++ MPP_GPIO_RANGE(0, 0, 0, 32),
> +};
> +
> static int armada_xp_pinctrl_suspend(struct platform_device *pdev,
> @@ -767,7 +731,7 @@
> +};
> diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
> new file mode 100644
> -index 000000000000..4b7b2fe3b682
> +index 000000000000..9461128fae24
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
> +/*
> @@ -785,17 +749,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -804,11 +768,11 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> @@ -851,9 +815,9 @@
> + MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
> +
> + /*
> -+ * 98DX3236 has 1 x1 PCIe unit Gen2.0: One unit can be
> ++ * 98DX3236 has 1 x1 PCIe unit Gen2.0
> + */
> -+ pcie-controller {
> ++ pciec: pcie-controller at 82000000 {
> + compatible = "marvell,armada-xp-pcie";
> + status = "disabled";
> + device_type = "pci";
> @@ -870,7 +834,7 @@
> + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
> + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;
> +
> -+ pcie at 1,0 {
> ++ pcie1: pcie at 1,0 {
> + device_type = "pci";
> + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
> + reg = <0x0800 0 0 0 0>;
> @@ -967,7 +931,7 @@
> + };
> + };
> +
> -+ dfx-registers {
> ++ dfxr: dfx-registers at ac000000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> @@ -987,7 +951,7 @@
> + };
> + };
> +
> -+ switch {
> ++ switch: switch at a8000000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> @@ -1026,7 +990,7 @@
> +};
> diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
> new file mode 100644
> -index 000000000000..a9b0f47f8df9
> +index 000000000000..e1580afdc260
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
> +/*
> @@ -1044,17 +1008,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -1063,16 +1027,16 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> -+ * Contains definitions specific to the 98dx3336 SoC that are not
> ++ * Contains definitions specific to the 98dx3236 SoC that are not
> + * common to all Armada XP SoCs.
> + */
> +
> @@ -1107,7 +1071,7 @@
> +};
> diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
> new file mode 100644
> -index 000000000000..446e6e65ec59
> +index 000000000000..4b0533a4ccb7
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
> +/*
> @@ -1125,17 +1089,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -1144,11 +1108,11 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> @@ -1213,15 +1177,15 @@
> diff --git a/arch/arm/boot/dts/db-dxbc2.dts b/arch/arm/boot/dts/db-dxbc2.dts
> new file mode 100644
> -index 000000000000..f56786cea5f8
> +index 000000000000..a8130805074e
> --- /dev/null
> +++ b/arch/arm/boot/dts/db-dxbc2.dts
> +/*
> @@ -1241,17 +1205,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -1260,11 +1224,11 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> @@ -1295,66 +1259,58 @@
> + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
> + };
> +
> -+ soc {
> -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
> -+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
> -+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
> -+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
> -+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
> ++};
> +
> -+ devbus-bootcs {
> -+ status = "okay";
> ++&devbus_bootcs {
> ++ status = "okay";
> +
> -+ /* Device Bus parameters are required */
> ++ /* Device Bus parameters are required */
> +
> -+ /* Read parameters */
> -+ devbus,bus-width = <16>;
> -+ devbus,turn-off-ps = <60000>;
> -+ devbus,badr-skew-ps = <0>;
> -+ devbus,acc-first-ps = <124000>;
> -+ devbus,acc-next-ps = <248000>;
> -+ devbus,rd-setup-ps = <0>;
> -+ devbus,rd-hold-ps = <0>;
> -+
> -+ /* Write parameters */
> -+ devbus,sync-enable = <0>;
> -+ devbus,wr-high-ps = <60000>;
> -+ devbus,wr-low-ps = <60000>;
> -+ devbus,ale-wr-ps = <60000>;
> -+ };
> ++ /* Read parameters */
> ++ devbus,bus-width = <16>;
> ++ devbus,turn-off-ps = <60000>;
> ++ devbus,badr-skew-ps = <0>;
> ++ devbus,acc-first-ps = <124000>;
> ++ devbus,acc-next-ps = <248000>;
> ++ devbus,rd-setup-ps = <0>;
> ++ devbus,rd-hold-ps = <0>;
> ++
> ++ /* Write parameters */
> ++ devbus,sync-enable = <0>;
> ++ devbus,wr-high-ps = <60000>;
> ++ devbus,wr-low-ps = <60000>;
> ++ devbus,ale-wr-ps = <60000>;
> ++};
> +
> -+ internal-regs {
> -+ serial at 12000 {
> -+ status = "okay";
> -+ };
> -+ serial at 12100 {
> -+ status = "okay";
> -+ };
> ++&i2c0 {
> ++ clock-frequency = <100000>;
> ++ status = "okay";
> ++};
> +
> -+ i2c at 11000 {
> -+ clock-frequency = <100000>;
> -+ status = "okay";
> -+ };
> ++&uart0 {
> ++ status = "okay";
> ++};
> +
> -+ mvsdio at d4000 {
> -+ pinctrl-0 = <&sdio_pins>;
> -+ pinctrl-names = "default";
> -+ status = "okay";
> -+ /* No CD or WP GPIOs */
> -+ broken-cd;
> -+ };
> ++&uart1 {
> ++ status = "okay";
> ++};
> +
> -+ nand at d0000 {
> -+ status = "okay";
> -+ num-cs = <1>;
> -+ marvell,nand-keep-config;
> -+ marvell,nand-enable-arbiter;
> -+ nand-on-flash-bbt;
> -+ nand-ecc-strength = <4>;
> -+ nand-ecc-step-size = <512>;
> -+ };
> -+ };
> -+ };
> ++&nand {
> ++ status = "okay";
> ++ num-cs = <1>;
> ++ marvell,nand-keep-config;
> ++ marvell,nand-enable-arbiter;
> ++ nand-on-flash-bbt;
> ++ nand-ecc-strength = <4>;
> ++ nand-ecc-step-size = <512>;
> ++};
> ++
> ++&sdio {
> ++ pinctrl-0 = <&sdio_pins>;
> ++ pinctrl-names = "default";
> ++ status = "okay";
> ++ /* No CD or WP GPIOs */
> ++ broken-cd;
> +};
> +
> +&spi0 {
> @@ -1385,7 +1341,7 @@
> +};
> diff --git a/arch/arm/boot/dts/db-xc3-24g4xg.dts b/arch/arm/boot/dts/db-xc3-24g4xg.dts
> new file mode 100644
> -index 000000000000..5eb89ffb9a7d
> +index 000000000000..4e07cb6ed800
> --- /dev/null
> +++ b/arch/arm/boot/dts/db-xc3-24g4xg.dts
> +/*
> @@ -1405,17 +1361,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -1424,11 +1380,11 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> @@ -1458,63 +1414,50 @@
> + device_type = "memory";
> + reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
> + };
> ++};
> +
> -+ soc {
> -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
> -+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
> -+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
> -+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
> -+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
> -+
> -+ devbus-bootcs {
> -+ status = "okay";
> ++&devbus_bootcs {
> ++ status = "okay";
> +
> -+ /* Device Bus parameters are required */
> ++ /* Device Bus parameters are required */
> +
> -+ /* Read parameters */
> -+ devbus,bus-width = <16>;
> -+ devbus,turn-off-ps = <60000>;
> -+ devbus,badr-skew-ps = <0>;
> -+ devbus,acc-first-ps = <124000>;
> -+ devbus,acc-next-ps = <248000>;
> -+ devbus,rd-setup-ps = <0>;
> -+ devbus,rd-hold-ps = <0>;
> -+
> -+ /* Write parameters */
> -+ devbus,sync-enable = <0>;
> -+ devbus,wr-high-ps = <60000>;
> -+ devbus,wr-low-ps = <60000>;
> -+ devbus,ale-wr-ps = <60000>;
> -+ };
> ++ /* Read parameters */
> ++ devbus,bus-width = <16>;
> ++ devbus,turn-off-ps = <60000>;
> ++ devbus,badr-skew-ps = <0>;
> ++ devbus,acc-first-ps = <124000>;
> ++ devbus,acc-next-ps = <248000>;
> ++ devbus,rd-setup-ps = <0>;
> ++ devbus,rd-hold-ps = <0>;
> ++
> ++ /* Write parameters */
> ++ devbus,sync-enable = <0>;
> ++ devbus,wr-high-ps = <60000>;
> ++ devbus,wr-low-ps = <60000>;
> ++ devbus,ale-wr-ps = <60000>;
> ++};
> +
> -+ internal-regs {
> -+ serial at 12000 {
> -+ status = "okay";
> -+ };
> -+ serial at 12100 {
> -+ status = "okay";
> -+ };
> ++&uart0 {
> ++ status = "okay";
> ++};
> +
> -+ i2c at 11000 {
> -+ clock-frequency = <100000>;
> -+ status = "okay";
> -+ };
> ++&uart1 {
> ++ status = "okay";
> ++};
> +
> -+ mvsdio at d4000 {
> -+ status = "disabled";
> -+ };
> ++&i2c0 {
> ++ clock-frequency = <100000>;
> ++ status = "okay";
> ++};
> +
> -+ nand at d0000 {
> -+ status = "okay";
> -+ num-cs = <1>;
> -+ marvell,nand-keep-config;
> -+ marvell,nand-enable-arbiter;
> -+ nand-on-flash-bbt;
> -+ nand-ecc-strength = <4>;
> -+ nand-ecc-step-size = <512>;
> -+ };
> -+ };
> -+ };
> ++&nand {
> ++ status = "okay";
> ++ num-cs = <1>;
> ++ marvell,nand-keep-config;
> ++ marvell,nand-enable-arbiter;
> ++ nand-on-flash-bbt;
> ++ nand-ecc-strength = <4>;
> ++ nand-ecc-step-size = <512>;
> +};
> +
> +&spi0 {
>
> --
> 2.11.0.24.ge6920cf
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-27 16:39 ` Gregory CLEMENT
0 siblings, 0 replies; 49+ messages in thread
From: Gregory CLEMENT @ 2017-01-27 16:39 UTC (permalink / raw)
To: Stephen Boyd, Linus Walleij, Chris Packham
Cc: linux, linux-arm-kernel, Rob Herring, Mark Rutland,
Michael Turquette, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Geert Uytterhoeven, Chris Brand,
Florian Fainelli, Arnd Bergmann, Thierry Reding, Sudeep Holla,
Juri Lelli, Thomas Petazzoni, Laxman Dewangan, Kalyan Kinthada,
devicetree, linux-kernel, linux-clk, linux-gpio
Hi all,
On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
> integrated CPUs. They CPU block is common within these product lines and
> (as far as I can tell/have been told) is based on the Armada XP. There
> are a few differences due to the fact they have to squeeze the CPU into
> the same package as the switch.
>
> I've rebased this series against linux-pinctrl/devel to get access to
> mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to
> v4.10.0-rc5.
Just to let you know that I plan to apply the 3 arm patch once Chris
will have sent the new series with the minor fixes I asked on patch 3.
I already applied them in the for-next branch to benefit of some build
test coverage.
Stephen,
you gave your Acked-by on the first patch, but don't you plan to apply
it on the clk branch?
If you really want I can apply on mvebu but there is no build
dependencies, so the order the patches will be merged is not important.
Linus,
I expect you will apply the pinctrl patch on your tree as it depend of
code already there.
Thanks,
Gregory
>
> Chris Packham (4):
> clk: mvebu: support for 98DX3236 SoC
> Changes in v2:
> - Update devicetree binding documentation for new compatible string
> Changes in v3:
> - Add 98dx3236 support to mvebu/clk-corediv.c rather than creating a new
> driver.
> - Document mv98dx3236-corediv-clock binding
> Changes in v4:
> - None
> Changes in v5:
> - Collect ack from Rob
> - Remove explicit initialisation of fields to 0 in mv98dx3236_coreclks
> - Register dummy clock provider for marvell,mv98dx3236-cpu-clock
> arm: mvebu: support for SMP on 98DX3336 SoC
> Changes in v2:
> - Document new enable-method value
> - Correct some references from 98DX4521 to 98DX3236
> Changes in v3:
> - Simplify mv98dx3236_resume_init by using of_io_request_and_map()
> Changes in v4:
> - integrate changes into platsmp.c instead of new init call
> - avoid duplicated code.
> - fix error return
> - Collect ack from Rob
> Changes in v5:
> - Remove useless casts (thanks to Stephen Boyd)
> arm: mvebu: Add device tree for 98DX3236 SoCs
> Changes in v2:
> - Update devicetree binding documentation to reflect that 98DX3336 and
> 984251 are supersets of 98DX3236.
> - disable crypto block
> - disable sdio for 98DX3236, enable for 98DX4251
> Changes in v3:
> - fix typo 4521 -> 4251
> - document prestera bindings
> - rework corediv-clock binding
> - add label to packet processor node
> - add new compatible string for DFX server
> Changes in v4:
> - Collect ack from Rob
> Changes in v5:
> - Fixup license text. Add labels to nodes.
> arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
> Changes in v5:
> - update license text
> - use node labels
>
> Kalyan Kinthada (1):
> pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
> Changes in v2:
> - include sdio support for the 98DX4251
> Changes in v3:
> - None
> Changes in v4:
> - Correct some discrepencies between binding and driver.
> - Collect acks from Rob and Sebastian
> Changes in v5:
> - Update bindings to reflect "gpo" pins
> - Use mvebu_mmio_mpp_ctrl instead of armada_xp_mpp_ctrl (note this is reliant
> on changes queued in linux-pinctrl)
>
> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> .../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 16 ++
> .../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ++
> .../bindings/clock/mvebu-corediv-clock.txt | 1 +
> .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 1 +
> .../devicetree/bindings/net/marvell,prestera.txt | 50 ++++
> .../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++
> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 254 +++++++++++++++++++++
> arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 76 ++++++
> arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 90 ++++++++
> arch/arm/boot/dts/db-dxbc2.dts | 151 ++++++++++++
> arch/arm/boot/dts/db-xc3-24g4xg.dts | 142 ++++++++++++
> arch/arm/mach-mvebu/platsmp.c | 86 +++++++
> drivers/clk/mvebu/armada-xp.c | 39 ++++
> drivers/clk/mvebu/clk-corediv.c | 23 ++
> drivers/clk/mvebu/clk-cpu.c | 8 +
> drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 156 +++++++++++++
> 17 files changed, 1163 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
> create mode 100644 Documentation/devicetree/bindings/net/marvell,prestera.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
> create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
> create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
> create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
>
> interdiff to v4:
>
> diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
> index 520562a7dc2a..c7b4e3a6b2c6 100644
> @@ -85,7 +86,7 @@
> by address and length of the PMU DFS registers
> - #clock-cells : should be set to 1.
> diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
> -index b3094315a3c0..0413bf8284e0 100644
> +index b3094315a3c0..890a863ae0d0 100644
> --- a/drivers/clk/mvebu/armada-xp.c
> +++ b/drivers/clk/mvebu/armada-xp.c
> return 250000000;
> @@ -118,9 +119,6 @@
> +static const struct coreclk_soc_desc mv98dx3236_coreclks = {
> + .get_tclk_freq = mv98dx3236_get_tclk_freq,
> + .get_cpu_freq = mv98dx3236_get_cpu_freq,
> -+ .get_clk_ratio = NULL,
> -+ .ratios = NULL,
> -+ .num_ratios = 0,
> +};
> +
> /*
> @@ -200,53 +198,16 @@
> +CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock",
> + mv98dx3236_corediv_clk_init);
> diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
> -index 5837eb8a212f..3b8f0e14fa01 100644
> +index 5837eb8a212f..044892b6534d 100644
> --- a/drivers/clk/mvebu/clk-cpu.c
> +++ b/drivers/clk/mvebu/clk-cpu.c
> - .set_rate = clk_cpu_set_rate,
> - };
> -
> --static void __init of_cpu_clk_setup(struct device_node *node)
> -+/* Add parameter to allow this to support different clock operations. */
> -+static void __init _of_cpu_clk_setup(struct device_node *node,
> -+ const struct clk_ops *cpu_clk_ops)
> - {
> - struct cpu_clk *cpuclk;
> - void __iomem *clock_complex_base = of_iomap(node, 0);
> - cpuclk[cpu].hw.init = &init;
>
> - init.name = cpuclk[cpu].clk_name;
> -- init.ops = &cpu_ops;
> -+ init.ops = cpu_clk_ops;
> - init.flags = 0;
> - init.parent_names = &cpuclk[cpu].parent_name;
> - init.num_parents = 1;
> - iounmap(clock_complex_base);
> - }
> -
> -+/* Use this function to call the generic setup with the correct
> -+ * clock operation
> -+ */
> -+static void __init of_cpu_clk_setup(struct device_node *node)
> -+{
> -+ _of_cpu_clk_setup(node, &cpu_ops);
> -+}
> -+
> CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
> of_cpu_clk_setup);
> +
> -+/* Define the clock and operations for the mv98dx3236 - it cannot perform
> -+ * any operations.
> -+ */
> -+static const struct clk_ops mv98dx3236_cpu_ops = {
> -+ .recalc_rate = NULL,
> -+ .round_rate = NULL,
> -+ .set_rate = NULL,
> -+};
> -+
> +static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
> +{
> -+ _of_cpu_clk_setup(node, &mv98dx3236_cpu_ops);
> ++ of_clk_add_provider(node, of_clk_src_simple_get, NULL);
> +}
> +
> +CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
> @@ -285,7 +247,7 @@
> "qcom,gcc-msm8660"
> diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> new file mode 100644
> -index 000000000000..8082ba872edd
> +index 000000000000..26eb9d3aa630
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> +Resume Control
> @@ -304,10 +266,8 @@
> + compatible = "marvell,98dx3336-resume-ctrl";
> + reg = <0x20980 0x10>;
> +};
> -+
> -+
> diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
> -index 46c742d3bd41..59be3ca0464f 100644
> +index 46c742d3bd41..a5b464497e1a 100644
> --- a/arch/arm/mach-mvebu/platsmp.c
> +++ b/arch/arm/mach-mvebu/platsmp.c
>
> @@ -327,7 +287,7 @@
> +static const struct of_device_id of_mv98dx3236_resume_table[] = {
> + {
> + .compatible = "marvell,98dx3336-resume-ctrl",
> -+ .data = (void *)&mv98dx3336_resume_controller,
> ++ .data = &mv98dx3336_resume_controller,
> + },
> + { /* end of list */ },
> +};
> @@ -337,7 +297,7 @@
> + const struct of_device_id *match;
> + struct device_node *np;
> + void __iomem *base;
> -+ struct resume_controller *rc;
> ++ const struct resume_controller *rc;
> +
> + WARN_ON(hw_cpu != 1);
> +
> @@ -347,7 +307,7 @@
> + return -ENODEV;
> +
> + base = of_io_request_and_map(np, 0, of_node_full_name(np));
> -+ rc = (struct resume_controller *)match->data;
> ++ rc = match->data;
> + of_node_put(np);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> @@ -411,15 +371,17 @@
> diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
> new file mode 100644
> -index 000000000000..d4e6ecdfc853
> +index 000000000000..97aef67ee769
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
> +* Marvell 98dx3236 pinctrl driver for mpp
> @@ -435,41 +397,41 @@
> +
> +name pins functions
> +================================================================================
> -+mpp0 0 gpio, spi0(mosi), dev(ad8)
> ++mpp0 0 gpo, spi0(mosi), dev(ad8)
> +mpp1 1 gpio, spi0(miso), dev(ad9)
> -+mpp2 2 gpio, spi0(sck), dev(ad10)
> ++mpp2 2 gpo, spi0(sck), dev(ad10)
> +mpp3 3 gpio, spi0(cs0), dev(ad11)
> +mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
> +mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
> -+mpp6 6 gpio, sd0(clk), dev(a2)
> ++mpp6 6 gpo, sd0(clk), dev(a2)
> +mpp7 7 gpio, sd0(d0), dev(ale0)
> +mpp8 8 gpio, sd0(d1), dev(ale1)
> +mpp9 9 gpio, sd0(d2), dev(ready0)
> +mpp10 10 gpio, sd0(d3), dev(ad12)
> +mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13)
> -+mpp12 12 gpio, uart1(txd), uart0(rts), dev(ad14)
> ++mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14)
> +mpp13 13 gpio, intr(out), dev(ad15)
> +mpp14 14 gpio, i2c0(sck)
> +mpp15 15 gpio, i2c0(sda)
> -+mpp16 16 gpio, dev(oe)
> -+mpp17 17 gpio, dev(clk)
> ++mpp16 16 gpo, dev(oe)
> ++mpp17 17 gpo, dev(clkout)
> +mpp18 18 gpio, uart1(txd)
> +mpp19 19 gpio, uart1(rxd), dev(rb)
> -+mpp20 20 gpio, dev(we)
> -+mpp21 21 gpio, dev(ad0)
> -+mpp22 22 gpio, dev(ad1)
> -+mpp23 23 gpio, dev(ad2)
> -+mpp24 24 gpio, dev(ad3)
> -+mpp25 25 gpio, dev(ad4)
> -+mpp26 26 gpio, dev(ad5)
> -+mpp27 27 gpio, dev(ad6)
> -+mpp28 28 gpio, dev(ad7)
> -+mpp29 29 gpio, dev(a0)
> -+mpp30 30 gpio, dev(a1)
> ++mpp20 20 gpo, dev(we0)
> ++mpp21 21 gpo, dev(ad0)
> ++mpp22 22 gpo, dev(ad1)
> ++mpp23 23 gpo, dev(ad2)
> ++mpp24 24 gpo, dev(ad3)
> ++mpp25 25 gpo, dev(ad4)
> ++mpp26 26 gpo, dev(ad5)
> ++mpp27 27 gpo, dev(ad6)
> ++mpp28 28 gpo, dev(ad7)
> ++mpp29 29 gpo, dev(a0)
> ++mpp30 30 gpo, dev(a1)
> +mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
> +mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
> diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
> -index e4ea71a9d985..554eeae8cd21 100644
> +index 63e1bd506983..61cbc138703e 100644
> --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
> +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
> V_MV78460 = BIT(2),
> @@ -495,8 +457,8 @@
> + MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)),
> + MPP_MODE(2,
> -+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
> -+ MPP_VAR_FUNCTION(0x2, "spi0", "csk", V_98DX3236_PLUS),
> ++ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
> ++ MPP_VAR_FUNCTION(0x2, "spi0", "sck", V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)),
> + MPP_MODE(3,
> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
> @@ -511,7 +473,7 @@
> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251),
> -+ MPP_VAR_FUNCTION(0x4, "dev", "bootcs0", V_98DX3236_PLUS)),
> ++ MPP_VAR_FUNCTION(0x4, "dev", "bootcs", V_98DX3236_PLUS)),
> + MPP_MODE(6,
> + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251),
> @@ -563,7 +525,8 @@
> + MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)),
> + MPP_MODE(19,
> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
> -+ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS)),
> ++ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS),
> ++ MPP_VAR_FUNCTION(0x4, "dev", "rb", V_98DX3236_PLUS)),
> + MPP_MODE(20,
> + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)),
> @@ -630,11 +593,11 @@
> };
>
> +static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = {
> -+ MPP_FUNC_CTRL(0, 32, NULL, armada_xp_mpp_ctrl),
> ++ MPP_FUNC_CTRL(0, 32, NULL, mvebu_mmio_mpp_ctrl),
> +};
> +
> +static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = {
> -+ MPP_GPIO_RANGE(0, 0, 0, 32),
> ++ MPP_GPIO_RANGE(0, 0, 0, 32),
> +};
> +
> static int armada_xp_pinctrl_suspend(struct platform_device *pdev,
> @@ -767,7 +731,7 @@
> +};
> diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
> new file mode 100644
> -index 000000000000..4b7b2fe3b682
> +index 000000000000..9461128fae24
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
> +/*
> @@ -785,17 +749,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -804,11 +768,11 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> @@ -851,9 +815,9 @@
> + MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
> +
> + /*
> -+ * 98DX3236 has 1 x1 PCIe unit Gen2.0: One unit can be
> ++ * 98DX3236 has 1 x1 PCIe unit Gen2.0
> + */
> -+ pcie-controller {
> ++ pciec: pcie-controller@82000000 {
> + compatible = "marvell,armada-xp-pcie";
> + status = "disabled";
> + device_type = "pci";
> @@ -870,7 +834,7 @@
> + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
> + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;
> +
> -+ pcie@1,0 {
> ++ pcie1: pcie@1,0 {
> + device_type = "pci";
> + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
> + reg = <0x0800 0 0 0 0>;
> @@ -967,7 +931,7 @@
> + };
> + };
> +
> -+ dfx-registers {
> ++ dfxr: dfx-registers@ac000000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> @@ -987,7 +951,7 @@
> + };
> + };
> +
> -+ switch {
> ++ switch: switch@a8000000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> @@ -1026,7 +990,7 @@
> +};
> diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
> new file mode 100644
> -index 000000000000..a9b0f47f8df9
> +index 000000000000..e1580afdc260
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
> +/*
> @@ -1044,17 +1008,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -1063,16 +1027,16 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> -+ * Contains definitions specific to the 98dx3336 SoC that are not
> ++ * Contains definitions specific to the 98dx3236 SoC that are not
> + * common to all Armada XP SoCs.
> + */
> +
> @@ -1107,7 +1071,7 @@
> +};
> diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
> new file mode 100644
> -index 000000000000..446e6e65ec59
> +index 000000000000..4b0533a4ccb7
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
> +/*
> @@ -1125,17 +1089,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -1144,11 +1108,11 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> @@ -1213,15 +1177,15 @@
> diff --git a/arch/arm/boot/dts/db-dxbc2.dts b/arch/arm/boot/dts/db-dxbc2.dts
> new file mode 100644
> -index 000000000000..f56786cea5f8
> +index 000000000000..a8130805074e
> --- /dev/null
> +++ b/arch/arm/boot/dts/db-dxbc2.dts
> +/*
> @@ -1241,17 +1205,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -1260,11 +1224,11 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> @@ -1295,66 +1259,58 @@
> + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
> + };
> +
> -+ soc {
> -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
> -+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
> -+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
> -+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
> -+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
> ++};
> +
> -+ devbus-bootcs {
> -+ status = "okay";
> ++&devbus_bootcs {
> ++ status = "okay";
> +
> -+ /* Device Bus parameters are required */
> ++ /* Device Bus parameters are required */
> +
> -+ /* Read parameters */
> -+ devbus,bus-width = <16>;
> -+ devbus,turn-off-ps = <60000>;
> -+ devbus,badr-skew-ps = <0>;
> -+ devbus,acc-first-ps = <124000>;
> -+ devbus,acc-next-ps = <248000>;
> -+ devbus,rd-setup-ps = <0>;
> -+ devbus,rd-hold-ps = <0>;
> -+
> -+ /* Write parameters */
> -+ devbus,sync-enable = <0>;
> -+ devbus,wr-high-ps = <60000>;
> -+ devbus,wr-low-ps = <60000>;
> -+ devbus,ale-wr-ps = <60000>;
> -+ };
> ++ /* Read parameters */
> ++ devbus,bus-width = <16>;
> ++ devbus,turn-off-ps = <60000>;
> ++ devbus,badr-skew-ps = <0>;
> ++ devbus,acc-first-ps = <124000>;
> ++ devbus,acc-next-ps = <248000>;
> ++ devbus,rd-setup-ps = <0>;
> ++ devbus,rd-hold-ps = <0>;
> ++
> ++ /* Write parameters */
> ++ devbus,sync-enable = <0>;
> ++ devbus,wr-high-ps = <60000>;
> ++ devbus,wr-low-ps = <60000>;
> ++ devbus,ale-wr-ps = <60000>;
> ++};
> +
> -+ internal-regs {
> -+ serial@12000 {
> -+ status = "okay";
> -+ };
> -+ serial@12100 {
> -+ status = "okay";
> -+ };
> ++&i2c0 {
> ++ clock-frequency = <100000>;
> ++ status = "okay";
> ++};
> +
> -+ i2c@11000 {
> -+ clock-frequency = <100000>;
> -+ status = "okay";
> -+ };
> ++&uart0 {
> ++ status = "okay";
> ++};
> +
> -+ mvsdio@d4000 {
> -+ pinctrl-0 = <&sdio_pins>;
> -+ pinctrl-names = "default";
> -+ status = "okay";
> -+ /* No CD or WP GPIOs */
> -+ broken-cd;
> -+ };
> ++&uart1 {
> ++ status = "okay";
> ++};
> +
> -+ nand@d0000 {
> -+ status = "okay";
> -+ num-cs = <1>;
> -+ marvell,nand-keep-config;
> -+ marvell,nand-enable-arbiter;
> -+ nand-on-flash-bbt;
> -+ nand-ecc-strength = <4>;
> -+ nand-ecc-step-size = <512>;
> -+ };
> -+ };
> -+ };
> ++&nand {
> ++ status = "okay";
> ++ num-cs = <1>;
> ++ marvell,nand-keep-config;
> ++ marvell,nand-enable-arbiter;
> ++ nand-on-flash-bbt;
> ++ nand-ecc-strength = <4>;
> ++ nand-ecc-step-size = <512>;
> ++};
> ++
> ++&sdio {
> ++ pinctrl-0 = <&sdio_pins>;
> ++ pinctrl-names = "default";
> ++ status = "okay";
> ++ /* No CD or WP GPIOs */
> ++ broken-cd;
> +};
> +
> +&spi0 {
> @@ -1385,7 +1341,7 @@
> +};
> diff --git a/arch/arm/boot/dts/db-xc3-24g4xg.dts b/arch/arm/boot/dts/db-xc3-24g4xg.dts
> new file mode 100644
> -index 000000000000..5eb89ffb9a7d
> +index 000000000000..4e07cb6ed800
> --- /dev/null
> +++ b/arch/arm/boot/dts/db-xc3-24g4xg.dts
> +/*
> @@ -1405,17 +1361,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -1424,11 +1380,11 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> @@ -1458,63 +1414,50 @@
> + device_type = "memory";
> + reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
> + };
> ++};
> +
> -+ soc {
> -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
> -+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
> -+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
> -+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
> -+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
> -+
> -+ devbus-bootcs {
> -+ status = "okay";
> ++&devbus_bootcs {
> ++ status = "okay";
> +
> -+ /* Device Bus parameters are required */
> ++ /* Device Bus parameters are required */
> +
> -+ /* Read parameters */
> -+ devbus,bus-width = <16>;
> -+ devbus,turn-off-ps = <60000>;
> -+ devbus,badr-skew-ps = <0>;
> -+ devbus,acc-first-ps = <124000>;
> -+ devbus,acc-next-ps = <248000>;
> -+ devbus,rd-setup-ps = <0>;
> -+ devbus,rd-hold-ps = <0>;
> -+
> -+ /* Write parameters */
> -+ devbus,sync-enable = <0>;
> -+ devbus,wr-high-ps = <60000>;
> -+ devbus,wr-low-ps = <60000>;
> -+ devbus,ale-wr-ps = <60000>;
> -+ };
> ++ /* Read parameters */
> ++ devbus,bus-width = <16>;
> ++ devbus,turn-off-ps = <60000>;
> ++ devbus,badr-skew-ps = <0>;
> ++ devbus,acc-first-ps = <124000>;
> ++ devbus,acc-next-ps = <248000>;
> ++ devbus,rd-setup-ps = <0>;
> ++ devbus,rd-hold-ps = <0>;
> ++
> ++ /* Write parameters */
> ++ devbus,sync-enable = <0>;
> ++ devbus,wr-high-ps = <60000>;
> ++ devbus,wr-low-ps = <60000>;
> ++ devbus,ale-wr-ps = <60000>;
> ++};
> +
> -+ internal-regs {
> -+ serial@12000 {
> -+ status = "okay";
> -+ };
> -+ serial@12100 {
> -+ status = "okay";
> -+ };
> ++&uart0 {
> ++ status = "okay";
> ++};
> +
> -+ i2c@11000 {
> -+ clock-frequency = <100000>;
> -+ status = "okay";
> -+ };
> ++&uart1 {
> ++ status = "okay";
> ++};
> +
> -+ mvsdio@d4000 {
> -+ status = "disabled";
> -+ };
> ++&i2c0 {
> ++ clock-frequency = <100000>;
> ++ status = "okay";
> ++};
> +
> -+ nand@d0000 {
> -+ status = "okay";
> -+ num-cs = <1>;
> -+ marvell,nand-keep-config;
> -+ marvell,nand-enable-arbiter;
> -+ nand-on-flash-bbt;
> -+ nand-ecc-strength = <4>;
> -+ nand-ecc-step-size = <512>;
> -+ };
> -+ };
> -+ };
> ++&nand {
> ++ status = "okay";
> ++ num-cs = <1>;
> ++ marvell,nand-keep-config;
> ++ marvell,nand-enable-arbiter;
> ++ nand-on-flash-bbt;
> ++ nand-ecc-strength = <4>;
> ++ nand-ecc-step-size = <512>;
> +};
> +
> +&spi0 {
>
> --
> 2.11.0.24.ge6920cf
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-27 16:39 ` Gregory CLEMENT
0 siblings, 0 replies; 49+ messages in thread
From: Gregory CLEMENT @ 2017-01-27 16:39 UTC (permalink / raw)
To: Stephen Boyd, Linus Walleij, Chris Packham
Cc: linux, linux-arm-kernel, Rob Herring, Mark Rutland,
Michael Turquette, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Geert Uytterhoeven, Chris Brand,
Florian Fainelli, Arnd Bergmann, Thierry Reding, Sudeep Holla,
Juri Lelli, Thomas Petazzoni, Laxman Dewangan, Kalyan Kinthada,
devicetree, linux-kernel, linux-clk, linux-gpio
Hi all,
On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
> integrated CPUs. They CPU block is common within these product lines and
> (as far as I can tell/have been told) is based on the Armada XP. There
> are a few differences due to the fact they have to squeeze the CPU into
> the same package as the switch.
>
> I've rebased this series against linux-pinctrl/devel to get access to
> mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to
> v4.10.0-rc5.
Just to let you know that I plan to apply the 3 arm patch once Chris
will have sent the new series with the minor fixes I asked on patch 3.
I already applied them in the for-next branch to benefit of some build
test coverage.
Stephen,
you gave your Acked-by on the first patch, but don't you plan to apply
it on the clk branch?
If you really want I can apply on mvebu but there is no build
dependencies, so the order the patches will be merged is not important.
Linus,
I expect you will apply the pinctrl patch on your tree as it depend of
code already there.
Thanks,
Gregory
>
> Chris Packham (4):
> clk: mvebu: support for 98DX3236 SoC
> Changes in v2:
> - Update devicetree binding documentation for new compatible string
> Changes in v3:
> - Add 98dx3236 support to mvebu/clk-corediv.c rather than creating a new
> driver.
> - Document mv98dx3236-corediv-clock binding
> Changes in v4:
> - None
> Changes in v5:
> - Collect ack from Rob
> - Remove explicit initialisation of fields to 0 in mv98dx3236_coreclks
> - Register dummy clock provider for marvell,mv98dx3236-cpu-clock
> arm: mvebu: support for SMP on 98DX3336 SoC
> Changes in v2:
> - Document new enable-method value
> - Correct some references from 98DX4521 to 98DX3236
> Changes in v3:
> - Simplify mv98dx3236_resume_init by using of_io_request_and_map()
> Changes in v4:
> - integrate changes into platsmp.c instead of new init call
> - avoid duplicated code.
> - fix error return
> - Collect ack from Rob
> Changes in v5:
> - Remove useless casts (thanks to Stephen Boyd)
> arm: mvebu: Add device tree for 98DX3236 SoCs
> Changes in v2:
> - Update devicetree binding documentation to reflect that 98DX3336 and
> 984251 are supersets of 98DX3236.
> - disable crypto block
> - disable sdio for 98DX3236, enable for 98DX4251
> Changes in v3:
> - fix typo 4521 -> 4251
> - document prestera bindings
> - rework corediv-clock binding
> - add label to packet processor node
> - add new compatible string for DFX server
> Changes in v4:
> - Collect ack from Rob
> Changes in v5:
> - Fixup license text. Add labels to nodes.
> arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
> Changes in v5:
> - update license text
> - use node labels
>
> Kalyan Kinthada (1):
> pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
> Changes in v2:
> - include sdio support for the 98DX4251
> Changes in v3:
> - None
> Changes in v4:
> - Correct some discrepencies between binding and driver.
> - Collect acks from Rob and Sebastian
> Changes in v5:
> - Update bindings to reflect "gpo" pins
> - Use mvebu_mmio_mpp_ctrl instead of armada_xp_mpp_ctrl (note this is reliant
> on changes queued in linux-pinctrl)
>
> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> .../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 16 ++
> .../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ++
> .../bindings/clock/mvebu-corediv-clock.txt | 1 +
> .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 1 +
> .../devicetree/bindings/net/marvell,prestera.txt | 50 ++++
> .../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++
> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 254 +++++++++++++++++++++
> arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 76 ++++++
> arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 90 ++++++++
> arch/arm/boot/dts/db-dxbc2.dts | 151 ++++++++++++
> arch/arm/boot/dts/db-xc3-24g4xg.dts | 142 ++++++++++++
> arch/arm/mach-mvebu/platsmp.c | 86 +++++++
> drivers/clk/mvebu/armada-xp.c | 39 ++++
> drivers/clk/mvebu/clk-corediv.c | 23 ++
> drivers/clk/mvebu/clk-cpu.c | 8 +
> drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 156 +++++++++++++
> 17 files changed, 1163 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
> create mode 100644 Documentation/devicetree/bindings/net/marvell,prestera.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
> create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
> create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
> create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
>
> interdiff to v4:
>
> diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
> index 520562a7dc2a..c7b4e3a6b2c6 100644
> @@ -85,7 +86,7 @@
> by address and length of the PMU DFS registers
> - #clock-cells : should be set to 1.
> diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
> -index b3094315a3c0..0413bf8284e0 100644
> +index b3094315a3c0..890a863ae0d0 100644
> --- a/drivers/clk/mvebu/armada-xp.c
> +++ b/drivers/clk/mvebu/armada-xp.c
> return 250000000;
> @@ -118,9 +119,6 @@
> +static const struct coreclk_soc_desc mv98dx3236_coreclks = {
> + .get_tclk_freq = mv98dx3236_get_tclk_freq,
> + .get_cpu_freq = mv98dx3236_get_cpu_freq,
> -+ .get_clk_ratio = NULL,
> -+ .ratios = NULL,
> -+ .num_ratios = 0,
> +};
> +
> /*
> @@ -200,53 +198,16 @@
> +CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock",
> + mv98dx3236_corediv_clk_init);
> diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
> -index 5837eb8a212f..3b8f0e14fa01 100644
> +index 5837eb8a212f..044892b6534d 100644
> --- a/drivers/clk/mvebu/clk-cpu.c
> +++ b/drivers/clk/mvebu/clk-cpu.c
> - .set_rate = clk_cpu_set_rate,
> - };
> -
> --static void __init of_cpu_clk_setup(struct device_node *node)
> -+/* Add parameter to allow this to support different clock operations. */
> -+static void __init _of_cpu_clk_setup(struct device_node *node,
> -+ const struct clk_ops *cpu_clk_ops)
> - {
> - struct cpu_clk *cpuclk;
> - void __iomem *clock_complex_base = of_iomap(node, 0);
> - cpuclk[cpu].hw.init = &init;
>
> - init.name = cpuclk[cpu].clk_name;
> -- init.ops = &cpu_ops;
> -+ init.ops = cpu_clk_ops;
> - init.flags = 0;
> - init.parent_names = &cpuclk[cpu].parent_name;
> - init.num_parents = 1;
> - iounmap(clock_complex_base);
> - }
> -
> -+/* Use this function to call the generic setup with the correct
> -+ * clock operation
> -+ */
> -+static void __init of_cpu_clk_setup(struct device_node *node)
> -+{
> -+ _of_cpu_clk_setup(node, &cpu_ops);
> -+}
> -+
> CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
> of_cpu_clk_setup);
> +
> -+/* Define the clock and operations for the mv98dx3236 - it cannot perform
> -+ * any operations.
> -+ */
> -+static const struct clk_ops mv98dx3236_cpu_ops = {
> -+ .recalc_rate = NULL,
> -+ .round_rate = NULL,
> -+ .set_rate = NULL,
> -+};
> -+
> +static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
> +{
> -+ _of_cpu_clk_setup(node, &mv98dx3236_cpu_ops);
> ++ of_clk_add_provider(node, of_clk_src_simple_get, NULL);
> +}
> +
> +CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
> @@ -285,7 +247,7 @@
> "qcom,gcc-msm8660"
> diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> new file mode 100644
> -index 000000000000..8082ba872edd
> +index 000000000000..26eb9d3aa630
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> +Resume Control
> @@ -304,10 +266,8 @@
> + compatible = "marvell,98dx3336-resume-ctrl";
> + reg = <0x20980 0x10>;
> +};
> -+
> -+
> diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
> -index 46c742d3bd41..59be3ca0464f 100644
> +index 46c742d3bd41..a5b464497e1a 100644
> --- a/arch/arm/mach-mvebu/platsmp.c
> +++ b/arch/arm/mach-mvebu/platsmp.c
>
> @@ -327,7 +287,7 @@
> +static const struct of_device_id of_mv98dx3236_resume_table[] = {
> + {
> + .compatible = "marvell,98dx3336-resume-ctrl",
> -+ .data = (void *)&mv98dx3336_resume_controller,
> ++ .data = &mv98dx3336_resume_controller,
> + },
> + { /* end of list */ },
> +};
> @@ -337,7 +297,7 @@
> + const struct of_device_id *match;
> + struct device_node *np;
> + void __iomem *base;
> -+ struct resume_controller *rc;
> ++ const struct resume_controller *rc;
> +
> + WARN_ON(hw_cpu != 1);
> +
> @@ -347,7 +307,7 @@
> + return -ENODEV;
> +
> + base = of_io_request_and_map(np, 0, of_node_full_name(np));
> -+ rc = (struct resume_controller *)match->data;
> ++ rc = match->data;
> + of_node_put(np);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> @@ -411,15 +371,17 @@
> diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
> new file mode 100644
> -index 000000000000..d4e6ecdfc853
> +index 000000000000..97aef67ee769
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
> +* Marvell 98dx3236 pinctrl driver for mpp
> @@ -435,41 +397,41 @@
> +
> +name pins functions
> +================================================================================
> -+mpp0 0 gpio, spi0(mosi), dev(ad8)
> ++mpp0 0 gpo, spi0(mosi), dev(ad8)
> +mpp1 1 gpio, spi0(miso), dev(ad9)
> -+mpp2 2 gpio, spi0(sck), dev(ad10)
> ++mpp2 2 gpo, spi0(sck), dev(ad10)
> +mpp3 3 gpio, spi0(cs0), dev(ad11)
> +mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
> +mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
> -+mpp6 6 gpio, sd0(clk), dev(a2)
> ++mpp6 6 gpo, sd0(clk), dev(a2)
> +mpp7 7 gpio, sd0(d0), dev(ale0)
> +mpp8 8 gpio, sd0(d1), dev(ale1)
> +mpp9 9 gpio, sd0(d2), dev(ready0)
> +mpp10 10 gpio, sd0(d3), dev(ad12)
> +mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13)
> -+mpp12 12 gpio, uart1(txd), uart0(rts), dev(ad14)
> ++mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14)
> +mpp13 13 gpio, intr(out), dev(ad15)
> +mpp14 14 gpio, i2c0(sck)
> +mpp15 15 gpio, i2c0(sda)
> -+mpp16 16 gpio, dev(oe)
> -+mpp17 17 gpio, dev(clk)
> ++mpp16 16 gpo, dev(oe)
> ++mpp17 17 gpo, dev(clkout)
> +mpp18 18 gpio, uart1(txd)
> +mpp19 19 gpio, uart1(rxd), dev(rb)
> -+mpp20 20 gpio, dev(we)
> -+mpp21 21 gpio, dev(ad0)
> -+mpp22 22 gpio, dev(ad1)
> -+mpp23 23 gpio, dev(ad2)
> -+mpp24 24 gpio, dev(ad3)
> -+mpp25 25 gpio, dev(ad4)
> -+mpp26 26 gpio, dev(ad5)
> -+mpp27 27 gpio, dev(ad6)
> -+mpp28 28 gpio, dev(ad7)
> -+mpp29 29 gpio, dev(a0)
> -+mpp30 30 gpio, dev(a1)
> ++mpp20 20 gpo, dev(we0)
> ++mpp21 21 gpo, dev(ad0)
> ++mpp22 22 gpo, dev(ad1)
> ++mpp23 23 gpo, dev(ad2)
> ++mpp24 24 gpo, dev(ad3)
> ++mpp25 25 gpo, dev(ad4)
> ++mpp26 26 gpo, dev(ad5)
> ++mpp27 27 gpo, dev(ad6)
> ++mpp28 28 gpo, dev(ad7)
> ++mpp29 29 gpo, dev(a0)
> ++mpp30 30 gpo, dev(a1)
> +mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
> +mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
> diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
> -index e4ea71a9d985..554eeae8cd21 100644
> +index 63e1bd506983..61cbc138703e 100644
> --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
> +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
> V_MV78460 = BIT(2),
> @@ -495,8 +457,8 @@
> + MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)),
> + MPP_MODE(2,
> -+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
> -+ MPP_VAR_FUNCTION(0x2, "spi0", "csk", V_98DX3236_PLUS),
> ++ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
> ++ MPP_VAR_FUNCTION(0x2, "spi0", "sck", V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)),
> + MPP_MODE(3,
> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
> @@ -511,7 +473,7 @@
> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251),
> -+ MPP_VAR_FUNCTION(0x4, "dev", "bootcs0", V_98DX3236_PLUS)),
> ++ MPP_VAR_FUNCTION(0x4, "dev", "bootcs", V_98DX3236_PLUS)),
> + MPP_MODE(6,
> + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251),
> @@ -563,7 +525,8 @@
> + MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)),
> + MPP_MODE(19,
> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
> -+ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS)),
> ++ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS),
> ++ MPP_VAR_FUNCTION(0x4, "dev", "rb", V_98DX3236_PLUS)),
> + MPP_MODE(20,
> + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
> + MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)),
> @@ -630,11 +593,11 @@
> };
>
> +static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = {
> -+ MPP_FUNC_CTRL(0, 32, NULL, armada_xp_mpp_ctrl),
> ++ MPP_FUNC_CTRL(0, 32, NULL, mvebu_mmio_mpp_ctrl),
> +};
> +
> +static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = {
> -+ MPP_GPIO_RANGE(0, 0, 0, 32),
> ++ MPP_GPIO_RANGE(0, 0, 0, 32),
> +};
> +
> static int armada_xp_pinctrl_suspend(struct platform_device *pdev,
> @@ -767,7 +731,7 @@
> +};
> diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
> new file mode 100644
> -index 000000000000..4b7b2fe3b682
> +index 000000000000..9461128fae24
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
> +/*
> @@ -785,17 +749,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -804,11 +768,11 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> @@ -851,9 +815,9 @@
> + MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
> +
> + /*
> -+ * 98DX3236 has 1 x1 PCIe unit Gen2.0: One unit can be
> ++ * 98DX3236 has 1 x1 PCIe unit Gen2.0
> + */
> -+ pcie-controller {
> ++ pciec: pcie-controller@82000000 {
> + compatible = "marvell,armada-xp-pcie";
> + status = "disabled";
> + device_type = "pci";
> @@ -870,7 +834,7 @@
> + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
> + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;
> +
> -+ pcie@1,0 {
> ++ pcie1: pcie@1,0 {
> + device_type = "pci";
> + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
> + reg = <0x0800 0 0 0 0>;
> @@ -967,7 +931,7 @@
> + };
> + };
> +
> -+ dfx-registers {
> ++ dfxr: dfx-registers@ac000000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> @@ -987,7 +951,7 @@
> + };
> + };
> +
> -+ switch {
> ++ switch: switch@a8000000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> @@ -1026,7 +990,7 @@
> +};
> diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
> new file mode 100644
> -index 000000000000..a9b0f47f8df9
> +index 000000000000..e1580afdc260
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
> +/*
> @@ -1044,17 +1008,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -1063,16 +1027,16 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> -+ * Contains definitions specific to the 98dx3336 SoC that are not
> ++ * Contains definitions specific to the 98dx3236 SoC that are not
> + * common to all Armada XP SoCs.
> + */
> +
> @@ -1107,7 +1071,7 @@
> +};
> diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
> new file mode 100644
> -index 000000000000..446e6e65ec59
> +index 000000000000..4b0533a4ccb7
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
> +/*
> @@ -1125,17 +1089,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -1144,11 +1108,11 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> @@ -1213,15 +1177,15 @@
> diff --git a/arch/arm/boot/dts/db-dxbc2.dts b/arch/arm/boot/dts/db-dxbc2.dts
> new file mode 100644
> -index 000000000000..f56786cea5f8
> +index 000000000000..a8130805074e
> --- /dev/null
> +++ b/arch/arm/boot/dts/db-dxbc2.dts
> +/*
> @@ -1241,17 +1205,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -1260,11 +1224,11 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> @@ -1295,66 +1259,58 @@
> + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
> + };
> +
> -+ soc {
> -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
> -+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
> -+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
> -+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
> -+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
> ++};
> +
> -+ devbus-bootcs {
> -+ status = "okay";
> ++&devbus_bootcs {
> ++ status = "okay";
> +
> -+ /* Device Bus parameters are required */
> ++ /* Device Bus parameters are required */
> +
> -+ /* Read parameters */
> -+ devbus,bus-width = <16>;
> -+ devbus,turn-off-ps = <60000>;
> -+ devbus,badr-skew-ps = <0>;
> -+ devbus,acc-first-ps = <124000>;
> -+ devbus,acc-next-ps = <248000>;
> -+ devbus,rd-setup-ps = <0>;
> -+ devbus,rd-hold-ps = <0>;
> -+
> -+ /* Write parameters */
> -+ devbus,sync-enable = <0>;
> -+ devbus,wr-high-ps = <60000>;
> -+ devbus,wr-low-ps = <60000>;
> -+ devbus,ale-wr-ps = <60000>;
> -+ };
> ++ /* Read parameters */
> ++ devbus,bus-width = <16>;
> ++ devbus,turn-off-ps = <60000>;
> ++ devbus,badr-skew-ps = <0>;
> ++ devbus,acc-first-ps = <124000>;
> ++ devbus,acc-next-ps = <248000>;
> ++ devbus,rd-setup-ps = <0>;
> ++ devbus,rd-hold-ps = <0>;
> ++
> ++ /* Write parameters */
> ++ devbus,sync-enable = <0>;
> ++ devbus,wr-high-ps = <60000>;
> ++ devbus,wr-low-ps = <60000>;
> ++ devbus,ale-wr-ps = <60000>;
> ++};
> +
> -+ internal-regs {
> -+ serial@12000 {
> -+ status = "okay";
> -+ };
> -+ serial@12100 {
> -+ status = "okay";
> -+ };
> ++&i2c0 {
> ++ clock-frequency = <100000>;
> ++ status = "okay";
> ++};
> +
> -+ i2c@11000 {
> -+ clock-frequency = <100000>;
> -+ status = "okay";
> -+ };
> ++&uart0 {
> ++ status = "okay";
> ++};
> +
> -+ mvsdio@d4000 {
> -+ pinctrl-0 = <&sdio_pins>;
> -+ pinctrl-names = "default";
> -+ status = "okay";
> -+ /* No CD or WP GPIOs */
> -+ broken-cd;
> -+ };
> ++&uart1 {
> ++ status = "okay";
> ++};
> +
> -+ nand@d0000 {
> -+ status = "okay";
> -+ num-cs = <1>;
> -+ marvell,nand-keep-config;
> -+ marvell,nand-enable-arbiter;
> -+ nand-on-flash-bbt;
> -+ nand-ecc-strength = <4>;
> -+ nand-ecc-step-size = <512>;
> -+ };
> -+ };
> -+ };
> ++&nand {
> ++ status = "okay";
> ++ num-cs = <1>;
> ++ marvell,nand-keep-config;
> ++ marvell,nand-enable-arbiter;
> ++ nand-on-flash-bbt;
> ++ nand-ecc-strength = <4>;
> ++ nand-ecc-step-size = <512>;
> ++};
> ++
> ++&sdio {
> ++ pinctrl-0 = <&sdio_pins>;
> ++ pinctrl-names = "default";
> ++ status = "okay";
> ++ /* No CD or WP GPIOs */
> ++ broken-cd;
> +};
> +
> +&spi0 {
> @@ -1385,7 +1341,7 @@
> +};
> diff --git a/arch/arm/boot/dts/db-xc3-24g4xg.dts b/arch/arm/boot/dts/db-xc3-24g4xg.dts
> new file mode 100644
> -index 000000000000..5eb89ffb9a7d
> +index 000000000000..4e07cb6ed800
> --- /dev/null
> +++ b/arch/arm/boot/dts/db-xc3-24g4xg.dts
> +/*
> @@ -1405,17 +1361,17 @@
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> -+ * This file is distributed in the hope that it will be useful
> ++ * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> -+ * Or, alternatively
> ++ * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> -+ * restriction, including without limitation the rights to use
> ++ * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> @@ -1424,11 +1380,11 @@
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> @@ -1458,63 +1414,50 @@
> + device_type = "memory";
> + reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
> + };
> ++};
> +
> -+ soc {
> -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
> -+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
> -+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
> -+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
> -+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
> -+
> -+ devbus-bootcs {
> -+ status = "okay";
> ++&devbus_bootcs {
> ++ status = "okay";
> +
> -+ /* Device Bus parameters are required */
> ++ /* Device Bus parameters are required */
> +
> -+ /* Read parameters */
> -+ devbus,bus-width = <16>;
> -+ devbus,turn-off-ps = <60000>;
> -+ devbus,badr-skew-ps = <0>;
> -+ devbus,acc-first-ps = <124000>;
> -+ devbus,acc-next-ps = <248000>;
> -+ devbus,rd-setup-ps = <0>;
> -+ devbus,rd-hold-ps = <0>;
> -+
> -+ /* Write parameters */
> -+ devbus,sync-enable = <0>;
> -+ devbus,wr-high-ps = <60000>;
> -+ devbus,wr-low-ps = <60000>;
> -+ devbus,ale-wr-ps = <60000>;
> -+ };
> ++ /* Read parameters */
> ++ devbus,bus-width = <16>;
> ++ devbus,turn-off-ps = <60000>;
> ++ devbus,badr-skew-ps = <0>;
> ++ devbus,acc-first-ps = <124000>;
> ++ devbus,acc-next-ps = <248000>;
> ++ devbus,rd-setup-ps = <0>;
> ++ devbus,rd-hold-ps = <0>;
> ++
> ++ /* Write parameters */
> ++ devbus,sync-enable = <0>;
> ++ devbus,wr-high-ps = <60000>;
> ++ devbus,wr-low-ps = <60000>;
> ++ devbus,ale-wr-ps = <60000>;
> ++};
> +
> -+ internal-regs {
> -+ serial@12000 {
> -+ status = "okay";
> -+ };
> -+ serial@12100 {
> -+ status = "okay";
> -+ };
> ++&uart0 {
> ++ status = "okay";
> ++};
> +
> -+ i2c@11000 {
> -+ clock-frequency = <100000>;
> -+ status = "okay";
> -+ };
> ++&uart1 {
> ++ status = "okay";
> ++};
> +
> -+ mvsdio@d4000 {
> -+ status = "disabled";
> -+ };
> ++&i2c0 {
> ++ clock-frequency = <100000>;
> ++ status = "okay";
> ++};
> +
> -+ nand@d0000 {
> -+ status = "okay";
> -+ num-cs = <1>;
> -+ marvell,nand-keep-config;
> -+ marvell,nand-enable-arbiter;
> -+ nand-on-flash-bbt;
> -+ nand-ecc-strength = <4>;
> -+ nand-ecc-step-size = <512>;
> -+ };
> -+ };
> -+ };
> ++&nand {
> ++ status = "okay";
> ++ num-cs = <1>;
> ++ marvell,nand-keep-config;
> ++ marvell,nand-enable-arbiter;
> ++ nand-on-flash-bbt;
> ++ nand-ecc-strength = <4>;
> ++ nand-ecc-step-size = <512>;
> +};
> +
> +&spi0 {
>
> --
> 2.11.0.24.ge6920cf
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
2017-01-27 16:39 ` Gregory CLEMENT
(?)
(?)
@ 2017-01-27 16:49 ` Gregory CLEMENT
-1 siblings, 0 replies; 49+ messages in thread
From: Gregory CLEMENT @ 2017-01-27 16:49 UTC (permalink / raw)
To: Stephen Boyd
Cc: Linus Walleij, Chris Packham, Mark Rutland, Andrew Lunn,
Geert Uytterhoeven, Michael Turquette, Laxman Dewangan,
linux-clk, Florian Fainelli, Juri Lelli, linux, Thierry Reding,
Sebastian Hesselbarth, devicetree, Jason Cooper, Arnd Bergmann,
linux-gpio, Rob Herring, Chris Brand, linux-arm-kernel,
Thomas Petazzoni
Hi,
On ven., janv. 27 2017, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:
> Hi all,
>
> On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
>
>> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
>> integrated CPUs. They CPU block is common within these product lines and
>> (as far as I can tell/have been told) is based on the Armada XP. There
>> are a few differences due to the fact they have to squeeze the CPU into
>> the same package as the switch.
>>
>> I've rebased this series against linux-pinctrl/devel to get access to
>> mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to
>> v4.10.0-rc5.
>
> Just to let you know that I plan to apply the 3 arm patch once Chris
> will have sent the new series with the minor fixes I asked on patch 3.
I meant patch 2!
And now patch 5 too :)
Gregory
> I already applied them in the for-next branch to benefit of some build
> test coverage.
>
> Stephen,
>
> you gave your Acked-by on the first patch, but don't you plan to apply
> it on the clk branch?
>
> If you really want I can apply on mvebu but there is no build
> dependencies, so the order the patches will be merged is not important.
>
> Linus,
>
> I expect you will apply the pinctrl patch on your tree as it depend of
> code already there.
>
> Thanks,
>
> Gregory
>
>>
>> Chris Packham (4):
>> clk: mvebu: support for 98DX3236 SoC
>> Changes in v2:
>> - Update devicetree binding documentation for new compatible string
>> Changes in v3:
>> - Add 98dx3236 support to mvebu/clk-corediv.c rather than creating a new
>> driver.
>> - Document mv98dx3236-corediv-clock binding
>> Changes in v4:
>> - None
>> Changes in v5:
>> - Collect ack from Rob
>> - Remove explicit initialisation of fields to 0 in mv98dx3236_coreclks
>> - Register dummy clock provider for marvell,mv98dx3236-cpu-clock
>> arm: mvebu: support for SMP on 98DX3336 SoC
>> Changes in v2:
>> - Document new enable-method value
>> - Correct some references from 98DX4521 to 98DX3236
>> Changes in v3:
>> - Simplify mv98dx3236_resume_init by using of_io_request_and_map()
>> Changes in v4:
>> - integrate changes into platsmp.c instead of new init call
>> - avoid duplicated code.
>> - fix error return
>> - Collect ack from Rob
>> Changes in v5:
>> - Remove useless casts (thanks to Stephen Boyd)
>> arm: mvebu: Add device tree for 98DX3236 SoCs
>> Changes in v2:
>> - Update devicetree binding documentation to reflect that 98DX3336 and
>> 984251 are supersets of 98DX3236.
>> - disable crypto block
>> - disable sdio for 98DX3236, enable for 98DX4251
>> Changes in v3:
>> - fix typo 4521 -> 4251
>> - document prestera bindings
>> - rework corediv-clock binding
>> - add label to packet processor node
>> - add new compatible string for DFX server
>> Changes in v4:
>> - Collect ack from Rob
>> Changes in v5:
>> - Fixup license text. Add labels to nodes.
>> arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
>> Changes in v5:
>> - update license text
>> - use node labels
>>
>> Kalyan Kinthada (1):
>> pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
>> Changes in v2:
>> - include sdio support for the 98DX4251
>> Changes in v3:
>> - None
>> Changes in v4:
>> - Correct some discrepencies between binding and driver.
>> - Collect acks from Rob and Sebastian
>> Changes in v5:
>> - Update bindings to reflect "gpo" pins
>> - Use mvebu_mmio_mpp_ctrl instead of armada_xp_mpp_ctrl (note this is reliant
>> on changes queued in linux-pinctrl)
>>
>> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
>> .../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 16 ++
>> .../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ++
>> .../bindings/clock/mvebu-corediv-clock.txt | 1 +
>> .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 1 +
>> .../devicetree/bindings/net/marvell,prestera.txt | 50 ++++
>> .../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++
>> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 254 +++++++++++++++++++++
>> arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 76 ++++++
>> arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 90 ++++++++
>> arch/arm/boot/dts/db-dxbc2.dts | 151 ++++++++++++
>> arch/arm/boot/dts/db-xc3-24g4xg.dts | 142 ++++++++++++
>> arch/arm/mach-mvebu/platsmp.c | 86 +++++++
>> drivers/clk/mvebu/armada-xp.c | 39 ++++
>> drivers/clk/mvebu/clk-corediv.c | 23 ++
>> drivers/clk/mvebu/clk-cpu.c | 8 +
>> drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 156 +++++++++++++
>> 17 files changed, 1163 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
>> create mode 100644 Documentation/devicetree/bindings/net/marvell,prestera.txt
>> create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
>> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
>> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
>> create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
>> create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
>> create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
>>
>> interdiff to v4:
>>
>> diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
>> index 520562a7dc2a..c7b4e3a6b2c6 100644
>> @@ -85,7 +86,7 @@
>> by address and length of the PMU DFS registers
>> - #clock-cells : should be set to 1.
>> diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
>> -index b3094315a3c0..0413bf8284e0 100644
>> +index b3094315a3c0..890a863ae0d0 100644
>> --- a/drivers/clk/mvebu/armada-xp.c
>> +++ b/drivers/clk/mvebu/armada-xp.c
>> return 250000000;
>> @@ -118,9 +119,6 @@
>> +static const struct coreclk_soc_desc mv98dx3236_coreclks = {
>> + .get_tclk_freq = mv98dx3236_get_tclk_freq,
>> + .get_cpu_freq = mv98dx3236_get_cpu_freq,
>> -+ .get_clk_ratio = NULL,
>> -+ .ratios = NULL,
>> -+ .num_ratios = 0,
>> +};
>> +
>> /*
>> @@ -200,53 +198,16 @@
>> +CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock",
>> + mv98dx3236_corediv_clk_init);
>> diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
>> -index 5837eb8a212f..3b8f0e14fa01 100644
>> +index 5837eb8a212f..044892b6534d 100644
>> --- a/drivers/clk/mvebu/clk-cpu.c
>> +++ b/drivers/clk/mvebu/clk-cpu.c
>> - .set_rate = clk_cpu_set_rate,
>> - };
>> -
>> --static void __init of_cpu_clk_setup(struct device_node *node)
>> -+/* Add parameter to allow this to support different clock operations. */
>> -+static void __init _of_cpu_clk_setup(struct device_node *node,
>> -+ const struct clk_ops *cpu_clk_ops)
>> - {
>> - struct cpu_clk *cpuclk;
>> - void __iomem *clock_complex_base = of_iomap(node, 0);
>> - cpuclk[cpu].hw.init = &init;
>>
>> - init.name = cpuclk[cpu].clk_name;
>> -- init.ops = &cpu_ops;
>> -+ init.ops = cpu_clk_ops;
>> - init.flags = 0;
>> - init.parent_names = &cpuclk[cpu].parent_name;
>> - init.num_parents = 1;
>> - iounmap(clock_complex_base);
>> - }
>> -
>> -+/* Use this function to call the generic setup with the correct
>> -+ * clock operation
>> -+ */
>> -+static void __init of_cpu_clk_setup(struct device_node *node)
>> -+{
>> -+ _of_cpu_clk_setup(node, &cpu_ops);
>> -+}
>> -+
>> CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
>> of_cpu_clk_setup);
>> +
>> -+/* Define the clock and operations for the mv98dx3236 - it cannot perform
>> -+ * any operations.
>> -+ */
>> -+static const struct clk_ops mv98dx3236_cpu_ops = {
>> -+ .recalc_rate = NULL,
>> -+ .round_rate = NULL,
>> -+ .set_rate = NULL,
>> -+};
>> -+
>> +static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
>> +{
>> -+ _of_cpu_clk_setup(node, &mv98dx3236_cpu_ops);
>> ++ of_clk_add_provider(node, of_clk_src_simple_get, NULL);
>> +}
>> +
>> +CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
>> @@ -285,7 +247,7 @@
>> "qcom,gcc-msm8660"
>> diff --git
> a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
>> new file mode 100644
>> -index 000000000000..8082ba872edd
>> +index 000000000000..26eb9d3aa630
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
>> +Resume Control
>> @@ -304,10 +266,8 @@
>> + compatible = "marvell,98dx3336-resume-ctrl";
>> + reg = <0x20980 0x10>;
>> +};
>> -+
>> -+
>> diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
>> -index 46c742d3bd41..59be3ca0464f 100644
>> +index 46c742d3bd41..a5b464497e1a 100644
>> --- a/arch/arm/mach-mvebu/platsmp.c
>> +++ b/arch/arm/mach-mvebu/platsmp.c
>>
>> @@ -327,7 +287,7 @@
>> +static const struct of_device_id of_mv98dx3236_resume_table[] = {
>> + {
>> + .compatible = "marvell,98dx3336-resume-ctrl",
>> -+ .data = (void *)&mv98dx3336_resume_controller,
>> ++ .data = &mv98dx3336_resume_controller,
>> + },
>> + { /* end of list */ },
>> +};
>> @@ -337,7 +297,7 @@
>> + const struct of_device_id *match;
>> + struct device_node *np;
>> + void __iomem *base;
>> -+ struct resume_controller *rc;
>> ++ const struct resume_controller *rc;
>> +
>> + WARN_ON(hw_cpu != 1);
>> +
>> @@ -347,7 +307,7 @@
>> + return -ENODEV;
>> +
>> + base = of_io_request_and_map(np, 0, of_node_full_name(np));
>> -+ rc = (struct resume_controller *)match->data;
>> ++ rc = match->data;
>> + of_node_put(np);
>> + if (IS_ERR(base))
>> + return PTR_ERR(base);
>> @@ -411,15 +371,17 @@
>> diff --git
> a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
> b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
>> new file mode 100644
>> -index 000000000000..d4e6ecdfc853
>> +index 000000000000..97aef67ee769
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
>> +* Marvell 98dx3236 pinctrl driver for mpp
>> @@ -435,41 +397,41 @@
>> +
>> +name pins functions
>> +================================================================================
>> -+mpp0 0 gpio, spi0(mosi), dev(ad8)
>> ++mpp0 0 gpo, spi0(mosi), dev(ad8)
>> +mpp1 1 gpio, spi0(miso), dev(ad9)
>> -+mpp2 2 gpio, spi0(sck), dev(ad10)
>> ++mpp2 2 gpo, spi0(sck), dev(ad10)
>> +mpp3 3 gpio, spi0(cs0), dev(ad11)
>> +mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
>> +mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
>> -+mpp6 6 gpio, sd0(clk), dev(a2)
>> ++mpp6 6 gpo, sd0(clk), dev(a2)
>> +mpp7 7 gpio, sd0(d0), dev(ale0)
>> +mpp8 8 gpio, sd0(d1), dev(ale1)
>> +mpp9 9 gpio, sd0(d2), dev(ready0)
>> +mpp10 10 gpio, sd0(d3), dev(ad12)
>> +mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13)
>> -+mpp12 12 gpio, uart1(txd), uart0(rts), dev(ad14)
>> ++mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14)
>> +mpp13 13 gpio, intr(out), dev(ad15)
>> +mpp14 14 gpio, i2c0(sck)
>> +mpp15 15 gpio, i2c0(sda)
>> -+mpp16 16 gpio, dev(oe)
>> -+mpp17 17 gpio, dev(clk)
>> ++mpp16 16 gpo, dev(oe)
>> ++mpp17 17 gpo, dev(clkout)
>> +mpp18 18 gpio, uart1(txd)
>> +mpp19 19 gpio, uart1(rxd), dev(rb)
>> -+mpp20 20 gpio, dev(we)
>> -+mpp21 21 gpio, dev(ad0)
>> -+mpp22 22 gpio, dev(ad1)
>> -+mpp23 23 gpio, dev(ad2)
>> -+mpp24 24 gpio, dev(ad3)
>> -+mpp25 25 gpio, dev(ad4)
>> -+mpp26 26 gpio, dev(ad5)
>> -+mpp27 27 gpio, dev(ad6)
>> -+mpp28 28 gpio, dev(ad7)
>> -+mpp29 29 gpio, dev(a0)
>> -+mpp30 30 gpio, dev(a1)
>> ++mpp20 20 gpo, dev(we0)
>> ++mpp21 21 gpo, dev(ad0)
>> ++mpp22 22 gpo, dev(ad1)
>> ++mpp23 23 gpo, dev(ad2)
>> ++mpp24 24 gpo, dev(ad3)
>> ++mpp25 25 gpo, dev(ad4)
>> ++mpp26 26 gpo, dev(ad5)
>> ++mpp27 27 gpo, dev(ad6)
>> ++mpp28 28 gpo, dev(ad7)
>> ++mpp29 29 gpo, dev(a0)
>> ++mpp30 30 gpo, dev(a1)
>> +mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
>> +mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
>> diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
>> -index e4ea71a9d985..554eeae8cd21 100644
>> +index 63e1bd506983..61cbc138703e 100644
>> --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
>> +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
>> V_MV78460 = BIT(2),
>> @@ -495,8 +457,8 @@
>> + MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)),
>> + MPP_MODE(2,
>> -+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
>> -+ MPP_VAR_FUNCTION(0x2, "spi0", "csk", V_98DX3236_PLUS),
>> ++ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
>> ++ MPP_VAR_FUNCTION(0x2, "spi0", "sck", V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)),
>> + MPP_MODE(3,
>> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
>> @@ -511,7 +473,7 @@
>> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251),
>> -+ MPP_VAR_FUNCTION(0x4, "dev", "bootcs0", V_98DX3236_PLUS)),
>> ++ MPP_VAR_FUNCTION(0x4, "dev", "bootcs", V_98DX3236_PLUS)),
>> + MPP_MODE(6,
>> + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251),
>> @@ -563,7 +525,8 @@
>> + MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)),
>> + MPP_MODE(19,
>> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
>> -+ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS)),
>> ++ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS),
>> ++ MPP_VAR_FUNCTION(0x4, "dev", "rb", V_98DX3236_PLUS)),
>> + MPP_MODE(20,
>> + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)),
>> @@ -630,11 +593,11 @@
>> };
>>
>> +static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = {
>> -+ MPP_FUNC_CTRL(0, 32, NULL, armada_xp_mpp_ctrl),
>> ++ MPP_FUNC_CTRL(0, 32, NULL, mvebu_mmio_mpp_ctrl),
>> +};
>> +
>> +static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = {
>> -+ MPP_GPIO_RANGE(0, 0, 0, 32),
>> ++ MPP_GPIO_RANGE(0, 0, 0, 32),
>> +};
>> +
>> static int armada_xp_pinctrl_suspend(struct platform_device *pdev,
>> @@ -767,7 +731,7 @@
>> +};
>> diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
>> new file mode 100644
>> -index 000000000000..4b7b2fe3b682
>> +index 000000000000..9461128fae24
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
>> +/*
>> @@ -785,17 +749,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -804,11 +768,11 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> @@ -851,9 +815,9 @@
>> + MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
>> +
>> + /*
>> -+ * 98DX3236 has 1 x1 PCIe unit Gen2.0: One unit can be
>> ++ * 98DX3236 has 1 x1 PCIe unit Gen2.0
>> + */
>> -+ pcie-controller {
>> ++ pciec: pcie-controller@82000000 {
>> + compatible = "marvell,armada-xp-pcie";
>> + status = "disabled";
>> + device_type = "pci";
>> @@ -870,7 +834,7 @@
>> + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
>> + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;
>> +
>> -+ pcie@1,0 {
>> ++ pcie1: pcie@1,0 {
>> + device_type = "pci";
>> + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
>> + reg = <0x0800 0 0 0 0>;
>> @@ -967,7 +931,7 @@
>> + };
>> + };
>> +
>> -+ dfx-registers {
>> ++ dfxr: dfx-registers@ac000000 {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> @@ -987,7 +951,7 @@
>> + };
>> + };
>> +
>> -+ switch {
>> ++ switch: switch@a8000000 {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> @@ -1026,7 +990,7 @@
>> +};
>> diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
>> new file mode 100644
>> -index 000000000000..a9b0f47f8df9
>> +index 000000000000..e1580afdc260
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
>> +/*
>> @@ -1044,17 +1008,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -1063,16 +1027,16 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + *
>> -+ * Contains definitions specific to the 98dx3336 SoC that are not
>> ++ * Contains definitions specific to the 98dx3236 SoC that are not
>> + * common to all Armada XP SoCs.
>> + */
>> +
>> @@ -1107,7 +1071,7 @@
>> +};
>> diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
>> new file mode 100644
>> -index 000000000000..446e6e65ec59
>> +index 000000000000..4b0533a4ccb7
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
>> +/*
>> @@ -1125,17 +1089,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -1144,11 +1108,11 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> @@ -1213,15 +1177,15 @@
>> diff --git a/arch/arm/boot/dts/db-dxbc2.dts b/arch/arm/boot/dts/db-dxbc2.dts
>> new file mode 100644
>> -index 000000000000..f56786cea5f8
>> +index 000000000000..a8130805074e
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/db-dxbc2.dts
>> +/*
>> @@ -1241,17 +1205,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -1260,11 +1224,11 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> @@ -1295,66 +1259,58 @@
>> + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
>> + };
>> +
>> -+ soc {
>> -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
>> -+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
>> -+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
>> -+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
>> -+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
>> ++};
>> +
>> -+ devbus-bootcs {
>> -+ status = "okay";
>> ++&devbus_bootcs {
>> ++ status = "okay";
>> +
>> -+ /* Device Bus parameters are required */
>> ++ /* Device Bus parameters are required */
>> +
>> -+ /* Read parameters */
>> -+ devbus,bus-width = <16>;
>> -+ devbus,turn-off-ps = <60000>;
>> -+ devbus,badr-skew-ps = <0>;
>> -+ devbus,acc-first-ps = <124000>;
>> -+ devbus,acc-next-ps = <248000>;
>> -+ devbus,rd-setup-ps = <0>;
>> -+ devbus,rd-hold-ps = <0>;
>> -+
>> -+ /* Write parameters */
>> -+ devbus,sync-enable = <0>;
>> -+ devbus,wr-high-ps = <60000>;
>> -+ devbus,wr-low-ps = <60000>;
>> -+ devbus,ale-wr-ps = <60000>;
>> -+ };
>> ++ /* Read parameters */
>> ++ devbus,bus-width = <16>;
>> ++ devbus,turn-off-ps = <60000>;
>> ++ devbus,badr-skew-ps = <0>;
>> ++ devbus,acc-first-ps = <124000>;
>> ++ devbus,acc-next-ps = <248000>;
>> ++ devbus,rd-setup-ps = <0>;
>> ++ devbus,rd-hold-ps = <0>;
>> ++
>> ++ /* Write parameters */
>> ++ devbus,sync-enable = <0>;
>> ++ devbus,wr-high-ps = <60000>;
>> ++ devbus,wr-low-ps = <60000>;
>> ++ devbus,ale-wr-ps = <60000>;
>> ++};
>> +
>> -+ internal-regs {
>> -+ serial@12000 {
>> -+ status = "okay";
>> -+ };
>> -+ serial@12100 {
>> -+ status = "okay";
>> -+ };
>> ++&i2c0 {
>> ++ clock-frequency = <100000>;
>> ++ status = "okay";
>> ++};
>> +
>> -+ i2c@11000 {
>> -+ clock-frequency = <100000>;
>> -+ status = "okay";
>> -+ };
>> ++&uart0 {
>> ++ status = "okay";
>> ++};
>> +
>> -+ mvsdio@d4000 {
>> -+ pinctrl-0 = <&sdio_pins>;
>> -+ pinctrl-names = "default";
>> -+ status = "okay";
>> -+ /* No CD or WP GPIOs */
>> -+ broken-cd;
>> -+ };
>> ++&uart1 {
>> ++ status = "okay";
>> ++};
>> +
>> -+ nand@d0000 {
>> -+ status = "okay";
>> -+ num-cs = <1>;
>> -+ marvell,nand-keep-config;
>> -+ marvell,nand-enable-arbiter;
>> -+ nand-on-flash-bbt;
>> -+ nand-ecc-strength = <4>;
>> -+ nand-ecc-step-size = <512>;
>> -+ };
>> -+ };
>> -+ };
>> ++&nand {
>> ++ status = "okay";
>> ++ num-cs = <1>;
>> ++ marvell,nand-keep-config;
>> ++ marvell,nand-enable-arbiter;
>> ++ nand-on-flash-bbt;
>> ++ nand-ecc-strength = <4>;
>> ++ nand-ecc-step-size = <512>;
>> ++};
>> ++
>> ++&sdio {
>> ++ pinctrl-0 = <&sdio_pins>;
>> ++ pinctrl-names = "default";
>> ++ status = "okay";
>> ++ /* No CD or WP GPIOs */
>> ++ broken-cd;
>> +};
>> +
>> +&spi0 {
>> @@ -1385,7 +1341,7 @@
>> +};
>> diff --git a/arch/arm/boot/dts/db-xc3-24g4xg.dts b/arch/arm/boot/dts/db-xc3-24g4xg.dts
>> new file mode 100644
>> -index 000000000000..5eb89ffb9a7d
>> +index 000000000000..4e07cb6ed800
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/db-xc3-24g4xg.dts
>> +/*
>> @@ -1405,17 +1361,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -1424,11 +1380,11 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> @@ -1458,63 +1414,50 @@
>> + device_type = "memory";
>> + reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
>> + };
>> ++};
>> +
>> -+ soc {
>> -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
>> -+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
>> -+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
>> -+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
>> -+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
>> -+
>> -+ devbus-bootcs {
>> -+ status = "okay";
>> ++&devbus_bootcs {
>> ++ status = "okay";
>> +
>> -+ /* Device Bus parameters are required */
>> ++ /* Device Bus parameters are required */
>> +
>> -+ /* Read parameters */
>> -+ devbus,bus-width = <16>;
>> -+ devbus,turn-off-ps = <60000>;
>> -+ devbus,badr-skew-ps = <0>;
>> -+ devbus,acc-first-ps = <124000>;
>> -+ devbus,acc-next-ps = <248000>;
>> -+ devbus,rd-setup-ps = <0>;
>> -+ devbus,rd-hold-ps = <0>;
>> -+
>> -+ /* Write parameters */
>> -+ devbus,sync-enable = <0>;
>> -+ devbus,wr-high-ps = <60000>;
>> -+ devbus,wr-low-ps = <60000>;
>> -+ devbus,ale-wr-ps = <60000>;
>> -+ };
>> ++ /* Read parameters */
>> ++ devbus,bus-width = <16>;
>> ++ devbus,turn-off-ps = <60000>;
>> ++ devbus,badr-skew-ps = <0>;
>> ++ devbus,acc-first-ps = <124000>;
>> ++ devbus,acc-next-ps = <248000>;
>> ++ devbus,rd-setup-ps = <0>;
>> ++ devbus,rd-hold-ps = <0>;
>> ++
>> ++ /* Write parameters */
>> ++ devbus,sync-enable = <0>;
>> ++ devbus,wr-high-ps = <60000>;
>> ++ devbus,wr-low-ps = <60000>;
>> ++ devbus,ale-wr-ps = <60000>;
>> ++};
>> +
>> -+ internal-regs {
>> -+ serial@12000 {
>> -+ status = "okay";
>> -+ };
>> -+ serial@12100 {
>> -+ status = "okay";
>> -+ };
>> ++&uart0 {
>> ++ status = "okay";
>> ++};
>> +
>> -+ i2c@11000 {
>> -+ clock-frequency = <100000>;
>> -+ status = "okay";
>> -+ };
>> ++&uart1 {
>> ++ status = "okay";
>> ++};
>> +
>> -+ mvsdio@d4000 {
>> -+ status = "disabled";
>> -+ };
>> ++&i2c0 {
>> ++ clock-frequency = <100000>;
>> ++ status = "okay";
>> ++};
>> +
>> -+ nand@d0000 {
>> -+ status = "okay";
>> -+ num-cs = <1>;
>> -+ marvell,nand-keep-config;
>> -+ marvell,nand-enable-arbiter;
>> -+ nand-on-flash-bbt;
>> -+ nand-ecc-strength = <4>;
>> -+ nand-ecc-step-size = <512>;
>> -+ };
>> -+ };
>> -+ };
>> ++&nand {
>> ++ status = "okay";
>> ++ num-cs = <1>;
>> ++ marvell,nand-keep-config;
>> ++ marvell,nand-enable-arbiter;
>> ++ nand-on-flash-bbt;
>> ++ nand-ecc-strength = <4>;
>> ++ nand-ecc-step-size = <512>;
>> +};
>> +
>> +&spi0 {
>>
>> --
>> 2.11.0.24.ge6920cf
>>
>
> --
> Gregory Clement, Free Electrons
> Kernel, drivers, real-time and embedded Linux
> development, consulting, training and support.
> http://free-electrons.com
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 49+ messages in thread* [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-27 16:49 ` Gregory CLEMENT
0 siblings, 0 replies; 49+ messages in thread
From: Gregory CLEMENT @ 2017-01-27 16:49 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On ven., janv. 27 2017, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:
> Hi all,
>
> On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
>
>> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
>> integrated CPUs. They CPU block is common within these product lines and
>> (as far as I can tell/have been told) is based on the Armada XP. There
>> are a few differences due to the fact they have to squeeze the CPU into
>> the same package as the switch.
>>
>> I've rebased this series against linux-pinctrl/devel to get access to
>> mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to
>> v4.10.0-rc5.
>
> Just to let you know that I plan to apply the 3 arm patch once Chris
> will have sent the new series with the minor fixes I asked on patch 3.
I meant patch 2!
And now patch 5 too :)
Gregory
> I already applied them in the for-next branch to benefit of some build
> test coverage.
>
> Stephen,
>
> you gave your Acked-by on the first patch, but don't you plan to apply
> it on the clk branch?
>
> If you really want I can apply on mvebu but there is no build
> dependencies, so the order the patches will be merged is not important.
>
> Linus,
>
> I expect you will apply the pinctrl patch on your tree as it depend of
> code already there.
>
> Thanks,
>
> Gregory
>
>>
>> Chris Packham (4):
>> clk: mvebu: support for 98DX3236 SoC
>> Changes in v2:
>> - Update devicetree binding documentation for new compatible string
>> Changes in v3:
>> - Add 98dx3236 support to mvebu/clk-corediv.c rather than creating a new
>> driver.
>> - Document mv98dx3236-corediv-clock binding
>> Changes in v4:
>> - None
>> Changes in v5:
>> - Collect ack from Rob
>> - Remove explicit initialisation of fields to 0 in mv98dx3236_coreclks
>> - Register dummy clock provider for marvell,mv98dx3236-cpu-clock
>> arm: mvebu: support for SMP on 98DX3336 SoC
>> Changes in v2:
>> - Document new enable-method value
>> - Correct some references from 98DX4521 to 98DX3236
>> Changes in v3:
>> - Simplify mv98dx3236_resume_init by using of_io_request_and_map()
>> Changes in v4:
>> - integrate changes into platsmp.c instead of new init call
>> - avoid duplicated code.
>> - fix error return
>> - Collect ack from Rob
>> Changes in v5:
>> - Remove useless casts (thanks to Stephen Boyd)
>> arm: mvebu: Add device tree for 98DX3236 SoCs
>> Changes in v2:
>> - Update devicetree binding documentation to reflect that 98DX3336 and
>> 984251 are supersets of 98DX3236.
>> - disable crypto block
>> - disable sdio for 98DX3236, enable for 98DX4251
>> Changes in v3:
>> - fix typo 4521 -> 4251
>> - document prestera bindings
>> - rework corediv-clock binding
>> - add label to packet processor node
>> - add new compatible string for DFX server
>> Changes in v4:
>> - Collect ack from Rob
>> Changes in v5:
>> - Fixup license text. Add labels to nodes.
>> arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
>> Changes in v5:
>> - update license text
>> - use node labels
>>
>> Kalyan Kinthada (1):
>> pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
>> Changes in v2:
>> - include sdio support for the 98DX4251
>> Changes in v3:
>> - None
>> Changes in v4:
>> - Correct some discrepencies between binding and driver.
>> - Collect acks from Rob and Sebastian
>> Changes in v5:
>> - Update bindings to reflect "gpo" pins
>> - Use mvebu_mmio_mpp_ctrl instead of armada_xp_mpp_ctrl (note this is reliant
>> on changes queued in linux-pinctrl)
>>
>> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
>> .../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 16 ++
>> .../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ++
>> .../bindings/clock/mvebu-corediv-clock.txt | 1 +
>> .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 1 +
>> .../devicetree/bindings/net/marvell,prestera.txt | 50 ++++
>> .../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++
>> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 254 +++++++++++++++++++++
>> arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 76 ++++++
>> arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 90 ++++++++
>> arch/arm/boot/dts/db-dxbc2.dts | 151 ++++++++++++
>> arch/arm/boot/dts/db-xc3-24g4xg.dts | 142 ++++++++++++
>> arch/arm/mach-mvebu/platsmp.c | 86 +++++++
>> drivers/clk/mvebu/armada-xp.c | 39 ++++
>> drivers/clk/mvebu/clk-corediv.c | 23 ++
>> drivers/clk/mvebu/clk-cpu.c | 8 +
>> drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 156 +++++++++++++
>> 17 files changed, 1163 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
>> create mode 100644 Documentation/devicetree/bindings/net/marvell,prestera.txt
>> create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
>> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
>> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
>> create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
>> create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
>> create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
>>
>> interdiff to v4:
>>
>> diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
>> index 520562a7dc2a..c7b4e3a6b2c6 100644
>> @@ -85,7 +86,7 @@
>> by address and length of the PMU DFS registers
>> - #clock-cells : should be set to 1.
>> diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
>> -index b3094315a3c0..0413bf8284e0 100644
>> +index b3094315a3c0..890a863ae0d0 100644
>> --- a/drivers/clk/mvebu/armada-xp.c
>> +++ b/drivers/clk/mvebu/armada-xp.c
>> return 250000000;
>> @@ -118,9 +119,6 @@
>> +static const struct coreclk_soc_desc mv98dx3236_coreclks = {
>> + .get_tclk_freq = mv98dx3236_get_tclk_freq,
>> + .get_cpu_freq = mv98dx3236_get_cpu_freq,
>> -+ .get_clk_ratio = NULL,
>> -+ .ratios = NULL,
>> -+ .num_ratios = 0,
>> +};
>> +
>> /*
>> @@ -200,53 +198,16 @@
>> +CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock",
>> + mv98dx3236_corediv_clk_init);
>> diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
>> -index 5837eb8a212f..3b8f0e14fa01 100644
>> +index 5837eb8a212f..044892b6534d 100644
>> --- a/drivers/clk/mvebu/clk-cpu.c
>> +++ b/drivers/clk/mvebu/clk-cpu.c
>> - .set_rate = clk_cpu_set_rate,
>> - };
>> -
>> --static void __init of_cpu_clk_setup(struct device_node *node)
>> -+/* Add parameter to allow this to support different clock operations. */
>> -+static void __init _of_cpu_clk_setup(struct device_node *node,
>> -+ const struct clk_ops *cpu_clk_ops)
>> - {
>> - struct cpu_clk *cpuclk;
>> - void __iomem *clock_complex_base = of_iomap(node, 0);
>> - cpuclk[cpu].hw.init = &init;
>>
>> - init.name = cpuclk[cpu].clk_name;
>> -- init.ops = &cpu_ops;
>> -+ init.ops = cpu_clk_ops;
>> - init.flags = 0;
>> - init.parent_names = &cpuclk[cpu].parent_name;
>> - init.num_parents = 1;
>> - iounmap(clock_complex_base);
>> - }
>> -
>> -+/* Use this function to call the generic setup with the correct
>> -+ * clock operation
>> -+ */
>> -+static void __init of_cpu_clk_setup(struct device_node *node)
>> -+{
>> -+ _of_cpu_clk_setup(node, &cpu_ops);
>> -+}
>> -+
>> CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
>> of_cpu_clk_setup);
>> +
>> -+/* Define the clock and operations for the mv98dx3236 - it cannot perform
>> -+ * any operations.
>> -+ */
>> -+static const struct clk_ops mv98dx3236_cpu_ops = {
>> -+ .recalc_rate = NULL,
>> -+ .round_rate = NULL,
>> -+ .set_rate = NULL,
>> -+};
>> -+
>> +static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
>> +{
>> -+ _of_cpu_clk_setup(node, &mv98dx3236_cpu_ops);
>> ++ of_clk_add_provider(node, of_clk_src_simple_get, NULL);
>> +}
>> +
>> +CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
>> @@ -285,7 +247,7 @@
>> "qcom,gcc-msm8660"
>> diff --git
> a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
>> new file mode 100644
>> -index 000000000000..8082ba872edd
>> +index 000000000000..26eb9d3aa630
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
>> +Resume Control
>> @@ -304,10 +266,8 @@
>> + compatible = "marvell,98dx3336-resume-ctrl";
>> + reg = <0x20980 0x10>;
>> +};
>> -+
>> -+
>> diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
>> -index 46c742d3bd41..59be3ca0464f 100644
>> +index 46c742d3bd41..a5b464497e1a 100644
>> --- a/arch/arm/mach-mvebu/platsmp.c
>> +++ b/arch/arm/mach-mvebu/platsmp.c
>>
>> @@ -327,7 +287,7 @@
>> +static const struct of_device_id of_mv98dx3236_resume_table[] = {
>> + {
>> + .compatible = "marvell,98dx3336-resume-ctrl",
>> -+ .data = (void *)&mv98dx3336_resume_controller,
>> ++ .data = &mv98dx3336_resume_controller,
>> + },
>> + { /* end of list */ },
>> +};
>> @@ -337,7 +297,7 @@
>> + const struct of_device_id *match;
>> + struct device_node *np;
>> + void __iomem *base;
>> -+ struct resume_controller *rc;
>> ++ const struct resume_controller *rc;
>> +
>> + WARN_ON(hw_cpu != 1);
>> +
>> @@ -347,7 +307,7 @@
>> + return -ENODEV;
>> +
>> + base = of_io_request_and_map(np, 0, of_node_full_name(np));
>> -+ rc = (struct resume_controller *)match->data;
>> ++ rc = match->data;
>> + of_node_put(np);
>> + if (IS_ERR(base))
>> + return PTR_ERR(base);
>> @@ -411,15 +371,17 @@
>> diff --git
> a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
> b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
>> new file mode 100644
>> -index 000000000000..d4e6ecdfc853
>> +index 000000000000..97aef67ee769
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
>> +* Marvell 98dx3236 pinctrl driver for mpp
>> @@ -435,41 +397,41 @@
>> +
>> +name pins functions
>> +================================================================================
>> -+mpp0 0 gpio, spi0(mosi), dev(ad8)
>> ++mpp0 0 gpo, spi0(mosi), dev(ad8)
>> +mpp1 1 gpio, spi0(miso), dev(ad9)
>> -+mpp2 2 gpio, spi0(sck), dev(ad10)
>> ++mpp2 2 gpo, spi0(sck), dev(ad10)
>> +mpp3 3 gpio, spi0(cs0), dev(ad11)
>> +mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
>> +mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
>> -+mpp6 6 gpio, sd0(clk), dev(a2)
>> ++mpp6 6 gpo, sd0(clk), dev(a2)
>> +mpp7 7 gpio, sd0(d0), dev(ale0)
>> +mpp8 8 gpio, sd0(d1), dev(ale1)
>> +mpp9 9 gpio, sd0(d2), dev(ready0)
>> +mpp10 10 gpio, sd0(d3), dev(ad12)
>> +mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13)
>> -+mpp12 12 gpio, uart1(txd), uart0(rts), dev(ad14)
>> ++mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14)
>> +mpp13 13 gpio, intr(out), dev(ad15)
>> +mpp14 14 gpio, i2c0(sck)
>> +mpp15 15 gpio, i2c0(sda)
>> -+mpp16 16 gpio, dev(oe)
>> -+mpp17 17 gpio, dev(clk)
>> ++mpp16 16 gpo, dev(oe)
>> ++mpp17 17 gpo, dev(clkout)
>> +mpp18 18 gpio, uart1(txd)
>> +mpp19 19 gpio, uart1(rxd), dev(rb)
>> -+mpp20 20 gpio, dev(we)
>> -+mpp21 21 gpio, dev(ad0)
>> -+mpp22 22 gpio, dev(ad1)
>> -+mpp23 23 gpio, dev(ad2)
>> -+mpp24 24 gpio, dev(ad3)
>> -+mpp25 25 gpio, dev(ad4)
>> -+mpp26 26 gpio, dev(ad5)
>> -+mpp27 27 gpio, dev(ad6)
>> -+mpp28 28 gpio, dev(ad7)
>> -+mpp29 29 gpio, dev(a0)
>> -+mpp30 30 gpio, dev(a1)
>> ++mpp20 20 gpo, dev(we0)
>> ++mpp21 21 gpo, dev(ad0)
>> ++mpp22 22 gpo, dev(ad1)
>> ++mpp23 23 gpo, dev(ad2)
>> ++mpp24 24 gpo, dev(ad3)
>> ++mpp25 25 gpo, dev(ad4)
>> ++mpp26 26 gpo, dev(ad5)
>> ++mpp27 27 gpo, dev(ad6)
>> ++mpp28 28 gpo, dev(ad7)
>> ++mpp29 29 gpo, dev(a0)
>> ++mpp30 30 gpo, dev(a1)
>> +mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
>> +mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
>> diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
>> -index e4ea71a9d985..554eeae8cd21 100644
>> +index 63e1bd506983..61cbc138703e 100644
>> --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
>> +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
>> V_MV78460 = BIT(2),
>> @@ -495,8 +457,8 @@
>> + MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)),
>> + MPP_MODE(2,
>> -+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
>> -+ MPP_VAR_FUNCTION(0x2, "spi0", "csk", V_98DX3236_PLUS),
>> ++ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
>> ++ MPP_VAR_FUNCTION(0x2, "spi0", "sck", V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)),
>> + MPP_MODE(3,
>> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
>> @@ -511,7 +473,7 @@
>> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251),
>> -+ MPP_VAR_FUNCTION(0x4, "dev", "bootcs0", V_98DX3236_PLUS)),
>> ++ MPP_VAR_FUNCTION(0x4, "dev", "bootcs", V_98DX3236_PLUS)),
>> + MPP_MODE(6,
>> + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251),
>> @@ -563,7 +525,8 @@
>> + MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)),
>> + MPP_MODE(19,
>> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
>> -+ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS)),
>> ++ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS),
>> ++ MPP_VAR_FUNCTION(0x4, "dev", "rb", V_98DX3236_PLUS)),
>> + MPP_MODE(20,
>> + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)),
>> @@ -630,11 +593,11 @@
>> };
>>
>> +static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = {
>> -+ MPP_FUNC_CTRL(0, 32, NULL, armada_xp_mpp_ctrl),
>> ++ MPP_FUNC_CTRL(0, 32, NULL, mvebu_mmio_mpp_ctrl),
>> +};
>> +
>> +static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = {
>> -+ MPP_GPIO_RANGE(0, 0, 0, 32),
>> ++ MPP_GPIO_RANGE(0, 0, 0, 32),
>> +};
>> +
>> static int armada_xp_pinctrl_suspend(struct platform_device *pdev,
>> @@ -767,7 +731,7 @@
>> +};
>> diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
>> new file mode 100644
>> -index 000000000000..4b7b2fe3b682
>> +index 000000000000..9461128fae24
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
>> +/*
>> @@ -785,17 +749,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -804,11 +768,11 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> @@ -851,9 +815,9 @@
>> + MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
>> +
>> + /*
>> -+ * 98DX3236 has 1 x1 PCIe unit Gen2.0: One unit can be
>> ++ * 98DX3236 has 1 x1 PCIe unit Gen2.0
>> + */
>> -+ pcie-controller {
>> ++ pciec: pcie-controller at 82000000 {
>> + compatible = "marvell,armada-xp-pcie";
>> + status = "disabled";
>> + device_type = "pci";
>> @@ -870,7 +834,7 @@
>> + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
>> + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;
>> +
>> -+ pcie at 1,0 {
>> ++ pcie1: pcie at 1,0 {
>> + device_type = "pci";
>> + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
>> + reg = <0x0800 0 0 0 0>;
>> @@ -967,7 +931,7 @@
>> + };
>> + };
>> +
>> -+ dfx-registers {
>> ++ dfxr: dfx-registers at ac000000 {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> @@ -987,7 +951,7 @@
>> + };
>> + };
>> +
>> -+ switch {
>> ++ switch: switch at a8000000 {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> @@ -1026,7 +990,7 @@
>> +};
>> diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
>> new file mode 100644
>> -index 000000000000..a9b0f47f8df9
>> +index 000000000000..e1580afdc260
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
>> +/*
>> @@ -1044,17 +1008,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -1063,16 +1027,16 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + *
>> -+ * Contains definitions specific to the 98dx3336 SoC that are not
>> ++ * Contains definitions specific to the 98dx3236 SoC that are not
>> + * common to all Armada XP SoCs.
>> + */
>> +
>> @@ -1107,7 +1071,7 @@
>> +};
>> diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
>> new file mode 100644
>> -index 000000000000..446e6e65ec59
>> +index 000000000000..4b0533a4ccb7
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
>> +/*
>> @@ -1125,17 +1089,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -1144,11 +1108,11 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> @@ -1213,15 +1177,15 @@
>> diff --git a/arch/arm/boot/dts/db-dxbc2.dts b/arch/arm/boot/dts/db-dxbc2.dts
>> new file mode 100644
>> -index 000000000000..f56786cea5f8
>> +index 000000000000..a8130805074e
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/db-dxbc2.dts
>> +/*
>> @@ -1241,17 +1205,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -1260,11 +1224,11 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> @@ -1295,66 +1259,58 @@
>> + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
>> + };
>> +
>> -+ soc {
>> -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
>> -+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
>> -+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
>> -+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
>> -+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
>> ++};
>> +
>> -+ devbus-bootcs {
>> -+ status = "okay";
>> ++&devbus_bootcs {
>> ++ status = "okay";
>> +
>> -+ /* Device Bus parameters are required */
>> ++ /* Device Bus parameters are required */
>> +
>> -+ /* Read parameters */
>> -+ devbus,bus-width = <16>;
>> -+ devbus,turn-off-ps = <60000>;
>> -+ devbus,badr-skew-ps = <0>;
>> -+ devbus,acc-first-ps = <124000>;
>> -+ devbus,acc-next-ps = <248000>;
>> -+ devbus,rd-setup-ps = <0>;
>> -+ devbus,rd-hold-ps = <0>;
>> -+
>> -+ /* Write parameters */
>> -+ devbus,sync-enable = <0>;
>> -+ devbus,wr-high-ps = <60000>;
>> -+ devbus,wr-low-ps = <60000>;
>> -+ devbus,ale-wr-ps = <60000>;
>> -+ };
>> ++ /* Read parameters */
>> ++ devbus,bus-width = <16>;
>> ++ devbus,turn-off-ps = <60000>;
>> ++ devbus,badr-skew-ps = <0>;
>> ++ devbus,acc-first-ps = <124000>;
>> ++ devbus,acc-next-ps = <248000>;
>> ++ devbus,rd-setup-ps = <0>;
>> ++ devbus,rd-hold-ps = <0>;
>> ++
>> ++ /* Write parameters */
>> ++ devbus,sync-enable = <0>;
>> ++ devbus,wr-high-ps = <60000>;
>> ++ devbus,wr-low-ps = <60000>;
>> ++ devbus,ale-wr-ps = <60000>;
>> ++};
>> +
>> -+ internal-regs {
>> -+ serial at 12000 {
>> -+ status = "okay";
>> -+ };
>> -+ serial at 12100 {
>> -+ status = "okay";
>> -+ };
>> ++&i2c0 {
>> ++ clock-frequency = <100000>;
>> ++ status = "okay";
>> ++};
>> +
>> -+ i2c at 11000 {
>> -+ clock-frequency = <100000>;
>> -+ status = "okay";
>> -+ };
>> ++&uart0 {
>> ++ status = "okay";
>> ++};
>> +
>> -+ mvsdio at d4000 {
>> -+ pinctrl-0 = <&sdio_pins>;
>> -+ pinctrl-names = "default";
>> -+ status = "okay";
>> -+ /* No CD or WP GPIOs */
>> -+ broken-cd;
>> -+ };
>> ++&uart1 {
>> ++ status = "okay";
>> ++};
>> +
>> -+ nand at d0000 {
>> -+ status = "okay";
>> -+ num-cs = <1>;
>> -+ marvell,nand-keep-config;
>> -+ marvell,nand-enable-arbiter;
>> -+ nand-on-flash-bbt;
>> -+ nand-ecc-strength = <4>;
>> -+ nand-ecc-step-size = <512>;
>> -+ };
>> -+ };
>> -+ };
>> ++&nand {
>> ++ status = "okay";
>> ++ num-cs = <1>;
>> ++ marvell,nand-keep-config;
>> ++ marvell,nand-enable-arbiter;
>> ++ nand-on-flash-bbt;
>> ++ nand-ecc-strength = <4>;
>> ++ nand-ecc-step-size = <512>;
>> ++};
>> ++
>> ++&sdio {
>> ++ pinctrl-0 = <&sdio_pins>;
>> ++ pinctrl-names = "default";
>> ++ status = "okay";
>> ++ /* No CD or WP GPIOs */
>> ++ broken-cd;
>> +};
>> +
>> +&spi0 {
>> @@ -1385,7 +1341,7 @@
>> +};
>> diff --git a/arch/arm/boot/dts/db-xc3-24g4xg.dts b/arch/arm/boot/dts/db-xc3-24g4xg.dts
>> new file mode 100644
>> -index 000000000000..5eb89ffb9a7d
>> +index 000000000000..4e07cb6ed800
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/db-xc3-24g4xg.dts
>> +/*
>> @@ -1405,17 +1361,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -1424,11 +1380,11 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> @@ -1458,63 +1414,50 @@
>> + device_type = "memory";
>> + reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
>> + };
>> ++};
>> +
>> -+ soc {
>> -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
>> -+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
>> -+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
>> -+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
>> -+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
>> -+
>> -+ devbus-bootcs {
>> -+ status = "okay";
>> ++&devbus_bootcs {
>> ++ status = "okay";
>> +
>> -+ /* Device Bus parameters are required */
>> ++ /* Device Bus parameters are required */
>> +
>> -+ /* Read parameters */
>> -+ devbus,bus-width = <16>;
>> -+ devbus,turn-off-ps = <60000>;
>> -+ devbus,badr-skew-ps = <0>;
>> -+ devbus,acc-first-ps = <124000>;
>> -+ devbus,acc-next-ps = <248000>;
>> -+ devbus,rd-setup-ps = <0>;
>> -+ devbus,rd-hold-ps = <0>;
>> -+
>> -+ /* Write parameters */
>> -+ devbus,sync-enable = <0>;
>> -+ devbus,wr-high-ps = <60000>;
>> -+ devbus,wr-low-ps = <60000>;
>> -+ devbus,ale-wr-ps = <60000>;
>> -+ };
>> ++ /* Read parameters */
>> ++ devbus,bus-width = <16>;
>> ++ devbus,turn-off-ps = <60000>;
>> ++ devbus,badr-skew-ps = <0>;
>> ++ devbus,acc-first-ps = <124000>;
>> ++ devbus,acc-next-ps = <248000>;
>> ++ devbus,rd-setup-ps = <0>;
>> ++ devbus,rd-hold-ps = <0>;
>> ++
>> ++ /* Write parameters */
>> ++ devbus,sync-enable = <0>;
>> ++ devbus,wr-high-ps = <60000>;
>> ++ devbus,wr-low-ps = <60000>;
>> ++ devbus,ale-wr-ps = <60000>;
>> ++};
>> +
>> -+ internal-regs {
>> -+ serial at 12000 {
>> -+ status = "okay";
>> -+ };
>> -+ serial at 12100 {
>> -+ status = "okay";
>> -+ };
>> ++&uart0 {
>> ++ status = "okay";
>> ++};
>> +
>> -+ i2c at 11000 {
>> -+ clock-frequency = <100000>;
>> -+ status = "okay";
>> -+ };
>> ++&uart1 {
>> ++ status = "okay";
>> ++};
>> +
>> -+ mvsdio at d4000 {
>> -+ status = "disabled";
>> -+ };
>> ++&i2c0 {
>> ++ clock-frequency = <100000>;
>> ++ status = "okay";
>> ++};
>> +
>> -+ nand at d0000 {
>> -+ status = "okay";
>> -+ num-cs = <1>;
>> -+ marvell,nand-keep-config;
>> -+ marvell,nand-enable-arbiter;
>> -+ nand-on-flash-bbt;
>> -+ nand-ecc-strength = <4>;
>> -+ nand-ecc-step-size = <512>;
>> -+ };
>> -+ };
>> -+ };
>> ++&nand {
>> ++ status = "okay";
>> ++ num-cs = <1>;
>> ++ marvell,nand-keep-config;
>> ++ marvell,nand-enable-arbiter;
>> ++ nand-on-flash-bbt;
>> ++ nand-ecc-strength = <4>;
>> ++ nand-ecc-step-size = <512>;
>> +};
>> +
>> +&spi0 {
>>
>> --
>> 2.11.0.24.ge6920cf
>>
>
> --
> Gregory Clement, Free Electrons
> Kernel, drivers, real-time and embedded Linux
> development, consulting, training and support.
> http://free-electrons.com
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-27 16:49 ` Gregory CLEMENT
0 siblings, 0 replies; 49+ messages in thread
From: Gregory CLEMENT @ 2017-01-27 16:49 UTC (permalink / raw)
To: Stephen Boyd
Cc: Linus Walleij, Chris Packham, Mark Rutland, Andrew Lunn,
Geert Uytterhoeven, Michael Turquette, Laxman Dewangan,
linux-clk, Florian Fainelli, Juri Lelli, linux, Thierry Reding,
Sebastian Hesselbarth, devicetree, Jason Cooper, Arnd Bergmann,
linux-gpio, Rob Herring, Chris Brand, linux-arm-kernel,
Thomas Petazzoni, Kalyan Kinthada, linux-kernel, Sudeep Holla
Hi,
On ven., janv. 27 2017, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:
> Hi all,
>
> On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
>
>> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
>> integrated CPUs. They CPU block is common within these product lines and
>> (as far as I can tell/have been told) is based on the Armada XP. There
>> are a few differences due to the fact they have to squeeze the CPU into
>> the same package as the switch.
>>
>> I've rebased this series against linux-pinctrl/devel to get access to
>> mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to
>> v4.10.0-rc5.
>
> Just to let you know that I plan to apply the 3 arm patch once Chris
> will have sent the new series with the minor fixes I asked on patch 3.
I meant patch 2!
And now patch 5 too :)
Gregory
> I already applied them in the for-next branch to benefit of some build
> test coverage.
>
> Stephen,
>
> you gave your Acked-by on the first patch, but don't you plan to apply
> it on the clk branch?
>
> If you really want I can apply on mvebu but there is no build
> dependencies, so the order the patches will be merged is not important.
>
> Linus,
>
> I expect you will apply the pinctrl patch on your tree as it depend of
> code already there.
>
> Thanks,
>
> Gregory
>
>>
>> Chris Packham (4):
>> clk: mvebu: support for 98DX3236 SoC
>> Changes in v2:
>> - Update devicetree binding documentation for new compatible string
>> Changes in v3:
>> - Add 98dx3236 support to mvebu/clk-corediv.c rather than creating a new
>> driver.
>> - Document mv98dx3236-corediv-clock binding
>> Changes in v4:
>> - None
>> Changes in v5:
>> - Collect ack from Rob
>> - Remove explicit initialisation of fields to 0 in mv98dx3236_coreclks
>> - Register dummy clock provider for marvell,mv98dx3236-cpu-clock
>> arm: mvebu: support for SMP on 98DX3336 SoC
>> Changes in v2:
>> - Document new enable-method value
>> - Correct some references from 98DX4521 to 98DX3236
>> Changes in v3:
>> - Simplify mv98dx3236_resume_init by using of_io_request_and_map()
>> Changes in v4:
>> - integrate changes into platsmp.c instead of new init call
>> - avoid duplicated code.
>> - fix error return
>> - Collect ack from Rob
>> Changes in v5:
>> - Remove useless casts (thanks to Stephen Boyd)
>> arm: mvebu: Add device tree for 98DX3236 SoCs
>> Changes in v2:
>> - Update devicetree binding documentation to reflect that 98DX3336 and
>> 984251 are supersets of 98DX3236.
>> - disable crypto block
>> - disable sdio for 98DX3236, enable for 98DX4251
>> Changes in v3:
>> - fix typo 4521 -> 4251
>> - document prestera bindings
>> - rework corediv-clock binding
>> - add label to packet processor node
>> - add new compatible string for DFX server
>> Changes in v4:
>> - Collect ack from Rob
>> Changes in v5:
>> - Fixup license text. Add labels to nodes.
>> arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
>> Changes in v5:
>> - update license text
>> - use node labels
>>
>> Kalyan Kinthada (1):
>> pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
>> Changes in v2:
>> - include sdio support for the 98DX4251
>> Changes in v3:
>> - None
>> Changes in v4:
>> - Correct some discrepencies between binding and driver.
>> - Collect acks from Rob and Sebastian
>> Changes in v5:
>> - Update bindings to reflect "gpo" pins
>> - Use mvebu_mmio_mpp_ctrl instead of armada_xp_mpp_ctrl (note this is reliant
>> on changes queued in linux-pinctrl)
>>
>> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
>> .../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 16 ++
>> .../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ++
>> .../bindings/clock/mvebu-corediv-clock.txt | 1 +
>> .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 1 +
>> .../devicetree/bindings/net/marvell,prestera.txt | 50 ++++
>> .../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++
>> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 254 +++++++++++++++++++++
>> arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 76 ++++++
>> arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 90 ++++++++
>> arch/arm/boot/dts/db-dxbc2.dts | 151 ++++++++++++
>> arch/arm/boot/dts/db-xc3-24g4xg.dts | 142 ++++++++++++
>> arch/arm/mach-mvebu/platsmp.c | 86 +++++++
>> drivers/clk/mvebu/armada-xp.c | 39 ++++
>> drivers/clk/mvebu/clk-corediv.c | 23 ++
>> drivers/clk/mvebu/clk-cpu.c | 8 +
>> drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 156 +++++++++++++
>> 17 files changed, 1163 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
>> create mode 100644 Documentation/devicetree/bindings/net/marvell,prestera.txt
>> create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
>> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
>> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
>> create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
>> create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
>> create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
>>
>> interdiff to v4:
>>
>> diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
>> index 520562a7dc2a..c7b4e3a6b2c6 100644
>> @@ -85,7 +86,7 @@
>> by address and length of the PMU DFS registers
>> - #clock-cells : should be set to 1.
>> diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
>> -index b3094315a3c0..0413bf8284e0 100644
>> +index b3094315a3c0..890a863ae0d0 100644
>> --- a/drivers/clk/mvebu/armada-xp.c
>> +++ b/drivers/clk/mvebu/armada-xp.c
>> return 250000000;
>> @@ -118,9 +119,6 @@
>> +static const struct coreclk_soc_desc mv98dx3236_coreclks = {
>> + .get_tclk_freq = mv98dx3236_get_tclk_freq,
>> + .get_cpu_freq = mv98dx3236_get_cpu_freq,
>> -+ .get_clk_ratio = NULL,
>> -+ .ratios = NULL,
>> -+ .num_ratios = 0,
>> +};
>> +
>> /*
>> @@ -200,53 +198,16 @@
>> +CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock",
>> + mv98dx3236_corediv_clk_init);
>> diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
>> -index 5837eb8a212f..3b8f0e14fa01 100644
>> +index 5837eb8a212f..044892b6534d 100644
>> --- a/drivers/clk/mvebu/clk-cpu.c
>> +++ b/drivers/clk/mvebu/clk-cpu.c
>> - .set_rate = clk_cpu_set_rate,
>> - };
>> -
>> --static void __init of_cpu_clk_setup(struct device_node *node)
>> -+/* Add parameter to allow this to support different clock operations. */
>> -+static void __init _of_cpu_clk_setup(struct device_node *node,
>> -+ const struct clk_ops *cpu_clk_ops)
>> - {
>> - struct cpu_clk *cpuclk;
>> - void __iomem *clock_complex_base = of_iomap(node, 0);
>> - cpuclk[cpu].hw.init = &init;
>>
>> - init.name = cpuclk[cpu].clk_name;
>> -- init.ops = &cpu_ops;
>> -+ init.ops = cpu_clk_ops;
>> - init.flags = 0;
>> - init.parent_names = &cpuclk[cpu].parent_name;
>> - init.num_parents = 1;
>> - iounmap(clock_complex_base);
>> - }
>> -
>> -+/* Use this function to call the generic setup with the correct
>> -+ * clock operation
>> -+ */
>> -+static void __init of_cpu_clk_setup(struct device_node *node)
>> -+{
>> -+ _of_cpu_clk_setup(node, &cpu_ops);
>> -+}
>> -+
>> CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
>> of_cpu_clk_setup);
>> +
>> -+/* Define the clock and operations for the mv98dx3236 - it cannot perform
>> -+ * any operations.
>> -+ */
>> -+static const struct clk_ops mv98dx3236_cpu_ops = {
>> -+ .recalc_rate = NULL,
>> -+ .round_rate = NULL,
>> -+ .set_rate = NULL,
>> -+};
>> -+
>> +static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
>> +{
>> -+ _of_cpu_clk_setup(node, &mv98dx3236_cpu_ops);
>> ++ of_clk_add_provider(node, of_clk_src_simple_get, NULL);
>> +}
>> +
>> +CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
>> @@ -285,7 +247,7 @@
>> "qcom,gcc-msm8660"
>> diff --git
> a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
>> new file mode 100644
>> -index 000000000000..8082ba872edd
>> +index 000000000000..26eb9d3aa630
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
>> +Resume Control
>> @@ -304,10 +266,8 @@
>> + compatible = "marvell,98dx3336-resume-ctrl";
>> + reg = <0x20980 0x10>;
>> +};
>> -+
>> -+
>> diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
>> -index 46c742d3bd41..59be3ca0464f 100644
>> +index 46c742d3bd41..a5b464497e1a 100644
>> --- a/arch/arm/mach-mvebu/platsmp.c
>> +++ b/arch/arm/mach-mvebu/platsmp.c
>>
>> @@ -327,7 +287,7 @@
>> +static const struct of_device_id of_mv98dx3236_resume_table[] = {
>> + {
>> + .compatible = "marvell,98dx3336-resume-ctrl",
>> -+ .data = (void *)&mv98dx3336_resume_controller,
>> ++ .data = &mv98dx3336_resume_controller,
>> + },
>> + { /* end of list */ },
>> +};
>> @@ -337,7 +297,7 @@
>> + const struct of_device_id *match;
>> + struct device_node *np;
>> + void __iomem *base;
>> -+ struct resume_controller *rc;
>> ++ const struct resume_controller *rc;
>> +
>> + WARN_ON(hw_cpu != 1);
>> +
>> @@ -347,7 +307,7 @@
>> + return -ENODEV;
>> +
>> + base = of_io_request_and_map(np, 0, of_node_full_name(np));
>> -+ rc = (struct resume_controller *)match->data;
>> ++ rc = match->data;
>> + of_node_put(np);
>> + if (IS_ERR(base))
>> + return PTR_ERR(base);
>> @@ -411,15 +371,17 @@
>> diff --git
> a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
> b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
>> new file mode 100644
>> -index 000000000000..d4e6ecdfc853
>> +index 000000000000..97aef67ee769
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
>> +* Marvell 98dx3236 pinctrl driver for mpp
>> @@ -435,41 +397,41 @@
>> +
>> +name pins functions
>> +================================================================================
>> -+mpp0 0 gpio, spi0(mosi), dev(ad8)
>> ++mpp0 0 gpo, spi0(mosi), dev(ad8)
>> +mpp1 1 gpio, spi0(miso), dev(ad9)
>> -+mpp2 2 gpio, spi0(sck), dev(ad10)
>> ++mpp2 2 gpo, spi0(sck), dev(ad10)
>> +mpp3 3 gpio, spi0(cs0), dev(ad11)
>> +mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
>> +mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
>> -+mpp6 6 gpio, sd0(clk), dev(a2)
>> ++mpp6 6 gpo, sd0(clk), dev(a2)
>> +mpp7 7 gpio, sd0(d0), dev(ale0)
>> +mpp8 8 gpio, sd0(d1), dev(ale1)
>> +mpp9 9 gpio, sd0(d2), dev(ready0)
>> +mpp10 10 gpio, sd0(d3), dev(ad12)
>> +mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13)
>> -+mpp12 12 gpio, uart1(txd), uart0(rts), dev(ad14)
>> ++mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14)
>> +mpp13 13 gpio, intr(out), dev(ad15)
>> +mpp14 14 gpio, i2c0(sck)
>> +mpp15 15 gpio, i2c0(sda)
>> -+mpp16 16 gpio, dev(oe)
>> -+mpp17 17 gpio, dev(clk)
>> ++mpp16 16 gpo, dev(oe)
>> ++mpp17 17 gpo, dev(clkout)
>> +mpp18 18 gpio, uart1(txd)
>> +mpp19 19 gpio, uart1(rxd), dev(rb)
>> -+mpp20 20 gpio, dev(we)
>> -+mpp21 21 gpio, dev(ad0)
>> -+mpp22 22 gpio, dev(ad1)
>> -+mpp23 23 gpio, dev(ad2)
>> -+mpp24 24 gpio, dev(ad3)
>> -+mpp25 25 gpio, dev(ad4)
>> -+mpp26 26 gpio, dev(ad5)
>> -+mpp27 27 gpio, dev(ad6)
>> -+mpp28 28 gpio, dev(ad7)
>> -+mpp29 29 gpio, dev(a0)
>> -+mpp30 30 gpio, dev(a1)
>> ++mpp20 20 gpo, dev(we0)
>> ++mpp21 21 gpo, dev(ad0)
>> ++mpp22 22 gpo, dev(ad1)
>> ++mpp23 23 gpo, dev(ad2)
>> ++mpp24 24 gpo, dev(ad3)
>> ++mpp25 25 gpo, dev(ad4)
>> ++mpp26 26 gpo, dev(ad5)
>> ++mpp27 27 gpo, dev(ad6)
>> ++mpp28 28 gpo, dev(ad7)
>> ++mpp29 29 gpo, dev(a0)
>> ++mpp30 30 gpo, dev(a1)
>> +mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
>> +mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
>> diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
>> -index e4ea71a9d985..554eeae8cd21 100644
>> +index 63e1bd506983..61cbc138703e 100644
>> --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
>> +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
>> V_MV78460 = BIT(2),
>> @@ -495,8 +457,8 @@
>> + MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)),
>> + MPP_MODE(2,
>> -+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
>> -+ MPP_VAR_FUNCTION(0x2, "spi0", "csk", V_98DX3236_PLUS),
>> ++ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
>> ++ MPP_VAR_FUNCTION(0x2, "spi0", "sck", V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)),
>> + MPP_MODE(3,
>> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
>> @@ -511,7 +473,7 @@
>> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251),
>> -+ MPP_VAR_FUNCTION(0x4, "dev", "bootcs0", V_98DX3236_PLUS)),
>> ++ MPP_VAR_FUNCTION(0x4, "dev", "bootcs", V_98DX3236_PLUS)),
>> + MPP_MODE(6,
>> + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251),
>> @@ -563,7 +525,8 @@
>> + MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)),
>> + MPP_MODE(19,
>> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
>> -+ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS)),
>> ++ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS),
>> ++ MPP_VAR_FUNCTION(0x4, "dev", "rb", V_98DX3236_PLUS)),
>> + MPP_MODE(20,
>> + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)),
>> @@ -630,11 +593,11 @@
>> };
>>
>> +static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = {
>> -+ MPP_FUNC_CTRL(0, 32, NULL, armada_xp_mpp_ctrl),
>> ++ MPP_FUNC_CTRL(0, 32, NULL, mvebu_mmio_mpp_ctrl),
>> +};
>> +
>> +static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = {
>> -+ MPP_GPIO_RANGE(0, 0, 0, 32),
>> ++ MPP_GPIO_RANGE(0, 0, 0, 32),
>> +};
>> +
>> static int armada_xp_pinctrl_suspend(struct platform_device *pdev,
>> @@ -767,7 +731,7 @@
>> +};
>> diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
>> new file mode 100644
>> -index 000000000000..4b7b2fe3b682
>> +index 000000000000..9461128fae24
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
>> +/*
>> @@ -785,17 +749,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -804,11 +768,11 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> @@ -851,9 +815,9 @@
>> + MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
>> +
>> + /*
>> -+ * 98DX3236 has 1 x1 PCIe unit Gen2.0: One unit can be
>> ++ * 98DX3236 has 1 x1 PCIe unit Gen2.0
>> + */
>> -+ pcie-controller {
>> ++ pciec: pcie-controller@82000000 {
>> + compatible = "marvell,armada-xp-pcie";
>> + status = "disabled";
>> + device_type = "pci";
>> @@ -870,7 +834,7 @@
>> + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
>> + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;
>> +
>> -+ pcie@1,0 {
>> ++ pcie1: pcie@1,0 {
>> + device_type = "pci";
>> + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
>> + reg = <0x0800 0 0 0 0>;
>> @@ -967,7 +931,7 @@
>> + };
>> + };
>> +
>> -+ dfx-registers {
>> ++ dfxr: dfx-registers@ac000000 {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> @@ -987,7 +951,7 @@
>> + };
>> + };
>> +
>> -+ switch {
>> ++ switch: switch@a8000000 {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> @@ -1026,7 +990,7 @@
>> +};
>> diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
>> new file mode 100644
>> -index 000000000000..a9b0f47f8df9
>> +index 000000000000..e1580afdc260
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
>> +/*
>> @@ -1044,17 +1008,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -1063,16 +1027,16 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + *
>> -+ * Contains definitions specific to the 98dx3336 SoC that are not
>> ++ * Contains definitions specific to the 98dx3236 SoC that are not
>> + * common to all Armada XP SoCs.
>> + */
>> +
>> @@ -1107,7 +1071,7 @@
>> +};
>> diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
>> new file mode 100644
>> -index 000000000000..446e6e65ec59
>> +index 000000000000..4b0533a4ccb7
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
>> +/*
>> @@ -1125,17 +1089,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -1144,11 +1108,11 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> @@ -1213,15 +1177,15 @@
>> diff --git a/arch/arm/boot/dts/db-dxbc2.dts b/arch/arm/boot/dts/db-dxbc2.dts
>> new file mode 100644
>> -index 000000000000..f56786cea5f8
>> +index 000000000000..a8130805074e
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/db-dxbc2.dts
>> +/*
>> @@ -1241,17 +1205,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -1260,11 +1224,11 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> @@ -1295,66 +1259,58 @@
>> + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
>> + };
>> +
>> -+ soc {
>> -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
>> -+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
>> -+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
>> -+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
>> -+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
>> ++};
>> +
>> -+ devbus-bootcs {
>> -+ status = "okay";
>> ++&devbus_bootcs {
>> ++ status = "okay";
>> +
>> -+ /* Device Bus parameters are required */
>> ++ /* Device Bus parameters are required */
>> +
>> -+ /* Read parameters */
>> -+ devbus,bus-width = <16>;
>> -+ devbus,turn-off-ps = <60000>;
>> -+ devbus,badr-skew-ps = <0>;
>> -+ devbus,acc-first-ps = <124000>;
>> -+ devbus,acc-next-ps = <248000>;
>> -+ devbus,rd-setup-ps = <0>;
>> -+ devbus,rd-hold-ps = <0>;
>> -+
>> -+ /* Write parameters */
>> -+ devbus,sync-enable = <0>;
>> -+ devbus,wr-high-ps = <60000>;
>> -+ devbus,wr-low-ps = <60000>;
>> -+ devbus,ale-wr-ps = <60000>;
>> -+ };
>> ++ /* Read parameters */
>> ++ devbus,bus-width = <16>;
>> ++ devbus,turn-off-ps = <60000>;
>> ++ devbus,badr-skew-ps = <0>;
>> ++ devbus,acc-first-ps = <124000>;
>> ++ devbus,acc-next-ps = <248000>;
>> ++ devbus,rd-setup-ps = <0>;
>> ++ devbus,rd-hold-ps = <0>;
>> ++
>> ++ /* Write parameters */
>> ++ devbus,sync-enable = <0>;
>> ++ devbus,wr-high-ps = <60000>;
>> ++ devbus,wr-low-ps = <60000>;
>> ++ devbus,ale-wr-ps = <60000>;
>> ++};
>> +
>> -+ internal-regs {
>> -+ serial@12000 {
>> -+ status = "okay";
>> -+ };
>> -+ serial@12100 {
>> -+ status = "okay";
>> -+ };
>> ++&i2c0 {
>> ++ clock-frequency = <100000>;
>> ++ status = "okay";
>> ++};
>> +
>> -+ i2c@11000 {
>> -+ clock-frequency = <100000>;
>> -+ status = "okay";
>> -+ };
>> ++&uart0 {
>> ++ status = "okay";
>> ++};
>> +
>> -+ mvsdio@d4000 {
>> -+ pinctrl-0 = <&sdio_pins>;
>> -+ pinctrl-names = "default";
>> -+ status = "okay";
>> -+ /* No CD or WP GPIOs */
>> -+ broken-cd;
>> -+ };
>> ++&uart1 {
>> ++ status = "okay";
>> ++};
>> +
>> -+ nand@d0000 {
>> -+ status = "okay";
>> -+ num-cs = <1>;
>> -+ marvell,nand-keep-config;
>> -+ marvell,nand-enable-arbiter;
>> -+ nand-on-flash-bbt;
>> -+ nand-ecc-strength = <4>;
>> -+ nand-ecc-step-size = <512>;
>> -+ };
>> -+ };
>> -+ };
>> ++&nand {
>> ++ status = "okay";
>> ++ num-cs = <1>;
>> ++ marvell,nand-keep-config;
>> ++ marvell,nand-enable-arbiter;
>> ++ nand-on-flash-bbt;
>> ++ nand-ecc-strength = <4>;
>> ++ nand-ecc-step-size = <512>;
>> ++};
>> ++
>> ++&sdio {
>> ++ pinctrl-0 = <&sdio_pins>;
>> ++ pinctrl-names = "default";
>> ++ status = "okay";
>> ++ /* No CD or WP GPIOs */
>> ++ broken-cd;
>> +};
>> +
>> +&spi0 {
>> @@ -1385,7 +1341,7 @@
>> +};
>> diff --git a/arch/arm/boot/dts/db-xc3-24g4xg.dts b/arch/arm/boot/dts/db-xc3-24g4xg.dts
>> new file mode 100644
>> -index 000000000000..5eb89ffb9a7d
>> +index 000000000000..4e07cb6ed800
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/db-xc3-24g4xg.dts
>> +/*
>> @@ -1405,17 +1361,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -1424,11 +1380,11 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> @@ -1458,63 +1414,50 @@
>> + device_type = "memory";
>> + reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
>> + };
>> ++};
>> +
>> -+ soc {
>> -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
>> -+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
>> -+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
>> -+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
>> -+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
>> -+
>> -+ devbus-bootcs {
>> -+ status = "okay";
>> ++&devbus_bootcs {
>> ++ status = "okay";
>> +
>> -+ /* Device Bus parameters are required */
>> ++ /* Device Bus parameters are required */
>> +
>> -+ /* Read parameters */
>> -+ devbus,bus-width = <16>;
>> -+ devbus,turn-off-ps = <60000>;
>> -+ devbus,badr-skew-ps = <0>;
>> -+ devbus,acc-first-ps = <124000>;
>> -+ devbus,acc-next-ps = <248000>;
>> -+ devbus,rd-setup-ps = <0>;
>> -+ devbus,rd-hold-ps = <0>;
>> -+
>> -+ /* Write parameters */
>> -+ devbus,sync-enable = <0>;
>> -+ devbus,wr-high-ps = <60000>;
>> -+ devbus,wr-low-ps = <60000>;
>> -+ devbus,ale-wr-ps = <60000>;
>> -+ };
>> ++ /* Read parameters */
>> ++ devbus,bus-width = <16>;
>> ++ devbus,turn-off-ps = <60000>;
>> ++ devbus,badr-skew-ps = <0>;
>> ++ devbus,acc-first-ps = <124000>;
>> ++ devbus,acc-next-ps = <248000>;
>> ++ devbus,rd-setup-ps = <0>;
>> ++ devbus,rd-hold-ps = <0>;
>> ++
>> ++ /* Write parameters */
>> ++ devbus,sync-enable = <0>;
>> ++ devbus,wr-high-ps = <60000>;
>> ++ devbus,wr-low-ps = <60000>;
>> ++ devbus,ale-wr-ps = <60000>;
>> ++};
>> +
>> -+ internal-regs {
>> -+ serial@12000 {
>> -+ status = "okay";
>> -+ };
>> -+ serial@12100 {
>> -+ status = "okay";
>> -+ };
>> ++&uart0 {
>> ++ status = "okay";
>> ++};
>> +
>> -+ i2c@11000 {
>> -+ clock-frequency = <100000>;
>> -+ status = "okay";
>> -+ };
>> ++&uart1 {
>> ++ status = "okay";
>> ++};
>> +
>> -+ mvsdio@d4000 {
>> -+ status = "disabled";
>> -+ };
>> ++&i2c0 {
>> ++ clock-frequency = <100000>;
>> ++ status = "okay";
>> ++};
>> +
>> -+ nand@d0000 {
>> -+ status = "okay";
>> -+ num-cs = <1>;
>> -+ marvell,nand-keep-config;
>> -+ marvell,nand-enable-arbiter;
>> -+ nand-on-flash-bbt;
>> -+ nand-ecc-strength = <4>;
>> -+ nand-ecc-step-size = <512>;
>> -+ };
>> -+ };
>> -+ };
>> ++&nand {
>> ++ status = "okay";
>> ++ num-cs = <1>;
>> ++ marvell,nand-keep-config;
>> ++ marvell,nand-enable-arbiter;
>> ++ nand-on-flash-bbt;
>> ++ nand-ecc-strength = <4>;
>> ++ nand-ecc-step-size = <512>;
>> +};
>> +
>> +&spi0 {
>>
>> --
>> 2.11.0.24.ge6920cf
>>
>
> --
> Gregory Clement, Free Electrons
> Kernel, drivers, real-time and embedded Linux
> development, consulting, training and support.
> http://free-electrons.com
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-27 16:49 ` Gregory CLEMENT
0 siblings, 0 replies; 49+ messages in thread
From: Gregory CLEMENT @ 2017-01-27 16:49 UTC (permalink / raw)
To: Stephen Boyd
Cc: Linus Walleij, Chris Packham, Mark Rutland, Andrew Lunn,
Geert Uytterhoeven, Michael Turquette, Laxman Dewangan,
linux-clk, Florian Fainelli, Juri Lelli, linux, Thierry Reding,
Sebastian Hesselbarth, devicetree, Jason Cooper, Arnd Bergmann,
linux-gpio, Rob Herring, Chris Brand, linux-arm-kernel,
Thomas Petazzoni, Kalyan Kinthada, linux-kernel, Sudeep Holla
Hi,
On ven., janv. 27 2017, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:
> Hi all,
>
> On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
>
>> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
>> integrated CPUs. They CPU block is common within these product lines and
>> (as far as I can tell/have been told) is based on the Armada XP. There
>> are a few differences due to the fact they have to squeeze the CPU into
>> the same package as the switch.
>>
>> I've rebased this series against linux-pinctrl/devel to get access to
>> mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to
>> v4.10.0-rc5.
>
> Just to let you know that I plan to apply the 3 arm patch once Chris
> will have sent the new series with the minor fixes I asked on patch 3.
I meant patch 2!
And now patch 5 too :)
Gregory
> I already applied them in the for-next branch to benefit of some build
> test coverage.
>
> Stephen,
>
> you gave your Acked-by on the first patch, but don't you plan to apply
> it on the clk branch?
>
> If you really want I can apply on mvebu but there is no build
> dependencies, so the order the patches will be merged is not important.
>
> Linus,
>
> I expect you will apply the pinctrl patch on your tree as it depend of
> code already there.
>
> Thanks,
>
> Gregory
>
>>
>> Chris Packham (4):
>> clk: mvebu: support for 98DX3236 SoC
>> Changes in v2:
>> - Update devicetree binding documentation for new compatible string
>> Changes in v3:
>> - Add 98dx3236 support to mvebu/clk-corediv.c rather than creating a new
>> driver.
>> - Document mv98dx3236-corediv-clock binding
>> Changes in v4:
>> - None
>> Changes in v5:
>> - Collect ack from Rob
>> - Remove explicit initialisation of fields to 0 in mv98dx3236_coreclks
>> - Register dummy clock provider for marvell,mv98dx3236-cpu-clock
>> arm: mvebu: support for SMP on 98DX3336 SoC
>> Changes in v2:
>> - Document new enable-method value
>> - Correct some references from 98DX4521 to 98DX3236
>> Changes in v3:
>> - Simplify mv98dx3236_resume_init by using of_io_request_and_map()
>> Changes in v4:
>> - integrate changes into platsmp.c instead of new init call
>> - avoid duplicated code.
>> - fix error return
>> - Collect ack from Rob
>> Changes in v5:
>> - Remove useless casts (thanks to Stephen Boyd)
>> arm: mvebu: Add device tree for 98DX3236 SoCs
>> Changes in v2:
>> - Update devicetree binding documentation to reflect that 98DX3336 and
>> 984251 are supersets of 98DX3236.
>> - disable crypto block
>> - disable sdio for 98DX3236, enable for 98DX4251
>> Changes in v3:
>> - fix typo 4521 -> 4251
>> - document prestera bindings
>> - rework corediv-clock binding
>> - add label to packet processor node
>> - add new compatible string for DFX server
>> Changes in v4:
>> - Collect ack from Rob
>> Changes in v5:
>> - Fixup license text. Add labels to nodes.
>> arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
>> Changes in v5:
>> - update license text
>> - use node labels
>>
>> Kalyan Kinthada (1):
>> pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
>> Changes in v2:
>> - include sdio support for the 98DX4251
>> Changes in v3:
>> - None
>> Changes in v4:
>> - Correct some discrepencies between binding and driver.
>> - Collect acks from Rob and Sebastian
>> Changes in v5:
>> - Update bindings to reflect "gpo" pins
>> - Use mvebu_mmio_mpp_ctrl instead of armada_xp_mpp_ctrl (note this is reliant
>> on changes queued in linux-pinctrl)
>>
>> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
>> .../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 16 ++
>> .../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ++
>> .../bindings/clock/mvebu-corediv-clock.txt | 1 +
>> .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 1 +
>> .../devicetree/bindings/net/marvell,prestera.txt | 50 ++++
>> .../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++
>> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 254 +++++++++++++++++++++
>> arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 76 ++++++
>> arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 90 ++++++++
>> arch/arm/boot/dts/db-dxbc2.dts | 151 ++++++++++++
>> arch/arm/boot/dts/db-xc3-24g4xg.dts | 142 ++++++++++++
>> arch/arm/mach-mvebu/platsmp.c | 86 +++++++
>> drivers/clk/mvebu/armada-xp.c | 39 ++++
>> drivers/clk/mvebu/clk-corediv.c | 23 ++
>> drivers/clk/mvebu/clk-cpu.c | 8 +
>> drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 156 +++++++++++++
>> 17 files changed, 1163 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
>> create mode 100644 Documentation/devicetree/bindings/net/marvell,prestera.txt
>> create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
>> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
>> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
>> create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
>> create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
>> create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
>>
>> interdiff to v4:
>>
>> diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
>> index 520562a7dc2a..c7b4e3a6b2c6 100644
>> @@ -85,7 +86,7 @@
>> by address and length of the PMU DFS registers
>> - #clock-cells : should be set to 1.
>> diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
>> -index b3094315a3c0..0413bf8284e0 100644
>> +index b3094315a3c0..890a863ae0d0 100644
>> --- a/drivers/clk/mvebu/armada-xp.c
>> +++ b/drivers/clk/mvebu/armada-xp.c
>> return 250000000;
>> @@ -118,9 +119,6 @@
>> +static const struct coreclk_soc_desc mv98dx3236_coreclks = {
>> + .get_tclk_freq = mv98dx3236_get_tclk_freq,
>> + .get_cpu_freq = mv98dx3236_get_cpu_freq,
>> -+ .get_clk_ratio = NULL,
>> -+ .ratios = NULL,
>> -+ .num_ratios = 0,
>> +};
>> +
>> /*
>> @@ -200,53 +198,16 @@
>> +CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock",
>> + mv98dx3236_corediv_clk_init);
>> diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
>> -index 5837eb8a212f..3b8f0e14fa01 100644
>> +index 5837eb8a212f..044892b6534d 100644
>> --- a/drivers/clk/mvebu/clk-cpu.c
>> +++ b/drivers/clk/mvebu/clk-cpu.c
>> - .set_rate = clk_cpu_set_rate,
>> - };
>> -
>> --static void __init of_cpu_clk_setup(struct device_node *node)
>> -+/* Add parameter to allow this to support different clock operations. */
>> -+static void __init _of_cpu_clk_setup(struct device_node *node,
>> -+ const struct clk_ops *cpu_clk_ops)
>> - {
>> - struct cpu_clk *cpuclk;
>> - void __iomem *clock_complex_base = of_iomap(node, 0);
>> - cpuclk[cpu].hw.init = &init;
>>
>> - init.name = cpuclk[cpu].clk_name;
>> -- init.ops = &cpu_ops;
>> -+ init.ops = cpu_clk_ops;
>> - init.flags = 0;
>> - init.parent_names = &cpuclk[cpu].parent_name;
>> - init.num_parents = 1;
>> - iounmap(clock_complex_base);
>> - }
>> -
>> -+/* Use this function to call the generic setup with the correct
>> -+ * clock operation
>> -+ */
>> -+static void __init of_cpu_clk_setup(struct device_node *node)
>> -+{
>> -+ _of_cpu_clk_setup(node, &cpu_ops);
>> -+}
>> -+
>> CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
>> of_cpu_clk_setup);
>> +
>> -+/* Define the clock and operations for the mv98dx3236 - it cannot perform
>> -+ * any operations.
>> -+ */
>> -+static const struct clk_ops mv98dx3236_cpu_ops = {
>> -+ .recalc_rate = NULL,
>> -+ .round_rate = NULL,
>> -+ .set_rate = NULL,
>> -+};
>> -+
>> +static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
>> +{
>> -+ _of_cpu_clk_setup(node, &mv98dx3236_cpu_ops);
>> ++ of_clk_add_provider(node, of_clk_src_simple_get, NULL);
>> +}
>> +
>> +CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
>> @@ -285,7 +247,7 @@
>> "qcom,gcc-msm8660"
>> diff --git
> a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
>> new file mode 100644
>> -index 000000000000..8082ba872edd
>> +index 000000000000..26eb9d3aa630
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
>> +Resume Control
>> @@ -304,10 +266,8 @@
>> + compatible = "marvell,98dx3336-resume-ctrl";
>> + reg = <0x20980 0x10>;
>> +};
>> -+
>> -+
>> diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
>> -index 46c742d3bd41..59be3ca0464f 100644
>> +index 46c742d3bd41..a5b464497e1a 100644
>> --- a/arch/arm/mach-mvebu/platsmp.c
>> +++ b/arch/arm/mach-mvebu/platsmp.c
>>
>> @@ -327,7 +287,7 @@
>> +static const struct of_device_id of_mv98dx3236_resume_table[] = {
>> + {
>> + .compatible = "marvell,98dx3336-resume-ctrl",
>> -+ .data = (void *)&mv98dx3336_resume_controller,
>> ++ .data = &mv98dx3336_resume_controller,
>> + },
>> + { /* end of list */ },
>> +};
>> @@ -337,7 +297,7 @@
>> + const struct of_device_id *match;
>> + struct device_node *np;
>> + void __iomem *base;
>> -+ struct resume_controller *rc;
>> ++ const struct resume_controller *rc;
>> +
>> + WARN_ON(hw_cpu != 1);
>> +
>> @@ -347,7 +307,7 @@
>> + return -ENODEV;
>> +
>> + base = of_io_request_and_map(np, 0, of_node_full_name(np));
>> -+ rc = (struct resume_controller *)match->data;
>> ++ rc = match->data;
>> + of_node_put(np);
>> + if (IS_ERR(base))
>> + return PTR_ERR(base);
>> @@ -411,15 +371,17 @@
>> diff --git
> a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
> b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
>> new file mode 100644
>> -index 000000000000..d4e6ecdfc853
>> +index 000000000000..97aef67ee769
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
>> +* Marvell 98dx3236 pinctrl driver for mpp
>> @@ -435,41 +397,41 @@
>> +
>> +name pins functions
>> +================================================================================
>> -+mpp0 0 gpio, spi0(mosi), dev(ad8)
>> ++mpp0 0 gpo, spi0(mosi), dev(ad8)
>> +mpp1 1 gpio, spi0(miso), dev(ad9)
>> -+mpp2 2 gpio, spi0(sck), dev(ad10)
>> ++mpp2 2 gpo, spi0(sck), dev(ad10)
>> +mpp3 3 gpio, spi0(cs0), dev(ad11)
>> +mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
>> +mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
>> -+mpp6 6 gpio, sd0(clk), dev(a2)
>> ++mpp6 6 gpo, sd0(clk), dev(a2)
>> +mpp7 7 gpio, sd0(d0), dev(ale0)
>> +mpp8 8 gpio, sd0(d1), dev(ale1)
>> +mpp9 9 gpio, sd0(d2), dev(ready0)
>> +mpp10 10 gpio, sd0(d3), dev(ad12)
>> +mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13)
>> -+mpp12 12 gpio, uart1(txd), uart0(rts), dev(ad14)
>> ++mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14)
>> +mpp13 13 gpio, intr(out), dev(ad15)
>> +mpp14 14 gpio, i2c0(sck)
>> +mpp15 15 gpio, i2c0(sda)
>> -+mpp16 16 gpio, dev(oe)
>> -+mpp17 17 gpio, dev(clk)
>> ++mpp16 16 gpo, dev(oe)
>> ++mpp17 17 gpo, dev(clkout)
>> +mpp18 18 gpio, uart1(txd)
>> +mpp19 19 gpio, uart1(rxd), dev(rb)
>> -+mpp20 20 gpio, dev(we)
>> -+mpp21 21 gpio, dev(ad0)
>> -+mpp22 22 gpio, dev(ad1)
>> -+mpp23 23 gpio, dev(ad2)
>> -+mpp24 24 gpio, dev(ad3)
>> -+mpp25 25 gpio, dev(ad4)
>> -+mpp26 26 gpio, dev(ad5)
>> -+mpp27 27 gpio, dev(ad6)
>> -+mpp28 28 gpio, dev(ad7)
>> -+mpp29 29 gpio, dev(a0)
>> -+mpp30 30 gpio, dev(a1)
>> ++mpp20 20 gpo, dev(we0)
>> ++mpp21 21 gpo, dev(ad0)
>> ++mpp22 22 gpo, dev(ad1)
>> ++mpp23 23 gpo, dev(ad2)
>> ++mpp24 24 gpo, dev(ad3)
>> ++mpp25 25 gpo, dev(ad4)
>> ++mpp26 26 gpo, dev(ad5)
>> ++mpp27 27 gpo, dev(ad6)
>> ++mpp28 28 gpo, dev(ad7)
>> ++mpp29 29 gpo, dev(a0)
>> ++mpp30 30 gpo, dev(a1)
>> +mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
>> +mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
>> diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
>> -index e4ea71a9d985..554eeae8cd21 100644
>> +index 63e1bd506983..61cbc138703e 100644
>> --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
>> +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
>> V_MV78460 = BIT(2),
>> @@ -495,8 +457,8 @@
>> + MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)),
>> + MPP_MODE(2,
>> -+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
>> -+ MPP_VAR_FUNCTION(0x2, "spi0", "csk", V_98DX3236_PLUS),
>> ++ MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
>> ++ MPP_VAR_FUNCTION(0x2, "spi0", "sck", V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)),
>> + MPP_MODE(3,
>> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
>> @@ -511,7 +473,7 @@
>> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251),
>> -+ MPP_VAR_FUNCTION(0x4, "dev", "bootcs0", V_98DX3236_PLUS)),
>> ++ MPP_VAR_FUNCTION(0x4, "dev", "bootcs", V_98DX3236_PLUS)),
>> + MPP_MODE(6,
>> + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251),
>> @@ -563,7 +525,8 @@
>> + MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)),
>> + MPP_MODE(19,
>> + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
>> -+ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS)),
>> ++ MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS),
>> ++ MPP_VAR_FUNCTION(0x4, "dev", "rb", V_98DX3236_PLUS)),
>> + MPP_MODE(20,
>> + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
>> + MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)),
>> @@ -630,11 +593,11 @@
>> };
>>
>> +static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = {
>> -+ MPP_FUNC_CTRL(0, 32, NULL, armada_xp_mpp_ctrl),
>> ++ MPP_FUNC_CTRL(0, 32, NULL, mvebu_mmio_mpp_ctrl),
>> +};
>> +
>> +static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = {
>> -+ MPP_GPIO_RANGE(0, 0, 0, 32),
>> ++ MPP_GPIO_RANGE(0, 0, 0, 32),
>> +};
>> +
>> static int armada_xp_pinctrl_suspend(struct platform_device *pdev,
>> @@ -767,7 +731,7 @@
>> +};
>> diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
>> new file mode 100644
>> -index 000000000000..4b7b2fe3b682
>> +index 000000000000..9461128fae24
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
>> +/*
>> @@ -785,17 +749,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -804,11 +768,11 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> @@ -851,9 +815,9 @@
>> + MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
>> +
>> + /*
>> -+ * 98DX3236 has 1 x1 PCIe unit Gen2.0: One unit can be
>> ++ * 98DX3236 has 1 x1 PCIe unit Gen2.0
>> + */
>> -+ pcie-controller {
>> ++ pciec: pcie-controller@82000000 {
>> + compatible = "marvell,armada-xp-pcie";
>> + status = "disabled";
>> + device_type = "pci";
>> @@ -870,7 +834,7 @@
>> + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
>> + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;
>> +
>> -+ pcie@1,0 {
>> ++ pcie1: pcie@1,0 {
>> + device_type = "pci";
>> + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
>> + reg = <0x0800 0 0 0 0>;
>> @@ -967,7 +931,7 @@
>> + };
>> + };
>> +
>> -+ dfx-registers {
>> ++ dfxr: dfx-registers@ac000000 {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> @@ -987,7 +951,7 @@
>> + };
>> + };
>> +
>> -+ switch {
>> ++ switch: switch@a8000000 {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> @@ -1026,7 +990,7 @@
>> +};
>> diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
>> new file mode 100644
>> -index 000000000000..a9b0f47f8df9
>> +index 000000000000..e1580afdc260
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
>> +/*
>> @@ -1044,17 +1008,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -1063,16 +1027,16 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + *
>> -+ * Contains definitions specific to the 98dx3336 SoC that are not
>> ++ * Contains definitions specific to the 98dx3236 SoC that are not
>> + * common to all Armada XP SoCs.
>> + */
>> +
>> @@ -1107,7 +1071,7 @@
>> +};
>> diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
>> new file mode 100644
>> -index 000000000000..446e6e65ec59
>> +index 000000000000..4b0533a4ccb7
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
>> +/*
>> @@ -1125,17 +1089,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -1144,11 +1108,11 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> @@ -1213,15 +1177,15 @@
>> diff --git a/arch/arm/boot/dts/db-dxbc2.dts b/arch/arm/boot/dts/db-dxbc2.dts
>> new file mode 100644
>> -index 000000000000..f56786cea5f8
>> +index 000000000000..a8130805074e
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/db-dxbc2.dts
>> +/*
>> @@ -1241,17 +1205,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -1260,11 +1224,11 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> @@ -1295,66 +1259,58 @@
>> + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
>> + };
>> +
>> -+ soc {
>> -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
>> -+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
>> -+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
>> -+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
>> -+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
>> ++};
>> +
>> -+ devbus-bootcs {
>> -+ status = "okay";
>> ++&devbus_bootcs {
>> ++ status = "okay";
>> +
>> -+ /* Device Bus parameters are required */
>> ++ /* Device Bus parameters are required */
>> +
>> -+ /* Read parameters */
>> -+ devbus,bus-width = <16>;
>> -+ devbus,turn-off-ps = <60000>;
>> -+ devbus,badr-skew-ps = <0>;
>> -+ devbus,acc-first-ps = <124000>;
>> -+ devbus,acc-next-ps = <248000>;
>> -+ devbus,rd-setup-ps = <0>;
>> -+ devbus,rd-hold-ps = <0>;
>> -+
>> -+ /* Write parameters */
>> -+ devbus,sync-enable = <0>;
>> -+ devbus,wr-high-ps = <60000>;
>> -+ devbus,wr-low-ps = <60000>;
>> -+ devbus,ale-wr-ps = <60000>;
>> -+ };
>> ++ /* Read parameters */
>> ++ devbus,bus-width = <16>;
>> ++ devbus,turn-off-ps = <60000>;
>> ++ devbus,badr-skew-ps = <0>;
>> ++ devbus,acc-first-ps = <124000>;
>> ++ devbus,acc-next-ps = <248000>;
>> ++ devbus,rd-setup-ps = <0>;
>> ++ devbus,rd-hold-ps = <0>;
>> ++
>> ++ /* Write parameters */
>> ++ devbus,sync-enable = <0>;
>> ++ devbus,wr-high-ps = <60000>;
>> ++ devbus,wr-low-ps = <60000>;
>> ++ devbus,ale-wr-ps = <60000>;
>> ++};
>> +
>> -+ internal-regs {
>> -+ serial@12000 {
>> -+ status = "okay";
>> -+ };
>> -+ serial@12100 {
>> -+ status = "okay";
>> -+ };
>> ++&i2c0 {
>> ++ clock-frequency = <100000>;
>> ++ status = "okay";
>> ++};
>> +
>> -+ i2c@11000 {
>> -+ clock-frequency = <100000>;
>> -+ status = "okay";
>> -+ };
>> ++&uart0 {
>> ++ status = "okay";
>> ++};
>> +
>> -+ mvsdio@d4000 {
>> -+ pinctrl-0 = <&sdio_pins>;
>> -+ pinctrl-names = "default";
>> -+ status = "okay";
>> -+ /* No CD or WP GPIOs */
>> -+ broken-cd;
>> -+ };
>> ++&uart1 {
>> ++ status = "okay";
>> ++};
>> +
>> -+ nand@d0000 {
>> -+ status = "okay";
>> -+ num-cs = <1>;
>> -+ marvell,nand-keep-config;
>> -+ marvell,nand-enable-arbiter;
>> -+ nand-on-flash-bbt;
>> -+ nand-ecc-strength = <4>;
>> -+ nand-ecc-step-size = <512>;
>> -+ };
>> -+ };
>> -+ };
>> ++&nand {
>> ++ status = "okay";
>> ++ num-cs = <1>;
>> ++ marvell,nand-keep-config;
>> ++ marvell,nand-enable-arbiter;
>> ++ nand-on-flash-bbt;
>> ++ nand-ecc-strength = <4>;
>> ++ nand-ecc-step-size = <512>;
>> ++};
>> ++
>> ++&sdio {
>> ++ pinctrl-0 = <&sdio_pins>;
>> ++ pinctrl-names = "default";
>> ++ status = "okay";
>> ++ /* No CD or WP GPIOs */
>> ++ broken-cd;
>> +};
>> +
>> +&spi0 {
>> @@ -1385,7 +1341,7 @@
>> +};
>> diff --git a/arch/arm/boot/dts/db-xc3-24g4xg.dts b/arch/arm/boot/dts/db-xc3-24g4xg.dts
>> new file mode 100644
>> -index 000000000000..5eb89ffb9a7d
>> +index 000000000000..4e07cb6ed800
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/db-xc3-24g4xg.dts
>> +/*
>> @@ -1405,17 +1361,17 @@
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> -+ * This file is distributed in the hope that it will be useful
>> ++ * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> -+ * Or, alternatively
>> ++ * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> -+ * restriction, including without limitation the rights to use
>> ++ * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> @@ -1424,11 +1380,11 @@
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
>> ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
>> ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> @@ -1458,63 +1414,50 @@
>> + device_type = "memory";
>> + reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
>> + };
>> ++};
>> +
>> -+ soc {
>> -+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
>> -+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
>> -+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
>> -+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
>> -+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
>> -+
>> -+ devbus-bootcs {
>> -+ status = "okay";
>> ++&devbus_bootcs {
>> ++ status = "okay";
>> +
>> -+ /* Device Bus parameters are required */
>> ++ /* Device Bus parameters are required */
>> +
>> -+ /* Read parameters */
>> -+ devbus,bus-width = <16>;
>> -+ devbus,turn-off-ps = <60000>;
>> -+ devbus,badr-skew-ps = <0>;
>> -+ devbus,acc-first-ps = <124000>;
>> -+ devbus,acc-next-ps = <248000>;
>> -+ devbus,rd-setup-ps = <0>;
>> -+ devbus,rd-hold-ps = <0>;
>> -+
>> -+ /* Write parameters */
>> -+ devbus,sync-enable = <0>;
>> -+ devbus,wr-high-ps = <60000>;
>> -+ devbus,wr-low-ps = <60000>;
>> -+ devbus,ale-wr-ps = <60000>;
>> -+ };
>> ++ /* Read parameters */
>> ++ devbus,bus-width = <16>;
>> ++ devbus,turn-off-ps = <60000>;
>> ++ devbus,badr-skew-ps = <0>;
>> ++ devbus,acc-first-ps = <124000>;
>> ++ devbus,acc-next-ps = <248000>;
>> ++ devbus,rd-setup-ps = <0>;
>> ++ devbus,rd-hold-ps = <0>;
>> ++
>> ++ /* Write parameters */
>> ++ devbus,sync-enable = <0>;
>> ++ devbus,wr-high-ps = <60000>;
>> ++ devbus,wr-low-ps = <60000>;
>> ++ devbus,ale-wr-ps = <60000>;
>> ++};
>> +
>> -+ internal-regs {
>> -+ serial@12000 {
>> -+ status = "okay";
>> -+ };
>> -+ serial@12100 {
>> -+ status = "okay";
>> -+ };
>> ++&uart0 {
>> ++ status = "okay";
>> ++};
>> +
>> -+ i2c@11000 {
>> -+ clock-frequency = <100000>;
>> -+ status = "okay";
>> -+ };
>> ++&uart1 {
>> ++ status = "okay";
>> ++};
>> +
>> -+ mvsdio@d4000 {
>> -+ status = "disabled";
>> -+ };
>> ++&i2c0 {
>> ++ clock-frequency = <100000>;
>> ++ status = "okay";
>> ++};
>> +
>> -+ nand@d0000 {
>> -+ status = "okay";
>> -+ num-cs = <1>;
>> -+ marvell,nand-keep-config;
>> -+ marvell,nand-enable-arbiter;
>> -+ nand-on-flash-bbt;
>> -+ nand-ecc-strength = <4>;
>> -+ nand-ecc-step-size = <512>;
>> -+ };
>> -+ };
>> -+ };
>> ++&nand {
>> ++ status = "okay";
>> ++ num-cs = <1>;
>> ++ marvell,nand-keep-config;
>> ++ marvell,nand-enable-arbiter;
>> ++ nand-on-flash-bbt;
>> ++ nand-ecc-strength = <4>;
>> ++ nand-ecc-step-size = <512>;
>> +};
>> +
>> +&spi0 {
>>
>> --
>> 2.11.0.24.ge6920cf
>>
>
> --
> Gregory Clement, Free Electrons
> Kernel, drivers, real-time and embedded Linux
> development, consulting, training and support.
> http://free-electrons.com
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
2017-01-27 16:39 ` Gregory CLEMENT
(?)
@ 2017-01-27 18:47 ` Stephen Boyd
-1 siblings, 0 replies; 49+ messages in thread
From: Stephen Boyd @ 2017-01-27 18:47 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Mark Rutland, Andrew Lunn, Geert Uytterhoeven, Linus Walleij,
Laxman Dewangan, linux-clk, Florian Fainelli, Juri Lelli, linux,
Thierry Reding, Michael Turquette, Sebastian Hesselbarth,
devicetree, Jason Cooper, Arnd Bergmann, Kalyan Kinthada,
Rob Herring, Chris Brand, linux-arm-kernel, Thomas Petazzoni,
linux-gpio, linux-kernel, Chris Packham
On 01/27, Gregory CLEMENT wrote:
> Hi all,
>
> On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
>
> > The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
> > integrated CPUs. They CPU block is common within these product lines and
> > (as far as I can tell/have been told) is based on the Armada XP. There
> > are a few differences due to the fact they have to squeeze the CPU into
> > the same package as the switch.
> >
> > I've rebased this series against linux-pinctrl/devel to get access to
> > mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to
> > v4.10.0-rc5.
>
> Just to let you know that I plan to apply the 3 arm patch once Chris
> will have sent the new series with the minor fixes I asked on patch 3.
>
> I already applied them in the for-next branch to benefit of some build
> test coverage.
>
> Stephen,
>
> you gave your Acked-by on the first patch, but don't you plan to apply
> it on the clk branch?
It must have not been clear if I should apply it, hence the ack.
I'll apply it now.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-27 18:47 ` Stephen Boyd
0 siblings, 0 replies; 49+ messages in thread
From: Stephen Boyd @ 2017-01-27 18:47 UTC (permalink / raw)
To: linux-arm-kernel
On 01/27, Gregory CLEMENT wrote:
> Hi all,
>
> On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
>
> > The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
> > integrated CPUs. They CPU block is common within these product lines and
> > (as far as I can tell/have been told) is based on the Armada XP. There
> > are a few differences due to the fact they have to squeeze the CPU into
> > the same package as the switch.
> >
> > I've rebased this series against linux-pinctrl/devel to get access to
> > mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to
> > v4.10.0-rc5.
>
> Just to let you know that I plan to apply the 3 arm patch once Chris
> will have sent the new series with the minor fixes I asked on patch 3.
>
> I already applied them in the for-next branch to benefit of some build
> test coverage.
>
> Stephen,
>
> you gave your Acked-by on the first patch, but don't you plan to apply
> it on the clk branch?
It must have not been clear if I should apply it, hence the ack.
I'll apply it now.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-27 18:47 ` Stephen Boyd
0 siblings, 0 replies; 49+ messages in thread
From: Stephen Boyd @ 2017-01-27 18:47 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Linus Walleij, Chris Packham, linux, linux-arm-kernel,
Rob Herring, Mark Rutland, Michael Turquette, Jason Cooper,
Andrew Lunn, Sebastian Hesselbarth, Geert Uytterhoeven,
Chris Brand, Florian Fainelli, Arnd Bergmann, Thierry Reding,
Sudeep Holla, Juri Lelli, Thomas Petazzoni, Laxman Dewangan,
Kalyan Kinthada, devicetree, linux-kernel, linux-clk, linux-gpio
On 01/27, Gregory CLEMENT wrote:
> Hi all,
>
> On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
>
> > The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
> > integrated CPUs. They CPU block is common within these product lines and
> > (as far as I can tell/have been told) is based on the Armada XP. There
> > are a few differences due to the fact they have to squeeze the CPU into
> > the same package as the switch.
> >
> > I've rebased this series against linux-pinctrl/devel to get access to
> > mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to
> > v4.10.0-rc5.
>
> Just to let you know that I plan to apply the 3 arm patch once Chris
> will have sent the new series with the minor fixes I asked on patch 3.
>
> I already applied them in the for-next branch to benefit of some build
> test coverage.
>
> Stephen,
>
> you gave your Acked-by on the first patch, but don't you plan to apply
> it on the clk branch?
It must have not been clear if I should apply it, hence the ack.
I'll apply it now.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
2017-01-27 18:47 ` Stephen Boyd
(?)
(?)
@ 2017-01-29 20:30 ` Chris Packham
-1 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-29 20:30 UTC (permalink / raw)
To: Stephen Boyd, Gregory CLEMENT
Cc: Linus Walleij, linux, linux-arm-kernel, Rob Herring,
Mark Rutland, Michael Turquette, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Geert Uytterhoeven, Chris Brand,
Florian Fainelli, Arnd Bergmann, Thierry Reding, Sudeep Holla,
Juri Lelli, Thomas Petazzoni
On 28/01/17 07:47, Stephen Boyd wrote:
> On 01/27, Gregory CLEMENT wrote:
>> Hi all,
>>
>> On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
>>
>>> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
>>> integrated CPUs. They CPU block is common within these product lines and
>>> (as far as I can tell/have been told) is based on the Armada XP. There
>>> are a few differences due to the fact they have to squeeze the CPU into
>>> the same package as the switch.
>>>
>>> I've rebased this series against linux-pinctrl/devel to get access to
>>> mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to
>>> v4.10.0-rc5.
>>
>> Just to let you know that I plan to apply the 3 arm patch once Chris
>> will have sent the new series with the minor fixes I asked on patch 3.
>>
>> I already applied them in the for-next branch to benefit of some build
>> test coverage.
>>
>> Stephen,
>>
>> you gave your Acked-by on the first patch, but don't you plan to apply
>> it on the clk branch?
>
> It must have not been clear if I should apply it, hence the ack.
> I'll apply it now.
>
Sorry my bad. I need all 5 together in one place to actually test the
series.
I wasn't sure whether the series should go through mvebu with Acks from
clk and pinctrl or if things should go to the separate maintainers and
come together when they hit the main linux repo. Up until the latest
pinctrl change either approach would have worked.
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-29 20:30 ` Chris Packham
0 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-29 20:30 UTC (permalink / raw)
To: linux-arm-kernel
On 28/01/17 07:47, Stephen Boyd wrote:
> On 01/27, Gregory CLEMENT wrote:
>> Hi all,
>>
>> On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
>>
>>> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
>>> integrated CPUs. They CPU block is common within these product lines and
>>> (as far as I can tell/have been told) is based on the Armada XP. There
>>> are a few differences due to the fact they have to squeeze the CPU into
>>> the same package as the switch.
>>>
>>> I've rebased this series against linux-pinctrl/devel to get access to
>>> mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to
>>> v4.10.0-rc5.
>>
>> Just to let you know that I plan to apply the 3 arm patch once Chris
>> will have sent the new series with the minor fixes I asked on patch 3.
>>
>> I already applied them in the for-next branch to benefit of some build
>> test coverage.
>>
>> Stephen,
>>
>> you gave your Acked-by on the first patch, but don't you plan to apply
>> it on the clk branch?
>
> It must have not been clear if I should apply it, hence the ack.
> I'll apply it now.
>
Sorry my bad. I need all 5 together in one place to actually test the
series.
I wasn't sure whether the series should go through mvebu with Acks from
clk and pinctrl or if things should go to the separate maintainers and
come together when they hit the main linux repo. Up until the latest
pinctrl change either approach would have worked.
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-29 20:30 ` Chris Packham
0 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-29 20:30 UTC (permalink / raw)
To: Stephen Boyd, Gregory CLEMENT
Cc: Linus Walleij, linux, linux-arm-kernel, Rob Herring,
Mark Rutland, Michael Turquette, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Geert Uytterhoeven, Chris Brand,
Florian Fainelli, Arnd Bergmann, Thierry Reding, Sudeep Holla,
Juri Lelli, Thomas Petazzoni, Laxman Dewangan, Kalyan Kinthada,
devicetree, linux-kernel, linux-clk, linux-gpio
On 28/01/17 07:47, Stephen Boyd wrote:=0A=
> On 01/27, Gregory CLEMENT wrote:=0A=
>> Hi all,=0A=
>>=0A=
>> On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.n=
z> wrote:=0A=
>>=0A=
>>> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with=0A=
>>> integrated CPUs. They CPU block is common within these product lines an=
d=0A=
>>> (as far as I can tell/have been told) is based on the Armada XP. There=
=0A=
>>> are a few differences due to the fact they have to squeeze the CPU into=
=0A=
>>> the same package as the switch.=0A=
>>>=0A=
>>> I've rebased this series against linux-pinctrl/devel to get access to=
=0A=
>>> mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to=0A=
>>> v4.10.0-rc5.=0A=
>>=0A=
>> Just to let you know that I plan to apply the 3 arm patch once Chris=0A=
>> will have sent the new series with the minor fixes I asked on patch 3.=
=0A=
>>=0A=
>> I already applied them in the for-next branch to benefit of some build=
=0A=
>> test coverage.=0A=
>>=0A=
>> Stephen,=0A=
>>=0A=
>> you gave your Acked-by on the first patch, but don't you plan to apply=
=0A=
>> it on the clk branch?=0A=
>=0A=
> It must have not been clear if I should apply it, hence the ack.=0A=
> I'll apply it now.=0A=
>=0A=
=0A=
Sorry my bad. I need all 5 together in one place to actually test the =0A=
series.=0A=
=0A=
I wasn't sure whether the series should go through mvebu with Acks from =0A=
clk and pinctrl or if things should go to the separate maintainers and =0A=
come together when they hit the main linux repo. Up until the latest =0A=
pinctrl change either approach would have worked.=0A=
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-29 20:30 ` Chris Packham
0 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-29 20:30 UTC (permalink / raw)
To: Stephen Boyd, Gregory CLEMENT
Cc: Linus Walleij, linux, linux-arm-kernel, Rob Herring,
Mark Rutland, Michael Turquette, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Geert Uytterhoeven, Chris Brand,
Florian Fainelli, Arnd Bergmann, Thierry Reding, Sudeep Holla,
Juri Lelli, Thomas Petazzoni, Laxman Dewangan, Kalyan Kinthada,
devicetree, linux-kernel, linux-clk, linux-gpio
On 28/01/17 07:47, Stephen Boyd wrote:
> On 01/27, Gregory CLEMENT wrote:
>> Hi all,
>>
>> On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
>>
>>> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
>>> integrated CPUs. They CPU block is common within these product lines and
>>> (as far as I can tell/have been told) is based on the Armada XP. There
>>> are a few differences due to the fact they have to squeeze the CPU into
>>> the same package as the switch.
>>>
>>> I've rebased this series against linux-pinctrl/devel to get access to
>>> mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to
>>> v4.10.0-rc5.
>>
>> Just to let you know that I plan to apply the 3 arm patch once Chris
>> will have sent the new series with the minor fixes I asked on patch 3.
>>
>> I already applied them in the for-next branch to benefit of some build
>> test coverage.
>>
>> Stephen,
>>
>> you gave your Acked-by on the first patch, but don't you plan to apply
>> it on the clk branch?
>
> It must have not been clear if I should apply it, hence the ack.
> I'll apply it now.
>
Sorry my bad. I need all 5 together in one place to actually test the
series.
I wasn't sure whether the series should go through mvebu with Acks from
clk and pinctrl or if things should go to the separate maintainers and
come together when they hit the main linux repo. Up until the latest
pinctrl change either approach would have worked.
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
2017-01-29 20:30 ` Chris Packham
(?)
(?)
@ 2017-01-30 14:40 ` Gregory CLEMENT
-1 siblings, 0 replies; 49+ messages in thread
From: Gregory CLEMENT @ 2017-01-30 14:40 UTC (permalink / raw)
To: Chris Packham
Cc: Mark Rutland, Andrew Lunn, Geert Uytterhoeven, Linus Walleij,
Laxman Dewangan, linux-clk, Florian Fainelli, Juri Lelli, linux,
Thierry Reding, Michael Turquette, Sebastian Hesselbarth,
devicetree, Jason Cooper, Arnd Bergmann, Kalyan Kinthada,
Rob Herring, Chris Brand, linux-arm-kernel, Thomas Petazzoni
Hi Chris,
On dim., janv. 29 2017, Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
> On 28/01/17 07:47, Stephen Boyd wrote:
>> On 01/27, Gregory CLEMENT wrote:
>>> Hi all,
>>>
>>> On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
>>>
>>>> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
>>>> integrated CPUs. They CPU block is common within these product lines and
>>>> (as far as I can tell/have been told) is based on the Armada XP. There
>>>> are a few differences due to the fact they have to squeeze the CPU into
>>>> the same package as the switch.
>>>>
>>>> I've rebased this series against linux-pinctrl/devel to get access to
>>>> mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to
>>>> v4.10.0-rc5.
>>>
>>> Just to let you know that I plan to apply the 3 arm patch once Chris
>>> will have sent the new series with the minor fixes I asked on patch 3.
>>>
>>> I already applied them in the for-next branch to benefit of some build
>>> test coverage.
>>>
>>> Stephen,
>>>
>>> you gave your Acked-by on the first patch, but don't you plan to apply
>>> it on the clk branch?
>>
>> It must have not been clear if I should apply it, hence the ack.
>> I'll apply it now.
>>
>
> Sorry my bad. I need all 5 together in one place to actually test the
> series.
The 5 patches should be available soon (if it is not already the case),
in the linux-next branch.
The clk patch is already there, the 3 arm patch have been merged in my
mvebu/for-next branch, and the pinctrl patch is about to be merged in
the pinctrl/for-next branch.
Gregory
>
> I wasn't sure whether the series should go through mvebu with Acks from
> clk and pinctrl or if things should go to the separate maintainers and
> come together when they hit the main linux repo. Up until the latest
> pinctrl change either approach would have worked.
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-30 14:40 ` Gregory CLEMENT
0 siblings, 0 replies; 49+ messages in thread
From: Gregory CLEMENT @ 2017-01-30 14:40 UTC (permalink / raw)
To: linux-arm-kernel
Hi Chris,
On dim., janv. 29 2017, Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
> On 28/01/17 07:47, Stephen Boyd wrote:
>> On 01/27, Gregory CLEMENT wrote:
>>> Hi all,
>>>
>>> On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
>>>
>>>> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
>>>> integrated CPUs. They CPU block is common within these product lines and
>>>> (as far as I can tell/have been told) is based on the Armada XP. There
>>>> are a few differences due to the fact they have to squeeze the CPU into
>>>> the same package as the switch.
>>>>
>>>> I've rebased this series against linux-pinctrl/devel to get access to
>>>> mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to
>>>> v4.10.0-rc5.
>>>
>>> Just to let you know that I plan to apply the 3 arm patch once Chris
>>> will have sent the new series with the minor fixes I asked on patch 3.
>>>
>>> I already applied them in the for-next branch to benefit of some build
>>> test coverage.
>>>
>>> Stephen,
>>>
>>> you gave your Acked-by on the first patch, but don't you plan to apply
>>> it on the clk branch?
>>
>> It must have not been clear if I should apply it, hence the ack.
>> I'll apply it now.
>>
>
> Sorry my bad. I need all 5 together in one place to actually test the
> series.
The 5 patches should be available soon (if it is not already the case),
in the linux-next branch.
The clk patch is already there, the 3 arm patch have been merged in my
mvebu/for-next branch, and the pinctrl patch is about to be merged in
the pinctrl/for-next branch.
Gregory
>
> I wasn't sure whether the series should go through mvebu with Acks from
> clk and pinctrl or if things should go to the separate maintainers and
> come together when they hit the main linux repo. Up until the latest
> pinctrl change either approach would have worked.
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-30 14:40 ` Gregory CLEMENT
0 siblings, 0 replies; 49+ messages in thread
From: Gregory CLEMENT @ 2017-01-30 14:40 UTC (permalink / raw)
To: Chris Packham
Cc: Stephen Boyd, Linus Walleij, linux, linux-arm-kernel,
Rob Herring, Mark Rutland, Michael Turquette, Jason Cooper,
Andrew Lunn, Sebastian Hesselbarth, Geert Uytterhoeven,
Chris Brand, Florian Fainelli, Arnd Bergmann, Thierry Reding,
Sudeep Holla, Juri Lelli, Thomas Petazzoni, Laxman Dewangan,
Kalyan Kinthada, devicetree, linux-kernel, linux-clk, linux-gpio
Hi Chris,
On dim., janv. 29 2017, Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
> On 28/01/17 07:47, Stephen Boyd wrote:
>> On 01/27, Gregory CLEMENT wrote:
>>> Hi all,
>>>
>>> On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
>>>
>>>> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
>>>> integrated CPUs. They CPU block is common within these product lines and
>>>> (as far as I can tell/have been told) is based on the Armada XP. There
>>>> are a few differences due to the fact they have to squeeze the CPU into
>>>> the same package as the switch.
>>>>
>>>> I've rebased this series against linux-pinctrl/devel to get access to
>>>> mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to
>>>> v4.10.0-rc5.
>>>
>>> Just to let you know that I plan to apply the 3 arm patch once Chris
>>> will have sent the new series with the minor fixes I asked on patch 3.
>>>
>>> I already applied them in the for-next branch to benefit of some build
>>> test coverage.
>>>
>>> Stephen,
>>>
>>> you gave your Acked-by on the first patch, but don't you plan to apply
>>> it on the clk branch?
>>
>> It must have not been clear if I should apply it, hence the ack.
>> I'll apply it now.
>>
>
> Sorry my bad. I need all 5 together in one place to actually test the
> series.
The 5 patches should be available soon (if it is not already the case),
in the linux-next branch.
The clk patch is already there, the 3 arm patch have been merged in my
mvebu/for-next branch, and the pinctrl patch is about to be merged in
the pinctrl/for-next branch.
Gregory
>
> I wasn't sure whether the series should go through mvebu with Acks from
> clk and pinctrl or if things should go to the separate maintainers and
> come together when they hit the main linux repo. Up until the latest
> pinctrl change either approach would have worked.
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-30 14:40 ` Gregory CLEMENT
0 siblings, 0 replies; 49+ messages in thread
From: Gregory CLEMENT @ 2017-01-30 14:40 UTC (permalink / raw)
To: Chris Packham
Cc: Stephen Boyd, Linus Walleij, linux, linux-arm-kernel,
Rob Herring, Mark Rutland, Michael Turquette, Jason Cooper,
Andrew Lunn, Sebastian Hesselbarth, Geert Uytterhoeven,
Chris Brand, Florian Fainelli, Arnd Bergmann, Thierry Reding,
Sudeep Holla, Juri Lelli, Thomas Petazzoni, Laxman Dewangan,
Kalyan Kinthada, devicetree, linux-kernel, linux-clk, linux-gpio
Hi Chris,
On dim., janv. 29 2017, Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
> On 28/01/17 07:47, Stephen Boyd wrote:
>> On 01/27, Gregory CLEMENT wrote:
>>> Hi all,
>>>
>>> On ven., janv. 27 2017, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote:
>>>
>>>> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
>>>> integrated CPUs. They CPU block is common within these product lines and
>>>> (as far as I can tell/have been told) is based on the Armada XP. There
>>>> are a few differences due to the fact they have to squeeze the CPU into
>>>> the same package as the switch.
>>>>
>>>> I've rebased this series against linux-pinctrl/devel to get access to
>>>> mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to
>>>> v4.10.0-rc5.
>>>
>>> Just to let you know that I plan to apply the 3 arm patch once Chris
>>> will have sent the new series with the minor fixes I asked on patch 3.
>>>
>>> I already applied them in the for-next branch to benefit of some build
>>> test coverage.
>>>
>>> Stephen,
>>>
>>> you gave your Acked-by on the first patch, but don't you plan to apply
>>> it on the clk branch?
>>
>> It must have not been clear if I should apply it, hence the ack.
>> I'll apply it now.
>>
>
> Sorry my bad. I need all 5 together in one place to actually test the
> series.
The 5 patches should be available soon (if it is not already the case),
in the linux-next branch.
The clk patch is already there, the 3 arm patch have been merged in my
mvebu/for-next branch, and the pinctrl patch is about to be merged in
the pinctrl/for-next branch.
Gregory
>
> I wasn't sure whether the series should go through mvebu with Acks from
> clk and pinctrl or if things should go to the separate maintainers and
> come together when they hit the main linux repo. Up until the latest
> pinctrl change either approach would have worked.
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
2017-01-30 14:40 ` Gregory CLEMENT
(?)
(?)
@ 2017-01-30 20:27 ` Chris Packham
-1 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-30 20:27 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Stephen Boyd, Linus Walleij, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring,
Mark Rutland, Michael Turquette, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Geert Uytterhoeven, Chris Brand,
Florian Fainelli, Arnd Bergmann, Thierry Reding, Sudeep Holla,
Juri Lelli, Thomas Petazzoni
On 31/01/17 03:40, Gregory CLEMENT wrote:
> Hi Chris,
>
> The 5 patches should be available soon (if it is not already the case),
> in the linux-next branch.
>
> The clk patch is already there, the 3 arm patch have been merged in my
> mvebu/for-next branch, and the pinctrl patch is about to be merged in
> the pinctrl/for-next branch.
>
> Gregory
>
Gregory, Stephen, Linus W, thanks for applying the patches. Numerous
reviewers thanks for your feedback.
--
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^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-30 20:27 ` Chris Packham
0 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-30 20:27 UTC (permalink / raw)
To: linux-arm-kernel
On 31/01/17 03:40, Gregory CLEMENT wrote:
> Hi Chris,
>
> The 5 patches should be available soon (if it is not already the case),
> in the linux-next branch.
>
> The clk patch is already there, the 3 arm patch have been merged in my
> mvebu/for-next branch, and the pinctrl patch is about to be merged in
> the pinctrl/for-next branch.
>
> Gregory
>
Gregory, Stephen, Linus W, thanks for applying the patches. Numerous
reviewers thanks for your feedback.
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-30 20:27 ` Chris Packham
0 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-30 20:27 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Stephen Boyd, Linus Walleij, linux, linux-arm-kernel,
Rob Herring, Mark Rutland, Michael Turquette, Jason Cooper,
Andrew Lunn, Sebastian Hesselbarth, Geert Uytterhoeven,
Chris Brand, Florian Fainelli, Arnd Bergmann, Thierry Reding,
Sudeep Holla, Juri Lelli, Thomas Petazzoni, Laxman Dewangan,
Kalyan Kinthada, devicetree, linux-kernel, linux-clk, linux-gpio
On 31/01/17 03:40, Gregory CLEMENT wrote:=0A=
> Hi Chris,=0A=
>=0A=
> The 5 patches should be available soon (if it is not already the case),=
=0A=
> in the linux-next branch.=0A=
>=0A=
> The clk patch is already there, the 3 arm patch have been merged in my=0A=
> mvebu/for-next branch, and the pinctrl patch is about to be merged in=0A=
> the pinctrl/for-next branch.=0A=
>=0A=
> Gregory=0A=
>=0A=
=0A=
Gregory, Stephen, Linus W, thanks for applying the patches. Numerous =0A=
reviewers thanks for your feedback.=0A=
=0A=
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCHv5 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-30 20:27 ` Chris Packham
0 siblings, 0 replies; 49+ messages in thread
From: Chris Packham @ 2017-01-30 20:27 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Stephen Boyd, Linus Walleij, linux, linux-arm-kernel,
Rob Herring, Mark Rutland, Michael Turquette, Jason Cooper,
Andrew Lunn, Sebastian Hesselbarth, Geert Uytterhoeven,
Chris Brand, Florian Fainelli, Arnd Bergmann, Thierry Reding,
Sudeep Holla, Juri Lelli, Thomas Petazzoni, Laxman Dewangan,
Kalyan Kinthada, devicetree, linux-kernel, linux-clk, linux-gpio
On 31/01/17 03:40, Gregory CLEMENT wrote:
> Hi Chris,
>
> The 5 patches should be available soon (if it is not already the case),
> in the linux-next branch.
>
> The clk patch is already there, the 3 arm patch have been merged in my
> mvebu/for-next branch, and the pinctrl patch is about to be merged in
> the pinctrl/for-next branch.
>
> Gregory
>
Gregory, Stephen, Linus W, thanks for applying the patches. Numerous
reviewers thanks for your feedback.
^ permalink raw reply [flat|nested] 49+ messages in thread