From: Stefan Agner <stefan@agner.ch> To: peter.chen@freescale.com, s.hauer@pengutronix.de, shawn.guo@freescale.com Cc: b35083@freescale.com, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, stefan@agner.ch Subject: [PATCH 2/6] ARM: imx: clk-vf610: add USBPHY clocks Date: Fri, 18 Jul 2014 19:01:38 +0200 [thread overview] Message-ID: <fe660ff42e95a286a954c0560b2b7b2aad81634b.1405702442.git.stefan@agner.ch> (raw) In-Reply-To: <cover.1405702442.git.stefan@agner.ch> This commit adds PLL7 which is required for USBPHY1. It also adds the USB PHY and USB Controller clocks and the gates to enable them. Signed-off-by: Stefan Agner <stefan@agner.ch> --- All the main PLLs are currently turned on by boot ROM or boot loader, within the kernel we only set the fixed factor. Altough, the function imx_clk_pllv3 would provide enabling and rate calculation support. Because PLL7 is _not_ enabled at boot up, we need enable support. With this, we make use of the imx_clk_pllv3 function the first time in clk-vf610. In order to be aligned, would it make sense to use the function for all the main PLLs? I think support for all types of PLL available in Vybrid is already there, altough this need to be verified first. arch/arm/mach-imx/clk-vf610.c | 12 ++++++++++-- include/dt-bindings/clock/vf610-clock.h | 5 ++++- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c index 22dc3ee..159c5c4 100644 --- a/arch/arm/mach-imx/clk-vf610.c +++ b/arch/arm/mach-imx/clk-vf610.c @@ -58,6 +58,8 @@ #define PFD_PLL1_BASE (anatop_base + 0x2b0) #define PFD_PLL2_BASE (anatop_base + 0x100) #define PFD_PLL3_BASE (anatop_base + 0xf0) +#define PLL3_CTRL (anatop_base + 0x10) +#define PLL7_CTRL (anatop_base + 0x20) static void __iomem *anatop_base; static void __iomem *ccm_base; @@ -148,6 +150,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6); /* pll6: default 960Mhz */ clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1); + /* pll7: USB1 PLL at 480MHz */ + clk[VF610_CLK_PLL7_MAIN] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_main", "fast_clk_sel", PLL7_CTRL, 0x2); + clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5); clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5); clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels)); @@ -160,8 +165,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock); clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1); - clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4)); - clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4)); + clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_main", PLL3_CTRL, 6); + clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_main", PLL7_CTRL, 6); + + clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4)); + clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4)); clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4); clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4); diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h index a916029..6593757 100644 --- a/include/dt-bindings/clock/vf610-clock.h +++ b/include/dt-bindings/clock/vf610-clock.h @@ -164,6 +164,9 @@ #define VF610_CLK_DMAMUX1 151 #define VF610_CLK_DMAMUX2 152 #define VF610_CLK_DMAMUX3 153 -#define VF610_CLK_END 154 +#define VF610_CLK_PLL7_MAIN 154 +#define VF610_CLK_USBPHY0 155 +#define VF610_CLK_USBPHY1 156 +#define VF610_CLK_END 157 #endif /* __DT_BINDINGS_CLOCK_VF610_H */ -- 2.0.1
WARNING: multiple messages have this Message-ID (diff)
From: stefan@agner.ch (Stefan Agner) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/6] ARM: imx: clk-vf610: add USBPHY clocks Date: Fri, 18 Jul 2014 19:01:38 +0200 [thread overview] Message-ID: <fe660ff42e95a286a954c0560b2b7b2aad81634b.1405702442.git.stefan@agner.ch> (raw) In-Reply-To: <cover.1405702442.git.stefan@agner.ch> This commit adds PLL7 which is required for USBPHY1. It also adds the USB PHY and USB Controller clocks and the gates to enable them. Signed-off-by: Stefan Agner <stefan@agner.ch> --- All the main PLLs are currently turned on by boot ROM or boot loader, within the kernel we only set the fixed factor. Altough, the function imx_clk_pllv3 would provide enabling and rate calculation support. Because PLL7 is _not_ enabled at boot up, we need enable support. With this, we make use of the imx_clk_pllv3 function the first time in clk-vf610. In order to be aligned, would it make sense to use the function for all the main PLLs? I think support for all types of PLL available in Vybrid is already there, altough this need to be verified first. arch/arm/mach-imx/clk-vf610.c | 12 ++++++++++-- include/dt-bindings/clock/vf610-clock.h | 5 ++++- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c index 22dc3ee..159c5c4 100644 --- a/arch/arm/mach-imx/clk-vf610.c +++ b/arch/arm/mach-imx/clk-vf610.c @@ -58,6 +58,8 @@ #define PFD_PLL1_BASE (anatop_base + 0x2b0) #define PFD_PLL2_BASE (anatop_base + 0x100) #define PFD_PLL3_BASE (anatop_base + 0xf0) +#define PLL3_CTRL (anatop_base + 0x10) +#define PLL7_CTRL (anatop_base + 0x20) static void __iomem *anatop_base; static void __iomem *ccm_base; @@ -148,6 +150,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6); /* pll6: default 960Mhz */ clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1); + /* pll7: USB1 PLL at 480MHz */ + clk[VF610_CLK_PLL7_MAIN] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_main", "fast_clk_sel", PLL7_CTRL, 0x2); + clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5); clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5); clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels)); @@ -160,8 +165,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock); clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1); - clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4)); - clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4)); + clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_main", PLL3_CTRL, 6); + clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_main", PLL7_CTRL, 6); + + clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4)); + clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4)); clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4); clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4); diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h index a916029..6593757 100644 --- a/include/dt-bindings/clock/vf610-clock.h +++ b/include/dt-bindings/clock/vf610-clock.h @@ -164,6 +164,9 @@ #define VF610_CLK_DMAMUX1 151 #define VF610_CLK_DMAMUX2 152 #define VF610_CLK_DMAMUX3 153 -#define VF610_CLK_END 154 +#define VF610_CLK_PLL7_MAIN 154 +#define VF610_CLK_USBPHY0 155 +#define VF610_CLK_USBPHY1 156 +#define VF610_CLK_END 157 #endif /* __DT_BINDINGS_CLOCK_VF610_H */ -- 2.0.1
next prev parent reply other threads:[~2014-07-18 17:01 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-07-18 17:01 [PATCH 0/6] vf610: Add USB support Stefan Agner 2014-07-18 17:01 ` Stefan Agner 2014-07-18 17:01 ` [PATCH 1/6] ARM: dts: vf610: add USB PHY and controller Stefan Agner 2014-07-18 17:01 ` Stefan Agner 2014-07-22 2:22 ` Shawn Guo 2014-07-22 2:22 ` Shawn Guo 2014-07-22 9:57 ` Stefan Agner 2014-07-22 9:57 ` Stefan Agner 2014-07-22 13:18 ` Shawn Guo 2014-07-22 13:18 ` Shawn Guo 2014-07-18 17:01 ` Stefan Agner [this message] 2014-07-18 17:01 ` [PATCH 2/6] ARM: imx: clk-vf610: add USBPHY clocks Stefan Agner 2014-07-22 2:32 ` Shawn Guo 2014-07-22 2:32 ` Shawn Guo 2014-07-22 6:58 ` Jingchang Lu 2014-07-22 6:58 ` Jingchang Lu 2014-07-18 17:01 ` [PATCH 3/6] ARM: dts: vf610: Add usbmisc for non-core registers Stefan Agner 2014-07-18 17:01 ` Stefan Agner 2014-07-18 17:01 ` [PATCH 4/6] chipidea: usbmisc_imx: Add USB support for VF610 SoCs Stefan Agner 2014-07-18 17:01 ` Stefan Agner 2014-07-22 1:52 ` Peter Chen 2014-07-22 1:52 ` Peter Chen 2014-07-22 2:34 ` Shawn Guo 2014-07-22 2:34 ` Shawn Guo 2014-07-18 17:01 ` [PATCH 5/6] usb: phy: mxs: Add VF610 USB PHY support Stefan Agner 2014-07-18 17:01 ` Stefan Agner 2014-07-22 1:43 ` Peter Chen 2014-07-22 1:43 ` Peter Chen 2014-07-22 2:16 ` Shawn Guo 2014-07-22 2:16 ` Shawn Guo 2014-07-18 17:01 ` [PATCH 6/6] ARM: dts: vf610-colibri: add USB support Stefan Agner 2014-07-18 17:01 ` Stefan Agner 2014-07-22 0:13 ` [PATCH 0/6] vf610: Add " Peter Chen 2014-07-22 0:13 ` Peter Chen 2014-07-26 12:24 ` Stefan Agner 2014-07-26 12:24 ` Stefan Agner
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