* [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model
@ 2016-05-05 13:28 Simon Glass
2016-05-05 13:28 ` [U-Boot] [PATCH v2 01/18] at91: Add support for the AT91 slow clock controller Simon Glass
` (17 more replies)
0 siblings, 18 replies; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
This series is mainly designed to move the macb Ethernet to driver model,
along with the LCD controller. It also includes a few fixes:
- NAND with ECC doesn't build properly
- The instruction cache is off by default
- Ethernet macb doesn't send packets when the cache is enabled
A Snapper 9G45-based board is used for this work. It includes an AT91SAM9G45
CPU so is a good test of driver model on this chip.
Changes in v2:
- Correct commit author in several cases
- Rebase to master
Andre Renaud (7):
at91: Add support for the AT91 slow clock controller
net: Handle an empty bootp extension section
arm: at91: Add a header file for the real-time clock
at91: Correct NAND ECC register access
at91: nand: Set up the ECC strength correctly
mtd: nand: Drop a blank line in nand_wait()
arm: at91: Add support for gurnard
Simon Glass (11):
arm: Allow skipping of low-level init with I-cache on
bootm: Align cache flush end address correctly
net: macb: Prepare for driver-model conversion
net: macb: Flush correct cache portion when sending
net: macb: Convert to driver model
arm: at91: dts: Bring in device tree file for AT91SAM9G45
at91: Add driver-model GPIO devices for AT91SAM9G45
at91: mtd: nand: Add dev_warn() to correct build error in driver
at91: video: Prepare for driver-model conversion
at91: video: Support driver-model for the LCD driver
fdt: Correct return value in fdtdec_decode_display_timing()
README | 5 +
arch/arm/cpu/arm1136/start.S | 2 +
arch/arm/cpu/arm920t/start.S | 3 +-
arch/arm/cpu/arm926ejs/start.S | 2 +
arch/arm/cpu/arm946es/start.S | 2 +
arch/arm/cpu/armv7/start.S | 5 +-
arch/arm/cpu/sa1100/start.S | 2 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/at91sam9g45-gurnard.dts | 157 ++
arch/arm/dts/at91sam9g45.dtsi | 1335 ++++++++++
arch/arm/mach-at91/Kconfig | 9 +
.../mach-at91/arm926ejs/at91sam9m10g45_devices.c | 18 +
arch/arm/mach-at91/include/mach/at91_rtc.h | 71 +
arch/arm/mach-at91/include/mach/at91_sck.h | 21 +
arch/arm/mach-at91/include/mach/at91sam9g45.h | 1 +
board/bluewater/gurnard/Kconfig | 12 +
board/bluewater/gurnard/MAINTAINERS | 6 +
board/bluewater/gurnard/Makefile | 11 +
board/bluewater/gurnard/gurnard.c | 449 ++++
board/bluewater/gurnard/splash_logo.h | 2619 ++++++++++++++++++++
common/bootm.c | 2 +-
configs/gurnard_defconfig | 19 +
drivers/mtd/nand/atmel_nand.c | 7 +-
drivers/mtd/nand/nand_base.c | 1 -
drivers/net/macb.c | 320 ++-
drivers/video/atmel_lcdfb.c | 197 +-
include/atmel_lcd.h | 9 +
include/configs/snapper9g45.h | 156 ++
include/dt-bindings/clock/at91.h | 23 +
include/dt-bindings/dma/at91.h | 52 +
include/dt-bindings/pinctrl/at91.h | 40 +
lib/fdtdec.c | 2 +-
net/bootp.c | 9 +
33 files changed, 5449 insertions(+), 119 deletions(-)
create mode 100644 arch/arm/dts/at91sam9g45-gurnard.dts
create mode 100644 arch/arm/dts/at91sam9g45.dtsi
create mode 100644 arch/arm/mach-at91/include/mach/at91_rtc.h
create mode 100644 arch/arm/mach-at91/include/mach/at91_sck.h
create mode 100644 board/bluewater/gurnard/Kconfig
create mode 100644 board/bluewater/gurnard/MAINTAINERS
create mode 100644 board/bluewater/gurnard/Makefile
create mode 100644 board/bluewater/gurnard/gurnard.c
create mode 100644 board/bluewater/gurnard/splash_logo.h
create mode 100644 configs/gurnard_defconfig
create mode 100644 include/configs/snapper9g45.h
create mode 100644 include/dt-bindings/clock/at91.h
create mode 100644 include/dt-bindings/dma/at91.h
create mode 100644 include/dt-bindings/pinctrl/at91.h
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 01/18] at91: Add support for the AT91 slow clock controller
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
@ 2016-05-05 13:28 ` Simon Glass
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 02/18] arm: Allow skipping of low-level init with I-cache on Simon Glass
` (16 subsequent siblings)
17 siblings, 1 reply; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
From: Andre Renaud <andre@designa-electronics.com>
This is available on AT91SAM9G45. Add the peripheral address and flag
definitions.
Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
---
Changes in v2: None
arch/arm/mach-at91/include/mach/at91_sck.h | 21 +++++++++++++++++++++
arch/arm/mach-at91/include/mach/at91sam9g45.h | 1 +
2 files changed, 22 insertions(+)
create mode 100644 arch/arm/mach-at91/include/mach/at91_sck.h
diff --git a/arch/arm/mach-at91/include/mach/at91_sck.h b/arch/arm/mach-at91/include/mach/at91_sck.h
new file mode 100644
index 0000000..ce8e577
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_sck.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_SCK_H
+#define AT91_SCK_H
+
+/*
+ * SCKCR flags
+ */
+#define AT91SAM9G45_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */
+#define AT91SAM9G45_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */
+#define AT91SAM9G45_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */
+#define AT91SAM9G45_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */
+#define AT91SAM9G45_SCKCR_OSCSEL_RC (0 << 3)
+#define AT91SAM9G45_SCKCR_OSCSEL_32 (1 << 3)
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index cf1c73f..5c32e24 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -109,6 +109,7 @@
#define ATMEL_BASE_RTT 0xfffffd20
#define ATMEL_BASE_PIT 0xfffffd30
#define ATMEL_BASE_WDT 0xfffffd40
+#define ATMEL_BASE_SCKCR 0xfffffd50
#define ATMEL_BASE_GPBR 0xfffffd60
#define ATMEL_BASE_RTC 0xfffffdb0
/* Reserved: 0xfffffdc0 - 0xffffffff */
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 02/18] arm: Allow skipping of low-level init with I-cache on
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
2016-05-05 13:28 ` [U-Boot] [PATCH v2 01/18] at91: Add support for the AT91 slow clock controller Simon Glass
@ 2016-05-05 13:28 ` Simon Glass
2016-05-05 14:07 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 03/18] bootm: Align cache flush end address correctly Simon Glass
` (15 subsequent siblings)
17 siblings, 2 replies; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
At present CONFIG_SKIP_LOWLEVEL_INIT prevents U-Boot from calling
lowlevel_init(). This means that the instruction cache is not enabled and
the board runs very slowly.
What is really needed in many cases is to skip the call to lowlevel_init()
but still perform CP15 init. Add an option to handle this.
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2: None
README | 5 +++++
arch/arm/cpu/arm1136/start.S | 2 ++
arch/arm/cpu/arm920t/start.S | 3 ++-
arch/arm/cpu/arm926ejs/start.S | 2 ++
arch/arm/cpu/arm946es/start.S | 2 ++
arch/arm/cpu/armv7/start.S | 5 ++++-
arch/arm/cpu/sa1100/start.S | 2 ++
7 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/README b/README
index 88ff837..9ab07b5 100644
--- a/README
+++ b/README
@@ -4829,6 +4829,11 @@ Low Level (hardware related) configuration options:
other boot loader or by a debugger which performs
these initializations itself.
+- CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+ [ARM926EJ-S only] This allows just the call to lowlevel_init()
+ to be skipped. The normal CPU15 init (such as enabling the
+ instruction cache) is still performed.
+
- CONFIG_SPL_BUILD
Modifies the behaviour of start.S when compiling a loader
that is executed before the actual U-Boot. E.g. when
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 3ebdfdd..2f8fd6a 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -82,6 +82,7 @@ cpu_init_crit:
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/*
* Jump to board specific initialization... The Mask ROM will have already initialized
* basic memory. Go here to bump up clock rate and handle wake up conditions.
@@ -89,5 +90,6 @@ cpu_init_crit:
mov ip, lr /* persevere link reg across call */
bl lowlevel_init /* go setup pll,mux,memory */
mov lr, ip /* restore link */
+#endif
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
index 69cabeb..3ada6d0 100644
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -135,6 +135,7 @@ cpu_init_crit:
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
@@ -143,7 +144,7 @@ cpu_init_crit:
mov ip, lr
bl lowlevel_init
-
mov lr, ip
+#endif
mov pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index f05113d..959d1ed 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -101,11 +101,13 @@ flush_dcache:
#endif
mcr p15, 0, r0, c1, c0, 0
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/*
* Go setup Memory and board specific bits prior to relocation.
*/
mov ip, lr /* perserve link reg across call */
bl lowlevel_init /* go setup pll,mux,memory */
mov lr, ip /* restore link */
+#endif
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S
index 214cd8c..51053c3 100644
--- a/arch/arm/cpu/arm946es/start.S
+++ b/arch/arm/cpu/arm946es/start.S
@@ -90,11 +90,13 @@ cpu_init_crit:
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
mcr p15, 0, r0, c1, c0, 0
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/*
* Go setup Memory and board specific bits prior to relocation.
*/
mov ip, lr /* perserve link reg across call */
bl lowlevel_init /* go setup memory */
mov lr, ip /* restore link */
+#endif
mov pc, lr /* back to my caller */
#endif
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index b180944..691e5d3 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -66,8 +66,10 @@ save_boot_params_ret:
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_cp15
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
bl cpu_init_crit
#endif
+#endif
bl _main
@@ -250,7 +252,8 @@ skip_errata_621766:
mov pc, r5 @ back to my caller
ENDPROC(cpu_init_cp15)
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+ !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
/*************************************************************************
*
* CPU_init_critical registers
diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
index 408b70d..f5318c9 100644
--- a/arch/arm/cpu/sa1100/start.S
+++ b/arch/arm/cpu/sa1100/start.S
@@ -96,6 +96,7 @@ cpu_init_crit:
ldr r1, cpuspeed
str r1, [r0, #PPCR]
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
@@ -104,6 +105,7 @@ cpu_init_crit:
mov ip, lr
bl lowlevel_init
mov lr, ip
+#endif
/*
* disable MMU stuff and enable I-cache
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 03/18] bootm: Align cache flush end address correctly
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
2016-05-05 13:28 ` [U-Boot] [PATCH v2 01/18] at91: Add support for the AT91 slow clock controller Simon Glass
2016-05-05 13:28 ` [U-Boot] [PATCH v2 02/18] arm: Allow skipping of low-level init with I-cache on Simon Glass
@ 2016-05-05 13:28 ` Simon Glass
2016-05-05 14:19 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 04/18] net: Handle an empty bootp extension section Simon Glass
` (14 subsequent siblings)
17 siblings, 2 replies; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
Flushing part of the cache should be done on cache boundaries. Trying to
flush part of a cache line is not supported and the request may be ignored
or print warnings.
Adjust the bootm code to align the end address to prevent this problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
---
Changes in v2: None
common/bootm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/bootm.c b/common/bootm.c
index c965326..7469c61 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -435,7 +435,7 @@ static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end,
bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
return err;
}
- flush_cache(load, *load_end - load);
+ flush_cache(load, ALIGN(*load_end - load, ARCH_DMA_MINALIGN));
debug(" kernel loaded at 0x%08lx, end = 0x%08lx\n", load, *load_end);
bootstage_mark(BOOTSTAGE_ID_KERNEL_LOADED);
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 04/18] net: Handle an empty bootp extension section
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
` (2 preceding siblings ...)
2016-05-05 13:28 ` [U-Boot] [PATCH v2 03/18] bootm: Align cache flush end address correctly Simon Glass
@ 2016-05-05 13:28 ` Simon Glass
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 05/18] net: macb: Prepare for driver-model conversion Simon Glass
` (13 subsequent siblings)
17 siblings, 1 reply; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
From: Andre Renaud <andre@designa-electronics.com>
Avoid generating this section if there is nothing in it.
Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
Changes in v2: None
net/bootp.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/net/bootp.c b/net/bootp.c
index d7852db..71f09bd 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -655,6 +655,15 @@ static int bootp_extended(u8 *e)
*e++ = 255; /* End of the list */
+ /*
+ * If nothing in list, remove it altogether. Some DHCP servers get
+ * upset by this minor faux pas and do not respond at all.
+ */
+ if (e == start + 3) {
+ printf("*** Warning: no DHCP options requested\n");
+ e -= 3;
+ }
+
return e - start;
}
#endif
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 05/18] net: macb: Prepare for driver-model conversion
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
` (3 preceding siblings ...)
2016-05-05 13:28 ` [U-Boot] [PATCH v2 04/18] net: Handle an empty bootp extension section Simon Glass
@ 2016-05-05 13:28 ` Simon Glass
2016-05-05 18:31 ` Joe Hershberger
` (2 more replies)
2016-05-05 13:28 ` [U-Boot] [PATCH v2 06/18] net: macb: Flush correct cache portion when sending Simon Glass
` (12 subsequent siblings)
17 siblings, 3 replies; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
Adjust this driver to avoid using struct netdev in functions that driver
model will call. Also refactor the receive function to be compatible with
driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
---
Changes in v2: None
drivers/net/macb.c | 199 +++++++++++++++++++++++++++++++++--------------------
1 file changed, 124 insertions(+), 75 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index be0659a..f0af40c 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -84,6 +84,8 @@ struct macb_device {
unsigned int rx_tail;
unsigned int tx_head;
unsigned int tx_tail;
+ unsigned int next_rx_tail;
+ bool wrapped;
void *rx_buffer;
void *tx_buffer;
@@ -255,9 +257,9 @@ static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
#if defined(CONFIG_CMD_NET)
-static int macb_send(struct eth_device *netdev, void *packet, int length)
+static int _macb_send(struct macb_device *macb, const char *name, void *packet,
+ int length)
{
- struct macb_device *macb = to_macb(netdev);
unsigned long paddr, ctrl;
unsigned int tx_head = macb->tx_head;
int i;
@@ -298,12 +300,11 @@ static int macb_send(struct eth_device *netdev, void *packet, int length)
if (i <= MACB_TX_TIMEOUT) {
if (ctrl & TXBUF_UNDERRUN)
- printf("%s: TX underrun\n", netdev->name);
+ printf("%s: TX underrun\n", name);
if (ctrl & TXBUF_EXHAUSTED)
- printf("%s: TX buffers exhausted in mid frame\n",
- netdev->name);
+ printf("%s: TX buffers exhausted in mid frame\n", name);
} else {
- printf("%s: TX timeout\n", netdev->name);
+ printf("%s: TX timeout\n", name);
}
/* No one cares anyway */
@@ -335,26 +336,25 @@ static void reclaim_rx_buffers(struct macb_device *macb,
macb->rx_tail = new_tail;
}
-static int macb_recv(struct eth_device *netdev)
+static int _macb_recv(struct macb_device *macb, uchar **packetp)
{
- struct macb_device *macb = to_macb(netdev);
- unsigned int rx_tail = macb->rx_tail;
+ unsigned int next_rx_tail = macb->next_rx_tail;
void *buffer;
int length;
- int wrapped = 0;
u32 status;
+ macb->wrapped = false;
for (;;) {
macb_invalidate_ring_desc(macb, RX);
- if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
- return -1;
+ if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED))
+ return -EAGAIN;
- status = macb->rx_ring[rx_tail].ctrl;
+ status = macb->rx_ring[next_rx_tail].ctrl;
if (status & RXBUF_FRAME_START) {
- if (rx_tail != macb->rx_tail)
- reclaim_rx_buffers(macb, rx_tail);
- wrapped = 0;
+ if (next_rx_tail != macb->rx_tail)
+ reclaim_rx_buffers(macb, next_rx_tail);
+ macb->wrapped = false;
}
if (status & RXBUF_FRAME_END) {
@@ -362,7 +362,7 @@ static int macb_recv(struct eth_device *netdev)
length = status & RXBUF_FRMLEN_MASK;
macb_invalidate_rx_buffer(macb);
- if (wrapped) {
+ if (macb->wrapped) {
unsigned int headlen, taillen;
headlen = 128 * (MACB_RX_RING_SIZE
@@ -372,34 +372,33 @@ static int macb_recv(struct eth_device *netdev)
buffer, headlen);
memcpy((void *)net_rx_packets[0] + headlen,
macb->rx_buffer, taillen);
- buffer = (void *)net_rx_packets[0];
+ *packetp = (void *)net_rx_packets[0];
+ } else {
+ *packetp = buffer;
}
- net_process_received_packet(buffer, length);
- if (++rx_tail >= MACB_RX_RING_SIZE)
- rx_tail = 0;
- reclaim_rx_buffers(macb, rx_tail);
+ if (++next_rx_tail >= MACB_RX_RING_SIZE)
+ next_rx_tail = 0;
+ macb->next_rx_tail = next_rx_tail;
+ return length;
} else {
- if (++rx_tail >= MACB_RX_RING_SIZE) {
- wrapped = 1;
- rx_tail = 0;
+ if (++next_rx_tail >= MACB_RX_RING_SIZE) {
+ macb->wrapped = true;
+ next_rx_tail = 0;
}
}
barrier();
}
-
- return 0;
}
-static void macb_phy_reset(struct macb_device *macb)
+static void macb_phy_reset(struct macb_device *macb, const char *name)
{
- struct eth_device *netdev = &macb->netdev;
int i;
u16 status, adv;
adv = ADVERTISE_CSMA | ADVERTISE_ALL;
macb_mdio_write(macb, MII_ADVERTISE, adv);
- printf("%s: Starting autonegotiation...\n", netdev->name);
+ printf("%s: Starting autonegotiation...\n", name);
macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
| BMCR_ANRESTART));
@@ -411,10 +410,10 @@ static void macb_phy_reset(struct macb_device *macb)
}
if (status & BMSR_ANEGCOMPLETE)
- printf("%s: Autonegotiation complete\n", netdev->name);
+ printf("%s: Autonegotiation complete\n", name);
else
printf("%s: Autonegotiation timed out (status=0x%04x)\n",
- netdev->name, status);
+ name, status);
}
#ifdef CONFIG_MACB_SEARCH_PHY
@@ -441,9 +440,8 @@ static int macb_phy_find(struct macb_device *macb)
#endif /* CONFIG_MACB_SEARCH_PHY */
-static int macb_phy_init(struct macb_device *macb)
+static int macb_phy_init(struct macb_device *macb, const char *name)
{
- struct eth_device *netdev = &macb->netdev;
#ifdef CONFIG_PHYLIB
struct phy_device *phydev;
#endif
@@ -452,7 +450,7 @@ static int macb_phy_init(struct macb_device *macb)
int media, speed, duplex;
int i;
- arch_get_mdio_control(netdev->name);
+ arch_get_mdio_control(name);
#ifdef CONFIG_MACB_SEARCH_PHY
/* Auto-detect phy_addr */
if (!macb_phy_find(macb))
@@ -462,13 +460,13 @@ static int macb_phy_init(struct macb_device *macb)
/* Check if the PHY is up to snuff... */
phy_id = macb_mdio_read(macb, MII_PHYSID1);
if (phy_id == 0xffff) {
- printf("%s: No PHY present\n", netdev->name);
+ printf("%s: No PHY present\n", name);
return 0;
}
#ifdef CONFIG_PHYLIB
/* need to consider other phy interface mode */
- phydev = phy_connect(macb->bus, macb->phy_addr, netdev,
+ phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
printf("phy_connect failed\n");
@@ -481,7 +479,7 @@ static int macb_phy_init(struct macb_device *macb)
status = macb_mdio_read(macb, MII_BMSR);
if (!(status & BMSR_LSTATUS)) {
/* Try to re-negotiate if we don't have link already. */
- macb_phy_reset(macb);
+ macb_phy_reset(macb, name);
for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
status = macb_mdio_read(macb, MII_BMSR);
@@ -493,7 +491,7 @@ static int macb_phy_init(struct macb_device *macb)
if (!(status & BMSR_LSTATUS)) {
printf("%s: link down (status: 0x%04x)\n",
- netdev->name, status);
+ name, status);
return 0;
}
@@ -505,7 +503,7 @@ static int macb_phy_init(struct macb_device *macb)
duplex = ((lpa & LPA_1000FULL) ? 1 : 0);
printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
- netdev->name,
+ name,
duplex ? "full" : "half",
lpa);
@@ -530,7 +528,7 @@ static int macb_phy_init(struct macb_device *macb)
? 1 : 0);
duplex = (media & ADVERTISE_FULL) ? 1 : 0;
printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
- netdev->name,
+ name,
speed ? "100" : "10",
duplex ? "full" : "half",
lpa);
@@ -570,9 +568,8 @@ static int gmac_init_multi_queues(struct macb_device *macb)
return 0;
}
-static int macb_init(struct eth_device *netdev, bd_t *bd)
+static int _macb_init(struct macb_device *macb, const char *name)
{
- struct macb_device *macb = to_macb(netdev);
unsigned long paddr;
int i;
@@ -605,6 +602,7 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
macb->rx_tail = 0;
macb->tx_head = 0;
macb->tx_tail = 0;
+ macb->next_rx_tail = 0;
macb_writel(macb, RBQP, macb->rx_ring_dma);
macb_writel(macb, TBQP, macb->tx_ring_dma);
@@ -641,7 +639,7 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
#endif /* CONFIG_RMII */
}
- if (!macb_phy_init(macb))
+ if (!macb_phy_init(macb, name))
return -1;
/* Enable TX and RX */
@@ -650,9 +648,8 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
return 0;
}
-static void macb_halt(struct eth_device *netdev)
+static void _macb_halt(struct macb_device *macb)
{
- struct macb_device *macb = to_macb(netdev);
u32 ncr, tsr;
/* Halt the controller and wait for any ongoing transmission to end. */
@@ -668,17 +665,16 @@ static void macb_halt(struct eth_device *netdev)
macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
}
-static int macb_write_hwaddr(struct eth_device *dev)
+static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
{
- struct macb_device *macb = to_macb(dev);
u32 hwaddr_bottom;
u16 hwaddr_top;
/* set hardware address */
- hwaddr_bottom = dev->enetaddr[0] | dev->enetaddr[1] << 8 |
- dev->enetaddr[2] << 16 | dev->enetaddr[3] << 24;
+ hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
+ enetaddr[2] << 16 | enetaddr[3] << 24;
macb_writel(macb, SA1B, hwaddr_bottom);
- hwaddr_top = dev->enetaddr[4] | dev->enetaddr[5] << 8;
+ hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
macb_writel(macb, SA1T, hwaddr_top);
return 0;
}
@@ -739,11 +735,86 @@ static u32 macb_dbw(struct macb_device *macb)
}
}
+static void _macb_eth_initialize(struct macb_device *macb)
+{
+ int id = 0; /* This is not used by functions we call */
+ u32 ncfgr;
+
+ /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
+ macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
+ &macb->rx_buffer_dma);
+ macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
+ &macb->rx_ring_dma);
+ macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
+ &macb->tx_ring_dma);
+ macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
+ &macb->dummy_desc_dma);
+
+ /*
+ * Do some basic initialization so that we at least can talk
+ * to the PHY
+ */
+ if (macb_is_gem(macb)) {
+ ncfgr = gem_mdc_clk_div(id, macb);
+ ncfgr |= macb_dbw(macb);
+ } else {
+ ncfgr = macb_mdc_clk_div(id, macb);
+ }
+
+ macb_writel(macb, NCFGR, ncfgr);
+}
+
+static int macb_send(struct eth_device *netdev, void *packet, int length)
+{
+ struct macb_device *macb = to_macb(netdev);
+
+ return _macb_send(macb, netdev->name, packet, length);
+}
+
+static int macb_recv(struct eth_device *netdev)
+{
+ struct macb_device *macb = to_macb(netdev);
+ uchar *packet;
+ int length;
+
+ macb->wrapped = false;
+ for (;;) {
+ macb->next_rx_tail = macb->rx_tail;
+ length = _macb_recv(macb, &packet);
+ if (length >= 0) {
+ net_process_received_packet(packet, length);
+ reclaim_rx_buffers(macb, macb->next_rx_tail);
+ } else if (length < 0) {
+ return length;
+ }
+ }
+}
+
+static int macb_init(struct eth_device *netdev, bd_t *bd)
+{
+ struct macb_device *macb = to_macb(netdev);
+
+ return _macb_init(macb, netdev->name);
+}
+
+static void macb_halt(struct eth_device *netdev)
+{
+ struct macb_device *macb = to_macb(netdev);
+
+ return _macb_halt(macb);
+}
+
+static int macb_write_hwaddr(struct eth_device *netdev)
+{
+ struct macb_device *macb = to_macb(netdev);
+
+ return _macb_write_hwaddr(macb, netdev->enetaddr);
+}
+
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
{
struct macb_device *macb;
struct eth_device *netdev;
- u32 ncfgr;
macb = malloc(sizeof(struct macb_device));
if (!macb) {
@@ -754,17 +825,6 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
netdev = &macb->netdev;
- macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
- &macb->rx_buffer_dma);
- macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
- &macb->rx_ring_dma);
- macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
- &macb->tx_ring_dma);
- macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
- &macb->dummy_desc_dma);
-
- /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
-
macb->regs = regs;
macb->phy_addr = phy_addr;
@@ -779,18 +839,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
netdev->recv = macb_recv;
netdev->write_hwaddr = macb_write_hwaddr;
- /*
- * Do some basic initialization so that we at least can talk
- * to the PHY
- */
- if (macb_is_gem(macb)) {
- ncfgr = gem_mdc_clk_div(id, macb);
- ncfgr |= macb_dbw(macb);
- } else {
- ncfgr = macb_mdc_clk_div(id, macb);
- }
-
- macb_writel(macb, NCFGR, ncfgr);
+ _macb_eth_initialize(macb);
eth_register(netdev);
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 06/18] net: macb: Flush correct cache portion when sending
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
` (4 preceding siblings ...)
2016-05-05 13:28 ` [U-Boot] [PATCH v2 05/18] net: macb: Prepare for driver-model conversion Simon Glass
@ 2016-05-05 13:28 ` Simon Glass
2016-05-28 12:35 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 07/18] net: macb: Convert to driver model Simon Glass
` (11 subsequent siblings)
17 siblings, 2 replies; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
The end address of the cache flush must be cache-line-aligned since
otherwise (at least on ARM926-EJS) the request is ignored. When the cache
is enabled this means that packets are not sent.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
Changes in v2: None
drivers/net/macb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index f0af40c..ecdfc1b 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -280,7 +280,7 @@ static int _macb_send(struct macb_device *macb, const char *name, void *packet,
barrier();
macb_flush_ring_desc(macb, TX);
/* Do we need check paddr and length is dcache line aligned? */
- flush_dcache_range(paddr, paddr + length);
+ flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
/*
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 07/18] net: macb: Convert to driver model
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
` (5 preceding siblings ...)
2016-05-05 13:28 ` [U-Boot] [PATCH v2 06/18] net: macb: Flush correct cache portion when sending Simon Glass
@ 2016-05-05 13:28 ` Simon Glass
2016-05-28 22:43 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot,v2,07/18] " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 08/18] arm: at91: dts: Bring in device tree file for AT91SAM9G45 Simon Glass
` (10 subsequent siblings)
17 siblings, 2 replies; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
Add driver-model support to this driver. The old code remains for now so
that we can convert boards one at a time.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
Changes in v2: None
drivers/net/macb.c | 119 +++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 119 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index ecdfc1b..63fb466 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -4,6 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
/*
* The u-boot networking stack is a little weird. It seems like the
@@ -28,7 +29,9 @@
*/
#include <net.h>
+#ifndef CONFIG_DM_ETH
#include <netdev.h>
+#endif
#include <malloc.h>
#include <miiphy.h>
@@ -100,11 +103,15 @@ struct macb_device {
unsigned long dummy_desc_dma;
const struct device *dev;
+#ifndef CONFIG_DM_ETH
struct eth_device netdev;
+#endif
unsigned short phy_addr;
struct mii_dev *bus;
};
+#ifndef CONFIG_DM_ETH
#define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
+#endif
static int macb_is_gem(struct macb_device *macb)
{
@@ -194,8 +201,13 @@ void __weak arch_get_mdio_control(const char *name)
int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
{
+#ifdef CONFIG_DM_ETH
+ struct udevice *dev = eth_get_dev_by_name(devname);
+ struct macb_device *macb = dev_get_priv(dev);
+#else
struct eth_device *dev = eth_get_dev_by_name(devname);
struct macb_device *macb = to_macb(dev);
+#endif
if (macb->phy_addr != phy_adr)
return -1;
@@ -208,8 +220,13 @@ int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
{
+#ifdef CONFIG_DM_ETH
+ struct udevice *dev = eth_get_dev_by_name(devname);
+ struct macb_device *macb = dev_get_priv(dev);
+#else
struct eth_device *dev = eth_get_dev_by_name(devname);
struct macb_device *macb = to_macb(dev);
+#endif
if (macb->phy_addr != phy_adr)
return -1;
@@ -764,6 +781,7 @@ static void _macb_eth_initialize(struct macb_device *macb)
macb_writel(macb, NCFGR, ncfgr);
}
+#ifndef CONFIG_DM_ETH
static int macb_send(struct eth_device *netdev, void *packet, int length)
{
struct macb_device *macb = to_macb(netdev);
@@ -849,5 +867,106 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
#endif
return 0;
}
+#endif /* !CONFIG_DM_ETH */
+
+#ifdef CONFIG_DM_ETH
+
+static int macb_start(struct udevice *dev)
+{
+ struct macb_device *macb = dev_get_priv(dev);
+
+ return _macb_init(macb, dev->name);
+}
+
+static int macb_send(struct udevice *dev, void *packet, int length)
+{
+ struct macb_device *macb = dev_get_priv(dev);
+
+ return _macb_send(macb, dev->name, packet, length);
+}
+
+static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct macb_device *macb = dev_get_priv(dev);
+
+ macb->next_rx_tail = macb->rx_tail;
+ macb->wrapped = false;
+
+ return _macb_recv(macb, packetp);
+}
+
+static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct macb_device *macb = dev_get_priv(dev);
+
+ reclaim_rx_buffers(macb, macb->next_rx_tail);
+
+ return 0;
+}
+
+static void macb_stop(struct udevice *dev)
+{
+ struct macb_device *macb = dev_get_priv(dev);
+
+ _macb_halt(macb);
+}
+
+static int macb_write_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct macb_device *macb = dev_get_priv(dev);
+
+ return _macb_write_hwaddr(macb, plat->enetaddr);
+}
+
+static const struct eth_ops macb_eth_ops = {
+ .start = macb_start,
+ .send = macb_send,
+ .recv = macb_recv,
+ .stop = macb_stop,
+ .free_pkt = macb_free_pkt,
+ .write_hwaddr = macb_write_hwaddr,
+};
+
+static int macb_eth_probe(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct macb_device *macb = dev_get_priv(dev);
+
+ macb->regs = (void *)pdata->iobase;
+
+ _macb_eth_initialize(macb);
+#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
+ miiphy_register(dev->name, macb_miiphy_read, macb_miiphy_write);
+ macb->bus = miiphy_get_dev_by_name(dev->name);
+#endif
+
+ return 0;
+}
+
+static int macb_eth_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ pdata->iobase = dev_get_addr(dev);
+ return 0;
+}
+
+static const struct udevice_id macb_eth_ids[] = {
+ { .compatible = "cdns,macb" },
+ { }
+};
+
+U_BOOT_DRIVER(eth_macb) = {
+ .name = "eth_macb",
+ .id = UCLASS_ETH,
+ .of_match = macb_eth_ids,
+ .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
+ .probe = macb_eth_probe,
+ .ops = &macb_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct macb_device),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+#endif
#endif
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 08/18] arm: at91: dts: Bring in device tree file for AT91SAM9G45
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
` (6 preceding siblings ...)
2016-05-05 13:28 ` [U-Boot] [PATCH v2 07/18] net: macb: Convert to driver model Simon Glass
@ 2016-05-05 13:28 ` Simon Glass
2016-05-28 22:45 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 09/18] arm: at91: Add a header file for the real-time clock Simon Glass
` (9 subsequent siblings)
17 siblings, 2 replies; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
Add this file from Linux v4.5.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <hs@denx.de>
---
Changes in v2: None
arch/arm/dts/Makefile | 1 +
arch/arm/dts/at91sam9g45.dtsi | 1335 ++++++++++++++++++++++++++++++++++++
include/dt-bindings/clock/at91.h | 23 +
include/dt-bindings/dma/at91.h | 52 ++
include/dt-bindings/pinctrl/at91.h | 40 ++
5 files changed, 1451 insertions(+)
create mode 100644 arch/arm/dts/at91sam9g45.dtsi
create mode 100644 include/dt-bindings/clock/at91.h
create mode 100644 include/dt-bindings/dma/at91.h
create mode 100644 include/dt-bindings/pinctrl/at91.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d1f8e22..a75a485 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -2,6 +2,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
+dtb-$(CONFIG_AT91FAMILY) += at91sam9g45-gurnard.dtb
dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
diff --git a/arch/arm/dts/at91sam9g45.dtsi b/arch/arm/dts/at91sam9g45.dtsi
new file mode 100644
index 0000000..af8b708
--- /dev/null
+++ b/arch/arm/dts/at91sam9g45.dtsi
@@ -0,0 +1,1335 @@
+/*
+ * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
+ * applies to AT91SAM9G45, AT91SAM9M10,
+ * AT91SAM9G46, AT91SAM9M11 SoC
+ *
+ * Copyright (C) 2011 Atmel,
+ * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
+
+/ {
+ model = "Atmel AT91SAM9G45 family SoC";
+ compatible = "atmel,at91sam9g45";
+ interrupt-parent = <&aic>;
+
+ aliases {
+ serial0 = &dbgu;
+ serial1 = &usart0;
+ serial2 = &usart1;
+ serial3 = &usart2;
+ serial4 = &usart3;
+ gpio0 = &pioA;
+ gpio1 = &pioB;
+ gpio2 = &pioC;
+ gpio3 = &pioD;
+ gpio4 = &pioE;
+ tcb0 = &tcb0;
+ tcb1 = &tcb1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ ssc0 = &ssc0;
+ ssc1 = &ssc1;
+ pwm0 = &pwm0;
+ };
+ cpus {
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ };
+ };
+
+ memory {
+ reg = <0x70000000 0x10000000>;
+ };
+
+ clocks {
+ slow_xtal: slow_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ main_xtal: main_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ adc_op_clk: adc_op_clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <300000>;
+ };
+ };
+
+ sram: sram at 00300000 {
+ compatible = "mmio-sram";
+ reg = <0x00300000 0x10000>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ apb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ aic: interrupt-controller at fffff000 {
+ #interrupt-cells = <3>;
+ compatible = "atmel,at91rm9200-aic";
+ interrupt-controller;
+ reg = <0xfffff000 0x200>;
+ atmel,external-irqs = <31>;
+ };
+
+ ramc0: ramc at ffffe400 {
+ compatible = "atmel,at91sam9g45-ddramc";
+ reg = <0xffffe400 0x200>;
+ clocks = <&ddrck>;
+ clock-names = "ddrck";
+ };
+
+ ramc1: ramc at ffffe600 {
+ compatible = "atmel,at91sam9g45-ddramc";
+ reg = <0xffffe600 0x200>;
+ clocks = <&ddrck>;
+ clock-names = "ddrck";
+ };
+
+ pmc: pmc at fffffc00 {
+ compatible = "atmel,at91sam9g45-pmc", "syscon";
+ reg = <0xfffffc00 0x100>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ main_osc: main_osc {
+ compatible = "atmel,at91rm9200-clk-main-osc";
+ #clock-cells = <0>;
+ interrupts-extended = <&pmc AT91_PMC_MOSCS>;
+ clocks = <&main_xtal>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main";
+ #clock-cells = <0>;
+ clocks = <&main_osc>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ interrupts-extended = <&pmc AT91_PMC_LOCKA>;
+ clocks = <&main>;
+ reg = <0>;
+ atmel,clk-input-range = <2000000 32000000>;
+ #atmel,pll-clk-output-range-cells = <4>;
+ atmel,pll-clk-output-ranges = <745000000 800000000 0 0
+ 695000000 750000000 1 0
+ 645000000 700000000 2 0
+ 595000000 650000000 3 0
+ 545000000 600000000 0 1
+ 495000000 555000000 1 1
+ 445000000 500000000 2 1
+ 400000000 450000000 3 1>;
+ };
+
+ plladiv: plladivck {
+ compatible = "atmel,at91sam9x5-clk-plldiv";
+ #clock-cells = <0>;
+ clocks = <&plla>;
+ };
+
+ utmi: utmick {
+ compatible = "atmel,at91sam9x5-clk-utmi";
+ #clock-cells = <0>;
+ interrupts-extended = <&pmc AT91_PMC_LOCKU>;
+ clocks = <&main>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
+ atmel,clk-output-range = <0 133333333>;
+ atmel,clk-divisors = <1 2 4 3>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91sam9x5-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91sam9g45-clk-programmable";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&pmc>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+
+ prog0: prog0 {
+ #clock-cells = <0>;
+ reg = <0>;
+ interrupts = <AT91_PMC_PCKRDY(0)>;
+ };
+
+ prog1: prog1 {
+ #clock-cells = <0>;
+ reg = <1>;
+ interrupts = <AT91_PMC_PCKRDY(1)>;
+ };
+ };
+
+ systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ddrck: ddrck {
+ #clock-cells = <0>;
+ reg = <2>;
+ clocks = <&mck>;
+ };
+
+ uhpck: uhpck {
+ #clock-cells = <0>;
+ reg = <6>;
+ clocks = <&usb>;
+ };
+
+ pck0: pck0 {
+ #clock-cells = <0>;
+ reg = <8>;
+ clocks = <&prog0>;
+ };
+
+ pck1: pck1 {
+ #clock-cells = <0>;
+ reg = <9>;
+ clocks = <&prog1>;
+ };
+ };
+
+ periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&mck>;
+
+ pioA_clk: pioA_clk {
+ #clock-cells = <0>;
+ reg = <2>;
+ };
+
+ pioB_clk: pioB_clk {
+ #clock-cells = <0>;
+ reg = <3>;
+ };
+
+ pioC_clk: pioC_clk {
+ #clock-cells = <0>;
+ reg = <4>;
+ };
+
+ pioDE_clk: pioDE_clk {
+ #clock-cells = <0>;
+ reg = <5>;
+ };
+
+ trng_clk: trng_clk {
+ #clock-cells = <0>;
+ reg = <6>;
+ };
+
+ usart0_clk: usart0_clk {
+ #clock-cells = <0>;
+ reg = <7>;
+ };
+
+ usart1_clk: usart1_clk {
+ #clock-cells = <0>;
+ reg = <8>;
+ };
+
+ usart2_clk: usart2_clk {
+ #clock-cells = <0>;
+ reg = <9>;
+ };
+
+ usart3_clk: usart3_clk {
+ #clock-cells = <0>;
+ reg = <10>;
+ };
+
+ mci0_clk: mci0_clk {
+ #clock-cells = <0>;
+ reg = <11>;
+ };
+
+ twi0_clk: twi0_clk {
+ #clock-cells = <0>;
+ reg = <12>;
+ };
+
+ twi1_clk: twi1_clk {
+ #clock-cells = <0>;
+ reg = <13>;
+ };
+
+ spi0_clk: spi0_clk {
+ #clock-cells = <0>;
+ reg = <14>;
+ };
+
+ spi1_clk: spi1_clk {
+ #clock-cells = <0>;
+ reg = <15>;
+ };
+
+ ssc0_clk: ssc0_clk {
+ #clock-cells = <0>;
+ reg = <16>;
+ };
+
+ ssc1_clk: ssc1_clk {
+ #clock-cells = <0>;
+ reg = <17>;
+ };
+
+ tcb0_clk: tcb0_clk {
+ #clock-cells = <0>;
+ reg = <18>;
+ };
+
+ pwm_clk: pwm_clk {
+ #clock-cells = <0>;
+ reg = <19>;
+ };
+
+ adc_clk: adc_clk {
+ #clock-cells = <0>;
+ reg = <20>;
+ };
+
+ dma0_clk: dma0_clk {
+ #clock-cells = <0>;
+ reg = <21>;
+ };
+
+ uhphs_clk: uhphs_clk {
+ #clock-cells = <0>;
+ reg = <22>;
+ };
+
+ lcd_clk: lcd_clk {
+ #clock-cells = <0>;
+ reg = <23>;
+ };
+
+ ac97_clk: ac97_clk {
+ #clock-cells = <0>;
+ reg = <24>;
+ };
+
+ macb0_clk: macb0_clk {
+ #clock-cells = <0>;
+ reg = <25>;
+ };
+
+ isi_clk: isi_clk {
+ #clock-cells = <0>;
+ reg = <26>;
+ };
+
+ udphs_clk: udphs_clk {
+ #clock-cells = <0>;
+ reg = <27>;
+ };
+
+ aestdessha_clk: aestdessha_clk {
+ #clock-cells = <0>;
+ reg = <28>;
+ };
+
+ mci1_clk: mci1_clk {
+ #clock-cells = <0>;
+ reg = <29>;
+ };
+
+ vdec_clk: vdec_clk {
+ #clock-cells = <0>;
+ reg = <30>;
+ };
+ };
+ };
+
+ rstc at fffffd00 {
+ compatible = "atmel,at91sam9g45-rstc";
+ reg = <0xfffffd00 0x10>;
+ clocks = <&clk32k>;
+ };
+
+ pit: timer at fffffd30 {
+ compatible = "atmel,at91sam9260-pit";
+ reg = <0xfffffd30 0xf>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
+ };
+
+
+ shdwc at fffffd10 {
+ compatible = "atmel,at91sam9rl-shdwc";
+ reg = <0xfffffd10 0x10>;
+ clocks = <&clk32k>;
+ };
+
+ tcb0: timer at fff7c000 {
+ compatible = "atmel,at91rm9200-tcb";
+ reg = <0xfff7c000 0x100>;
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+ };
+
+ tcb1: timer at fffd4000 {
+ compatible = "atmel,at91rm9200-tcb";
+ reg = <0xfffd4000 0x100>;
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+ };
+
+ dma: dma-controller at ffffec00 {
+ compatible = "atmel,at91sam9g45-dma";
+ reg = <0xffffec00 0x200>;
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
+ #dma-cells = <2>;
+ clocks = <&dma0_clk>;
+ clock-names = "dma_clk";
+ };
+
+ pinctrl at fffff200 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+ ranges = <0xfffff200 0xfffff200 0xa00>;
+
+ atmel,mux-mask = <
+ /* A B */
+ 0xffffffff 0xffc003ff /* pioA */
+ 0xffffffff 0x800f8f00 /* pioB */
+ 0xffffffff 0x00000e00 /* pioC */
+ 0xffffffff 0xff0c1381 /* pioD */
+ 0xffffffff 0x81ffff81 /* pioE */
+ >;
+
+ /* shared pinctrl settings */
+ adc0 {
+ pinctrl_adc0_adtrg: adc0_adtrg {
+ atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ pinctrl_adc0_ad0: adc0_ad0 {
+ atmel,pins = <AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ pinctrl_adc0_ad1: adc0_ad1 {
+ atmel,pins = <AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ pinctrl_adc0_ad2: adc0_ad2 {
+ atmel,pins = <AT91_PIOD 22 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ pinctrl_adc0_ad3: adc0_ad3 {
+ atmel,pins = <AT91_PIOD 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ pinctrl_adc0_ad4: adc0_ad4 {
+ atmel,pins = <AT91_PIOD 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ pinctrl_adc0_ad5: adc0_ad5 {
+ atmel,pins = <AT91_PIOD 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ pinctrl_adc0_ad6: adc0_ad6 {
+ atmel,pins = <AT91_PIOD 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ pinctrl_adc0_ad7: adc0_ad7 {
+ atmel,pins = <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+
+ dbgu {
+ pinctrl_dbgu: dbgu-0 {
+ atmel,pins =
+ <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
+ AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
+ };
+ };
+
+ i2c0 {
+ pinctrl_i2c0: i2c0-0 {
+ atmel,pins =
+ <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */
+ AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */
+ };
+ };
+
+ i2c1 {
+ pinctrl_i2c1: i2c1-0 {
+ atmel,pins =
+ <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */
+ AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */
+ };
+ };
+
+ isi {
+ pinctrl_isi_data_0_7: isi-0-data-0-7 {
+ atmel,pins =
+ <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */
+ AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */
+ AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */
+ AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */
+ AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */
+ AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */
+ AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */
+ AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */
+ AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */
+ AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */
+ AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */
+ };
+
+ pinctrl_isi_data_8_9: isi-0-data-8-9 {
+ atmel,pins =
+ <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */
+ AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D9 */
+ };
+
+ pinctrl_isi_data_10_11: isi-0-data-10-11 {
+ atmel,pins =
+ <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */
+ AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D11 */
+ };
+ };
+
+ usart0 {
+ pinctrl_usart0: usart0-0 {
+ atmel,pins =
+ <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */
+ AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
+ };
+
+ pinctrl_usart0_rts: usart0_rts-0 {
+ atmel,pins =
+ <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */
+ };
+
+ pinctrl_usart0_cts: usart0_cts-0 {
+ atmel,pins =
+ <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */
+ };
+ };
+
+ uart1 {
+ pinctrl_usart1: usart1-0 {
+ atmel,pins =
+ <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */
+ AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
+ };
+
+ pinctrl_usart1_rts: usart1_rts-0 {
+ atmel,pins =
+ <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */
+ };
+
+ pinctrl_usart1_cts: usart1_cts-0 {
+ atmel,pins =
+ <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */
+ };
+ };
+
+ usart2 {
+ pinctrl_usart2: usart2-0 {
+ atmel,pins =
+ <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
+ AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
+ };
+
+ pinctrl_usart2_rts: usart2_rts-0 {
+ atmel,pins =
+ <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */
+ };
+
+ pinctrl_usart2_cts: usart2_cts-0 {
+ atmel,pins =
+ <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */
+ };
+ };
+
+ usart3 {
+ pinctrl_usart3: usart3-0 {
+ atmel,pins =
+ <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */
+ AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
+ };
+
+ pinctrl_usart3_rts: usart3_rts-0 {
+ atmel,pins =
+ <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */
+ };
+
+ pinctrl_usart3_cts: usart3_cts-0 {
+ atmel,pins =
+ <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */
+ };
+ };
+
+ nand {
+ pinctrl_nand: nand-0 {
+ atmel,pins =
+ <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/
+ AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
+ };
+ };
+
+ macb {
+ pinctrl_macb_rmii: macb_rmii-0 {
+ atmel,pins =
+ <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
+ AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
+ AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
+ AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
+ AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
+ AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
+ AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */
+ AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
+ AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */
+ AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */
+ };
+
+ pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
+ atmel,pins =
+ <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */
+ AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */
+ AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */
+ AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */
+ AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
+ AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
+ AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */
+ AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
+ };
+ };
+
+ mmc0 {
+ pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
+ atmel,pins =
+ <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */
+ AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
+ AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */
+ };
+
+ pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+ atmel,pins =
+ <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
+ AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
+ AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
+ };
+
+ pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
+ atmel,pins =
+ <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
+ AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
+ AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
+ AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */
+ };
+ };
+
+ mmc1 {
+ pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
+ atmel,pins =
+ <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */
+ AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */
+ AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
+ };
+
+ pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
+ atmel,pins =
+ <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
+ AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */
+ AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */
+ };
+
+ pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
+ atmel,pins =
+ <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */
+ AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
+ AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */
+ AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */
+ };
+ };
+
+ ssc0 {
+ pinctrl_ssc0_tx: ssc0_tx-0 {
+ atmel,pins =
+ <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
+ AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */
+ AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */
+ };
+
+ pinctrl_ssc0_rx: ssc0_rx-0 {
+ atmel,pins =
+ <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */
+ AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */
+ AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */
+ };
+ };
+
+ ssc1 {
+ pinctrl_ssc1_tx: ssc1_tx-0 {
+ atmel,pins =
+ <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */
+ AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */
+ AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */
+ };
+
+ pinctrl_ssc1_rx: ssc1_rx-0 {
+ atmel,pins =
+ <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */
+ AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */
+ AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */
+ };
+ };
+
+ spi0 {
+ pinctrl_spi0: spi0-0 {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */
+ AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */
+ };
+ };
+
+ spi1 {
+ pinctrl_spi1: spi1-0 {
+ atmel,pins =
+ <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */
+ AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */
+ AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */
+ };
+ };
+
+ tcb0 {
+ pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+ atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+ atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+ atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+ atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+ atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+ atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+ atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+ atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+ atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ tcb1 {
+ pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+ atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+ atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+ atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+ atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+ atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+ atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+ atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+ atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+ atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ fb {
+ pinctrl_fb: fb-0 {
+ atmel,pins =
+ <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */
+ AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE2 periph A */
+ AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE3 periph A */
+ AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE4 periph A */
+ AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE5 periph A */
+ AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE6 periph A */
+ AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE7 periph A */
+ AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE8 periph A */
+ AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE9 periph A */
+ AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE10 periph A */
+ AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE11 periph A */
+ AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE12 periph A */
+ AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE13 periph A */
+ AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE14 periph A */
+ AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE15 periph A */
+ AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE16 periph A */
+ AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE17 periph A */
+ AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE18 periph A */
+ AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE19 periph A */
+ AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE20 periph A */
+ AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */
+ AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE22 periph A */
+ AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */
+ AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */
+ AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */
+ AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */
+ AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */
+ AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */
+ AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */
+ AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
+ };
+ };
+
+ pioA: gpio at fffff200 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff200 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioA_clk>;
+ };
+
+ pioB: gpio at fffff400 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioB_clk>;
+ };
+
+ pioC: gpio at fffff600 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff600 0x200>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioC_clk>;
+ };
+
+ pioD: gpio at fffff800 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff800 0x200>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioDE_clk>;
+ };
+
+ pioE: gpio at fffffa00 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffffa00 0x200>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioDE_clk>;
+ };
+ };
+
+ dbgu: serial at ffffee00 {
+ compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0xffffee00 0x200>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ usart0: serial at fff8c000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfff8c000 0x200>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&usart0_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ usart1: serial at fff90000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfff90000 0x200>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&usart1_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ usart2: serial at fff94000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfff94000 0x200>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&usart2_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ usart3: serial at fff98000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfff98000 0x200>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart3>;
+ clocks = <&usart3_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ macb0: ethernet at fffbc000 {
+ compatible = "cdns,at91sam9260-macb", "cdns,macb";
+ reg = <0xfffbc000 0x100>;
+ interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb_rmii>;
+ clocks = <&macb0_clk>, <&macb0_clk>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+
+ trng at fffcc000 {
+ compatible = "atmel,at91sam9g45-trng";
+ reg = <0xfffcc000 0x4000>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&trng_clk>;
+ };
+
+ i2c0: i2c at fff84000 {
+ compatible = "atmel,at91sam9g10-i2c";
+ reg = <0xfff84000 0x100>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&twi0_clk>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at fff88000 {
+ compatible = "atmel,at91sam9g10-i2c";
+ reg = <0xfff88000 0x100>;
+ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&twi1_clk>;
+ status = "disabled";
+ };
+
+ ssc0: ssc at fff9c000 {
+ compatible = "atmel,at91sam9g45-ssc";
+ reg = <0xfff9c000 0x4000>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&ssc0_clk>;
+ clock-names = "pclk";
+ status = "disabled";
+ };
+
+ ssc1: ssc at fffa0000 {
+ compatible = "atmel,at91sam9g45-ssc";
+ reg = <0xfffa0000 0x4000>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+ clocks = <&ssc1_clk>;
+ clock-names = "pclk";
+ status = "disabled";
+ };
+
+ adc0: adc at fffb0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91sam9g45-adc";
+ reg = <0xfffb0000 0x100>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&adc_clk>, <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
+ atmel,adc-channels-used = <0xff>;
+ atmel,adc-vref = <3300>;
+ atmel,adc-startup-time = <40>;
+ atmel,adc-res = <8 10>;
+ atmel,adc-res-names = "lowres", "highres";
+ atmel,adc-use-res = "highres";
+
+ trigger at 0 {
+ reg = <0>;
+ trigger-name = "external-rising";
+ trigger-value = <0x1>;
+ trigger-external;
+ };
+ trigger at 1 {
+ reg = <1>;
+ trigger-name = "external-falling";
+ trigger-value = <0x2>;
+ trigger-external;
+ };
+
+ trigger at 2 {
+ reg = <2>;
+ trigger-name = "external-any";
+ trigger-value = <0x3>;
+ trigger-external;
+ };
+
+ trigger at 3 {
+ reg = <3>;
+ trigger-name = "continuous";
+ trigger-value = <0x6>;
+ };
+ };
+
+ isi at fffb4000 {
+ compatible = "atmel,at91sam9g45-isi";
+ reg = <0xfffb4000 0x4000>;
+ interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>;
+ clocks = <&isi_clk>;
+ clock-names = "isi_clk";
+ status = "disabled";
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ pwm0: pwm at fffb8000 {
+ compatible = "atmel,at91sam9rl-pwm";
+ reg = <0xfffb8000 0x300>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
+ #pwm-cells = <3>;
+ clocks = <&pwm_clk>;
+ status = "disabled";
+ };
+
+ mmc0: mmc at fff80000 {
+ compatible = "atmel,hsmci";
+ reg = <0xfff80000 0x600>;
+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-names = "default";
+ dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
+ dma-names = "rxtx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&mci0_clk>;
+ clock-names = "mci_clk";
+ status = "disabled";
+ };
+
+ mmc1: mmc at fffd0000 {
+ compatible = "atmel,hsmci";
+ reg = <0xfffd0000 0x600>;
+ interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-names = "default";
+ dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
+ dma-names = "rxtx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&mci1_clk>;
+ clock-names = "mci_clk";
+ status = "disabled";
+ };
+
+ watchdog at fffffd40 {
+ compatible = "atmel,at91sam9260-wdt";
+ reg = <0xfffffd40 0x10>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
+ atmel,watchdog-type = "hardware";
+ atmel,reset-type = "all";
+ atmel,dbg-halt;
+ status = "disabled";
+ };
+
+ spi0: spi at fffa4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xfffa4000 0x200>;
+ interrupts = <14 4 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&spi0_clk>;
+ clock-names = "spi_clk";
+ status = "disabled";
+ };
+
+ spi1: spi at fffa8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xfffa8000 0x200>;
+ interrupts = <15 4 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&spi1_clk>;
+ clock-names = "spi_clk";
+ status = "disabled";
+ };
+
+ usb2: gadget at fff78000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91sam9g45-udc";
+ reg = <0x00600000 0x80000
+ 0xfff78000 0x400>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&udphs_clk>, <&utmi>;
+ clock-names = "pclk", "hclk";
+ status = "disabled";
+
+ ep0 {
+ reg = <0>;
+ atmel,fifo-size = <64>;
+ atmel,nb-banks = <1>;
+ };
+
+ ep1 {
+ reg = <1>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <2>;
+ atmel,can-dma;
+ atmel,can-isoc;
+ };
+
+ ep2 {
+ reg = <2>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <2>;
+ atmel,can-dma;
+ atmel,can-isoc;
+ };
+
+ ep3 {
+ reg = <3>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <3>;
+ atmel,can-dma;
+ };
+
+ ep4 {
+ reg = <4>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <3>;
+ atmel,can-dma;
+ };
+
+ ep5 {
+ reg = <5>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <3>;
+ atmel,can-dma;
+ atmel,can-isoc;
+ };
+
+ ep6 {
+ reg = <6>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <3>;
+ atmel,can-dma;
+ atmel,can-isoc;
+ };
+ };
+
+ sckc at fffffd50 {
+ compatible = "atmel,at91sam9x5-sckc";
+ reg = <0xfffffd50 0x4>;
+
+ slow_osc: slow_osc {
+ compatible = "atmel,at91sam9x5-clk-slow-osc";
+ #clock-cells = <0>;
+ atmel,startup-time-usec = <1200000>;
+ clocks = <&slow_xtal>;
+ };
+
+ slow_rc_osc: slow_rc_osc {
+ compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
+ #clock-cells = <0>;
+ atmel,startup-time-usec = <75>;
+ clock-frequency = <32768>;
+ clock-accuracy = <50000000>;
+ };
+
+ clk32k: slck {
+ compatible = "atmel,at91sam9x5-clk-slow";
+ #clock-cells = <0>;
+ clocks = <&slow_rc_osc &slow_osc>;
+ };
+ };
+
+ rtc at fffffd20 {
+ compatible = "atmel,at91sam9260-rtt";
+ reg = <0xfffffd20 0x10>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
+ status = "disabled";
+ };
+
+ rtc at fffffdb0 {
+ compatible = "atmel,at91rm9200-rtc";
+ reg = <0xfffffdb0 0x30>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
+ status = "disabled";
+ };
+
+ gpbr: syscon at fffffd60 {
+ compatible = "atmel,at91sam9260-gpbr", "syscon";
+ reg = <0xfffffd60 0x10>;
+ status = "disabled";
+ };
+ };
+
+ fb0: fb at 0x00500000 {
+ compatible = "atmel,at91sam9g45-lcdc";
+ reg = <0x00500000 0x1000>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fb>;
+ clocks = <&lcd_clk>, <&lcd_clk>;
+ clock-names = "hclk", "lcdc_clk";
+ status = "disabled";
+ };
+
+ nand0: nand at 40000000 {
+ compatible = "atmel,at91rm9200-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40000000 0x10000000
+ 0xffffe200 0x200
+ >;
+ atmel,nand-addr-offset = <21>;
+ atmel,nand-cmd-offset = <22>;
+ atmel,nand-has-dma;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+ gpios = <&pioC 8 GPIO_ACTIVE_HIGH
+ &pioC 14 GPIO_ACTIVE_HIGH
+ 0
+ >;
+ status = "disabled";
+ };
+
+ usb0: ohci at 00700000 {
+ compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+ reg = <0x00700000 0x100000>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
+ clock-names = "ohci_clk", "hclk", "uhpck";
+ status = "disabled";
+ };
+
+ usb1: ehci at 00800000 {
+ compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+ reg = <0x00800000 0x100000>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&utmi>, <&uhphs_clk>;
+ clock-names = "usb_clk", "ehci_clk";
+ status = "disabled";
+ };
+ };
+
+ i2c at 0 {
+ compatible = "i2c-gpio";
+ gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
+ &pioA 21 GPIO_ACTIVE_HIGH /* scl */
+ >;
+ i2c-gpio,sda-open-drain;
+ i2c-gpio,scl-open-drain;
+ i2c-gpio,delay-us = <5>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+};
diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
new file mode 100644
index 0000000..ab3ee24
--- /dev/null
+++ b/include/dt-bindings/clock/at91.h
@@ -0,0 +1,23 @@
+/*
+ * This header provides constants for AT91 pmc status.
+ *
+ * The constants defined in this header are being used in dts.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef _DT_BINDINGS_CLK_AT91_H
+#define _DT_BINDINGS_CLK_AT91_H
+
+#define AT91_PMC_MOSCS 0 /* MOSCS Flag */
+#define AT91_PMC_LOCKA 1 /* PLLA Lock */
+#define AT91_PMC_LOCKB 2 /* PLLB Lock */
+#define AT91_PMC_MCKRDY 3 /* Master Clock */
+#define AT91_PMC_LOCKU 6 /* UPLL Lock */
+#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */
+#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */
+#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */
+#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
+#define AT91_PMC_GCKRDY 24 /* Generated Clocks */
+
+#endif
diff --git a/include/dt-bindings/dma/at91.h b/include/dt-bindings/dma/at91.h
new file mode 100644
index 0000000..ab6cbba
--- /dev/null
+++ b/include/dt-bindings/dma/at91.h
@@ -0,0 +1,52 @@
+/*
+ * This header provides macros for at91 dma bindings.
+ *
+ * Copyright (C) 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * GPLv2 only
+ */
+
+#ifndef __DT_BINDINGS_AT91_DMA_H__
+#define __DT_BINDINGS_AT91_DMA_H__
+
+/* ---------- HDMAC ---------- */
+
+/*
+ * Source and/or destination peripheral ID
+ */
+#define AT91_DMA_CFG_PER_ID_MASK (0xff)
+#define AT91_DMA_CFG_PER_ID(id) (id & AT91_DMA_CFG_PER_ID_MASK)
+
+/*
+ * FIFO configuration: it defines when a request is serviced.
+ */
+#define AT91_DMA_CFG_FIFOCFG_OFFSET (8)
+#define AT91_DMA_CFG_FIFOCFG_MASK (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET)
+#define AT91_DMA_CFG_FIFOCFG_HALF (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* half FIFO (default behavior) */
+#define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */
+#define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */
+
+
+/* ---------- XDMAC ---------- */
+#define AT91_XDMAC_DT_MEM_IF_MASK (0x1)
+#define AT91_XDMAC_DT_MEM_IF_OFFSET (13)
+#define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \
+ << AT91_XDMAC_DT_MEM_IF_OFFSET)
+#define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
+ & AT91_XDMAC_DT_MEM_IF_MASK)
+
+#define AT91_XDMAC_DT_PER_IF_MASK (0x1)
+#define AT91_XDMAC_DT_PER_IF_OFFSET (14)
+#define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \
+ << AT91_XDMAC_DT_PER_IF_OFFSET)
+#define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
+ & AT91_XDMAC_DT_PER_IF_MASK)
+
+#define AT91_XDMAC_DT_PERID_MASK (0x7f)
+#define AT91_XDMAC_DT_PERID_OFFSET (24)
+#define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \
+ << AT91_XDMAC_DT_PERID_OFFSET)
+#define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
+ & AT91_XDMAC_DT_PERID_MASK)
+
+#endif /* __DT_BINDINGS_AT91_DMA_H__ */
diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
new file mode 100644
index 0000000..bbca3d0
--- /dev/null
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -0,0 +1,40 @@
+/*
+ * This header provides constants for most at91 pinctrl bindings.
+ *
+ * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * GPLv2 only
+ */
+
+#ifndef __DT_BINDINGS_AT91_PINCTRL_H__
+#define __DT_BINDINGS_AT91_PINCTRL_H__
+
+#define AT91_PINCTRL_NONE (0 << 0)
+#define AT91_PINCTRL_PULL_UP (1 << 0)
+#define AT91_PINCTRL_MULTI_DRIVE (1 << 1)
+#define AT91_PINCTRL_DEGLITCH (1 << 2)
+#define AT91_PINCTRL_PULL_DOWN (1 << 3)
+#define AT91_PINCTRL_DIS_SCHMIT (1 << 4)
+#define AT91_PINCTRL_DEBOUNCE (1 << 16)
+#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17)
+
+#define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH)
+
+#define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT (0x0 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_LOW (0x1 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5)
+
+#define AT91_PIOA 0
+#define AT91_PIOB 1
+#define AT91_PIOC 2
+#define AT91_PIOD 3
+#define AT91_PIOE 4
+
+#define AT91_PERIPH_GPIO 0
+#define AT91_PERIPH_A 1
+#define AT91_PERIPH_B 2
+#define AT91_PERIPH_C 3
+#define AT91_PERIPH_D 4
+
+#endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 09/18] arm: at91: Add a header file for the real-time clock
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
` (7 preceding siblings ...)
2016-05-05 13:28 ` [U-Boot] [PATCH v2 08/18] arm: at91: dts: Bring in device tree file for AT91SAM9G45 Simon Glass
@ 2016-05-05 13:28 ` Simon Glass
2016-05-28 12:49 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 10/18] at91: Correct NAND ECC register access Simon Glass
` (8 subsequent siblings)
17 siblings, 2 replies; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
From: Andre Renaud <andre@designa-electronics.com>
Add register definitions for the AT91 RTC so that this can potentially be
used in U-Boot.
Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
---
Changes in v2: None
arch/arm/mach-at91/include/mach/at91_rtc.h | 71 ++++++++++++++++++++++++++++++
1 file changed, 71 insertions(+)
create mode 100644 arch/arm/mach-at91/include/mach/at91_rtc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_rtc.h b/arch/arm/mach-at91/include/mach/at91_rtc.h
new file mode 100644
index 0000000..73070e3
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_rtc.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Real Time Clock (RTC) - System peripheral registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef AT91_RTC_H
+#define AT91_RTC_H
+
+/* Control Register */
+#define AT91_RTC_CR (ATMEL_BASE_RTC + 0x00)
+#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time */
+#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar */
+#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */
+#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8)
+#define AT91_RTC_TIMEVSEL_HOUR (1 << 8)
+#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8)
+#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8)
+#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */
+#define AT91_RTC_CALEVSEL_WEEK (0 << 16)
+#define AT91_RTC_CALEVSEL_MONTH (1 << 16)
+#define AT91_RTC_CALEVSEL_YEAR (2 << 16)
+
+#define AT91_RTC_MR (ATMEL_BASE_RTC + 0x04) /* Mode Register */
+#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */
+
+#define AT91_RTC_TIMR (ATMEL_BASE_RTC + 0x08) /* Time Register */
+#define AT91_RTC_SEC (0x7f << 0) /* Current Second */
+#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
+#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
+#define AT91_RTC_AMPM (1 << 22) /* AM/PM */
+
+#define AT91_RTC_CALR (ATMEL_BASE_RTC + 0x0c) /* Calendar Register */
+#define AT91_RTC_CENT (0x7f << 0) /* Current Century */
+#define AT91_RTC_YEAR (0xff << 8) /* Current Year */
+#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */
+#define AT91_RTC_DAY (7 << 21) /* Current Day */
+#define AT91_RTC_DATE (0x3f << 24) /* Current Date */
+
+#define AT91_RTC_TIMALR (ATMEL_BASE_RTC + 0x10) /* Time Alarm */
+#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enab */
+#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enab */
+#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */
+
+#define AT91_RTC_CALALR (ATMEL_BASE_RTC + 0x14) /* Calendar Alarm */
+#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */
+#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */
+
+#define AT91_RTC_SR (ATMEL_BASE_RTC + 0x18) /* Status Register */
+#define AT91_RTC_ACKUPD (1 << 0) /* Ack for Update */
+#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */
+#define AT91_RTC_SECEV (1 << 2) /* Second Event */
+#define AT91_RTC_TIMEV (1 << 3) /* Time Event */
+#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */
+
+#define AT91_RTC_SCCR (ATMEL_BASE_RTC + 0x1c) /* Status Clear Cmd */
+#define AT91_RTC_IER (ATMEL_BASE_RTC + 0x20) /* Interrupt Enable */
+#define AT91_RTC_IDR (ATMEL_BASE_RTC + 0x24) /* Interrupt Disable */
+#define AT91_RTC_IMR (ATMEL_BASE_RTC + 0x28) /* Interrupt Mask */
+
+#define AT91_RTC_VER (ATMEL_BASE_RTC + 0x2c) /* Valid Entry */
+#define AT91_RTC_NVTIM (1 << 0) /* Non-valid Time */
+#define AT91_RTC_NVCAL (1 << 1) /* Non-valid Calendar */
+#define AT91_RTC_NVTIMALR (1 << 2) /* .. Time Alarm */
+#define AT91_RTC_NVCALALR (1 << 3) /* .. Calendar Alarm */
+
+#endif
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 10/18] at91: Correct NAND ECC register access
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
` (8 preceding siblings ...)
2016-05-05 13:28 ` [U-Boot] [PATCH v2 09/18] arm: at91: Add a header file for the real-time clock Simon Glass
@ 2016-05-05 13:28 ` Simon Glass
2016-05-28 21:06 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 11/18] at91: nand: Set up the ECC strength correctly Simon Glass
` (7 subsequent siblings)
17 siblings, 2 replies; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
From: Andre Renaud <andre@designa-electronics.com>
This uses the wrote base register value. Fix it.
Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2: None
drivers/mtd/nand/atmel_nand.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 7cc1de0..4e278fa 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -24,9 +24,9 @@
/* Register access macros */
#define ecc_readl(add, reg) \
- readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
+ readl(add + ATMEL_ECC_##reg)
#define ecc_writel(add, reg, value) \
- writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
+ writel((value), add + ATMEL_ECC_##reg)
#include "atmel_nand_ecc.h" /* Hardware ECC registers */
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 11/18] at91: nand: Set up the ECC strength correctly
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
` (9 preceding siblings ...)
2016-05-05 13:28 ` [U-Boot] [PATCH v2 10/18] at91: Correct NAND ECC register access Simon Glass
@ 2016-05-05 13:28 ` Simon Glass
2016-05-28 21:12 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 12/18] mtd: nand: Drop a blank line in nand_wait() Simon Glass
` (6 subsequent siblings)
17 siblings, 2 replies; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
From: Andre Renaud <andre@designa-electronics.com>
This needs to be set to avoid a fatal error when ECC is used.
Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2: None
drivers/mtd/nand/atmel_nand.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 4e278fa..8fac824 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1155,6 +1155,7 @@ int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
nand->ecc.hwctl = atmel_nand_hwctl;
nand->ecc.read_page = atmel_nand_read_page;
nand->ecc.bytes = 4;
+ nand->ecc.strength = 4;
if (nand->ecc.mode == NAND_ECC_HW) {
/* ECC is calculated for the whole page (1 step) */
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 12/18] mtd: nand: Drop a blank line in nand_wait()
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
` (10 preceding siblings ...)
2016-05-05 13:28 ` [U-Boot] [PATCH v2 11/18] at91: nand: Set up the ECC strength correctly Simon Glass
@ 2016-05-05 13:28 ` Simon Glass
2016-05-28 12:53 ` Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 13/18] at91: Add driver-model GPIO devices for AT91SAM9G45 Simon Glass
` (5 subsequent siblings)
17 siblings, 1 reply; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
From: Andre Renaud <andre@designa-electronics.com>
This empty line should not be there. Remove it.
Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2: None
drivers/mtd/nand/nand_base.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 9e8fc1f..bcd4d70 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -877,7 +877,6 @@ static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
*/
static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
{
-
int status, state = chip->state;
unsigned long timeo = (state == FL_ERASING ? 400 : 20);
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 13/18] at91: Add driver-model GPIO devices for AT91SAM9G45
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
` (11 preceding siblings ...)
2016-05-05 13:28 ` [U-Boot] [PATCH v2 12/18] mtd: nand: Drop a blank line in nand_wait() Simon Glass
@ 2016-05-05 13:28 ` Simon Glass
2016-05-28 22:46 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 14/18] at91: mtd: nand: Add dev_warn() to correct build error in driver Simon Glass
` (4 subsequent siblings)
17 siblings, 2 replies; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
Add these definitions so that GPIOs can be used with driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <hs@denx.de>
---
Changes in v2: None
arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c
index 0d83426..eddfdb0 100644
--- a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c
+++ b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <dm.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
@@ -165,3 +166,20 @@ void at91_mci_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_MCI0);
}
#endif
+
+/* Platform data for the GPIOs */
+static const struct at91_port_platdata at91sam9260_plat[] = {
+ { ATMEL_BASE_PIOA, "PA" },
+ { ATMEL_BASE_PIOB, "PB" },
+ { ATMEL_BASE_PIOC, "PC" },
+ { ATMEL_BASE_PIOD, "PD" },
+ { ATMEL_BASE_PIOE, "PE" },
+};
+
+U_BOOT_DEVICES(at91sam9260_gpios) = {
+ { "gpio_at91", &at91sam9260_plat[0] },
+ { "gpio_at91", &at91sam9260_plat[1] },
+ { "gpio_at91", &at91sam9260_plat[2] },
+ { "gpio_at91", &at91sam9260_plat[3] },
+ { "gpio_at91", &at91sam9260_plat[4] },
+};
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 14/18] at91: mtd: nand: Add dev_warn() to correct build error in driver
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
` (12 preceding siblings ...)
2016-05-05 13:28 ` [U-Boot] [PATCH v2 13/18] at91: Add driver-model GPIO devices for AT91SAM9G45 Simon Glass
@ 2016-05-05 13:28 ` Simon Glass
2016-05-28 23:04 ` Andreas Bießmann
2016-06-04 20:27 ` [U-Boot] [PATCH] linux/compat.h: add dev_warn() Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 15/18] at91: video: Prepare for driver-model conversion Simon Glass
` (3 subsequent siblings)
17 siblings, 2 replies; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
The code does not compile if ECC is enabled.
Signed-off-by: Andre Renaud <arenaud@bluewatersys.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2: None
drivers/mtd/nand/atmel_nand.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 8fac824..15958cb 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -20,6 +20,8 @@
#include <watchdog.h>
#include <linux/mtd/nand_ecc.h>
+#define dev_warn(dev, msg...)
+
#ifdef CONFIG_ATMEL_NAND_HWECC
/* Register access macros */
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 15/18] at91: video: Prepare for driver-model conversion
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
` (13 preceding siblings ...)
2016-05-05 13:28 ` [U-Boot] [PATCH v2 14/18] at91: mtd: nand: Add dev_warn() to correct build error in driver Simon Glass
@ 2016-05-05 13:28 ` Simon Glass
2016-06-04 20:08 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 16/18] at91: video: Support driver-model for the LCD driver Simon Glass
` (2 subsequent siblings)
17 siblings, 2 replies; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
Adjust the driver to use struct display_timing for its display timing.
This is what is used by driver-model and allows the LCD init code to be
common.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2: None
drivers/video/atmel_lcdfb.c | 106 +++++++++++++++++++++++++++++---------------
1 file changed, 70 insertions(+), 36 deletions(-)
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index d43d8a5..37838a8 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <fdtdec.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
@@ -91,39 +92,41 @@ void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
}
}
-void lcd_ctrl_init(void *lcdbase)
+static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
+ bool tft, bool cont_pol_low, ulong lcdbase)
{
unsigned long value;
+ void *reg = (void *)addr;
/* Turn off the LCD controller and the DMA controller */
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
+ lcdc_writel(reg, ATMEL_LCDC_PWRCON,
ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
/* Wait for the LCDC core to become idle */
- while (lcdc_readl(panel_info.mmio, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
+ while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
udelay(10);
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, 0);
+ lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);
/* Reset LCDC DMA */
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
+ lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
/* ...set frame size and burst length = 8 words (?) */
- value = (panel_info.vl_col * panel_info.vl_row *
- NBITS(panel_info.vl_bpix)) / 32;
+ value = (timing->hactive.typ * timing->vactive.typ *
+ (1 << bpix)) / 32;
value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMAFRMCFG, value);
+ lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);
/* Set pixel clock */
- value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
- if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
+ value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
+ if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
value++;
value = (value / 2) - 1;
if (!value) {
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
+ lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
} else
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1,
+ lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
value << ATMEL_LCDC_CLKVAL_OFFSET);
/* Initialize control register 2 */
@@ -132,56 +135,87 @@ void lcd_ctrl_init(void *lcdbase)
#else
value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
#endif
- if (panel_info.vl_tft)
+ if (tft)
value |= ATMEL_LCDC_DISTYPE_TFT;
- value |= panel_info.vl_sync;
- value |= (panel_info.vl_bpix << 5);
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value);
+ if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
+ value |= ATMEL_LCDC_INVLINE_INVERTED;
+ if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
+ value |= ATMEL_LCDC_INVFRAME_INVERTED;
+ value |= bpix << 5;
+ lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);
/* Vertical timing */
- value = (panel_info.vl_vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
- value |= panel_info.vl_upper_margin << ATMEL_LCDC_VBP_OFFSET;
- value |= panel_info.vl_lower_margin;
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM1, value);
+ value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
+ value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
+ value |= timing->vfront_porch.typ;
+ /* Magic! (Datasheet says "Bit 31 must be written to 1") */
+ value |= 1U << 31;
+ lcdc_writel(reg, ATMEL_LCDC_TIM1, value);
/* Horizontal timing */
- value = (panel_info.vl_right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
- value |= (panel_info.vl_hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
- value |= (panel_info.vl_left_margin - 1);
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM2, value);
+ value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
+ value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
+ value |= (timing->hback_porch.typ - 1);
+ lcdc_writel(reg, ATMEL_LCDC_TIM2, value);
/* Display size */
- value = (panel_info.vl_col - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
- value |= panel_info.vl_row - 1;
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDFRMCFG, value);
+ value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
+ value |= timing->vactive.typ - 1;
+ lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);
/* FIFO Threshold: Use formula from data sheet */
value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_FIFO, value);
+ lcdc_writel(reg, ATMEL_LCDC_FIFO, value);
/* Toggle LCD_MODE every frame */
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_MVAL, 0);
+ lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);
/* Disable all interrupts */
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_IDR, ~0UL);
+ lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);
/* Set contrast */
value = ATMEL_LCDC_PS_DIV8 |
ATMEL_LCDC_ENA_PWMENABLE;
- if (!panel_info.vl_cont_pol_low)
+ if (!cont_pol_low)
value |= ATMEL_LCDC_POL_POSITIVE;
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value);
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
+ lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
+ lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
/* Set framebuffer DMA base address and pixel offset */
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMABADDR1, (u_long)lcdbase);
+ lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
+ lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
+ lcdc_writel(reg, ATMEL_LCDC_PWRCON,
(ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
}
+void lcd_ctrl_init(void *lcdbase)
+{
+ struct display_timing timing;
+
+ timing.flags = 0;
+ if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
+ timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
+ if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
+ timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
+ timing.pixelclock.typ = panel_info.vl_clk;
+
+ timing.hactive.typ = panel_info.vl_col;
+ timing.hfront_porch.typ = panel_info.vl_right_margin;
+ timing.hback_porch.typ = panel_info.vl_left_margin;
+ timing.hsync_len.typ = panel_info.vl_hsync_len;
+
+ timing.vactive.typ = panel_info.vl_row;
+ timing.vfront_porch.typ = panel_info.vl_clk;
+ timing.vback_porch.typ = panel_info.vl_clk;
+ timing.vsync_len.typ = panel_info.vl_clk;
+
+ atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
+ panel_info.vl_tft, panel_info.vl_cont_pol_low,
+ (ulong)lcdbase);
+}
+
ulong calc_fbsize(void)
{
return ((panel_info.vl_col * panel_info.vl_row *
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 16/18] at91: video: Support driver-model for the LCD driver
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
` (14 preceding siblings ...)
2016-05-05 13:28 ` [U-Boot] [PATCH v2 15/18] at91: video: Prepare for driver-model conversion Simon Glass
@ 2016-05-05 13:28 ` Simon Glass
2016-06-04 20:11 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 17/18] fdt: Correct return value in fdtdec_decode_display_timing() Simon Glass
2016-05-05 13:28 ` [U-Boot] [PATCH v2 18/18] arm: at91: Add support for gurnard Simon Glass
17 siblings, 2 replies; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
Add driver-model support to this driver. Most features can be controlled
from the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2: None
drivers/video/atmel_lcdfb.c | 91 +++++++++++++++++++++++++++++++++++++++++++++
include/atmel_lcd.h | 9 +++++
2 files changed, 100 insertions(+)
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index 37838a8..39cd7ca 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -7,7 +7,10 @@
*/
#include <common.h>
+#include <atmel_lcd.h>
+#include <dm.h>
#include <fdtdec.h>
+#include <video.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
@@ -15,6 +18,21 @@
#include <bmp_layout.h>
#include <atmel_lcdc.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DM_VIDEO
+enum {
+ /* Maximum LCD size we support */
+ LCD_MAX_WIDTH = 1366,
+ LCD_MAX_HEIGHT = 768,
+ LCD_MAX_LOG2_BPP = VIDEO_BPP16,
+};
+#endif
+
+struct atmel_fb_priv {
+ struct display_timing timing;
+};
+
/* configurable parameters */
#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
#define ATMEL_LCDC_DMA_BURST_LEN 8
@@ -31,6 +49,7 @@
#define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg))
#define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg))
+#ifndef CONFIG_DM_VIDEO
ushort *configuration_get_cmap(void)
{
return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
@@ -91,6 +110,7 @@ void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
lcd_setcolreg(i, cte.red, cte.green, cte.blue);
}
}
+#endif
static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
bool tft, bool cont_pol_low, ulong lcdbase)
@@ -190,6 +210,7 @@ static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
(ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
}
+#ifndef CONFIG_DM_VIDEO
void lcd_ctrl_init(void *lcdbase)
{
struct display_timing timing;
@@ -221,3 +242,73 @@ ulong calc_fbsize(void)
return ((panel_info.vl_col * panel_info.vl_row *
NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
}
+#endif
+
+#ifdef CONFIG_DM_VIDEO
+static int atmel_fb_lcd_probe(struct udevice *dev)
+{
+ struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct atmel_fb_priv *priv = dev_get_priv(dev);
+ struct display_timing *timing = &priv->timing;
+
+ /*
+ * For now some values are hard-coded. We could use the device tree
+ * bindings in simple-framebuffer.txt to specify the format/bpp and
+ * some Atmel-specific binding for tft and cont_pol_low.
+ */
+ atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
+ uc_plat->base);
+ uc_priv->xsize = timing->hactive.typ;
+ uc_priv->ysize = timing->vactive.typ;
+ uc_priv->bpix = VIDEO_BPP16;
+ video_set_flush_dcache(dev, true);
+ debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
+ uc_plat->size, uc_priv->xsize, uc_priv->ysize);
+
+ return 0;
+}
+
+static int atmel_fb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
+ struct atmel_fb_priv *priv = dev_get_priv(dev);
+ struct display_timing *timing = &priv->timing;
+ const void *blob = gd->fdt_blob;
+
+ if (fdtdec_decode_display_timing(blob, dev->of_offset,
+ plat->timing_index, timing)) {
+ debug("%s: Failed to decode display timing\n", __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int atmel_fb_lcd_bind(struct udevice *dev)
+{
+ struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+
+ uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
+ (1 << VIDEO_BPP16) / 8;
+ debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
+
+ return 0;
+}
+
+static const struct udevice_id atmel_fb_lcd_ids[] = {
+ { .compatible = "atmel,at91sam9g45-lcdc" },
+ { }
+};
+
+U_BOOT_DRIVER(atmel_fb) = {
+ .name = "atmel_fb",
+ .id = UCLASS_VIDEO,
+ .of_match = atmel_fb_lcd_ids,
+ .bind = atmel_fb_lcd_bind,
+ .ofdata_to_platdata = atmel_fb_ofdata_to_platdata,
+ .probe = atmel_fb_lcd_probe,
+ .platdata_auto_alloc_size = sizeof(struct atmel_lcd_platdata),
+ .priv_auto_alloc_size = sizeof(struct atmel_fb_priv),
+};
+#endif
diff --git a/include/atmel_lcd.h b/include/atmel_lcd.h
index 6993128..8a2f46f 100644
--- a/include/atmel_lcd.h
+++ b/include/atmel_lcd.h
@@ -10,6 +10,15 @@
#ifndef _ATMEL_LCD_H_
#define _ATMEL_LCD_H_
+/**
+ * struct atmel_lcd_platdata - platform data for Atmel LCDs with driver model
+ *
+ * @timing_index: Index of LCD timing to use in device tree node
+ */
+struct atmel_lcd_platdata {
+ int timing_index;
+};
+
typedef struct vidinfo {
ushort vl_col; /* Number of columns (i.e. 640) */
ushort vl_row; /* Number of rows (i.e. 480) */
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 17/18] fdt: Correct return value in fdtdec_decode_display_timing()
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
` (15 preceding siblings ...)
2016-05-05 13:28 ` [U-Boot] [PATCH v2 16/18] at91: video: Support driver-model for the LCD driver Simon Glass
@ 2016-05-05 13:28 ` Simon Glass
2016-06-04 20:14 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 18/18] arm: at91: Add support for gurnard Simon Glass
17 siblings, 2 replies; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
This should return a non-zero value if there is a missing property. Update
the return value accordingly. The only expected error is -FDT_ERR_NOTFOUND.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2: None
lib/fdtdec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 70acc29..9782c93 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1169,7 +1169,7 @@ int fdtdec_decode_display_timing(const void *blob, int parent, int index,
if (fdtdec_get_bool(blob, node, "doubleclk"))
dt->flags |= DISPLAY_FLAGS_DOUBLECLK;
- return 0;
+ return ret;
}
int fdtdec_setup(void)
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 18/18] arm: at91: Add support for gurnard
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
` (16 preceding siblings ...)
2016-05-05 13:28 ` [U-Boot] [PATCH v2 17/18] fdt: Correct return value in fdtdec_decode_display_timing() Simon Glass
@ 2016-05-05 13:28 ` Simon Glass
2016-06-04 20:31 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot,v2,18/18] " Andreas Bießmann
17 siblings, 2 replies; 56+ messages in thread
From: Simon Glass @ 2016-05-05 13:28 UTC (permalink / raw)
To: u-boot
From: Andre Renaud <andre@designa-electronics.com>
This board is based on Snapper 9G45 which has an Atmel AT91SAM9G45 chip and
128MB of SDRAM. It includes a small LCD, 2xUSB host, SD card, Ethernet and
two UARTs.
Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2:
- Correct commit author in several cases
- Rebase to master
arch/arm/dts/at91sam9g45-gurnard.dts | 157 ++
arch/arm/mach-at91/Kconfig | 9 +
board/bluewater/gurnard/Kconfig | 12 +
board/bluewater/gurnard/MAINTAINERS | 6 +
board/bluewater/gurnard/Makefile | 11 +
board/bluewater/gurnard/gurnard.c | 449 ++++++
board/bluewater/gurnard/splash_logo.h | 2619 +++++++++++++++++++++++++++++++++
configs/gurnard_defconfig | 19 +
include/configs/snapper9g45.h | 156 ++
9 files changed, 3438 insertions(+)
create mode 100644 arch/arm/dts/at91sam9g45-gurnard.dts
create mode 100644 board/bluewater/gurnard/Kconfig
create mode 100644 board/bluewater/gurnard/MAINTAINERS
create mode 100644 board/bluewater/gurnard/Makefile
create mode 100644 board/bluewater/gurnard/gurnard.c
create mode 100644 board/bluewater/gurnard/splash_logo.h
create mode 100644 configs/gurnard_defconfig
create mode 100644 include/configs/snapper9g45.h
diff --git a/arch/arm/dts/at91sam9g45-gurnard.dts b/arch/arm/dts/at91sam9g45-gurnard.dts
new file mode 100644
index 0000000..75c1e99
--- /dev/null
+++ b/arch/arm/dts/at91sam9g45-gurnard.dts
@@ -0,0 +1,157 @@
+/*
+ * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+#include "at91sam9g45.dtsi"
+
+/ {
+ model = "Bluewater Systems Gurnard";
+ compatible = "atmel,at91sam9g45", "atmel,at91sam9";
+
+ chosen {
+ bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x20000000 0x8000000>;
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <18432000>;
+ };
+ };
+
+ ahb {
+ u-boot,dm-pre-reloc;
+
+ fb at 0x00500000 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+ display-timings {
+ rev1 {
+ clock-frequency = <4166666>;
+ hactive = <480>;
+ vactive = <272>;
+ hfront-porch = <1>;
+ hback-porch = <1>;
+ hsync-len = <1>;
+ vback-porch = <4>;
+ vfront-porch = <2>;
+ vsync-len = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ };
+
+ rev2 {
+ clock-frequency = <4166666>;
+ hactive = <480>;
+ vactive = <272>;
+ hfront-porch = <2>;
+ hback-porch = <2>;
+ hsync-len = <10>;
+ vback-porch = <2>;
+ vfront-porch = <2>;
+ vsync-len = <10>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ };
+ };
+ };
+
+ apb {
+ pinctrl at fffff400 {
+ board {
+ pinctrl_pck0_as_mck: pck0_as_mck {
+ atmel,pins =
+ <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC1 periph B */
+ };
+
+ };
+
+ mmc0_slot1 {
+ pinctrl_board_mmc0_slot1: mmc0_slot1-board {
+ atmel,pins =
+ <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PC9 gpio CD pin pull up and deglitch */
+ };
+ };
+ };
+
+ dbgu: serial at ffffee00 {
+ status = "okay";
+ };
+
+ macb0: ethernet at fffbc000 {
+ phy-mode = "rmii";
+ status = "okay";
+ };
+
+ mmc0: mmc at fff80000 {
+ pinctrl-0 = <
+ &pinctrl_board_mmc0_slot1
+ &pinctrl_mmc0_slot0_clk_cmd_dat0
+ &pinctrl_mmc0_slot0_dat1_3>;
+ status = "okay";
+ slot at 1 {
+ reg = <1>;
+ bus-width = <4>;
+ cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ ssc0: ssc at fff9c000 {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_ssc0_tx>;
+ };
+
+ spi0: spi at fffa4000 {
+ cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
+ mtd_dataflash at 0 {
+ compatible = "atmel,at45", "atmel,dataflash";
+ spi-max-frequency = <50000000>;
+ reg = <1>;
+ };
+ };
+
+ shdwc at fffffd10 {
+ atmel,wakeup-counter = <10>;
+ atmel,wakeup-rtt-timer;
+ };
+
+ rtc at fffffd20 {
+ atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+ status = "okay";
+ };
+
+ watchdog at fffffd40 {
+ status = "okay";
+ };
+
+ gpbr: syscon at fffffd60 {
+ status = "okay";
+ };
+ };
+
+ nand0: nand at 40000000 {
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hardware";
+ nand-on-flash-bbt;
+ status = "okay";
+ };
+
+ usb1: ehci at 00800000 {
+ atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+ };
+
+};
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 9ce775e..d092d29 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -23,6 +23,14 @@ config TARGET_SNAPPER9260
select DM_SERIAL
select DM_GPIO
+config TARGET_GURNARD
+ bool "Support gurnard"
+ select CPU_ARM926EJS
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+ select DM_ETH
+
config TARGET_AT91SAM9261EK
bool "Atmel at91sam9261 reference board"
select CPU_ARM926EJS
@@ -143,6 +151,7 @@ source "board/atmel/sama5d3_xplained/Kconfig"
source "board/atmel/sama5d3xek/Kconfig"
source "board/atmel/sama5d4_xplained/Kconfig"
source "board/atmel/sama5d4ek/Kconfig"
+source "board/bluewater/gurnard/Kconfig"
source "board/bluewater/snapper9260/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/denx/ma5d4evk/Kconfig"
diff --git a/board/bluewater/gurnard/Kconfig b/board/bluewater/gurnard/Kconfig
new file mode 100644
index 0000000..e2cd9f0
--- /dev/null
+++ b/board/bluewater/gurnard/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_GURNARD
+
+config SYS_BOARD
+ default "gurnard"
+
+config SYS_VENDOR
+ default "bluewater"
+
+config SYS_CONFIG_NAME
+ default "snapper9g45"
+
+endif
diff --git a/board/bluewater/gurnard/MAINTAINERS b/board/bluewater/gurnard/MAINTAINERS
new file mode 100644
index 0000000..5e546d4
--- /dev/null
+++ b/board/bluewater/gurnard/MAINTAINERS
@@ -0,0 +1,6 @@
+GURNARD BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/bluewater/gurnard/
+F: include/configs/snapper9g45.h
+F: configs/gurnard_defconfig
diff --git a/board/bluewater/gurnard/Makefile b/board/bluewater/gurnard/Makefile
new file mode 100644
index 0000000..f646d35
--- /dev/null
+++ b/board/bluewater/gurnard/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2011 Bluewater Systems
+# Ryan Mallon <ryan@bluewatersys.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += gurnard.o
diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c
new file mode 100644
index 0000000..2a36d29
--- /dev/null
+++ b/board/bluewater/gurnard/gurnard.c
@@ -0,0 +1,449 @@
+/*
+ * Bluewater Systems Snapper 9260/9G20 modules
+ *
+ * (C) Copyright 2011 Bluewater Systems
+ * Author: Andre Renaud <andre@bluewatersys.com>
+ * Author: Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <atmel_lcd.h>
+#include <atmel_lcdc.h>
+#include <atmel_mci.h>
+#include <dm.h>
+#include <lcd.h>
+#include <net.h>
+#ifndef CONFIG_DM_ETH
+#include <netdev.h>
+#endif
+#include <spi.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9g45_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_emac.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_rtc.h>
+#include <asm/arch/at91_sck.h>
+#include <asm/arch/atmel_serial.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <dm/uclass-internal.h>
+
+#ifdef CONFIG_GURNARD_SPLASH
+#include "splash_logo.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* IO Expander pins */
+#define IO_EXP_ETH_RESET (0 << 1)
+#define IO_EXP_ETH_POWER (1 << 1)
+
+#ifdef CONFIG_MACB
+static void gurnard_macb_hw_init(void)
+{
+ struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+
+ at91_periph_clk_enable(ATMEL_ID_EMAC);
+
+ /*
+ * Enable pull-up on:
+ * RXDV (PA12) => MODE0 - PHY also has pull-up
+ * ERX0 (PA13) => MODE1 - PHY also has pull-up
+ * ERX1 (PA15) => MODE2 - PHY also has pull-up
+ */
+ writel(pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA12) |
+ pin_to_mask(AT91_PIN_PA13),
+ &pioa->puer);
+
+ at91_phy_reset();
+
+ at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_CMD_NAND
+static int gurnard_nand_hw_init(void)
+{
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ ulong flags;
+ int ret;
+
+ /* Enable CS3 as NAND/SmartMedia */
+ setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
+ AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+ &smc->cs[3].cycle);
+#ifdef CONFIG_SYS_NAND_DBW_16
+ flags = AT91_SMC_MODE_DBW_16;
+#else
+ flags = AT91_SMC_MODE_DBW_8;
+#endif
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ flags |
+ AT91_SMC_MODE_TDF_CYCLE(3),
+ &smc->cs[3].mode);
+
+ ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
+ if (ret)
+ return ret;
+ gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+ /* Enable NandFlash */
+ ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
+ if (ret)
+ return ret;
+ gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_GURNARD_SPLASH
+static void lcd_splash(int width, int height)
+{
+ u16 colour;
+ int x, y;
+ u16 *base_addr = (u16 *)gd->video_bottom;
+
+ memset(base_addr, 0xff, width * height * 2);
+ /*
+ * Blit the logo to the center of the screen
+ */
+ for (y = 0; y < BMP_LOGO_HEIGHT; y++) {
+ for (x = 0; x < BMP_LOGO_WIDTH; x++) {
+ int posx, posy;
+ colour = bmp_logo_palette[bmp_logo_bitmap[
+ y * BMP_LOGO_WIDTH + x]];
+ posx = x + (width - BMP_LOGO_WIDTH) / 2;
+ posy = y;
+ base_addr[posy * width + posx] = colour;
+ }
+ }
+}
+#endif
+
+#ifdef CONFIG_DM_VIDEO
+static void at91sam9g45_lcd_hw_init(void)
+{
+ at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
+ at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
+ at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
+ at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
+ at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
+
+ at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
+ at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
+ at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
+ at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
+ at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
+ at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
+ at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
+ at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
+ at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
+ at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
+ at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
+ at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
+ at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
+ at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
+ at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
+ at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
+ at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
+ at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
+ at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
+ at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
+ at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
+ at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
+ at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
+ at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
+
+ at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+#endif
+
+#ifdef CONFIG_GURNARD_FPGA
+/**
+ * Initialise the memory bus settings so that we can talk to the
+ * memory mapped FPGA
+ */
+static int fpga_hw_init(void)
+{
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ int i;
+
+ setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS1A_SDRAMC);
+
+ at91_set_a_periph(2, 4, 0); /* EBIA21 */
+ at91_set_a_periph(2, 5, 0); /* EBIA22 */
+ at91_set_a_periph(2, 6, 0); /* EBIA23 */
+ at91_set_a_periph(2, 7, 0); /* EBIA24 */
+ at91_set_a_periph(2, 12, 0); /* EBIA25 */
+ for (i = 15; i <= 31; i++) /* EBINWAIT & EBID16 - 31 */
+ at91_set_a_periph(2, i, 0);
+
+ /* configure SMC cs0 for FPGA access timing */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(2) |
+ AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(2),
+ &smc->cs[0].setup);
+ writel(AT91_SMC_PULSE_NWE(5) | AT91_SMC_PULSE_NCS_WR(4) |
+ AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(4),
+ &smc->cs[0].pulse);
+ writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
+ &smc->cs[0].cycle);
+ writel(AT91_SMC_MODE_BAT |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_32 |
+ AT91_SMC_MODE_TDF |
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[0].mode);
+
+ /* Do a write to within EBI_CS1 to enable the SDCK */
+ writel(0, ATMEL_BASE_CS1);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+
+#define USB0_ENABLE_PIN AT91_PIN_PB22
+#define USB1_ENABLE_PIN AT91_PIN_PB23
+
+void gurnard_usb_init(void)
+{
+ at91_set_gpio_output(USB0_ENABLE_PIN, 1);
+ at91_set_gpio_value(USB0_ENABLE_PIN, 0);
+ at91_set_gpio_output(USB1_ENABLE_PIN, 1);
+ at91_set_gpio_value(USB1_ENABLE_PIN, 0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int cpu_mmc_init(bd_t *bis)
+{
+ return atmel_mci_init((void *)ATMEL_BASE_MCI0);
+}
+#endif
+
+static void gurnard_enable_console(int enable)
+{
+ at91_set_gpio_output(AT91_PIN_PB14, 1);
+ at91_set_gpio_value(AT91_PIN_PB14, enable ? 0 : 1);
+}
+
+void at91sam9g45_slowclock_init(void)
+{
+ /*
+ * On AT91SAM9G45 revC CPUs, the slow clock can be based on an
+ * internal impreciseRC oscillator or an external 32kHz oscillator.
+ * Switch to the latter.
+ */
+ unsigned i, tmp;
+ ulong *reg = (ulong *)ATMEL_BASE_SCKCR;
+
+ tmp = readl(reg);
+ if ((tmp & AT91SAM9G45_SCKCR_OSCSEL) == AT91SAM9G45_SCKCR_OSCSEL_RC) {
+ timer_init();
+ tmp |= AT91SAM9G45_SCKCR_OSC32EN;
+ writel(tmp, reg);
+ for (i = 0; i < 1200; i++)
+ udelay(1000);
+ tmp |= AT91SAM9G45_SCKCR_OSCSEL_32;
+ writel(tmp, reg);
+ udelay(200);
+ tmp &= ~AT91SAM9G45_SCKCR_RCEN;
+ writel(tmp, reg);
+ }
+}
+
+int board_early_init_f(void)
+{
+ at91_seriald_hw_init();
+ gurnard_enable_console(1);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ const char *rev_str;
+#ifdef CONFIG_CMD_NAND
+ int ret;
+#endif
+
+ at91_periph_clk_enable(ATMEL_ID_PIOA);
+ at91_periph_clk_enable(ATMEL_ID_PIOB);
+ at91_periph_clk_enable(ATMEL_ID_PIOC);
+ at91_periph_clk_enable(ATMEL_ID_PIODE);
+
+ at91sam9g45_slowclock_init();
+
+ /*
+ * Clear the RTC IDR to disable all IRQs. Avoid issues when Linux
+ * boots with spurious IRQs.
+ */
+ writel(0xffffffff, AT91_RTC_IDR);
+
+ /* Make sure that the reset signal is attached properly */
+ setbits_le32(AT91_ASM_RSTC_MR, AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN);
+
+ gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+ ret = gurnard_nand_hw_init();
+ if (ret)
+ return ret;
+#endif
+#ifdef CONFIG_ATMEL_SPI
+ at91_spi0_hw_init(1 << 4);
+#endif
+
+#ifdef CONFIG_MACB
+ gurnard_macb_hw_init();
+#endif
+
+#ifdef CONFIG_GURNARD_FPGA
+ fpga_hw_init();
+#endif
+
+#ifdef CONFIG_CMD_USB
+ gurnard_usb_init();
+#endif
+
+#ifdef CONFIG_CMD_MMC
+ at91_set_A_periph(AT91_PIN_PA12, 0);
+ at91_set_gpio_output(AT91_PIN_PA8, 1);
+ at91_set_gpio_value(AT91_PIN_PA8, 0);
+ at91_mci_hw_init();
+#endif
+
+#ifdef CONFIG_DM_VIDEO
+ at91sam9g45_lcd_hw_init();
+ at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
+
+ /* Select the second timing index for board rev 2 */
+ rev_str = getenv("board_rev");
+ if (rev_str && !strncmp(rev_str, "2", 1)) {
+ struct udevice *dev;
+
+ uclass_find_first_device(UCLASS_VIDEO, &dev);
+ if (dev) {
+ struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
+
+ plat->timing_index = 1;
+ }
+ }
+#endif
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ u_int8_t env_enetaddr[8];
+ char *env_str;
+ char *end;
+ int i;
+
+ /*
+ * Set MAC address so we do not need to init Ethernet before Linux
+ * boot
+ */
+ env_str = getenv("ethaddr");
+ if (env_str) {
+ struct at91_emac *emac = (struct at91_emac *)ATMEL_BASE_EMAC;
+ /* Parse MAC address */
+ for (i = 0; i < 6; i++) {
+ env_enetaddr[i] = env_str ?
+ simple_strtoul(env_str, &end, 16) : 0;
+ if (env_str)
+ env_str = (*end) ? end+1 : end;
+ }
+
+ /* Set hardware address */
+ writel(env_enetaddr[0] | env_enetaddr[1] << 8 |
+ env_enetaddr[2] << 16 | env_enetaddr[3] << 24,
+ &emac->sa2l);
+ writel((env_enetaddr[4] | env_enetaddr[5] << 8), &emac->sa2h);
+
+ printf("MAC: %s\n", getenv("ethaddr"));
+ } else {
+ /* Not set in environment */
+ printf("MAC: not set\n");
+ }
+#ifdef CONFIG_GURNARD_SPLASH
+ lcd_splash(480, 272);
+#endif
+
+ return 0;
+}
+
+#ifndef CONFIG_DM_ETH
+int board_eth_init(bd_t *bis)
+{
+ return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0);
+}
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+void reset_phy(void)
+{
+}
+
+/* This breaks the Ethernet MAC at present */
+void enable_caches(void)
+{
+ dcache_enable();
+}
+
+/* SPI chip select control - only used for FPGA programming */
+#ifdef CONFIG_ATMEL_SPI
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* We don't use chipselects for FPGA programming */
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* We don't use chipselects for FPGA programming */
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+static struct atmel_serial_platdata at91sam9260_serial_plat = {
+ .base_addr = ATMEL_BASE_DBGU,
+};
+
+U_BOOT_DEVICE(at91sam9260_serial) = {
+ .name = "serial_atmel",
+ .platdata = &at91sam9260_serial_plat,
+};
diff --git a/board/bluewater/gurnard/splash_logo.h b/board/bluewater/gurnard/splash_logo.h
new file mode 100644
index 0000000..fb87dea
--- /dev/null
+++ b/board/bluewater/gurnard/splash_logo.h
@@ -0,0 +1,2619 @@
+/* generated by ppm_logo (c) 2004 by Andre Renaud from logo_gurnard_small.ppm*/
+#ifndef __BMP_LOGO_H__
+#define __BMP_LOGO_H__
+#define BMP_LOGO_WIDTH 187
+#define BMP_LOGO_HEIGHT 139
+#define BMP_LOGO_COLORS 255
+#define BMP_LOGO_OFFSET 50
+
+unsigned short bmp_logo_palette[] = {
+ 0xb61a, 0x9d78, 0xdefc, 0xffff, 0x7455, 0x32b1, 0xb5fa, 0xe75e,
+ 0xffdf, 0xc65b, 0x9538, 0xd6dc, 0xce9b, 0xf7df, 0xadb9, 0x84d7,
+ 0xffff, 0xffff, 0xffdf, 0x5bb4, 0x4b11, 0x3ad1, 0xf7bf, 0xf7bf,
+ 0xffff, 0xffff, 0xf79e, 0xef9e, 0x6c35, 0xef7e, 0xe75d, 0xdf1d,
+ 0xdf1c, 0xf7df, 0xde9a, 0xed96, 0xe6fb, 0xdb4d, 0xc945, 0xe410,
+ 0xffdf, 0xc965, 0xc986, 0xd2aa, 0xe451, 0xed14, 0xef5d, 0xffbe,
+ 0xffff, 0xef3c, };
+
+unsigned char bmp_logo_bitmap[] = {
+ 0x0000, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001,
+ 0x0001, 0x0001, 0x0001, 0x0002, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0004, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0006, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0004, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0006, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0004, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0006, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0004, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0001, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+ 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+ 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+ 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+ 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+ 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+ 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+ 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+ 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+ 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+ 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+ 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+ 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+ 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+ 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+ 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+ 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
+ 0x0008, 0x0003, 0x0003, 0x0003, 0x0003, 0x0004, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0009, 0x0003, 0x0003,
+ 0x0003, 0x0003, 0x0004, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0009, 0x0003, 0x0003, 0x0003, 0x0003, 0x0004,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0009, 0x0003, 0x0003, 0x0003, 0x0003, 0x0004, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0009, 0x0003,
+ 0x0003, 0x0003, 0x0003, 0x0004, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x000a, 0x000b, 0x000b, 0x000b,
+ 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b,
+ 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b,
+ 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b,
+ 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b,
+ 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b,
+ 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b,
+ 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b,
+ 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b,
+ 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b,
+ 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b,
+ 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b, 0x000b,
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+ 0x000e, 0x000e, 0x0009, };
+#endif
diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig
new file mode 100644
index 0000000..ab907ba
--- /dev/null
+++ b/configs/gurnard_defconfig
@@ -0,0 +1,19 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_GURNARD=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM_VIDEO=y
+CONFIG_CMD_DHRYSTONE=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
new file mode 100644
index 0000000..2d6f89d
--- /dev/null
+++ b/include/configs/snapper9g45.h
@@ -0,0 +1,156 @@
+/*
+ * Bluewater Systems Snapper 9G45 module
+ *
+ * (C) Copyright 2011 Bluewater Systems
+ * Author: Andre Renaud <andre@bluewatersys.com>
+ * Author: Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* SoC type is defined in boards.cfg */
+#include <asm/hardware.h>
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_TEXT_BASE 0x73f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
+
+/* CPU */
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
+#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */
+#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM + 0x1000 - \
+ GENERATED_GBL_DATA_SIZE)
+
+/* Mem test settings */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024))
+
+/* NAND Flash */
+#define CONFIG_NAND_ATMEL
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
+#define CONFIG_TFTP_PORT
+#define CONFIG_TFTP_TSIZE
+
+/* USB */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_USB_STORAGE
+#define CONFIG_PARTITION_UUIDS
+
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+
+/* LCD */
+#define CONFIG_ATMEL_LCD
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_GURNARD_SPLASH
+
+#define CONFIG_ATMEL_SPI
+
+/* GPIOs and IO expander */
+#define CONFIG_ATMEL_LEGACY
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP 1
+
+/* UARTs/Serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_BAUDRATE 115200
+
+/* Boot options */
+#define CONFIG_SYS_LOAD_ADDR 0x23000000
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Environment settings */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (512 << 10)
+#define CONFIG_ENV_SIZE (256 << 10)
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "ethaddr=00:00:00:00:00:00\0" \
+ "serial=0\0" \
+ "stdout=serial_atmel\0" \
+ "stderr=serial_atmel\0" \
+ "stdin=serial_atmel\0" \
+ "bootlimit=3\0" \
+ "loadaddr=0x71000000\0" \
+ "board_rev=2\0" \
+ "bootfile=/tftpboot/uImage\0" \
+ "bootargs_def=console=ttyS0,115200 panic=5 quiet lpj=997376\0" \
+ "nfsroot=/export/root\0" \
+ "boot_working=setenv bootargs $bootargs_def; nboot $loadaddr 0 0x20c0000 && bootm\0" \
+ "boot_safe=setenv bootargs $bootargs_def; nboot $loadaddr 0 0xc0000 && bootm\0" \
+ "boot_tftp=setenv bootargs $bootargs_def ip=any nfsroot=$nfsroot; setenv autoload y && bootp && bootm\0" \
+ "boot_usb=setenv bootargs $bootargs_def; usb start && usb storage && fatload usb 0:1 $loadaddr dds-xm200.bin && bootm\0" \
+ "boot_mmc=setenv bootargs $bootargs_def; mmc rescan && fatload mmc 0:1 $loadaddr dds-xm200.bin && bootm\0" \
+ "bootcmd=run boot_mmc ; run boot_usb ; run boot_working ; run boot_safe\0" \
+ "altbootcmd=run boot_mmc ; run boot_usb ; run boot_safe ; run boot_working\0"
+
+/* Console settings */
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/* U-Boot memory settings */
+#define CONFIG_SYS_MALLOC_LEN (1 << 20)
+
+/* Command line configuration */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_PART
+
+#endif /* __CONFIG_H */
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 02/18] arm: Allow skipping of low-level init with I-cache on
2016-05-05 13:28 ` [U-Boot] [PATCH v2 02/18] arm: Allow skipping of low-level init with I-cache on Simon Glass
@ 2016-05-05 14:07 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-05-05 14:07 UTC (permalink / raw)
To: u-boot
Hi Simon,
On 05.05.16 15:28, Simon Glass wrote:
> At present CONFIG_SKIP_LOWLEVEL_INIT prevents U-Boot from calling
> lowlevel_init(). This means that the instruction cache is not enabled and
> the board runs very slowly.
>
> What is really needed in many cases is to skip the call to lowlevel_init()
> but still perform CP15 init. Add an option to handle this.
>
> Reviewed-by: Heiko Schocher <hs@denx.de>
> Tested-on: smartweb, corvus, taurus, axm
> Tested-by: Heiko Schocher <hs@denx.de>
> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
> README | 5 +++++
> arch/arm/cpu/arm1136/start.S | 2 ++
> arch/arm/cpu/arm920t/start.S | 3 ++-
> arch/arm/cpu/arm926ejs/start.S | 2 ++
> arch/arm/cpu/arm946es/start.S | 2 ++
> arch/arm/cpu/armv7/start.S | 5 ++++-
> arch/arm/cpu/sa1100/start.S | 2 ++
> 7 files changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/README b/README
> index 88ff837..9ab07b5 100644
> --- a/README
> +++ b/README
> @@ -4829,6 +4829,11 @@ Low Level (hardware related) configuration options:
> other boot loader or by a debugger which performs
> these initializations itself.
>
> +- CONFIG_SKIP_LOWLEVEL_INIT_ONLY
> + [ARM926EJ-S only] This allows just the call to lowlevel_init()
> + to be skipped. The normal CPU15 init (such as enabling the
CPU15 -> CP15
> + instruction cache) is still performed.
> +
> - CONFIG_SPL_BUILD
> Modifies the behaviour of start.S when compiling a loader
> that is executed before the actual U-Boot. E.g. when
> diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
> index 3ebdfdd..2f8fd6a 100644
> --- a/arch/arm/cpu/arm1136/start.S
> +++ b/arch/arm/cpu/arm1136/start.S
> @@ -82,6 +82,7 @@ cpu_init_crit:
> orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
> mcr p15, 0, r0, c1, c0, 0
>
> +#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
> /*
> * Jump to board specific initialization... The Mask ROM will have already initialized
> * basic memory. Go here to bump up clock rate and handle wake up conditions.
> @@ -89,5 +90,6 @@ cpu_init_crit:
> mov ip, lr /* persevere link reg across call */
> bl lowlevel_init /* go setup pll,mux,memory */
> mov lr, ip /* restore link */
> +#endif
> mov pc, lr /* back to my caller */
> #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
> diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
> index 69cabeb..3ada6d0 100644
> --- a/arch/arm/cpu/arm920t/start.S
> +++ b/arch/arm/cpu/arm920t/start.S
> @@ -135,6 +135,7 @@ cpu_init_crit:
> orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
> mcr p15, 0, r0, c1, c0, 0
>
> +#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
> /*
> * before relocating, we have to setup RAM timing
> * because memory timing is board-dependend, you will
> @@ -143,7 +144,7 @@ cpu_init_crit:
> mov ip, lr
>
> bl lowlevel_init
> -
> mov lr, ip
> +#endif
> mov pc, lr
> #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
> diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
> index f05113d..959d1ed 100644
> --- a/arch/arm/cpu/arm926ejs/start.S
> +++ b/arch/arm/cpu/arm926ejs/start.S
> @@ -101,11 +101,13 @@ flush_dcache:
> #endif
> mcr p15, 0, r0, c1, c0, 0
>
> +#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
> /*
> * Go setup Memory and board specific bits prior to relocation.
> */
> mov ip, lr /* perserve link reg across call */
> bl lowlevel_init /* go setup pll,mux,memory */
> mov lr, ip /* restore link */
> +#endif
> mov pc, lr /* back to my caller */
> #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
> diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S
> index 214cd8c..51053c3 100644
> --- a/arch/arm/cpu/arm946es/start.S
> +++ b/arch/arm/cpu/arm946es/start.S
> @@ -90,11 +90,13 @@ cpu_init_crit:
> orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
> mcr p15, 0, r0, c1, c0, 0
>
> +#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
> /*
> * Go setup Memory and board specific bits prior to relocation.
> */
> mov ip, lr /* perserve link reg across call */
> bl lowlevel_init /* go setup memory */
> mov lr, ip /* restore link */
> +#endif
> mov pc, lr /* back to my caller */
> #endif
> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
> index b180944..691e5d3 100644
> --- a/arch/arm/cpu/armv7/start.S
> +++ b/arch/arm/cpu/armv7/start.S
> @@ -66,8 +66,10 @@ save_boot_params_ret:
> /* the mask ROM code should have PLL and others stable */
> #ifndef CONFIG_SKIP_LOWLEVEL_INIT
> bl cpu_init_cp15
> +#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
> bl cpu_init_crit
> #endif
> +#endif
>
> bl _main
>
> @@ -250,7 +252,8 @@ skip_errata_621766:
> mov pc, r5 @ back to my caller
> ENDPROC(cpu_init_cp15)
>
> -#ifndef CONFIG_SKIP_LOWLEVEL_INIT
> +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
> + !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
> /*************************************************************************
> *
> * CPU_init_critical registers
> diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
> index 408b70d..f5318c9 100644
> --- a/arch/arm/cpu/sa1100/start.S
> +++ b/arch/arm/cpu/sa1100/start.S
> @@ -96,6 +96,7 @@ cpu_init_crit:
> ldr r1, cpuspeed
> str r1, [r0, #PPCR]
>
> +#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
> /*
> * before relocating, we have to setup RAM timing
> * because memory timing is board-dependend, you will
> @@ -104,6 +105,7 @@ cpu_init_crit:
> mov ip, lr
> bl lowlevel_init
> mov lr, ip
> +#endif
>
> /*
> * disable MMU stuff and enable I-cache
>
Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 03/18] bootm: Align cache flush end address correctly
2016-05-05 13:28 ` [U-Boot] [PATCH v2 03/18] bootm: Align cache flush end address correctly Simon Glass
@ 2016-05-05 14:19 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-05-05 14:19 UTC (permalink / raw)
To: u-boot
On 05.05.16 15:28, Simon Glass wrote:
> Flushing part of the cache should be done on cache boundaries. Trying to
> flush part of a cache line is not supported and the request may be ignored
> or print warnings.
>
> Adjust the bootm code to align the end address to prevent this problem.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Heiko Schocher <hs@denx.de>
> Tested-on: smartweb, corvus, taurus, axm
> Tested-by: Heiko Schocher <hs@denx.de>
> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
> ---
>
> Changes in v2: None
>
> common/bootm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/common/bootm.c b/common/bootm.c
> index c965326..7469c61 100644
> --- a/common/bootm.c
> +++ b/common/bootm.c
> @@ -435,7 +435,7 @@ static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end,
> bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
> return err;
> }
> - flush_cache(load, *load_end - load);
> + flush_cache(load, ALIGN(*load_end - load, ARCH_DMA_MINALIGN));
>
> debug(" kernel loaded at 0x%08lx, end = 0x%08lx\n", load, *load_end);
> bootstage_mark(BOOTSTAGE_ID_KERNEL_LOADED);
>
Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 05/18] net: macb: Prepare for driver-model conversion
2016-05-05 13:28 ` [U-Boot] [PATCH v2 05/18] net: macb: Prepare for driver-model conversion Simon Glass
@ 2016-05-05 18:31 ` Joe Hershberger
2016-05-28 22:32 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2 siblings, 0 replies; 56+ messages in thread
From: Joe Hershberger @ 2016-05-05 18:31 UTC (permalink / raw)
To: u-boot
On Thu, May 5, 2016 at 8:28 AM, Simon Glass <sjg@chromium.org> wrote:
> Adjust this driver to avoid using struct netdev in functions that driver
> model will call. Also refactor the receive function to be compatible with
> driver model.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Heiko Schocher <hs@denx.de>
> Tested-on: smartweb, corvus, taurus, axm
> Tested-by: Heiko Schocher <hs@denx.de>
> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Pretty sure I acked this last time...
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 06/18] net: macb: Flush correct cache portion when sending
2016-05-05 13:28 ` [U-Boot] [PATCH v2 06/18] net: macb: Flush correct cache portion when sending Simon Glass
@ 2016-05-28 12:35 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-05-28 12:35 UTC (permalink / raw)
To: u-boot
On 05.05.16 15:28, Simon Glass wrote:
> The end address of the cache flush must be cache-line-aligned since
> otherwise (at least on ARM926-EJS) the request is ignored. When the cache
> is enabled this means that packets are not sent.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Heiko Schocher <hs@denx.de>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
> ---
>
> Changes in v2: None
>
> drivers/net/macb.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> index f0af40c..ecdfc1b 100644
> --- a/drivers/net/macb.c
> +++ b/drivers/net/macb.c
> @@ -280,7 +280,7 @@ static int _macb_send(struct macb_device *macb, const char *name, void *packet,
> barrier();
> macb_flush_ring_desc(macb, TX);
> /* Do we need check paddr and length is dcache line aligned? */
> - flush_dcache_range(paddr, paddr + length);
> + flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
> macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
>
> /*
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 09/18] arm: at91: Add a header file for the real-time clock
2016-05-05 13:28 ` [U-Boot] [PATCH v2 09/18] arm: at91: Add a header file for the real-time clock Simon Glass
@ 2016-05-28 12:49 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-05-28 12:49 UTC (permalink / raw)
To: u-boot
On 05.05.16 15:28, Simon Glass wrote:
> From: Andre Renaud <andre@designa-electronics.com>
>
> Add register definitions for the AT91 RTC so that this can potentially be
> used in U-Boot.
>
> Signed-off-by: Andre Renaud <andre@designa-electronics.com>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 12/18] mtd: nand: Drop a blank line in nand_wait()
2016-05-05 13:28 ` [U-Boot] [PATCH v2 12/18] mtd: nand: Drop a blank line in nand_wait() Simon Glass
@ 2016-05-28 12:53 ` Andreas Bießmann
0 siblings, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-05-28 12:53 UTC (permalink / raw)
To: u-boot
On 05.05.16 15:28, Simon Glass wrote:
> From: Andre Renaud <andre@designa-electronics.com>
>
> This empty line should not be there. Remove it.
>
> Signed-off-by: Andre Renaud <andre@designa-electronics.com>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 10/18] at91: Correct NAND ECC register access
2016-05-05 13:28 ` [U-Boot] [PATCH v2 10/18] at91: Correct NAND ECC register access Simon Glass
@ 2016-05-28 21:06 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-05-28 21:06 UTC (permalink / raw)
To: u-boot
On 05.05.16 15:28, Simon Glass wrote:
> From: Andre Renaud <andre@designa-electronics.com>
>
> This uses the wrote base register value. Fix it.
>
> Signed-off-by: Andre Renaud <andre@designa-electronics.com>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 11/18] at91: nand: Set up the ECC strength correctly
2016-05-05 13:28 ` [U-Boot] [PATCH v2 11/18] at91: nand: Set up the ECC strength correctly Simon Glass
@ 2016-05-28 21:12 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-05-28 21:12 UTC (permalink / raw)
To: u-boot
On 05.05.16 15:28, Simon Glass wrote:
> From: Andre Renaud <andre@designa-electronics.com>
>
> This needs to be set to avoid a fatal error when ECC is used.
>
> Signed-off-by: Andre Renaud <andre@designa-electronics.com>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 05/18] net: macb: Prepare for driver-model conversion
2016-05-05 13:28 ` [U-Boot] [PATCH v2 05/18] net: macb: Prepare for driver-model conversion Simon Glass
2016-05-05 18:31 ` Joe Hershberger
@ 2016-05-28 22:32 ` Andreas Bießmann
2016-06-20 1:30 ` Simon Glass
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2 siblings, 1 reply; 56+ messages in thread
From: Andreas Bießmann @ 2016-05-28 22:32 UTC (permalink / raw)
To: u-boot
Hi Simon,
On 05.05.16 15:28, Simon Glass wrote:
> Adjust this driver to avoid using struct netdev in functions that driver
> model will call. Also refactor the receive function to be compatible with
> driver model.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Heiko Schocher <hs@denx.de>
> Tested-on: smartweb, corvus, taurus, axm
> Tested-by: Heiko Schocher <hs@denx.de>
> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
> ---
>
> Changes in v2: None
>
> drivers/net/macb.c | 199 +++++++++++++++++++++++++++++++++--------------------
> 1 file changed, 124 insertions(+), 75 deletions(-)
<snip>
> -static int macb_phy_init(struct macb_device *macb)
> +static int macb_phy_init(struct macb_device *macb, const char *name)
> {
> - struct eth_device *netdev = &macb->netdev;
> #ifdef CONFIG_PHYLIB
> struct phy_device *phydev;
> #endif
> @@ -452,7 +450,7 @@ static int macb_phy_init(struct macb_device *macb)
> int media, speed, duplex;
> int i;
>
> - arch_get_mdio_control(netdev->name);
> + arch_get_mdio_control(name);
> #ifdef CONFIG_MACB_SEARCH_PHY
> /* Auto-detect phy_addr */
> if (!macb_phy_find(macb))
> @@ -462,13 +460,13 @@ static int macb_phy_init(struct macb_device *macb)
> /* Check if the PHY is up to snuff... */
> phy_id = macb_mdio_read(macb, MII_PHYSID1);
> if (phy_id == 0xffff) {
> - printf("%s: No PHY present\n", netdev->name);
> + printf("%s: No PHY present\n", name);
> return 0;
> }
>
> #ifdef CONFIG_PHYLIB
> /* need to consider other phy interface mode */
> - phydev = phy_connect(macb->bus, macb->phy_addr, netdev,
> + phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
is this intentional? You removed every reference to netdev but retained
this one.
Well, it's clear to me that you have to provide an eth_device to
phy_connect() but why change the function then and add the *name to
function parameters?
> PHY_INTERFACE_MODE_RGMII);
> if (!phydev) {
> printf("phy_connect failed\n");
No more questions ...
Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 07/18] net: macb: Convert to driver model
2016-05-05 13:28 ` [U-Boot] [PATCH v2 07/18] net: macb: Convert to driver model Simon Glass
@ 2016-05-28 22:43 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot,v2,07/18] " Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-05-28 22:43 UTC (permalink / raw)
To: u-boot
On 05.05.16 15:28, Simon Glass wrote:
> Add driver-model support to this driver. The old code remains for now so
> that we can convert boards one at a time.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Heiko Schocher <hs@denx.de>
> Tested-on: smartweb, corvus, taurus, axm
> Tested-by: Heiko Schocher <hs@denx.de>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 08/18] arm: at91: dts: Bring in device tree file for AT91SAM9G45
2016-05-05 13:28 ` [U-Boot] [PATCH v2 08/18] arm: at91: dts: Bring in device tree file for AT91SAM9G45 Simon Glass
@ 2016-05-28 22:45 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-05-28 22:45 UTC (permalink / raw)
To: u-boot
On 05.05.16 15:28, Simon Glass wrote:
> Add this file from Linux v4.5.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Heiko Schocher <hs@denx.de>
> Tested-on: smartweb, corvus, taurus, axm
> Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 13/18] at91: Add driver-model GPIO devices for AT91SAM9G45
2016-05-05 13:28 ` [U-Boot] [PATCH v2 13/18] at91: Add driver-model GPIO devices for AT91SAM9G45 Simon Glass
@ 2016-05-28 22:46 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-05-28 22:46 UTC (permalink / raw)
To: u-boot
On 05.05.16 15:28, Simon Glass wrote:
> Add these definitions so that GPIOs can be used with driver model.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Heiko Schocher <hs@denx.de>
> Tested-on: smartweb, corvus, taurus, axm
> Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 14/18] at91: mtd: nand: Add dev_warn() to correct build error in driver
2016-05-05 13:28 ` [U-Boot] [PATCH v2 14/18] at91: mtd: nand: Add dev_warn() to correct build error in driver Simon Glass
@ 2016-05-28 23:04 ` Andreas Bießmann
2016-06-04 20:27 ` [U-Boot] [PATCH] linux/compat.h: add dev_warn() Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-05-28 23:04 UTC (permalink / raw)
To: u-boot
Hi Simon,
On 05.05.16 15:28, Simon Glass wrote:
> The code does not compile if ECC is enabled.
>
> Signed-off-by: Andre Renaud <arenaud@bluewatersys.com>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
> drivers/mtd/nand/atmel_nand.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
> index 8fac824..15958cb 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -20,6 +20,8 @@
> #include <watchdog.h>
> #include <linux/mtd/nand_ecc.h>
>
> +#define dev_warn(dev, msg...)
> +
This change is good in general, but I think the better fix is to use
dev_err() for the uncorrectable error and dev_dbg() for the rest.
Andreas
> #ifdef CONFIG_ATMEL_NAND_HWECC
>
> /* Register access macros */
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 15/18] at91: video: Prepare for driver-model conversion
2016-05-05 13:28 ` [U-Boot] [PATCH v2 15/18] at91: video: Prepare for driver-model conversion Simon Glass
@ 2016-06-04 20:08 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-04 20:08 UTC (permalink / raw)
To: u-boot
On 05.05.16 15:28, Simon Glass wrote:
> Adjust the driver to use struct display_timing for its display timing.
> This is what is used by driver-model and allows the LCD init code to be
> common.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
> ---
>
> Changes in v2: None
>
> drivers/video/atmel_lcdfb.c | 106 +++++++++++++++++++++++++++++---------------
> 1 file changed, 70 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
> index d43d8a5..37838a8 100644
> --- a/drivers/video/atmel_lcdfb.c
> +++ b/drivers/video/atmel_lcdfb.c
> @@ -7,6 +7,7 @@
> */
>
> #include <common.h>
> +#include <fdtdec.h>
> #include <asm/io.h>
> #include <asm/arch/gpio.h>
> #include <asm/arch/clk.h>
> @@ -91,39 +92,41 @@ void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
> }
> }
>
> -void lcd_ctrl_init(void *lcdbase)
> +static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
> + bool tft, bool cont_pol_low, ulong lcdbase)
> {
> unsigned long value;
> + void *reg = (void *)addr;
>
> /* Turn off the LCD controller and the DMA controller */
> - lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
> + lcdc_writel(reg, ATMEL_LCDC_PWRCON,
> ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
>
> /* Wait for the LCDC core to become idle */
> - while (lcdc_readl(panel_info.mmio, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
> + while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
> udelay(10);
>
> - lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, 0);
> + lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);
>
> /* Reset LCDC DMA */
> - lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
> + lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
>
> /* ...set frame size and burst length = 8 words (?) */
> - value = (panel_info.vl_col * panel_info.vl_row *
> - NBITS(panel_info.vl_bpix)) / 32;
> + value = (timing->hactive.typ * timing->vactive.typ *
> + (1 << bpix)) / 32;
> value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
> - lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMAFRMCFG, value);
> + lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);
>
> /* Set pixel clock */
> - value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
> - if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
> + value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
> + if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
> value++;
> value = (value / 2) - 1;
>
> if (!value) {
> - lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
> + lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
> } else
> - lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1,
> + lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
> value << ATMEL_LCDC_CLKVAL_OFFSET);
>
> /* Initialize control register 2 */
> @@ -132,56 +135,87 @@ void lcd_ctrl_init(void *lcdbase)
> #else
> value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
> #endif
> - if (panel_info.vl_tft)
> + if (tft)
> value |= ATMEL_LCDC_DISTYPE_TFT;
>
> - value |= panel_info.vl_sync;
> - value |= (panel_info.vl_bpix << 5);
> - lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value);
> + if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
> + value |= ATMEL_LCDC_INVLINE_INVERTED;
> + if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
> + value |= ATMEL_LCDC_INVFRAME_INVERTED;
> + value |= bpix << 5;
> + lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);
>
> /* Vertical timing */
> - value = (panel_info.vl_vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
> - value |= panel_info.vl_upper_margin << ATMEL_LCDC_VBP_OFFSET;
> - value |= panel_info.vl_lower_margin;
> - lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM1, value);
> + value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
> + value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
> + value |= timing->vfront_porch.typ;
> + /* Magic! (Datasheet says "Bit 31 must be written to 1") */
> + value |= 1U << 31;
> + lcdc_writel(reg, ATMEL_LCDC_TIM1, value);
>
> /* Horizontal timing */
> - value = (panel_info.vl_right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
> - value |= (panel_info.vl_hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
> - value |= (panel_info.vl_left_margin - 1);
> - lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM2, value);
> + value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
> + value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
> + value |= (timing->hback_porch.typ - 1);
> + lcdc_writel(reg, ATMEL_LCDC_TIM2, value);
>
> /* Display size */
> - value = (panel_info.vl_col - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
> - value |= panel_info.vl_row - 1;
> - lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDFRMCFG, value);
> + value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
> + value |= timing->vactive.typ - 1;
> + lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);
>
> /* FIFO Threshold: Use formula from data sheet */
> value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
> - lcdc_writel(panel_info.mmio, ATMEL_LCDC_FIFO, value);
> + lcdc_writel(reg, ATMEL_LCDC_FIFO, value);
>
> /* Toggle LCD_MODE every frame */
> - lcdc_writel(panel_info.mmio, ATMEL_LCDC_MVAL, 0);
> + lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);
>
> /* Disable all interrupts */
> - lcdc_writel(panel_info.mmio, ATMEL_LCDC_IDR, ~0UL);
> + lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);
>
> /* Set contrast */
> value = ATMEL_LCDC_PS_DIV8 |
> ATMEL_LCDC_ENA_PWMENABLE;
> - if (!panel_info.vl_cont_pol_low)
> + if (!cont_pol_low)
> value |= ATMEL_LCDC_POL_POSITIVE;
> - lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value);
> - lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
> + lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
> + lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
>
> /* Set framebuffer DMA base address and pixel offset */
> - lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMABADDR1, (u_long)lcdbase);
> + lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);
>
> - lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
> - lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
> + lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
> + lcdc_writel(reg, ATMEL_LCDC_PWRCON,
> (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
> }
>
> +void lcd_ctrl_init(void *lcdbase)
> +{
> + struct display_timing timing;
> +
> + timing.flags = 0;
> + if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
> + timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
> + if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
> + timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
> + timing.pixelclock.typ = panel_info.vl_clk;
> +
> + timing.hactive.typ = panel_info.vl_col;
> + timing.hfront_porch.typ = panel_info.vl_right_margin;
> + timing.hback_porch.typ = panel_info.vl_left_margin;
> + timing.hsync_len.typ = panel_info.vl_hsync_len;
> +
> + timing.vactive.typ = panel_info.vl_row;
> + timing.vfront_porch.typ = panel_info.vl_clk;
> + timing.vback_porch.typ = panel_info.vl_clk;
> + timing.vsync_len.typ = panel_info.vl_clk;
> +
> + atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
> + panel_info.vl_tft, panel_info.vl_cont_pol_low,
> + (ulong)lcdbase);
> +}
> +
> ulong calc_fbsize(void)
> {
> return ((panel_info.vl_col * panel_info.vl_row *
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 16/18] at91: video: Support driver-model for the LCD driver
2016-05-05 13:28 ` [U-Boot] [PATCH v2 16/18] at91: video: Support driver-model for the LCD driver Simon Glass
@ 2016-06-04 20:11 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-04 20:11 UTC (permalink / raw)
To: u-boot
On 05.05.16 15:28, Simon Glass wrote:
> Add driver-model support to this driver. Most features can be controlled
> from the device tree.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
> ---
>
> Changes in v2: None
>
> drivers/video/atmel_lcdfb.c | 91 +++++++++++++++++++++++++++++++++++++++++++++
> include/atmel_lcd.h | 9 +++++
> 2 files changed, 100 insertions(+)
>
> diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
> index 37838a8..39cd7ca 100644
> --- a/drivers/video/atmel_lcdfb.c
> +++ b/drivers/video/atmel_lcdfb.c
> @@ -7,7 +7,10 @@
> */
>
> #include <common.h>
> +#include <atmel_lcd.h>
> +#include <dm.h>
> #include <fdtdec.h>
> +#include <video.h>
> #include <asm/io.h>
> #include <asm/arch/gpio.h>
> #include <asm/arch/clk.h>
> @@ -15,6 +18,21 @@
> #include <bmp_layout.h>
> #include <atmel_lcdc.h>
>
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#ifdef CONFIG_DM_VIDEO
> +enum {
> + /* Maximum LCD size we support */
> + LCD_MAX_WIDTH = 1366,
> + LCD_MAX_HEIGHT = 768,
> + LCD_MAX_LOG2_BPP = VIDEO_BPP16,
> +};
> +#endif
> +
> +struct atmel_fb_priv {
> + struct display_timing timing;
> +};
> +
> /* configurable parameters */
> #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
> #define ATMEL_LCDC_DMA_BURST_LEN 8
> @@ -31,6 +49,7 @@
> #define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg))
> #define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg))
>
> +#ifndef CONFIG_DM_VIDEO
> ushort *configuration_get_cmap(void)
> {
> return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
> @@ -91,6 +110,7 @@ void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
> lcd_setcolreg(i, cte.red, cte.green, cte.blue);
> }
> }
> +#endif
>
> static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
> bool tft, bool cont_pol_low, ulong lcdbase)
> @@ -190,6 +210,7 @@ static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
> (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
> }
>
> +#ifndef CONFIG_DM_VIDEO
> void lcd_ctrl_init(void *lcdbase)
> {
> struct display_timing timing;
> @@ -221,3 +242,73 @@ ulong calc_fbsize(void)
> return ((panel_info.vl_col * panel_info.vl_row *
> NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
> }
> +#endif
> +
> +#ifdef CONFIG_DM_VIDEO
> +static int atmel_fb_lcd_probe(struct udevice *dev)
> +{
> + struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
> + struct video_priv *uc_priv = dev_get_uclass_priv(dev);
> + struct atmel_fb_priv *priv = dev_get_priv(dev);
> + struct display_timing *timing = &priv->timing;
> +
> + /*
> + * For now some values are hard-coded. We could use the device tree
> + * bindings in simple-framebuffer.txt to specify the format/bpp and
> + * some Atmel-specific binding for tft and cont_pol_low.
> + */
> + atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
> + uc_plat->base);
> + uc_priv->xsize = timing->hactive.typ;
> + uc_priv->ysize = timing->vactive.typ;
> + uc_priv->bpix = VIDEO_BPP16;
> + video_set_flush_dcache(dev, true);
> + debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
> + uc_plat->size, uc_priv->xsize, uc_priv->ysize);
> +
> + return 0;
> +}
> +
> +static int atmel_fb_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
> + struct atmel_fb_priv *priv = dev_get_priv(dev);
> + struct display_timing *timing = &priv->timing;
> + const void *blob = gd->fdt_blob;
> +
> + if (fdtdec_decode_display_timing(blob, dev->of_offset,
> + plat->timing_index, timing)) {
> + debug("%s: Failed to decode display timing\n", __func__);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int atmel_fb_lcd_bind(struct udevice *dev)
> +{
> + struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
> +
> + uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
> + (1 << VIDEO_BPP16) / 8;
> + debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
> +
> + return 0;
> +}
> +
> +static const struct udevice_id atmel_fb_lcd_ids[] = {
> + { .compatible = "atmel,at91sam9g45-lcdc" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(atmel_fb) = {
> + .name = "atmel_fb",
> + .id = UCLASS_VIDEO,
> + .of_match = atmel_fb_lcd_ids,
> + .bind = atmel_fb_lcd_bind,
> + .ofdata_to_platdata = atmel_fb_ofdata_to_platdata,
> + .probe = atmel_fb_lcd_probe,
> + .platdata_auto_alloc_size = sizeof(struct atmel_lcd_platdata),
> + .priv_auto_alloc_size = sizeof(struct atmel_fb_priv),
> +};
> +#endif
> diff --git a/include/atmel_lcd.h b/include/atmel_lcd.h
> index 6993128..8a2f46f 100644
> --- a/include/atmel_lcd.h
> +++ b/include/atmel_lcd.h
> @@ -10,6 +10,15 @@
> #ifndef _ATMEL_LCD_H_
> #define _ATMEL_LCD_H_
>
> +/**
> + * struct atmel_lcd_platdata - platform data for Atmel LCDs with driver model
> + *
> + * @timing_index: Index of LCD timing to use in device tree node
> + */
> +struct atmel_lcd_platdata {
> + int timing_index;
> +};
> +
> typedef struct vidinfo {
> ushort vl_col; /* Number of columns (i.e. 640) */
> ushort vl_row; /* Number of rows (i.e. 480) */
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 17/18] fdt: Correct return value in fdtdec_decode_display_timing()
2016-05-05 13:28 ` [U-Boot] [PATCH v2 17/18] fdt: Correct return value in fdtdec_decode_display_timing() Simon Glass
@ 2016-06-04 20:14 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-04 20:14 UTC (permalink / raw)
To: u-boot
On 05.05.16 15:28, Simon Glass wrote:
> This should return a non-zero value if there is a missing property. Update
> the return value accordingly. The only expected error is -FDT_ERR_NOTFOUND.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
> ---
>
> Changes in v2: None
>
> lib/fdtdec.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
> index 70acc29..9782c93 100644
> --- a/lib/fdtdec.c
> +++ b/lib/fdtdec.c
> @@ -1169,7 +1169,7 @@ int fdtdec_decode_display_timing(const void *blob, int parent, int index,
> if (fdtdec_get_bool(blob, node, "doubleclk"))
> dt->flags |= DISPLAY_FLAGS_DOUBLECLK;
>
> - return 0;
> + return ret;
> }
>
> int fdtdec_setup(void)
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH] linux/compat.h: add dev_warn()
2016-05-05 13:28 ` [U-Boot] [PATCH v2 14/18] at91: mtd: nand: Add dev_warn() to correct build error in driver Simon Glass
2016-05-28 23:04 ` Andreas Bießmann
@ 2016-06-04 20:27 ` Andreas Bießmann
2016-06-10 0:35 ` Simon Glass
2016-06-12 22:01 ` [U-Boot] " Andreas Bießmann
1 sibling, 2 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-04 20:27 UTC (permalink / raw)
To: u-boot
In order to prevent build errors for copied code from linux introduce
dev_warn().
Suggested-by: Scott Wood <oss@buserror.net>
Signed-off-by: Andreas Bie?mann <andreas@biessmann.org>
---
This is a replacement patch for '[PATCH v2 14/18] at91: mtd: nand: Add
dev_warn() to correct build error in driver'
include/linux/compat.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/compat.h b/include/linux/compat.h
index e561ee3..7236b8d 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -25,6 +25,8 @@ extern struct p_current *current;
printf(fmt, ##args)
#define dev_err(dev, fmt, args...) \
printf(fmt, ##args)
+#define dev_warn(dev, fmt, args...) \
+ printf(fmt, ##args)
#define printk printf
#define printk_once printf
--
2.7.4 (Apple Git-66)
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 18/18] arm: at91: Add support for gurnard
2016-05-05 13:28 ` [U-Boot] [PATCH v2 18/18] arm: at91: Add support for gurnard Simon Glass
@ 2016-06-04 20:31 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot,v2,18/18] " Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-04 20:31 UTC (permalink / raw)
To: u-boot
On 05.05.16 15:28, Simon Glass wrote:
> From: Andre Renaud <andre@designa-electronics.com>
>
> This board is based on Snapper 9G45 which has an Atmel AT91SAM9G45 chip and
> 128MB of SDRAM. It includes a small LCD, 2xUSB host, SD card, Ethernet and
> two UARTs.
>
> Signed-off-by: Andre Renaud <andre@designa-electronics.com>
> Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH] linux/compat.h: add dev_warn()
2016-06-04 20:27 ` [U-Boot] [PATCH] linux/compat.h: add dev_warn() Andreas Bießmann
@ 2016-06-10 0:35 ` Simon Glass
2016-06-12 22:01 ` [U-Boot] " Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Simon Glass @ 2016-06-10 0:35 UTC (permalink / raw)
To: u-boot
On 4 June 2016 at 14:27, Andreas Bie?mann <andreas@biessmann.org> wrote:
> In order to prevent build errors for copied code from linux introduce
> dev_warn().
>
> Suggested-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Andreas Bie?mann <andreas@biessmann.org>
> ---
> This is a replacement patch for '[PATCH v2 14/18] at91: mtd: nand: Add
> dev_warn() to correct build error in driver'
>
> include/linux/compat.h | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [U-Boot, v2, 01/18] at91: Add support for the AT91 slow clock controller
2016-05-05 13:28 ` [U-Boot] [PATCH v2 01/18] at91: Add support for the AT91 slow clock controller Simon Glass
@ 2016-06-12 22:01 ` Andreas Bießmann
0 siblings, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-12 22:01 UTC (permalink / raw)
To: u-boot
Dear Simon Glass,
Simon Glass <sjg@chromium.org> writes:
>From: Andre Renaud <andre@designa-electronics.com>
>
>This is available on AT91SAM9G45. Add the peripheral address and flag
>definitions.
>
>Signed-off-by: Andre Renaud <andre@designa-electronics.com>
>Signed-off-by: Simon Glass <sjg@chromium.org>
>Reviewed-by: Heiko Schocher <hs@denx.de>
>Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
>---
>
>Changes in v2: None
>
> arch/arm/mach-at91/include/mach/at91_sck.h | 21 +++++++++++++++++++++
> arch/arm/mach-at91/include/mach/at91sam9g45.h | 1 +
> 2 files changed, 22 insertions(+)
> create mode 100644 arch/arm/mach-at91/include/mach/at91_sck.h
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [U-Boot, v2, 02/18] arm: Allow skipping of low-level init with I-cache on
2016-05-05 13:28 ` [U-Boot] [PATCH v2 02/18] arm: Allow skipping of low-level init with I-cache on Simon Glass
2016-05-05 14:07 ` Andreas Bießmann
@ 2016-06-12 22:01 ` Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-12 22:01 UTC (permalink / raw)
To: u-boot
Dear Simon Glass,
Simon Glass <sjg@chromium.org> writes:
>At present CONFIG_SKIP_LOWLEVEL_INIT prevents U-Boot from calling
>lowlevel_init(). This means that the instruction cache is not enabled and
>the board runs very slowly.
>
>What is really needed in many cases is to skip the call to lowlevel_init()
>but still perform CP15 init. Add an option to handle this.
>
>Reviewed-by: Heiko Schocher <hs@denx.de>
>Tested-on: smartweb, corvus, taurus, axm
>Tested-by: Heiko Schocher <hs@denx.de>
>Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
>Signed-off-by: Simon Glass <sjg@chromium.org>
>Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
>---
>
>Changes in v2: None
>
> README | 5 +++++
> arch/arm/cpu/arm1136/start.S | 2 ++
> arch/arm/cpu/arm920t/start.S | 3 ++-
> arch/arm/cpu/arm926ejs/start.S | 2 ++
> arch/arm/cpu/arm946es/start.S | 2 ++
> arch/arm/cpu/armv7/start.S | 5 ++++-
> arch/arm/cpu/sa1100/start.S | 2 ++
> 7 files changed, 19 insertions(+), 2 deletions(-)
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [U-Boot, v2, 03/18] bootm: Align cache flush end address correctly
2016-05-05 13:28 ` [U-Boot] [PATCH v2 03/18] bootm: Align cache flush end address correctly Simon Glass
2016-05-05 14:19 ` Andreas Bießmann
@ 2016-06-12 22:01 ` Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-12 22:01 UTC (permalink / raw)
To: u-boot
Dear Simon Glass,
Simon Glass <sjg@chromium.org> writes:
>Flushing part of the cache should be done on cache boundaries. Trying to
>flush part of a cache line is not supported and the request may be ignored
>or print warnings.
>
>Adjust the bootm code to align the end address to prevent this problem.
>
>Signed-off-by: Simon Glass <sjg@chromium.org>
>Reviewed-by: Heiko Schocher <hs@denx.de>
>Tested-on: smartweb, corvus, taurus, axm
>Tested-by: Heiko Schocher <hs@denx.de>
>Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
>Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
>---
>
>Changes in v2: None
>
> common/bootm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [U-Boot, v2, 04/18] net: Handle an empty bootp extension section
2016-05-05 13:28 ` [U-Boot] [PATCH v2 04/18] net: Handle an empty bootp extension section Simon Glass
@ 2016-06-12 22:01 ` Andreas Bießmann
0 siblings, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-12 22:01 UTC (permalink / raw)
To: u-boot
Dear Simon Glass,
Simon Glass <sjg@chromium.org> writes:
>From: Andre Renaud <andre@designa-electronics.com>
>
>Avoid generating this section if there is nothing in it.
>
>Signed-off-by: Andre Renaud <andre@designa-electronics.com>
>Signed-off-by: Simon Glass <sjg@chromium.org>
>Acked-by: Joe Hershberger <joe.hershberger@ni.com>
>---
>
>Changes in v2: None
>
> net/bootp.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [U-Boot, v2, 05/18] net: macb: Prepare for driver-model conversion
2016-05-05 13:28 ` [U-Boot] [PATCH v2 05/18] net: macb: Prepare for driver-model conversion Simon Glass
2016-05-05 18:31 ` Joe Hershberger
2016-05-28 22:32 ` Andreas Bießmann
@ 2016-06-12 22:01 ` Andreas Bießmann
2 siblings, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-12 22:01 UTC (permalink / raw)
To: u-boot
Dear Simon Glass,
Simon Glass <sjg@chromium.org> writes:
>Adjust this driver to avoid using struct netdev in functions that driver
>model will call. Also refactor the receive function to be compatible with
>driver model.
>
>Signed-off-by: Simon Glass <sjg@chromium.org>
>Reviewed-by: Heiko Schocher <hs@denx.de>
>Tested-on: smartweb, corvus, taurus, axm
>Tested-by: Heiko Schocher <hs@denx.de>
>Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
>Acked-by: Joe Hershberger <joe.hershberger@ni.com>
>Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
>---
>
>Changes in v2: None
>
> drivers/net/macb.c | 199 +++++++++++++++++++++++++++++++++--------------------
> 1 file changed, 124 insertions(+), 75 deletions(-)
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [U-Boot, v2, 06/18] net: macb: Flush correct cache portion when sending
2016-05-05 13:28 ` [U-Boot] [PATCH v2 06/18] net: macb: Flush correct cache portion when sending Simon Glass
2016-05-28 12:35 ` Andreas Bießmann
@ 2016-06-12 22:01 ` Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-12 22:01 UTC (permalink / raw)
To: u-boot
Dear Simon Glass,
Simon Glass <sjg@chromium.org> writes:
>The end address of the cache flush must be cache-line-aligned since
>otherwise (at least on ARM926-EJS) the request is ignored. When the cache
>is enabled this means that packets are not sent.
>
>Signed-off-by: Simon Glass <sjg@chromium.org>
>Reviewed-by: Heiko Schocher <hs@denx.de>
>Acked-by: Joe Hershberger <joe.hershberger@ni.com>
>Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
>---
>
>Changes in v2: None
>
> drivers/net/macb.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [U-Boot,v2,07/18] net: macb: Convert to driver model
2016-05-05 13:28 ` [U-Boot] [PATCH v2 07/18] net: macb: Convert to driver model Simon Glass
2016-05-28 22:43 ` Andreas Bießmann
@ 2016-06-12 22:01 ` Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-12 22:01 UTC (permalink / raw)
To: u-boot
Dear Simon Glass,
Simon Glass <sjg@chromium.org> writes:
>Add driver-model support to this driver. The old code remains for now so
>that we can convert boards one at a time.
>
>Signed-off-by: Simon Glass <sjg@chromium.org>
>Reviewed-by: Heiko Schocher <hs@denx.de>
>Tested-on: smartweb, corvus, taurus, axm
>Tested-by: Heiko Schocher <hs@denx.de>
>Acked-by: Joe Hershberger <joe.hershberger@ni.com>
>Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
>---
>
>Changes in v2: None
>
> drivers/net/macb.c | 119 +++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 119 insertions(+)
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [U-Boot, v2, 08/18] arm: at91: dts: Bring in device tree file for AT91SAM9G45
2016-05-05 13:28 ` [U-Boot] [PATCH v2 08/18] arm: at91: dts: Bring in device tree file for AT91SAM9G45 Simon Glass
2016-05-28 22:45 ` Andreas Bießmann
@ 2016-06-12 22:01 ` Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-12 22:01 UTC (permalink / raw)
To: u-boot
Dear Simon Glass,
Simon Glass <sjg@chromium.org> writes:
>Add this file from Linux v4.5.
>
>Signed-off-by: Simon Glass <sjg@chromium.org>
>Reviewed-by: Heiko Schocher <hs@denx.de>
>Tested-on: smartweb, corvus, taurus, axm
>Tested-by: Heiko Schocher <hs@denx.de>
>Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
>---
>
>Changes in v2: None
>
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/at91sam9g45.dtsi | 1335 ++++++++++++++++++++++++++++++++++++
> include/dt-bindings/clock/at91.h | 23 +
> include/dt-bindings/dma/at91.h | 52 ++
> include/dt-bindings/pinctrl/at91.h | 40 ++
> 5 files changed, 1451 insertions(+)
> create mode 100644 arch/arm/dts/at91sam9g45.dtsi
> create mode 100644 include/dt-bindings/clock/at91.h
> create mode 100644 include/dt-bindings/dma/at91.h
> create mode 100644 include/dt-bindings/pinctrl/at91.h
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [U-Boot, v2, 09/18] arm: at91: Add a header file for the real-time clock
2016-05-05 13:28 ` [U-Boot] [PATCH v2 09/18] arm: at91: Add a header file for the real-time clock Simon Glass
2016-05-28 12:49 ` Andreas Bießmann
@ 2016-06-12 22:01 ` Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-12 22:01 UTC (permalink / raw)
To: u-boot
Dear Simon Glass,
Simon Glass <sjg@chromium.org> writes:
>From: Andre Renaud <andre@designa-electronics.com>
>
>Add register definitions for the AT91 RTC so that this can potentially be
>used in U-Boot.
>
>Signed-off-by: Andre Renaud <andre@designa-electronics.com>
>Signed-off-by: Simon Glass <sjg@chromium.org>
>Reviewed-by: Heiko Schocher <hs@denx.de>
>Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
>---
>
>Changes in v2: None
>
> arch/arm/mach-at91/include/mach/at91_rtc.h | 71 ++++++++++++++++++++++++++++++
> 1 file changed, 71 insertions(+)
> create mode 100644 arch/arm/mach-at91/include/mach/at91_rtc.h
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [U-Boot, v2, 10/18] at91: Correct NAND ECC register access
2016-05-05 13:28 ` [U-Boot] [PATCH v2 10/18] at91: Correct NAND ECC register access Simon Glass
2016-05-28 21:06 ` Andreas Bießmann
@ 2016-06-12 22:01 ` Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-12 22:01 UTC (permalink / raw)
To: u-boot
Dear Simon Glass,
Simon Glass <sjg@chromium.org> writes:
>From: Andre Renaud <andre@designa-electronics.com>
>
>This uses the wrote base register value. Fix it.
>
>Signed-off-by: Andre Renaud <andre@designa-electronics.com>
>Signed-off-by: Simon Glass <sjg@chromium.org>
>Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
>---
>
>Changes in v2: None
>
> drivers/mtd/nand/atmel_nand.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [U-Boot, v2, 11/18] at91: nand: Set up the ECC strength correctly
2016-05-05 13:28 ` [U-Boot] [PATCH v2 11/18] at91: nand: Set up the ECC strength correctly Simon Glass
2016-05-28 21:12 ` Andreas Bießmann
@ 2016-06-12 22:01 ` Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-12 22:01 UTC (permalink / raw)
To: u-boot
Dear Simon Glass,
Simon Glass <sjg@chromium.org> writes:
>From: Andre Renaud <andre@designa-electronics.com>
>
>This needs to be set to avoid a fatal error when ECC is used.
>
>Signed-off-by: Andre Renaud <andre@designa-electronics.com>
>Signed-off-by: Simon Glass <sjg@chromium.org>
>Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
>---
>
>Changes in v2: None
>
> drivers/mtd/nand/atmel_nand.c | 1 +
> 1 file changed, 1 insertion(+)
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [U-Boot, v2, 13/18] at91: Add driver-model GPIO devices for AT91SAM9G45
2016-05-05 13:28 ` [U-Boot] [PATCH v2 13/18] at91: Add driver-model GPIO devices for AT91SAM9G45 Simon Glass
2016-05-28 22:46 ` Andreas Bießmann
@ 2016-06-12 22:01 ` Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-12 22:01 UTC (permalink / raw)
To: u-boot
Dear Simon Glass,
Simon Glass <sjg@chromium.org> writes:
>Add these definitions so that GPIOs can be used with driver model.
>
>Signed-off-by: Simon Glass <sjg@chromium.org>
>Reviewed-by: Heiko Schocher <hs@denx.de>
>Tested-on: smartweb, corvus, taurus, axm
>Tested-by: Heiko Schocher <hs@denx.de>
>Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
>---
>
>Changes in v2: None
>
> arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] linux/compat.h: add dev_warn()
2016-06-04 20:27 ` [U-Boot] [PATCH] linux/compat.h: add dev_warn() Andreas Bießmann
2016-06-10 0:35 ` Simon Glass
@ 2016-06-12 22:01 ` Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-12 22:01 UTC (permalink / raw)
To: u-boot
Dear =?utf-8?q?Andreas_Bie=C3=9Fmann?=,
<andreas@biessmann.org> writes:
>In order to prevent build errors for copied code from linux introduce
>dev_warn().
>
>Suggested-by: Scott Wood <oss@buserror.net>
>Signed-off-by: Andreas Bie?mann <andreas@biessmann.org>
>Acked-by: Simon Glass <sjg@chromium.org>
>---
>This is a replacement patch for '[PATCH v2 14/18] at91: mtd: nand: Add
>dev_warn() to correct build error in driver'
>
> include/linux/compat.h | 2 ++
> 1 file changed, 2 insertions(+)
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [U-Boot, v2, 15/18] at91: video: Prepare for driver-model conversion
2016-05-05 13:28 ` [U-Boot] [PATCH v2 15/18] at91: video: Prepare for driver-model conversion Simon Glass
2016-06-04 20:08 ` Andreas Bießmann
@ 2016-06-12 22:01 ` Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-12 22:01 UTC (permalink / raw)
To: u-boot
Dear Simon Glass,
Simon Glass <sjg@chromium.org> writes:
>Adjust the driver to use struct display_timing for its display timing.
>This is what is used by driver-model and allows the LCD init code to be
>common.
>
>Signed-off-by: Simon Glass <sjg@chromium.org>
>Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
>---
>
>Changes in v2: None
>
> drivers/video/atmel_lcdfb.c | 106 +++++++++++++++++++++++++++++---------------
> 1 file changed, 70 insertions(+), 36 deletions(-)
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [U-Boot, v2, 16/18] at91: video: Support driver-model for the LCD driver
2016-05-05 13:28 ` [U-Boot] [PATCH v2 16/18] at91: video: Support driver-model for the LCD driver Simon Glass
2016-06-04 20:11 ` Andreas Bießmann
@ 2016-06-12 22:01 ` Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-12 22:01 UTC (permalink / raw)
To: u-boot
Dear Simon Glass,
Simon Glass <sjg@chromium.org> writes:
>Add driver-model support to this driver. Most features can be controlled
>from the device tree.
>
>Signed-off-by: Simon Glass <sjg@chromium.org>
>Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
>---
>
>Changes in v2: None
>
> drivers/video/atmel_lcdfb.c | 91 +++++++++++++++++++++++++++++++++++++++++++++
> include/atmel_lcd.h | 9 +++++
> 2 files changed, 100 insertions(+)
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [U-Boot, v2, 17/18] fdt: Correct return value in fdtdec_decode_display_timing()
2016-05-05 13:28 ` [U-Boot] [PATCH v2 17/18] fdt: Correct return value in fdtdec_decode_display_timing() Simon Glass
2016-06-04 20:14 ` Andreas Bießmann
@ 2016-06-12 22:01 ` Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-12 22:01 UTC (permalink / raw)
To: u-boot
Dear Simon Glass,
Simon Glass <sjg@chromium.org> writes:
>This should return a non-zero value if there is a missing property. Update
>the return value accordingly. The only expected error is -FDT_ERR_NOTFOUND.
>
>Signed-off-by: Simon Glass <sjg@chromium.org>
>Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
>---
>
>Changes in v2: None
>
> lib/fdtdec.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [U-Boot,v2,18/18] arm: at91: Add support for gurnard
2016-05-05 13:28 ` [U-Boot] [PATCH v2 18/18] arm: at91: Add support for gurnard Simon Glass
2016-06-04 20:31 ` Andreas Bießmann
@ 2016-06-12 22:01 ` Andreas Bießmann
1 sibling, 0 replies; 56+ messages in thread
From: Andreas Bießmann @ 2016-06-12 22:01 UTC (permalink / raw)
To: u-boot
Dear Simon Glass,
Simon Glass <sjg@chromium.org> writes:
>From: Andre Renaud <andre@designa-electronics.com>
>
>This board is based on Snapper 9G45 which has an Atmel AT91SAM9G45 chip and
>128MB of SDRAM. It includes a small LCD, 2xUSB host, SD card, Ethernet and
>two UARTs.
>
>Signed-off-by: Andre Renaud <andre@designa-electronics.com>
>Signed-off-by: Simon Glass <sjg@chromium.org>
>Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
>[apply CONFIG_BOOTDELAY transition]
>Signed-off-by: Andreas Bie?mann <andreas@biessmann.org>
>---
>
>Changes in v2:
>- Correct commit author in several cases
>- Rebase to master
>
> arch/arm/dts/at91sam9g45-gurnard.dts | 157 ++
> arch/arm/mach-at91/Kconfig | 9 +
> board/bluewater/gurnard/Kconfig | 12 +
> board/bluewater/gurnard/MAINTAINERS | 6 +
> board/bluewater/gurnard/Makefile | 11 +
> board/bluewater/gurnard/gurnard.c | 449 ++++++
> board/bluewater/gurnard/splash_logo.h | 2619 +++++++++++++++++++++++++++++++++
> configs/gurnard_defconfig | 19 +
> include/configs/snapper9g45.h | 156 ++
> 9 files changed, 3438 insertions(+)
> create mode 100644 arch/arm/dts/at91sam9g45-gurnard.dts
> create mode 100644 board/bluewater/gurnard/Kconfig
> create mode 100644 board/bluewater/gurnard/MAINTAINERS
> create mode 100644 board/bluewater/gurnard/Makefile
> create mode 100644 board/bluewater/gurnard/gurnard.c
> create mode 100644 board/bluewater/gurnard/splash_logo.h
> create mode 100644 configs/gurnard_defconfig
> create mode 100644 include/configs/snapper9g45.h
applied to u-boot-atmel/master, thanks!
Best regards,
Andreas Bie?mann
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 05/18] net: macb: Prepare for driver-model conversion
2016-05-28 22:32 ` Andreas Bießmann
@ 2016-06-20 1:30 ` Simon Glass
0 siblings, 0 replies; 56+ messages in thread
From: Simon Glass @ 2016-06-20 1:30 UTC (permalink / raw)
To: u-boot
Hi Andreas,
On 28 May 2016 at 16:32, Andreas Bie?mann <andreas@biessmann.org> wrote:
> Hi Simon,
>
> On 05.05.16 15:28, Simon Glass wrote:
>> Adjust this driver to avoid using struct netdev in functions that driver
>> model will call. Also refactor the receive function to be compatible with
>> driver model.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> Reviewed-by: Heiko Schocher <hs@denx.de>
>> Tested-on: smartweb, corvus, taurus, axm
>> Tested-by: Heiko Schocher <hs@denx.de>
>> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
>> ---
>>
>> Changes in v2: None
>>
>> drivers/net/macb.c | 199 +++++++++++++++++++++++++++++++++--------------------
>> 1 file changed, 124 insertions(+), 75 deletions(-)
>
> <snip>
>
>> -static int macb_phy_init(struct macb_device *macb)
>> +static int macb_phy_init(struct macb_device *macb, const char *name)
>> {
>> - struct eth_device *netdev = &macb->netdev;
>> #ifdef CONFIG_PHYLIB
>> struct phy_device *phydev;
>> #endif
>> @@ -452,7 +450,7 @@ static int macb_phy_init(struct macb_device *macb)
>> int media, speed, duplex;
>> int i;
>>
>> - arch_get_mdio_control(netdev->name);
>> + arch_get_mdio_control(name);
>> #ifdef CONFIG_MACB_SEARCH_PHY
>> /* Auto-detect phy_addr */
>> if (!macb_phy_find(macb))
>> @@ -462,13 +460,13 @@ static int macb_phy_init(struct macb_device *macb)
>> /* Check if the PHY is up to snuff... */
>> phy_id = macb_mdio_read(macb, MII_PHYSID1);
>> if (phy_id == 0xffff) {
>> - printf("%s: No PHY present\n", netdev->name);
>> + printf("%s: No PHY present\n", name);
>> return 0;
>> }
>>
>> #ifdef CONFIG_PHYLIB
>> /* need to consider other phy interface mode */
>> - phydev = phy_connect(macb->bus, macb->phy_addr, netdev,
>> + phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
>
> is this intentional? You removed every reference to netdev but retained
> this one.
> Well, it's clear to me that you have to provide an eth_device to
> phy_connect() but why change the function then and add the *name to
> function parameters?
>
>> PHY_INTERFACE_MODE_RGMII);
>> if (!phydev) {
>> printf("phy_connect failed\n");
>
> No more questions ...
>
> Reviewed-by: Andreas Bie?mann <andreas@biessmann.org>
Sorry for missing this. Actually this will need tweaking - I think Joe
pointed out that CONFIG_PHYLIB should not be used in modern code. But
in any case it is closer to converted (to driver model) than it was. I
think when something tries this out on a board that uses that they can
fix it and test. It will need to call phy_connect_dev() instead.
Regards,
Simon
^ permalink raw reply [flat|nested] 56+ messages in thread
end of thread, other threads:[~2016-06-20 1:30 UTC | newest]
Thread overview: 56+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-05-05 13:28 [U-Boot] [PATCH v2 00/18] at91: Convert Ethernet and LCD to driver model Simon Glass
2016-05-05 13:28 ` [U-Boot] [PATCH v2 01/18] at91: Add support for the AT91 slow clock controller Simon Glass
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 02/18] arm: Allow skipping of low-level init with I-cache on Simon Glass
2016-05-05 14:07 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 03/18] bootm: Align cache flush end address correctly Simon Glass
2016-05-05 14:19 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 04/18] net: Handle an empty bootp extension section Simon Glass
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 05/18] net: macb: Prepare for driver-model conversion Simon Glass
2016-05-05 18:31 ` Joe Hershberger
2016-05-28 22:32 ` Andreas Bießmann
2016-06-20 1:30 ` Simon Glass
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 06/18] net: macb: Flush correct cache portion when sending Simon Glass
2016-05-28 12:35 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 07/18] net: macb: Convert to driver model Simon Glass
2016-05-28 22:43 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot,v2,07/18] " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 08/18] arm: at91: dts: Bring in device tree file for AT91SAM9G45 Simon Glass
2016-05-28 22:45 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 09/18] arm: at91: Add a header file for the real-time clock Simon Glass
2016-05-28 12:49 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 10/18] at91: Correct NAND ECC register access Simon Glass
2016-05-28 21:06 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 11/18] at91: nand: Set up the ECC strength correctly Simon Glass
2016-05-28 21:12 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 12/18] mtd: nand: Drop a blank line in nand_wait() Simon Glass
2016-05-28 12:53 ` Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 13/18] at91: Add driver-model GPIO devices for AT91SAM9G45 Simon Glass
2016-05-28 22:46 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 14/18] at91: mtd: nand: Add dev_warn() to correct build error in driver Simon Glass
2016-05-28 23:04 ` Andreas Bießmann
2016-06-04 20:27 ` [U-Boot] [PATCH] linux/compat.h: add dev_warn() Andreas Bießmann
2016-06-10 0:35 ` Simon Glass
2016-06-12 22:01 ` [U-Boot] " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 15/18] at91: video: Prepare for driver-model conversion Simon Glass
2016-06-04 20:08 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 16/18] at91: video: Support driver-model for the LCD driver Simon Glass
2016-06-04 20:11 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 17/18] fdt: Correct return value in fdtdec_decode_display_timing() Simon Glass
2016-06-04 20:14 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot, v2, " Andreas Bießmann
2016-05-05 13:28 ` [U-Boot] [PATCH v2 18/18] arm: at91: Add support for gurnard Simon Glass
2016-06-04 20:31 ` Andreas Bießmann
2016-06-12 22:01 ` [U-Boot] [U-Boot,v2,18/18] " Andreas Bießmann
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