* [PATCH 0/3] tip-queue 2015-10-30 @ 2015-10-30 12:11 Borislav Petkov 2015-10-30 12:11 ` [PATCH 1/3] x86/mce: Add a Scalable MCA vendor flags bit Borislav Petkov ` (2 more replies) 0 siblings, 3 replies; 7+ messages in thread From: Borislav Petkov @ 2015-10-30 12:11 UTC (permalink / raw) To: Ingo Molnar; +Cc: LKML From: Borislav Petkov <bp@suse.de> Hi Ingo, please queue those non-critical platform enablement patches. Thanks. Aravind Gopalakrishnan (1): x86/mce: Add a Scalable MCA vendor flags bit Borislav Petkov (1): x86/mce: Add a default case to the switch in __mcheck_cpu_ancient_init() Wan Zongshun (1): x86/cpu: Add CLZERO detection arch/x86/include/asm/cpufeature.h | 5 ++++- arch/x86/include/asm/mce.h | 34 +++++++++++++++++++++------------- arch/x86/kernel/cpu/common.c | 1 + arch/x86/kernel/cpu/mcheck/mce.c | 4 ++++ 4 files changed, 30 insertions(+), 14 deletions(-) -- 2.3.5 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/3] x86/mce: Add a Scalable MCA vendor flags bit 2015-10-30 12:11 [PATCH 0/3] tip-queue 2015-10-30 Borislav Petkov @ 2015-10-30 12:11 ` Borislav Petkov 2015-11-01 10:27 ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan 2015-10-30 12:11 ` [PATCH 2/3] x86/mce: Add a default case to the switch in __mcheck_cpu_ancient_init() Borislav Petkov 2015-10-30 12:11 ` [PATCH 3/3] x86/cpu: Add CLZERO detection Borislav Petkov 2 siblings, 1 reply; 7+ messages in thread From: Borislav Petkov @ 2015-10-30 12:11 UTC (permalink / raw) To: Ingo Molnar; +Cc: LKML From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> Scalable MCA (SMCA) is a new feature in AMD Fam17h processors which indicates presence of MCA extensions. MCA extensions expands existing register space for the MCE banks and also introduces a new MSR range to accommodate new banks. Add the detection bit. Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> Cc: Ashok Raj <ashok.raj@intel.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@kernel.org> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: x86-ml <x86@kernel.org> Link: http://lkml.kernel.org/r/1446059010-28010-2-git-send-email-Aravind.Gopalakrishnan@amd.com [ Reformat mce_vendor_flags definitions and save indentation levels. Improve comments. ] Signed-off-by: Borislav Petkov <bp@suse.de> --- arch/x86/include/asm/mce.h | 34 +++++++++++++++++++++------------- arch/x86/kernel/cpu/mcheck/mce.c | 2 ++ 2 files changed, 23 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 2dbc0bf2b9f3..2ea4527e462f 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -123,19 +123,27 @@ struct mca_config { }; struct mce_vendor_flags { - /* - * overflow recovery cpuid bit indicates that overflow - * conditions are not fatal - */ - __u64 overflow_recov : 1, - - /* - * SUCCOR stands for S/W UnCorrectable error COntainment - * and Recovery. It indicates support for data poisoning - * in HW and deferred error interrupts. - */ - succor : 1, - __reserved_0 : 62; + /* + * Indicates that overflow conditions are not fatal, when set. + */ + __u64 overflow_recov : 1, + + /* + * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and + * Recovery. It indicates support for data poisoning in HW and deferred + * error interrupts. + */ + succor : 1, + + /* + * (AMD) SMCA: This bit indicates support for Scalable MCA which expands + * the register space for each MCA bank and also increases number of + * banks. Also, to accommodate the new banks and registers, the MCA + * register space is moved to a new MSR range. + */ + smca : 1, + + __reserved_0 : 61; }; extern struct mce_vendor_flags mce_flags; diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 9d014b82a124..c7c59d13e3f4 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -1605,6 +1605,8 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) mce_amd_feature_init(c); mce_flags.overflow_recov = !!(ebx & BIT(0)); mce_flags.succor = !!(ebx & BIT(1)); + mce_flags.smca = !!(ebx & BIT(3)); + break; } -- 2.3.5 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [tip:ras/core] x86/mce: Add a Scalable MCA vendor flags bit 2015-10-30 12:11 ` [PATCH 1/3] x86/mce: Add a Scalable MCA vendor flags bit Borislav Petkov @ 2015-11-01 10:27 ` tip-bot for Aravind Gopalakrishnan 0 siblings, 0 replies; 7+ messages in thread From: tip-bot for Aravind Gopalakrishnan @ 2015-11-01 10:27 UTC (permalink / raw) To: linux-tip-commits Cc: ashok.raj, bp, peterz, Aravind.Gopalakrishnan, linux-kernel, tony.luck, torvalds, linux-edac, hpa, tglx, mingo, bp Commit-ID: c7f54d21fb02e90042e6233b46716dcb244e70e6 Gitweb: http://git.kernel.org/tip/c7f54d21fb02e90042e6233b46716dcb244e70e6 Author: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> AuthorDate: Fri, 30 Oct 2015 13:11:37 +0100 Committer: Ingo Molnar <mingo@kernel.org> CommitDate: Sun, 1 Nov 2015 11:26:13 +0100 x86/mce: Add a Scalable MCA vendor flags bit Scalable MCA (SMCA) is a new feature in AMD Fam17h processors which indicates presence of MCA extensions. MCA extensions expands existing register space for the MCE banks and also introduces a new MSR range to accommodate new banks. Add the detection bit. Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> [ Reformat mce_vendor_flags definitions and save indentation levels. Improve comments. ] Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Ashok Raj <ashok.raj@intel.com> Cc: Borislav Petkov <bp@alien8.de> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1446207099-24948-2-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@kernel.org> --- arch/x86/include/asm/mce.h | 34 +++++++++++++++++++++------------- arch/x86/kernel/cpu/mcheck/mce.c | 2 ++ 2 files changed, 23 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 2dbc0bf..2ea4527 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -123,19 +123,27 @@ struct mca_config { }; struct mce_vendor_flags { - /* - * overflow recovery cpuid bit indicates that overflow - * conditions are not fatal - */ - __u64 overflow_recov : 1, - - /* - * SUCCOR stands for S/W UnCorrectable error COntainment - * and Recovery. It indicates support for data poisoning - * in HW and deferred error interrupts. - */ - succor : 1, - __reserved_0 : 62; + /* + * Indicates that overflow conditions are not fatal, when set. + */ + __u64 overflow_recov : 1, + + /* + * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and + * Recovery. It indicates support for data poisoning in HW and deferred + * error interrupts. + */ + succor : 1, + + /* + * (AMD) SMCA: This bit indicates support for Scalable MCA which expands + * the register space for each MCA bank and also increases number of + * banks. Also, to accommodate the new banks and registers, the MCA + * register space is moved to a new MSR range. + */ + smca : 1, + + __reserved_0 : 61; }; extern struct mce_vendor_flags mce_flags; diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 17b5ec6..3d631c4 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -1605,6 +1605,8 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) mce_amd_feature_init(c); mce_flags.overflow_recov = !!(ebx & BIT(0)); mce_flags.succor = !!(ebx & BIT(1)); + mce_flags.smca = !!(ebx & BIT(3)); + break; } ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] x86/mce: Add a default case to the switch in __mcheck_cpu_ancient_init() 2015-10-30 12:11 [PATCH 0/3] tip-queue 2015-10-30 Borislav Petkov 2015-10-30 12:11 ` [PATCH 1/3] x86/mce: Add a Scalable MCA vendor flags bit Borislav Petkov @ 2015-10-30 12:11 ` Borislav Petkov 2015-11-01 10:28 ` [tip:ras/core] " tip-bot for Borislav Petkov 2015-10-30 12:11 ` [PATCH 3/3] x86/cpu: Add CLZERO detection Borislav Petkov 2 siblings, 1 reply; 7+ messages in thread From: Borislav Petkov @ 2015-10-30 12:11 UTC (permalink / raw) To: Ingo Molnar; +Cc: LKML From: Borislav Petkov <bp@suse.de> Caught by building with W= which enable -Wswitch-default also. Signed-off-by: Borislav Petkov <bp@suse.de> --- arch/x86/kernel/cpu/mcheck/mce.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index c7c59d13e3f4..78c6f8d65d58 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -1586,6 +1586,8 @@ static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) winchip_mcheck_init(c); return 1; break; + default: + return 0; } return 0; -- 2.3.5 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [tip:ras/core] x86/mce: Add a default case to the switch in __mcheck_cpu_ancient_init() 2015-10-30 12:11 ` [PATCH 2/3] x86/mce: Add a default case to the switch in __mcheck_cpu_ancient_init() Borislav Petkov @ 2015-11-01 10:28 ` tip-bot for Borislav Petkov 0 siblings, 0 replies; 7+ messages in thread From: tip-bot for Borislav Petkov @ 2015-11-01 10:28 UTC (permalink / raw) To: linux-tip-commits Cc: mingo, linux-kernel, torvalds, tony.luck, bp, hpa, bp, peterz, tglx Commit-ID: dc34bdd2367fd31744ee3ba1de1b1cc0fa2ce193 Gitweb: http://git.kernel.org/tip/dc34bdd2367fd31744ee3ba1de1b1cc0fa2ce193 Author: Borislav Petkov <bp@suse.de> AuthorDate: Fri, 30 Oct 2015 13:11:38 +0100 Committer: Ingo Molnar <mingo@kernel.org> CommitDate: Sun, 1 Nov 2015 11:26:14 +0100 x86/mce: Add a default case to the switch in __mcheck_cpu_ancient_init() Caught by building with W= which enable -Wswitch-default also. Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Link: http://lkml.kernel.org/r/1446207099-24948-3-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@kernel.org> --- arch/x86/kernel/cpu/mcheck/mce.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 3d631c4..c5b0d56 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -1586,6 +1586,8 @@ static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) winchip_mcheck_init(c); return 1; break; + default: + return 0; } return 0; ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] x86/cpu: Add CLZERO detection 2015-10-30 12:11 [PATCH 0/3] tip-queue 2015-10-30 Borislav Petkov 2015-10-30 12:11 ` [PATCH 1/3] x86/mce: Add a Scalable MCA vendor flags bit Borislav Petkov 2015-10-30 12:11 ` [PATCH 2/3] x86/mce: Add a default case to the switch in __mcheck_cpu_ancient_init() Borislav Petkov @ 2015-10-30 12:11 ` Borislav Petkov 2015-11-01 10:28 ` [tip:x86/cpu] " tip-bot for Wan Zongshun 2 siblings, 1 reply; 7+ messages in thread From: Borislav Petkov @ 2015-10-30 12:11 UTC (permalink / raw) To: Ingo Molnar; +Cc: LKML From: Wan Zongshun <Vincent.Wan@amd.com> AMD Fam17h processors introduce support for the CLZERO instruction. It zeroes out the 64 byte cache line specified in RAX. Add the bit here to allow /proc/cpuinfo to list the feature. Boris: we're adding this as a separate ->x86_capability leaf because CPUID_80000008_EBX is going to contain more feature bits and it will fill out with time. Signed-off-by: Wan Zongshun <Vincent.Wan@amd.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Huang Rui <ray.huang@amd.com> Cc: Ingo Molnar <mingo@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: x86-ml <x86@kernel.org> Link: http://lkml.kernel.org/r/1446059010-28010-3-git-send-email-Aravind.Gopalakrishnan@amd.com [Wrap code in patch form, fix comments. ] Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> --- arch/x86/include/asm/cpufeature.h | 5 ++++- arch/x86/kernel/cpu/common.c | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 9727b3b48bd1..e4f8010f22e0 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -12,7 +12,7 @@ #include <asm/disabled-features.h> #endif -#define NCAPINTS 13 /* N 32-bit words worth of info */ +#define NCAPINTS 14 /* N 32-bit words worth of info */ #define NBUGINTS 1 /* N 32-bit bug flags */ /* @@ -255,6 +255,9 @@ /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ +/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ +#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ + /* * BUG word(s) */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index de22ea7ff82f..4ddd780aeac9 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -670,6 +670,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c) c->x86_virt_bits = (eax >> 8) & 0xff; c->x86_phys_bits = eax & 0xff; + c->x86_capability[13] = cpuid_ebx(0x80000008); } #ifdef CONFIG_X86_32 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) -- 2.3.5 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [tip:x86/cpu] x86/cpu: Add CLZERO detection 2015-10-30 12:11 ` [PATCH 3/3] x86/cpu: Add CLZERO detection Borislav Petkov @ 2015-11-01 10:28 ` tip-bot for Wan Zongshun 0 siblings, 0 replies; 7+ messages in thread From: tip-bot for Wan Zongshun @ 2015-11-01 10:28 UTC (permalink / raw) To: linux-tip-commits Cc: hpa, mingo, tony.luck, bp, Vincent.Wan, ray.huang, dvlasenk, bp, tglx, aravind.gopalakrishnan, peterz, linux-kernel, torvalds, luto Commit-ID: 2167ceabf34163727ca4e283c0f030e3960932e5 Gitweb: http://git.kernel.org/tip/2167ceabf34163727ca4e283c0f030e3960932e5 Author: Wan Zongshun <Vincent.Wan@amd.com> AuthorDate: Fri, 30 Oct 2015 13:11:39 +0100 Committer: Ingo Molnar <mingo@kernel.org> CommitDate: Sun, 1 Nov 2015 11:26:23 +0100 x86/cpu: Add CLZERO detection AMD Fam17h processors introduce support for the CLZERO instruction. It zeroes out the 64 byte cache line specified in RAX. Add the bit here to allow /proc/cpuinfo to list the feature. Boris: we're adding this as a separate ->x86_capability leaf because CPUID_80000008_EBX is going to contain more feature bits and it will fill out with time. Signed-off-by: Wan Zongshun <Vincent.Wan@amd.com> Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com> [ Wrap code in patch form, fix comments. ] Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Huang Rui <ray.huang@amd.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Link: http://lkml.kernel.org/r/1446207099-24948-4-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@kernel.org> --- arch/x86/include/asm/cpufeature.h | 5 ++++- arch/x86/kernel/cpu/common.c | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 9727b3b..e4f8010 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -12,7 +12,7 @@ #include <asm/disabled-features.h> #endif -#define NCAPINTS 13 /* N 32-bit words worth of info */ +#define NCAPINTS 14 /* N 32-bit words worth of info */ #define NBUGINTS 1 /* N 32-bit bug flags */ /* @@ -255,6 +255,9 @@ /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ +/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ +#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ + /* * BUG word(s) */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index de22ea7..4ddd780 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -670,6 +670,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c) c->x86_virt_bits = (eax >> 8) & 0xff; c->x86_phys_bits = eax & 0xff; + c->x86_capability[13] = cpuid_ebx(0x80000008); } #ifdef CONFIG_X86_32 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) ^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2015-11-01 10:29 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2015-10-30 12:11 [PATCH 0/3] tip-queue 2015-10-30 Borislav Petkov 2015-10-30 12:11 ` [PATCH 1/3] x86/mce: Add a Scalable MCA vendor flags bit Borislav Petkov 2015-11-01 10:27 ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan 2015-10-30 12:11 ` [PATCH 2/3] x86/mce: Add a default case to the switch in __mcheck_cpu_ancient_init() Borislav Petkov 2015-11-01 10:28 ` [tip:ras/core] " tip-bot for Borislav Petkov 2015-10-30 12:11 ` [PATCH 3/3] x86/cpu: Add CLZERO detection Borislav Petkov 2015-11-01 10:28 ` [tip:x86/cpu] " tip-bot for Wan Zongshun
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