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* [PATCH 0/3] Prevent set of DCEFCLK on smu_v11 gpus
@ 2021-04-16 22:29 Darren Powell
  2021-04-16 22:29 ` [PATCH 1/3] amdgpu/pm: add extra info to SMU msg pre-check failed message Darren Powell
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Darren Powell @ 2021-04-16 22:29 UTC (permalink / raw)
  To: amd-gfx; +Cc: Darren Powell

=== Description ===
Set of simple patches to prevent attempts to set dcefclk on NAVI10

=== Test System ===
* DESKTOP(AMD FX-8350 + NAVI10(731F/ca), BIOS: F2)
 + ISO(Ubuntu 20.04.1 LTS)
 + Kernel(5.11.0-custom-amdinternal-dirty)

=== Patch Summary ===
   linux: (git@gitlab.freedesktop.org:agd5f) origin/amd-staging-drm-next @ ef08e194c809
    + d3c010c89301  amdgpu/pm: add extra info to SMU msg pre-check failed message
    + 318e4244c61f  amdgpu/pm: Prevent force of DCEFCLK on NAVI10 and SIENNA_CICHLID
    + d2a9f4653269  amdgpu/pm: set pp_dpm_dcefclk to readonly on smu_v11 gpus


=== Tests ===
General Test Sequence
---------------------
* monitor dmesg output in a shell
  dmesg -w

* launch a root shell
  sudo bash

* set control to manual
  cd /sys/class/drm/card0/device
  echo manual > power_dpm_force_performance_level

* next step is expected to crash the GPU in unpatched and with patch 0001
** system usually continues operation so you can reboot gracefully

* TEST 1: modify pp_dpm_dcefclk to each level (0,1,2) and read setting after each write
  echo "1" > pp_dpm_dcefclk ; sleep 2 ; echo " ---set 1---" ; cat  pp_dpm_dcefclk ;\
  echo "2" > pp_dpm_dcefclk ; sleep 2 ; echo " ---set 2---" ; cat  pp_dpm_dcefclk ;\
  echo "0" > pp_dpm_dcefclk ; sleep 2 ; echo " ---set 0---" ; cat  pp_dpm_dcefclk 
** example output
  [   74.493190] amdgpu 0000:03:00.0: amdgpu: failed send message: SetSoftMaxByFreq (27)  param: 0x000504f2 response 0xff
  [   76.497102] amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state!
  [   76.497114] amdgpu 0000:03:00.0: amdgpu: Failed to export SMU metrics table!
  [   76.497649] amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state!
  [   78.501229] amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state!
  [   78.501241] amdgpu 0000:03:00.0: amdgpu: Failed to export SMU metrics table!
  [   78.501766] amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state!
  [   80.505401] amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed and SMU may be not in the right state!
  [   80.505414] amdgpu 0000:03:00.0: amdgpu: Failed to export SMU metrics table!

* TEST 2:
   ls -la  /sys/class/drm/card0/device/pp_dpm_dcefclk 
** example output
  -rw-r--r-- 1 root root 4096 Apr  7 18:33 /sys/class/drm/card0/device/pp_dpm_dcefclk

* POST TEST
** restore dpm clock to auto 
  echo auto > power_dpm_force_performance_level


Test Results
------------
* 0001 amdgpu/pm: add extra info to SMU msg pre-check failed message
** TEST 1 dmesg output
  [  101.414826] amdgpu 0000:03:00.0: amdgpu: failed send message: SetSoftMaxByFreq (27) 	param: 0x000504f2 response 0xff
  [  103.418916] amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed(0xff) and SMU may be not in the right state!
  [  103.418930] amdgpu 0000:03:00.0: amdgpu: Failed to export SMU metrics table!
  [  103.419474] amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed(0xff) and SMU may be not in the right state!
  [  105.423226] amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed(0xff) and SMU may be not in the right state!
  [  105.423239] amdgpu 0000:03:00.0: amdgpu: Failed to export SMU metrics table!
  [  105.423649] amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed(0xff) and SMU may be not in the right state!
  [  107.427502] amdgpu 0000:03:00.0: amdgpu: Msg issuing pre-check failed(0xff) and SMU may be not in the right state!
  [  107.427516] amdgpu 0000:03:00.0: amdgpu: Failed to export SMU metrics table!

* 0002  amdgpu/pm: Prevent force of DCEFCLK on NAVI10 and SIENNA_CICHLID
** GPU remains operational after test
** TEST 1 dmesg output
  [  263.087136] amdgpu 0000:03:00.0: amdgpu: Setting DCEFCLK min/max dpm level is not supported!
  [  265.092026] amdgpu 0000:03:00.0: amdgpu: Setting DCEFCLK min/max dpm level is not supported!
  [  267.096648] amdgpu 0000:03:00.0: amdgpu: Setting DCEFCLK min/max dpm level is not supported!

* 0003  amdgpu/pm: set pp_dpm_dcefclk to readonly on smu_v11 gpus
** TEST 2 shell output
  bash: pp_dpm_dcefclk: Permission denied
   ---set 1---
  0: 506Mhz *
  1: 886Mhz 
  2: 1266Mhz 
  bash: pp_dpm_dcefclk: Permission denied
   ---set 2---
  0: 506Mhz *
  1: 886Mhz 
  2: 1266Mhz 
  bash: pp_dpm_dcefclk: Permission denied
   ---set 0---
  0: 506Mhz *
  1: 886Mhz 
  2: 1266Mhz 

Darren Powell (3):
  amdgpu/pm: add extra info to SMU msg pre-check failed message
  amdgpu/pm: Prevent force of DCEFCLK on NAVI10 and SIENNA_CICHLID
  amdgpu/pm: set pp_dpm_dcefclk to readonly on smu_v11 gpus

 drivers/gpu/drm/amd/pm/amdgpu_pm.c                  | 13 +++++++++++++
 drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c     |  5 ++++-
 .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c |  4 +++-
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c              |  4 ++--
 4 files changed, 22 insertions(+), 4 deletions(-)


base-commit: ef08e194c80952585718ae70a32654f2c0a93bc5
-- 
2.25.1

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^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 1/3] amdgpu/pm: add extra info to SMU msg pre-check failed message
  2021-04-16 22:29 [PATCH 0/3] Prevent set of DCEFCLK on smu_v11 gpus Darren Powell
@ 2021-04-16 22:29 ` Darren Powell
  2021-04-16 22:29 ` [PATCH 2/3] amdgpu/pm: Prevent force of DCEFCLK on NAVI10 and SIENNA_CICHLID Darren Powell
  2021-04-16 22:29 ` [PATCH 3/3] amdgpu/pm: set pp_dpm_dcefclk to readonly on smu_v11 gpus Darren Powell
  2 siblings, 0 replies; 6+ messages in thread
From: Darren Powell @ 2021-04-16 22:29 UTC (permalink / raw)
  To: amd-gfx; +Cc: Darren Powell

Insert the value of the response to error message emitted when the
SMU msg pre-check failes

Signed-off-by: Darren Powell <darren.powell@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index dc7d2e71aa6f..5d1743f3321e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -104,8 +104,8 @@ int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
 
 	ret = smu_cmn_wait_for_response(smu);
 	if (ret != 0x1) {
-		dev_err(adev->dev, "Msg issuing pre-check failed and "
-		       "SMU may be not in the right state!\n");
+		dev_err(adev->dev, "Msg issuing pre-check failed(0x%x) and "
+		       "SMU may be not in the right state!\n", ret);
 		if (ret != -ETIME)
 			ret = -EIO;
 		return ret;
-- 
2.25.1

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^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 2/3] amdgpu/pm: Prevent force of DCEFCLK on NAVI10 and SIENNA_CICHLID
  2021-04-16 22:29 [PATCH 0/3] Prevent set of DCEFCLK on smu_v11 gpus Darren Powell
  2021-04-16 22:29 ` [PATCH 1/3] amdgpu/pm: add extra info to SMU msg pre-check failed message Darren Powell
@ 2021-04-16 22:29 ` Darren Powell
  2021-04-16 22:29 ` [PATCH 3/3] amdgpu/pm: set pp_dpm_dcefclk to readonly on smu_v11 gpus Darren Powell
  2 siblings, 0 replies; 6+ messages in thread
From: Darren Powell @ 2021-04-16 22:29 UTC (permalink / raw)
  To: amd-gfx; +Cc: Darren Powell

Writing to dcefclk causes the gpu to become unresponsive, and requires a reboot.
Patch ignores a .force_clk_levels(SMU_DCEFCLK) call and issues an
info message.

Signed-off-by: Darren Powell <darren.powell@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c         | 5 ++++-
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 +++-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index f827096dc849..ac13042672ea 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1443,7 +1443,6 @@ static int navi10_force_clk_levels(struct smu_context *smu,
 	case SMU_SOCCLK:
 	case SMU_MCLK:
 	case SMU_UCLK:
-	case SMU_DCEFCLK:
 	case SMU_FCLK:
 		/* There is only 2 levels for fine grained DPM */
 		if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
@@ -1463,6 +1462,10 @@ static int navi10_force_clk_levels(struct smu_context *smu,
 		if (ret)
 			return size;
 		break;
+	case SMU_DCEFCLK:
+		dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
+		break;
+
 	default:
 		break;
 	}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 72d9c1be1835..d2fd44b903ca 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1127,7 +1127,6 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
 	case SMU_SOCCLK:
 	case SMU_MCLK:
 	case SMU_UCLK:
-	case SMU_DCEFCLK:
 	case SMU_FCLK:
 		/* There is only 2 levels for fine grained DPM */
 		if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
@@ -1147,6 +1146,9 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
 		if (ret)
 			goto forec_level_out;
 		break;
+	case SMU_DCEFCLK:
+		dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
+		break;
 	default:
 		break;
 	}
-- 
2.25.1

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^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 3/3] amdgpu/pm: set pp_dpm_dcefclk to readonly on smu_v11 gpus
  2021-04-16 22:29 [PATCH 0/3] Prevent set of DCEFCLK on smu_v11 gpus Darren Powell
  2021-04-16 22:29 ` [PATCH 1/3] amdgpu/pm: add extra info to SMU msg pre-check failed message Darren Powell
  2021-04-16 22:29 ` [PATCH 2/3] amdgpu/pm: Prevent force of DCEFCLK on NAVI10 and SIENNA_CICHLID Darren Powell
@ 2021-04-16 22:29 ` Darren Powell
  2021-04-19  0:47   ` Feng, Kenneth
  2 siblings, 1 reply; 6+ messages in thread
From: Darren Powell @ 2021-04-16 22:29 UTC (permalink / raw)
  To: amd-gfx; +Cc: Darren Powell

Writing to dcefclk causes the gpu to become unresponsive, and requires a reboot.
Patch prevents user from successfully writing to file pp_dpm_dcefclk on smu_vv11
parts and gives better user feedback that this operation is not allowed.

Signed-off-by: Darren Powell <darren.powell@amd.com>
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 204e34549013..317e9b47db53 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -1891,6 +1891,19 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
 		}
 	}
 
+	if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
+		/* SMU MP1 does not support dcefclk level setting */
+		if (asic_type == CHIP_NAVI10          ||
+		    asic_type == CHIP_NAVI14          ||
+		    asic_type == CHIP_NAVI12          ||
+		    asic_type == CHIP_SIENNA_CICHLID  ||
+		    asic_type == CHIP_NAVY_FLOUNDER   ||
+		    asic_type == CHIP_DIMGREY_CAVEFISH  ) {
+			dev_attr->attr.mode &= ~S_IWUGO;
+			dev_attr->store = NULL;
+		}
+	}
+
 #undef DEVICE_ATTR_IS
 
 	return 0;
-- 
2.25.1

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^ permalink raw reply	[flat|nested] 6+ messages in thread

* RE: [PATCH 3/3] amdgpu/pm: set pp_dpm_dcefclk to readonly on smu_v11 gpus
  2021-04-16 22:29 ` [PATCH 3/3] amdgpu/pm: set pp_dpm_dcefclk to readonly on smu_v11 gpus Darren Powell
@ 2021-04-19  0:47   ` Feng, Kenneth
  0 siblings, 0 replies; 6+ messages in thread
From: Feng, Kenneth @ 2021-04-19  0:47 UTC (permalink / raw)
  To: Powell, Darren, amd-gfx

[AMD Official Use Only - Internal Distribution Only]

Hi Darren,
It would be better if the condition is " asic_type >=CHIP_NAVI10".
We assume that from navi10, this restriction is on all.
With this change, the patch is Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Thanks.


-----Original Message-----
From: Powell, Darren <Darren.Powell@amd.com> 
Sent: Saturday, April 17, 2021 6:30 AM
To: amd-gfx@lists.freedesktop.org
Cc: Powell, Darren <Darren.Powell@amd.com>
Subject: [PATCH 3/3] amdgpu/pm: set pp_dpm_dcefclk to readonly on smu_v11 gpus

Writing to dcefclk causes the gpu to become unresponsive, and requires a reboot.
Patch prevents user from successfully writing to file pp_dpm_dcefclk on smu_vv11 parts and gives better user feedback that this operation is not allowed.

Signed-off-by: Darren Powell <darren.powell@amd.com>
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 204e34549013..317e9b47db53 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -1891,6 +1891,19 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
 		}
 	}
 
+	if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
+		/* SMU MP1 does not support dcefclk level setting */
+		if (asic_type == CHIP_NAVI10          ||
+		    asic_type == CHIP_NAVI14          ||
+		    asic_type == CHIP_NAVI12          ||
+		    asic_type == CHIP_SIENNA_CICHLID  ||
+		    asic_type == CHIP_NAVY_FLOUNDER   ||
+		    asic_type == CHIP_DIMGREY_CAVEFISH  ) {
+			dev_attr->attr.mode &= ~S_IWUGO;
+			dev_attr->store = NULL;
+		}
+	}
+
 #undef DEVICE_ATTR_IS
 
 	return 0;
--
2.25.1
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^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 2/3] amdgpu/pm: Prevent force of DCEFCLK on NAVI10 and SIENNA_CICHLID
  2021-04-23  3:22 [PATCH v2 0/3] Prevent set of DCEFCLK " Darren Powell
@ 2021-04-23  3:22 ` Darren Powell
  0 siblings, 0 replies; 6+ messages in thread
From: Darren Powell @ 2021-04-23  3:22 UTC (permalink / raw)
  To: amd-gfx; +Cc: Darren Powell

Writing to dcefclk causes the gpu to become unresponsive, and requires a reboot.
Patch ignores a .force_clk_levels(SMU_DCEFCLK) call and issues an
info message.

Signed-off-by: Darren Powell <darren.powell@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c         | 5 ++++-
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 +++-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index f827096dc849..ac13042672ea 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1443,7 +1443,6 @@ static int navi10_force_clk_levels(struct smu_context *smu,
 	case SMU_SOCCLK:
 	case SMU_MCLK:
 	case SMU_UCLK:
-	case SMU_DCEFCLK:
 	case SMU_FCLK:
 		/* There is only 2 levels for fine grained DPM */
 		if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
@@ -1463,6 +1462,10 @@ static int navi10_force_clk_levels(struct smu_context *smu,
 		if (ret)
 			return size;
 		break;
+	case SMU_DCEFCLK:
+		dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
+		break;
+
 	default:
 		break;
 	}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 72d9c1be1835..d2fd44b903ca 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1127,7 +1127,6 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
 	case SMU_SOCCLK:
 	case SMU_MCLK:
 	case SMU_UCLK:
-	case SMU_DCEFCLK:
 	case SMU_FCLK:
 		/* There is only 2 levels for fine grained DPM */
 		if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
@@ -1147,6 +1146,9 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
 		if (ret)
 			goto forec_level_out;
 		break;
+	case SMU_DCEFCLK:
+		dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
+		break;
 	default:
 		break;
 	}
-- 
2.25.1

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^ permalink raw reply	[flat|nested] 6+ messages in thread

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Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-16 22:29 [PATCH 0/3] Prevent set of DCEFCLK on smu_v11 gpus Darren Powell
2021-04-16 22:29 ` [PATCH 1/3] amdgpu/pm: add extra info to SMU msg pre-check failed message Darren Powell
2021-04-16 22:29 ` [PATCH 2/3] amdgpu/pm: Prevent force of DCEFCLK on NAVI10 and SIENNA_CICHLID Darren Powell
2021-04-16 22:29 ` [PATCH 3/3] amdgpu/pm: set pp_dpm_dcefclk to readonly on smu_v11 gpus Darren Powell
2021-04-19  0:47   ` Feng, Kenneth
2021-04-23  3:22 [PATCH v2 0/3] Prevent set of DCEFCLK " Darren Powell
2021-04-23  3:22 ` [PATCH 2/3] amdgpu/pm: Prevent force of DCEFCLK on NAVI10 and SIENNA_CICHLID Darren Powell

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