* [PATCH v2 0/4] Invalidate and flush caches at the beginning of every gfx IB
@ 2020-03-26 20:02 Andrey Grodzovsky
2020-03-26 20:02 ` [PATCH v2 1/4] drm/amdgpu: Add new ring callback to insert memory sync Andrey Grodzovsky
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Andrey Grodzovsky @ 2020-03-26 20:02 UTC (permalink / raw)
To: amd-gfx
Cc: Andrey Grodzovsky, ckoenig.leichtzumerken, Marek.Olsak, Ken.Qiao,
luben.tuikov, alexdeucher
This patchset introduces AQUIRE_MEM packet submission at the begining of each gfx IB
if requested by user mode client. This is helpful in solving issues with cache coherency
during amdgpu_test and Vulkan CTS tests.
Andrey Grodzovsky (4):
drm/amdgpu: Add new ring callback to insert memory sync
drm/amdgpu: Add AQUIRE_MEM PACKET3 fields defintion
drm/amdgpu: Add mem_sync implementation for all the ASICs.
drm/amdgpu: Add a UAPI flag for user to call mem_sync
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 27 +++++++++++++++++-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 16 ++++++++++-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 16 ++++++++++-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 17 ++++++++++-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 22 ++++++++++++++-
drivers/gpu/drm/amd/amdgpu/nvd.h | 48 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/soc15d.h | 25 ++++++++++++++++-
include/uapi/drm/amdgpu_drm.h | 4 +++
11 files changed, 175 insertions(+), 7 deletions(-)
--
2.7.4
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^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v2 1/4] drm/amdgpu: Add new ring callback to insert memory sync 2020-03-26 20:02 [PATCH v2 0/4] Invalidate and flush caches at the beginning of every gfx IB Andrey Grodzovsky @ 2020-03-26 20:02 ` Andrey Grodzovsky 2020-03-26 20:02 ` [PATCH v2 2/4] drm/amdgpu: Add AQUIRE_MEM PACKET3 fields defintion Andrey Grodzovsky ` (3 subsequent siblings) 4 siblings, 0 replies; 8+ messages in thread From: Andrey Grodzovsky @ 2020-03-26 20:02 UTC (permalink / raw) To: amd-gfx Cc: Andrey Grodzovsky, ckoenig.leichtzumerken, Marek.Olsak, Ken.Qiao, luben.tuikov, alexdeucher Used to flush and invalidate various caches. v2: Raname function hook Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 448c76c..080024d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -171,6 +171,7 @@ struct amdgpu_ring_funcs { /* Try to soft recover the ring to make the fence signal */ void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid); int (*preempt_ib)(struct amdgpu_ring *ring); + void (*emit_mem_sync)(struct amdgpu_ring *ring); }; struct amdgpu_ring { -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/4] drm/amdgpu: Add AQUIRE_MEM PACKET3 fields defintion 2020-03-26 20:02 [PATCH v2 0/4] Invalidate and flush caches at the beginning of every gfx IB Andrey Grodzovsky 2020-03-26 20:02 ` [PATCH v2 1/4] drm/amdgpu: Add new ring callback to insert memory sync Andrey Grodzovsky @ 2020-03-26 20:02 ` Andrey Grodzovsky 2020-03-26 23:09 ` Luben Tuikov 2020-03-26 20:02 ` [PATCH v2 3/4] drm/amdgpu: Add mem_sync implementation for all the ASICs Andrey Grodzovsky ` (2 subsequent siblings) 4 siblings, 1 reply; 8+ messages in thread From: Andrey Grodzovsky @ 2020-03-26 20:02 UTC (permalink / raw) To: amd-gfx Cc: Andrey Grodzovsky, ckoenig.leichtzumerken, Marek.Olsak, Ken.Qiao, luben.tuikov, alexdeucher Add this for gfx10 and gfx9. v2: Fix identation Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> --- drivers/gpu/drm/amd/amdgpu/nvd.h | 48 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/soc15d.h | 25 ++++++++++++++++++- 2 files changed, 72 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nvd.h b/drivers/gpu/drm/amd/amdgpu/nvd.h index f3d8771..fd6b582 100644 --- a/drivers/gpu/drm/amd/amdgpu/nvd.h +++ b/drivers/gpu/drm/amd/amdgpu/nvd.h @@ -256,6 +256,54 @@ #define PACKET3_BLK_CNTX_UPDATE 0x53 #define PACKET3_INCR_UPDT_STATE 0x55 #define PACKET3_ACQUIRE_MEM 0x58 +/* 1. HEADER + * 2. COHER_CNTL [30:0] + * 2.1 ENGINE_SEL [31:31] + * 2. COHER_SIZE [31:0] + * 3. COHER_SIZE_HI [7:0] + * 4. COHER_BASE_LO [31:0] + * 5. COHER_BASE_HI [23:0] + * 7. POLL_INTERVAL [15:0] + * 8. GCR_CNTL [18:0] + */ +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0) + /* + * 0:NOP + * 1:ALL + * 2:RANGE + * 3:FIRST_LAST + */ +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2) + /* + * 0:ALL + * 1:reserved + * 2:RANGE + * 3:FIRST_LAST + */ +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x) ((x) << 4) +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x) ((x) << 5) +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x) ((x) << 6) +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7) +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8) +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x) ((x) << 9) +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10) +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11) + /* + * 0:ALL + * 1:VOL + * 2:RANGE + * 3:FIRST_LAST + */ +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x) ((x) << 13) +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14) +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15) +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16) + /* + * 0: PARALLEL + * 1: FORWARD + * 2: REVERSE + */ +#define PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA (1 << 18) #define PACKET3_REWIND 0x59 #define PACKET3_INTERRUPT 0x5A #define PACKET3_GEN_PDEPTE 0x5B diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h b/drivers/gpu/drm/amd/amdgpu/soc15d.h index 295d68c..799925d 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15d.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h @@ -253,7 +253,30 @@ # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) -#define PACKET3_AQUIRE_MEM 0x58 +#define PACKET3_ACQUIRE_MEM 0x58 +/* 1. HEADER + * 2. COHER_CNTL [30:0] + * 2.1 ENGINE_SEL [31:31] + * 3. COHER_SIZE [31:0] + * 4. COHER_SIZE_HI [7:0] + * 5. COHER_BASE_LO [31:0] + * 6. COHER_BASE_HI [23:0] + * 7. POLL_INTERVAL [15:0] + */ +/* COHER_CNTL fields for CP_COHER_CNTL */ +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x) ((x) << 3) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA(x) ((x) << 4) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA(x) ((x) << 5) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA(x) ((x) << 15) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(x) ((x) << 18) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(x) ((x) << 22) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(x) ((x) << 23) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA(x) ((x) << 25) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA(x) ((x) << 26) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(x) ((x) << 27) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA(x) ((x) << 28) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(x) ((x) << 29) +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA(x) ((x) << 30) #define PACKET3_REWIND 0x59 #define PACKET3_LOAD_UCONFIG_REG 0x5E #define PACKET3_LOAD_SH_REG 0x5F -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/4] drm/amdgpu: Add AQUIRE_MEM PACKET3 fields defintion 2020-03-26 20:02 ` [PATCH v2 2/4] drm/amdgpu: Add AQUIRE_MEM PACKET3 fields defintion Andrey Grodzovsky @ 2020-03-26 23:09 ` Luben Tuikov 0 siblings, 0 replies; 8+ messages in thread From: Luben Tuikov @ 2020-03-26 23:09 UTC (permalink / raw) To: Andrey Grodzovsky, amd-gfx Cc: alexdeucher, Ken.Qiao, Marek.Olsak, ckoenig.leichtzumerken That looks so much better--thank you! Excellent! Regards, Luben On 2020-03-26 16:02, Andrey Grodzovsky wrote: > Add this for gfx10 and gfx9. > > v2: Fix identation > > Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/nvd.h | 48 +++++++++++++++++++++++++++++++++++++ > drivers/gpu/drm/amd/amdgpu/soc15d.h | 25 ++++++++++++++++++- > 2 files changed, 72 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/nvd.h b/drivers/gpu/drm/amd/amdgpu/nvd.h > index f3d8771..fd6b582 100644 > --- a/drivers/gpu/drm/amd/amdgpu/nvd.h > +++ b/drivers/gpu/drm/amd/amdgpu/nvd.h > @@ -256,6 +256,54 @@ > #define PACKET3_BLK_CNTX_UPDATE 0x53 > #define PACKET3_INCR_UPDT_STATE 0x55 > #define PACKET3_ACQUIRE_MEM 0x58 > +/* 1. HEADER > + * 2. COHER_CNTL [30:0] > + * 2.1 ENGINE_SEL [31:31] > + * 2. COHER_SIZE [31:0] > + * 3. COHER_SIZE_HI [7:0] > + * 4. COHER_BASE_LO [31:0] > + * 5. COHER_BASE_HI [23:0] > + * 7. POLL_INTERVAL [15:0] > + * 8. GCR_CNTL [18:0] > + */ > +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0) > + /* > + * 0:NOP > + * 1:ALL > + * 2:RANGE > + * 3:FIRST_LAST > + */ > +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2) > + /* > + * 0:ALL > + * 1:reserved > + * 2:RANGE > + * 3:FIRST_LAST > + */ > +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x) ((x) << 4) > +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x) ((x) << 5) > +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x) ((x) << 6) > +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7) > +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8) > +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x) ((x) << 9) > +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10) > +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11) > + /* > + * 0:ALL > + * 1:VOL > + * 2:RANGE > + * 3:FIRST_LAST > + */ > +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x) ((x) << 13) > +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14) > +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15) > +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16) > + /* > + * 0: PARALLEL > + * 1: FORWARD > + * 2: REVERSE > + */ > +#define PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA (1 << 18) > #define PACKET3_REWIND 0x59 > #define PACKET3_INTERRUPT 0x5A > #define PACKET3_GEN_PDEPTE 0x5B > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h b/drivers/gpu/drm/amd/amdgpu/soc15d.h > index 295d68c..799925d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/soc15d.h > +++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h > @@ -253,7 +253,30 @@ > # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) > # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) > # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) > -#define PACKET3_AQUIRE_MEM 0x58 > +#define PACKET3_ACQUIRE_MEM 0x58 > +/* 1. HEADER > + * 2. COHER_CNTL [30:0] > + * 2.1 ENGINE_SEL [31:31] > + * 3. COHER_SIZE [31:0] > + * 4. COHER_SIZE_HI [7:0] > + * 5. COHER_BASE_LO [31:0] > + * 6. COHER_BASE_HI [23:0] > + * 7. POLL_INTERVAL [15:0] > + */ > +/* COHER_CNTL fields for CP_COHER_CNTL */ > +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x) ((x) << 3) > +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA(x) ((x) << 4) > +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA(x) ((x) << 5) > +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA(x) ((x) << 15) > +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(x) ((x) << 18) > +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(x) ((x) << 22) > +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(x) ((x) << 23) > +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA(x) ((x) << 25) > +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA(x) ((x) << 26) > +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(x) ((x) << 27) > +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA(x) ((x) << 28) > +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(x) ((x) << 29) > +#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA(x) ((x) << 30) > #define PACKET3_REWIND 0x59 > #define PACKET3_LOAD_UCONFIG_REG 0x5E > #define PACKET3_LOAD_SH_REG 0x5F > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/4] drm/amdgpu: Add mem_sync implementation for all the ASICs. 2020-03-26 20:02 [PATCH v2 0/4] Invalidate and flush caches at the beginning of every gfx IB Andrey Grodzovsky 2020-03-26 20:02 ` [PATCH v2 1/4] drm/amdgpu: Add new ring callback to insert memory sync Andrey Grodzovsky 2020-03-26 20:02 ` [PATCH v2 2/4] drm/amdgpu: Add AQUIRE_MEM PACKET3 fields defintion Andrey Grodzovsky @ 2020-03-26 20:02 ` Andrey Grodzovsky 2020-03-26 20:02 ` [PATCH v2 4/4] drm/amdgpu: Add a UAPI flag for user to call mem_sync Andrey Grodzovsky 2020-03-26 23:20 ` [PATCH v2 0/4] Invalidate and flush caches at the beginning of every gfx IB Luben Tuikov 4 siblings, 0 replies; 8+ messages in thread From: Andrey Grodzovsky @ 2020-03-26 20:02 UTC (permalink / raw) To: amd-gfx Cc: Andrey Grodzovsky, ckoenig.leichtzumerken, Marek.Olsak, Ken.Qiao, luben.tuikov, alexdeucher Implement the .mem_sync hook defined earlier. v2: Rename functions Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 27 ++++++++++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 16 +++++++++++++++- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 16 +++++++++++++++- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 17 ++++++++++++++++- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 22 +++++++++++++++++++++- 5 files changed, 93 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 91c8238..974f1b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -5236,6 +5236,29 @@ static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, return 0; } +static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) +{ + unsigned gcr_cntl = PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | + PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | + PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | + PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | + PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | + PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | + PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | + /* TODO is this eqvivalent to V_586_GLI_ALL ? */ + PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); + + /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ + amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); + amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ + amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ + amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ + amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ + amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ + amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ + amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ +} + static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { .name = "gfx_v10_0", .early_init = gfx_v10_0_early_init, @@ -5283,7 +5306,8 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 3 + /* CNTX_CTRL */ 5 + /* HDP_INVL */ 8 + 8 + /* FENCE x2 */ - 2, /* SWITCH_BUFFER */ + 2 + /* SWITCH_BUFFER */ + 8, /* gfx_v10_0_emit_mem_sync */ .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ .emit_ib = gfx_v10_0_ring_emit_ib_gfx, .emit_fence = gfx_v10_0_ring_emit_fence, @@ -5304,6 +5328,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { .emit_wreg = gfx_v10_0_ring_emit_wreg, .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, + .emit_mem_sync = gfx_v10_0_emit_mem_sync, }; static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 31f44d0..07917f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -3466,6 +3466,18 @@ static int gfx_v6_0_set_powergating_state(void *handle, return 0; } +static void gfx_v6_0_emit_mem_sync(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); + amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | + PACKET3_TC_ACTION_ENA | + PACKET3_SH_KCACHE_ACTION_ENA | + PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */ + amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ + amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ + amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ +} + static const struct amd_ip_funcs gfx_v6_0_ip_funcs = { .name = "gfx_v6_0", .early_init = gfx_v6_0_early_init, @@ -3496,7 +3508,8 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ - 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */ + 3 + 2 + /* gfx_v6_ring_emit_cntxcntl including vgt flush */ + 5, /* SURFACE_SYNC */ .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ .emit_ib = gfx_v6_0_ring_emit_ib, .emit_fence = gfx_v6_0_ring_emit_fence, @@ -3507,6 +3520,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { .insert_nop = amdgpu_ring_insert_nop, .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl, .emit_wreg = gfx_v6_0_ring_emit_wreg, + .emit_mem_sync = gfx_v6_0_emit_mem_sync, }; static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 733d398..6f52b16f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -5001,6 +5001,18 @@ static int gfx_v7_0_set_powergating_state(void *handle, return 0; } +static void gfx_v7_0_emit_mem_sync(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); + amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | + PACKET3_TC_ACTION_ENA | + PACKET3_SH_KCACHE_ACTION_ENA | + PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */ + amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ + amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ + amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ +} + static const struct amd_ip_funcs gfx_v7_0_ip_funcs = { .name = "gfx_v7_0", .early_init = gfx_v7_0_early_init, @@ -5033,7 +5045,8 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */ 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */ CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v7_0_ring_emit_vm_flush */ - 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/ + 3 + 4 + /* gfx_v7_ring_emit_cntxcntl including vgt flush*/ + 5, /* SURFACE_SYNC */ .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */ .emit_ib = gfx_v7_0_ring_emit_ib_gfx, .emit_fence = gfx_v7_0_ring_emit_fence_gfx, @@ -5048,6 +5061,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl, .emit_wreg = gfx_v7_0_ring_emit_wreg, .soft_recovery = gfx_v7_0_ring_soft_recovery, + .emit_mem_sync = gfx_v7_0_emit_mem_sync, }; static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index fc32586..5e95326 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -6815,6 +6815,19 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev, return 0; } +static void gfx_v8_0_emit_mem_sync(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); + amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | + PACKET3_TC_ACTION_ENA | + PACKET3_SH_KCACHE_ACTION_ENA | + PACKET3_SH_ICACHE_ACTION_ENA | + PACKET3_TC_WB_ACTION_ENA); /* CP_COHER_CNTL */ + amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ + amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ + amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ +} + static const struct amd_ip_funcs gfx_v8_0_ip_funcs = { .name = "gfx_v8_0", .early_init = gfx_v8_0_early_init, @@ -6861,7 +6874,8 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { 3 + /* CNTX_CTRL */ 5 + /* HDP_INVL */ 12 + 12 + /* FENCE x2 */ - 2, /* SWITCH_BUFFER */ + 2 + /* SWITCH_BUFFER */ + 5, /* SURFACE_SYNC */ .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */ .emit_ib = gfx_v8_0_ring_emit_ib_gfx, .emit_fence = gfx_v8_0_ring_emit_fence_gfx, @@ -6879,6 +6893,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { .patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec, .emit_wreg = gfx_v8_0_ring_emit_wreg, .soft_recovery = gfx_v8_0_ring_soft_recovery, + .emit_mem_sync = gfx_v8_0_emit_mem_sync, }; static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 01b22da..a2855d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -6613,6 +6613,24 @@ static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, return 0; } +static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring) +{ + unsigned cp_coher_cntl = PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | + PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | + PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | + PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | + PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); + + /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ + amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); + amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ + amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ + amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ + amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ + amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ + amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ +} + static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { .name = "gfx_v9_0", .early_init = gfx_v9_0_early_init, @@ -6659,7 +6677,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 3 + /* CNTX_CTRL */ 5 + /* HDP_INVL */ 8 + 8 + /* FENCE x2 */ - 2, /* SWITCH_BUFFER */ + 2 + /* SWITCH_BUFFER */ + 7, /* gfx_v9_0_emit_mem_sync */ .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ .emit_ib = gfx_v9_0_ring_emit_ib_gfx, .emit_fence = gfx_v9_0_ring_emit_fence, @@ -6680,6 +6699,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, .soft_recovery = gfx_v9_0_ring_soft_recovery, + .emit_mem_sync = gfx_v9_0_emit_mem_sync, }; static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 4/4] drm/amdgpu: Add a UAPI flag for user to call mem_sync 2020-03-26 20:02 [PATCH v2 0/4] Invalidate and flush caches at the beginning of every gfx IB Andrey Grodzovsky ` (2 preceding siblings ...) 2020-03-26 20:02 ` [PATCH v2 3/4] drm/amdgpu: Add mem_sync implementation for all the ASICs Andrey Grodzovsky @ 2020-03-26 20:02 ` Andrey Grodzovsky 2020-03-26 23:17 ` Luben Tuikov 2020-03-26 23:20 ` [PATCH v2 0/4] Invalidate and flush caches at the beginning of every gfx IB Luben Tuikov 4 siblings, 1 reply; 8+ messages in thread From: Andrey Grodzovsky @ 2020-03-26 20:02 UTC (permalink / raw) To: amd-gfx Cc: Andrey Grodzovsky, ckoenig.leichtzumerken, Marek.Olsak, Ken.Qiao, luben.tuikov, alexdeucher This flag used to avoid calling mem_sync without need. v2: Move new flag to drm_amdgpu_cs_chunk_ib.flags Bump up UAPI version Remove condition on job != null to emit mem_sync Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 +++ include/uapi/drm/amdgpu_drm.h | 4 ++++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 28bb840..f18d974 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -85,9 +85,10 @@ * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask * - 3.36.0 - Allow reading more status registers on si/cik + * - 3.37.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC */ #define KMS_DRIVER_MAJOR 3 -#define KMS_DRIVER_MINOR 36 +#define KMS_DRIVER_MINOR 37 #define KMS_DRIVER_PATCHLEVEL 0 int amdgpu_vram_limit = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index bece01f..a8aa787 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -182,6 +182,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, dma_fence_put(tmp); } + if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync) + ring->funcs->emit_mem_sync(ring); + if (ring->funcs->insert_start) ring->funcs->insert_start(ring); diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index cfbec27..5f7a4f5 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -601,6 +601,10 @@ union drm_amdgpu_cs { */ #define AMDGPU_IB_FLAGS_SECURE (1 << 5) +/* Tell KMD to flush and invalidate caches + */ +#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) + struct drm_amdgpu_cs_chunk_ib { __u32 _pad; /** AMDGPU_IB_FLAG_* */ -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 4/4] drm/amdgpu: Add a UAPI flag for user to call mem_sync 2020-03-26 20:02 ` [PATCH v2 4/4] drm/amdgpu: Add a UAPI flag for user to call mem_sync Andrey Grodzovsky @ 2020-03-26 23:17 ` Luben Tuikov 0 siblings, 0 replies; 8+ messages in thread From: Luben Tuikov @ 2020-03-26 23:17 UTC (permalink / raw) To: Andrey Grodzovsky, amd-gfx Cc: alexdeucher, ckoenig.leichtzumerken, Marek.Olsak, Ken.Qiao On 2020-03-26 16:02, Andrey Grodzovsky wrote: > This flag used to avoid calling mem_sync without need. The title of this patch means that the flag is an "enabler" flag, i.e. when present, it enables something to happen (flush caches). While the description text in the commit implies that the flag is a "disabler" flag--i.e. when present, it, quote "avoids" mem sync, "without need". I'd much rather the commit text simply expound on the title of the commit, something like: "When this flag is set in the CS IB flags, it causes a memory cache flush of the GFX." or something to that effect. With that fixed, series is Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Regards, Luben > > v2: > Move new flag to drm_amdgpu_cs_chunk_ib.flags > Bump up UAPI version > Remove condition on job != null to emit mem_sync > > Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- > drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 +++ > include/uapi/drm/amdgpu_drm.h | 4 ++++ > 3 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > index 28bb840..f18d974 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > @@ -85,9 +85,10 @@ > * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches > * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask > * - 3.36.0 - Allow reading more status registers on si/cik > + * - 3.37.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC > */ > #define KMS_DRIVER_MAJOR 3 > -#define KMS_DRIVER_MINOR 36 > +#define KMS_DRIVER_MINOR 37 > #define KMS_DRIVER_PATCHLEVEL 0 > > int amdgpu_vram_limit = 0; > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c > index bece01f..a8aa787 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c > @@ -182,6 +182,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, > dma_fence_put(tmp); > } > > + if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync) > + ring->funcs->emit_mem_sync(ring); > + > if (ring->funcs->insert_start) > ring->funcs->insert_start(ring); > > diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h > index cfbec27..5f7a4f5 100644 > --- a/include/uapi/drm/amdgpu_drm.h > +++ b/include/uapi/drm/amdgpu_drm.h > @@ -601,6 +601,10 @@ union drm_amdgpu_cs { > */ > #define AMDGPU_IB_FLAGS_SECURE (1 << 5) > > +/* Tell KMD to flush and invalidate caches > + */ > +#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) > + > struct drm_amdgpu_cs_chunk_ib { > __u32 _pad; > /** AMDGPU_IB_FLAG_* */ > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/4] Invalidate and flush caches at the beginning of every gfx IB 2020-03-26 20:02 [PATCH v2 0/4] Invalidate and flush caches at the beginning of every gfx IB Andrey Grodzovsky ` (3 preceding siblings ...) 2020-03-26 20:02 ` [PATCH v2 4/4] drm/amdgpu: Add a UAPI flag for user to call mem_sync Andrey Grodzovsky @ 2020-03-26 23:20 ` Luben Tuikov 4 siblings, 0 replies; 8+ messages in thread From: Luben Tuikov @ 2020-03-26 23:20 UTC (permalink / raw) To: Andrey Grodzovsky, amd-gfx Cc: alexdeucher, Ken.Qiao, Marek.Olsak, ckoenig.leichtzumerken Looks great, except the note on patch 4 about the commit description text, and perhaps we don't need a period in the title of patch 3. With those fixed, the series is Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Thank you Andrey. Regards, Luben On 2020-03-26 16:02, Andrey Grodzovsky wrote: > This patchset introduces AQUIRE_MEM packet submission at the begining of each gfx IB > if requested by user mode client. This is helpful in solving issues with cache coherency > during amdgpu_test and Vulkan CTS tests. > > Andrey Grodzovsky (4): > drm/amdgpu: Add new ring callback to insert memory sync > drm/amdgpu: Add AQUIRE_MEM PACKET3 fields defintion > drm/amdgpu: Add mem_sync implementation for all the ASICs. > drm/amdgpu: Add a UAPI flag for user to call mem_sync > > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 ++ > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 + > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 27 +++++++++++++++++- > drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 16 ++++++++++- > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 16 ++++++++++- > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 17 ++++++++++- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 22 ++++++++++++++- > drivers/gpu/drm/amd/amdgpu/nvd.h | 48 ++++++++++++++++++++++++++++++++ > drivers/gpu/drm/amd/amdgpu/soc15d.h | 25 ++++++++++++++++- > include/uapi/drm/amdgpu_drm.h | 4 +++ > 11 files changed, 175 insertions(+), 7 deletions(-) > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-03-26 23:20 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-03-26 20:02 [PATCH v2 0/4] Invalidate and flush caches at the beginning of every gfx IB Andrey Grodzovsky 2020-03-26 20:02 ` [PATCH v2 1/4] drm/amdgpu: Add new ring callback to insert memory sync Andrey Grodzovsky 2020-03-26 20:02 ` [PATCH v2 2/4] drm/amdgpu: Add AQUIRE_MEM PACKET3 fields defintion Andrey Grodzovsky 2020-03-26 23:09 ` Luben Tuikov 2020-03-26 20:02 ` [PATCH v2 3/4] drm/amdgpu: Add mem_sync implementation for all the ASICs Andrey Grodzovsky 2020-03-26 20:02 ` [PATCH v2 4/4] drm/amdgpu: Add a UAPI flag for user to call mem_sync Andrey Grodzovsky 2020-03-26 23:17 ` Luben Tuikov 2020-03-26 23:20 ` [PATCH v2 0/4] Invalidate and flush caches at the beginning of every gfx IB Luben Tuikov
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