From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> To: Rob Herring <robh+dt@kernel.org> Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab <mchehab+huawei@kernel.org>, Kishon Vijay Abraham I <kishon@ti.com>, Vinod Koul <vkoul@kernel.org>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v3 4/4] dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY Date: Tue, 3 Aug 2021 06:38:58 +0200 [thread overview] Message-ID: <b5809d8acf257834dd84807aa0474f68a94d8084.1627965261.git.mchehab+huawei@kernel.org> (raw) In-Reply-To: <cover.1627965261.git.mchehab+huawei@kernel.org> Document the bindings for HiKey 970 (hi3670) PCIe PHY interface, supported via the pcie-kirin driver. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> --- .../phy/hisilicon,phy-hi3670-pcie.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml new file mode 100644 index 000000000000..1e0153e4f4a5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin970 PCIe PHY + +maintainers: + - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> + +description: |+ + Bindings for PCIe PHY on HiSilicon Kirin 970. + +properties: + compatible: + const: hisilicon,hi970-pcie-phy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + description: PHY Control registers + + phy-supply: + description: The PCIe PHY power supply + + clocks: + items: + - description: PCIe PHY clock + - description: PCIe AUX clock + - description: PCIe APB PHY clock + - description: PCIe APB SYS clock + - description: PCIe ACLK clock + + clock-names: + items: + - const: phy_ref + - const: aux + - const: apb_phy + - const: apb_sys + - const: aclk + + clkreq-gpios: + description: Clock request GPIOs + maxItems: 3 + + hisilicon,eye-diagram-param: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Eye diagram for phy. + +required: + - "#phy-cells" + - compatible + - reg + - clocks + - clock-names + - hisilicon,eye-diagram-param + - phy-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/hi3670-clock.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie_phy: pcie-phy@fc000000 { + compatible = "hisilicon,hi970-pcie-phy"; + reg = <0x0 0xfc000000 0x0 0x80000>; + #phy-cells = <0>; + phy-supply = <&ldo33>; + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "phy_ref", "aux", + "apb_phy", "apb_sys", "aclk"; + hisilicon,eye-diagram-param = <0xffffffff 0xffffffff + 0xffffffff 0xffffffff 0xffffffff>; + }; + }; -- 2.31.1
WARNING: multiple messages have this Message-ID (diff)
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> To: Rob Herring <robh+dt@kernel.org> Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab <mchehab+huawei@kernel.org>, Kishon Vijay Abraham I <kishon@ti.com>, Vinod Koul <vkoul@kernel.org>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v3 4/4] dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY Date: Tue, 3 Aug 2021 06:38:58 +0200 [thread overview] Message-ID: <b5809d8acf257834dd84807aa0474f68a94d8084.1627965261.git.mchehab+huawei@kernel.org> (raw) In-Reply-To: <cover.1627965261.git.mchehab+huawei@kernel.org> Document the bindings for HiKey 970 (hi3670) PCIe PHY interface, supported via the pcie-kirin driver. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> --- .../phy/hisilicon,phy-hi3670-pcie.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml new file mode 100644 index 000000000000..1e0153e4f4a5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin970 PCIe PHY + +maintainers: + - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> + +description: |+ + Bindings for PCIe PHY on HiSilicon Kirin 970. + +properties: + compatible: + const: hisilicon,hi970-pcie-phy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + description: PHY Control registers + + phy-supply: + description: The PCIe PHY power supply + + clocks: + items: + - description: PCIe PHY clock + - description: PCIe AUX clock + - description: PCIe APB PHY clock + - description: PCIe APB SYS clock + - description: PCIe ACLK clock + + clock-names: + items: + - const: phy_ref + - const: aux + - const: apb_phy + - const: apb_sys + - const: aclk + + clkreq-gpios: + description: Clock request GPIOs + maxItems: 3 + + hisilicon,eye-diagram-param: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Eye diagram for phy. + +required: + - "#phy-cells" + - compatible + - reg + - clocks + - clock-names + - hisilicon,eye-diagram-param + - phy-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/hi3670-clock.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie_phy: pcie-phy@fc000000 { + compatible = "hisilicon,hi970-pcie-phy"; + reg = <0x0 0xfc000000 0x0 0x80000>; + #phy-cells = <0>; + phy-supply = <&ldo33>; + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "phy_ref", "aux", + "apb_phy", "apb_sys", "aclk"; + hisilicon,eye-diagram-param = <0xffffffff 0xffffffff + 0xffffffff 0xffffffff 0xffffffff>; + }; + }; -- 2.31.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2021-08-03 4:39 UTC|newest] Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-03 4:38 [PATCH v3 0/4] DT schema changes for HiKey970 PCIe hardware to work Mauro Carvalho Chehab 2021-08-03 4:38 ` Mauro Carvalho Chehab 2021-08-03 4:38 ` [PATCH v3 1/4] dt-bindings: PCI: kirin: Fix compatible string Mauro Carvalho Chehab 2021-08-03 22:22 ` Rob Herring 2021-08-03 4:38 ` [PATCH v3 2/4] dt-bindings: PCI: kirin: Convert kirin-pcie.txt to yaml Mauro Carvalho Chehab 2021-08-03 22:27 ` Rob Herring 2021-08-03 4:38 ` [PATCH v3 3/4] dt-bindings: PCI: kirin: Add support for Kirin970 Mauro Carvalho Chehab 2021-08-03 4:38 ` Mauro Carvalho Chehab [this message] 2021-08-03 4:38 ` [PATCH v3 4/4] dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY Mauro Carvalho Chehab 2021-08-03 22:29 ` Rob Herring 2021-08-03 22:29 ` Rob Herring 2021-08-03 22:11 ` [PATCH v3 0/4] DT schema changes for HiKey970 PCIe hardware to work Rob Herring 2021-08-03 22:11 ` Rob Herring 2021-08-04 6:50 ` Mauro Carvalho Chehab 2021-08-04 6:50 ` Mauro Carvalho Chehab 2021-08-04 16:28 ` Rob Herring 2021-08-04 16:28 ` Rob Herring 2021-08-05 7:46 ` Mauro Carvalho Chehab 2021-08-05 7:46 ` Mauro Carvalho Chehab 2021-08-05 7:58 ` Mauro Carvalho Chehab 2021-08-05 7:58 ` Mauro Carvalho Chehab 2021-08-06 16:23 ` Rob Herring 2021-08-06 16:23 ` Rob Herring 2021-08-10 9:42 ` Mauro Carvalho Chehab 2021-08-10 9:42 ` Mauro Carvalho Chehab 2021-08-10 13:44 ` Rob Herring 2021-08-10 13:44 ` Rob Herring 2021-08-10 14:20 ` Mauro Carvalho Chehab 2021-08-10 14:20 ` Mauro Carvalho Chehab 2021-08-10 17:13 ` Rob Herring 2021-08-10 17:13 ` Rob Herring 2021-08-10 17:52 ` Rob Herring 2021-08-10 17:52 ` Rob Herring 2021-08-11 7:11 ` Mauro Carvalho Chehab 2021-08-11 7:11 ` Mauro Carvalho Chehab 2021-08-11 6:46 ` Mauro Carvalho Chehab 2021-08-11 6:46 ` Mauro Carvalho Chehab 2021-08-12 3:13 ` Rob Herring 2021-08-12 3:13 ` Rob Herring 2021-08-12 7:48 ` Mauro Carvalho Chehab 2021-08-12 7:48 ` Mauro Carvalho Chehab
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