From: Bart Van Assche <bart.vanassche@sandisk.com>
To: Christoph Hellwig <hch@lst.de>, <tglx@linutronix.de>, <axboe@fb.com>
Cc: linux-block@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-nvme@lists.infradead.org
Subject: Re: automatic interrupt affinity for MSI/MSI-X capable devices V2
Date: Thu, 16 Jun 2016 11:45:55 +0200 [thread overview]
Message-ID: <b8cdfc80-fa77-b7cc-69b8-fb6037114087@sandisk.com> (raw)
In-Reply-To: <1465934346-20648-1-git-send-email-hch@lst.de>
On 06/14/2016 09:58 PM, Christoph Hellwig wrote:
> This series enhances the irq and PCI code to allow spreading around MSI and
> MSI-X vectors so that they have per-cpu affinity if possible, or at least
> per-node. For that it takes the algorithm from blk-mq, moves it to
> a common place, and makes it available through a vastly simplified PCI
> interrupt allocation API. It then switches blk-mq to be able to pick up
> the queue mapping from the device if available, and demonstrates all this
> using the NVMe driver.
Hello Christoph,
Is my interpretation correct that for an adapter that supports two
interrupts and on a system with eight CPU cores and no hyperthreading
this patch series will assign interrupt vector 0 to CPU 0 and interrupt
vector 1 to CPU 1? Are you aware that drivers like ib_srp assume that
interrupts have been spread evenly, that means assigning vector 0 to CPU
0 and vector 1 to CPU 4?
Thanks,
Bart.
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WARNING: multiple messages have this Message-ID (diff)
From: Bart Van Assche <bart.vanassche@sandisk.com>
To: Christoph Hellwig <hch@lst.de>, <tglx@linutronix.de>, <axboe@fb.com>
Cc: <linux-block@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<linux-nvme@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: automatic interrupt affinity for MSI/MSI-X capable devices V2
Date: Thu, 16 Jun 2016 11:45:55 +0200 [thread overview]
Message-ID: <b8cdfc80-fa77-b7cc-69b8-fb6037114087@sandisk.com> (raw)
In-Reply-To: <1465934346-20648-1-git-send-email-hch@lst.de>
On 06/14/2016 09:58 PM, Christoph Hellwig wrote:
> This series enhances the irq and PCI code to allow spreading around MSI and
> MSI-X vectors so that they have per-cpu affinity if possible, or at least
> per-node. For that it takes the algorithm from blk-mq, moves it to
> a common place, and makes it available through a vastly simplified PCI
> interrupt allocation API. It then switches blk-mq to be able to pick up
> the queue mapping from the device if available, and demonstrates all this
> using the NVMe driver.
Hello Christoph,
Is my interpretation correct that for an adapter that supports two
interrupts and on a system with eight CPU cores and no hyperthreading
this patch series will assign interrupt vector 0 to CPU 0 and interrupt
vector 1 to CPU 1? Are you aware that drivers like ib_srp assume that
interrupts have been spread evenly, that means assigning vector 0 to CPU
0 and vector 1 to CPU 4?
Thanks,
Bart.
WARNING: multiple messages have this Message-ID (diff)
From: bart.vanassche@sandisk.com (Bart Van Assche)
Subject: automatic interrupt affinity for MSI/MSI-X capable devices V2
Date: Thu, 16 Jun 2016 11:45:55 +0200 [thread overview]
Message-ID: <b8cdfc80-fa77-b7cc-69b8-fb6037114087@sandisk.com> (raw)
In-Reply-To: <1465934346-20648-1-git-send-email-hch@lst.de>
On 06/14/2016 09:58 PM, Christoph Hellwig wrote:
> This series enhances the irq and PCI code to allow spreading around MSI and
> MSI-X vectors so that they have per-cpu affinity if possible, or at least
> per-node. For that it takes the algorithm from blk-mq, moves it to
> a common place, and makes it available through a vastly simplified PCI
> interrupt allocation API. It then switches blk-mq to be able to pick up
> the queue mapping from the device if available, and demonstrates all this
> using the NVMe driver.
Hello Christoph,
Is my interpretation correct that for an adapter that supports two
interrupts and on a system with eight CPU cores and no hyperthreading
this patch series will assign interrupt vector 0 to CPU 0 and interrupt
vector 1 to CPU 1? Are you aware that drivers like ib_srp assume that
interrupts have been spread evenly, that means assigning vector 0 to CPU
0 and vector 1 to CPU 4?
Thanks,
Bart.
next prev parent reply other threads:[~2016-06-16 9:45 UTC|newest]
Thread overview: 129+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-14 19:58 automatic interrupt affinity for MSI/MSI-X capable devices V2 Christoph Hellwig
2016-06-14 19:58 ` Christoph Hellwig
2016-06-14 19:58 ` [PATCH 01/13] irq/msi: Remove unused MSI_FLAG_IDENTITY_MAP Christoph Hellwig
2016-06-14 19:58 ` Christoph Hellwig
2016-06-14 19:58 ` Christoph Hellwig
2016-06-16 9:05 ` Bart Van Assche
2016-06-16 9:05 ` Bart Van Assche
2016-06-14 19:58 ` [PATCH 02/13] irq: Introduce IRQD_AFFINITY_MANAGED flag Christoph Hellwig
2016-06-14 19:58 ` Christoph Hellwig
2016-06-14 19:58 ` Christoph Hellwig
2016-06-15 8:44 ` Bart Van Assche
2016-06-15 8:44 ` Bart Van Assche
2016-06-15 10:23 ` Christoph Hellwig
2016-06-15 10:23 ` Christoph Hellwig
2016-06-15 10:42 ` Bart Van Assche
2016-06-15 10:42 ` Bart Van Assche
2016-06-15 10:42 ` Bart Van Assche
2016-06-15 15:14 ` Keith Busch
2016-06-15 15:14 ` Keith Busch
2016-06-15 15:28 ` Bart Van Assche
2016-06-15 15:28 ` Bart Van Assche
2016-06-15 16:03 ` Keith Busch
2016-06-15 16:03 ` Keith Busch
2016-06-15 19:36 ` Bart Van Assche
2016-06-15 19:36 ` Bart Van Assche
2016-06-15 20:06 ` Keith Busch
2016-06-15 20:06 ` Keith Busch
2016-06-15 20:12 ` Keith Busch
2016-06-15 20:12 ` Keith Busch
2016-06-15 20:50 ` Bart Van Assche
2016-06-15 20:50 ` Bart Van Assche
2016-06-16 15:19 ` Keith Busch
2016-06-16 15:19 ` Keith Busch
2016-06-22 11:56 ` Alexander Gordeev
2016-06-22 11:56 ` Alexander Gordeev
2016-06-22 11:56 ` Alexander Gordeev
2016-06-16 15:20 ` Christoph Hellwig
2016-06-16 15:20 ` Christoph Hellwig
2016-06-16 15:39 ` Bart Van Assche
2016-06-16 15:39 ` Bart Van Assche
2016-06-20 12:22 ` Christoph Hellwig
2016-06-20 12:22 ` Christoph Hellwig
2016-06-20 12:22 ` Christoph Hellwig
2016-06-20 13:21 ` Bart Van Assche
2016-06-20 13:21 ` Bart Van Assche
2016-06-20 13:21 ` Bart Van Assche
2016-06-21 14:31 ` Christoph Hellwig
2016-06-21 14:31 ` Christoph Hellwig
2016-06-21 14:31 ` Christoph Hellwig
2016-06-16 9:08 ` Bart Van Assche
2016-06-16 9:08 ` Bart Van Assche
2016-06-14 19:58 ` [PATCH 03/13] irq: Add affinity hint to irq allocation Christoph Hellwig
2016-06-14 19:58 ` Christoph Hellwig
2016-06-14 19:58 ` Christoph Hellwig
2016-06-14 19:58 ` [PATCH 04/13] irq: Use affinity hint in irqdesc allocation Christoph Hellwig
2016-06-14 19:58 ` Christoph Hellwig
2016-06-14 19:58 ` Christoph Hellwig
2016-06-14 19:58 ` [PATCH 05/13] irq/msi: Make use of affinity aware allocations Christoph Hellwig
2016-06-14 19:58 ` Christoph Hellwig
2016-06-14 19:58 ` Christoph Hellwig
2016-06-14 19:58 ` [PATCH 06/13] irq: add a helper spread an affinity mask for MSI/MSI-X vectors Christoph Hellwig
2016-06-14 19:58 ` Christoph Hellwig
2016-06-14 19:58 ` Christoph Hellwig
2016-06-14 21:54 ` Guilherme G. Piccoli
2016-06-14 21:54 ` Guilherme G. Piccoli
2016-06-15 8:35 ` Bart Van Assche
2016-06-15 8:35 ` Bart Van Assche
2016-06-15 8:35 ` Bart Van Assche
2016-06-15 10:10 ` Christoph Hellwig
2016-06-15 10:10 ` Christoph Hellwig
2016-06-15 13:09 ` Guilherme G. Piccoli
2016-06-15 13:09 ` Guilherme G. Piccoli
2016-06-16 15:16 ` Christoph Hellwig
2016-06-16 15:16 ` Christoph Hellwig
2016-06-25 20:05 ` Alexander Gordeev
2016-06-25 20:05 ` Alexander Gordeev
2016-06-30 17:48 ` Christoph Hellwig
2016-06-30 17:48 ` Christoph Hellwig
2016-06-30 17:48 ` Christoph Hellwig
2016-07-01 7:25 ` Alexander Gordeev
2016-07-01 7:25 ` Alexander Gordeev
2016-06-14 19:59 ` [PATCH 07/13] pci: Provide sensible irq vector alloc/free routines Christoph Hellwig
2016-06-14 19:59 ` Christoph Hellwig
2016-06-14 19:59 ` Christoph Hellwig
2016-06-23 11:16 ` Alexander Gordeev
2016-06-23 11:16 ` Alexander Gordeev
2016-06-30 16:54 ` Christoph Hellwig
2016-06-30 16:54 ` Christoph Hellwig
2016-06-30 17:28 ` Alexander Gordeev
2016-06-30 17:28 ` Alexander Gordeev
2016-06-30 17:35 ` Christoph Hellwig
2016-06-30 17:35 ` Christoph Hellwig
2016-06-14 19:59 ` [PATCH 08/13] pci: spread interrupt vectors in pci_alloc_irq_vectors Christoph Hellwig
2016-06-14 19:59 ` Christoph Hellwig
2016-06-14 19:59 ` Christoph Hellwig
2016-06-25 20:22 ` Alexander Gordeev
2016-06-25 20:22 ` Alexander Gordeev
2016-06-14 19:59 ` [PATCH 09/13] blk-mq: don't redistribute hardware queues on a CPU hotplug event Christoph Hellwig
2016-06-14 19:59 ` Christoph Hellwig
2016-06-14 19:59 ` Christoph Hellwig
2016-06-14 19:59 ` [PATCH 10/13] blk-mq: only allocate a single mq_map per tag_set Christoph Hellwig
2016-06-14 19:59 ` Christoph Hellwig
2016-06-14 19:59 ` Christoph Hellwig
2016-06-14 19:59 ` [PATCH 11/13] blk-mq: allow the driver to pass in an affinity mask Christoph Hellwig
2016-06-14 19:59 ` Christoph Hellwig
2016-06-14 19:59 ` Christoph Hellwig
2016-07-04 8:15 ` Alexander Gordeev
2016-07-04 8:15 ` Alexander Gordeev
2016-07-04 8:38 ` Christoph Hellwig
2016-07-04 8:38 ` Christoph Hellwig
2016-07-04 9:35 ` Alexander Gordeev
2016-07-04 9:35 ` Alexander Gordeev
2016-07-10 3:41 ` Christoph Hellwig
2016-07-10 3:41 ` Christoph Hellwig
2016-07-12 6:42 ` Alexander Gordeev
2016-07-12 6:42 ` Alexander Gordeev
2016-06-14 19:59 ` [PATCH 12/13] nvme: switch to use pci_alloc_irq_vectors Christoph Hellwig
2016-06-14 19:59 ` Christoph Hellwig
2016-06-14 19:59 ` Christoph Hellwig
2016-06-14 19:59 ` [PATCH 13/13] nvme: remove the post_scan callout Christoph Hellwig
2016-06-14 19:59 ` Christoph Hellwig
2016-06-14 19:59 ` Christoph Hellwig
2016-06-16 9:45 ` Bart Van Assche [this message]
2016-06-16 9:45 ` automatic interrupt affinity for MSI/MSI-X capable devices V2 Bart Van Assche
2016-06-16 9:45 ` Bart Van Assche
2016-06-16 15:22 ` Christoph Hellwig
2016-06-16 15:22 ` Christoph Hellwig
2016-06-26 19:40 ` Alexander Gordeev
2016-06-26 19:40 ` Alexander Gordeev
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