From: Mikko Perttunen <cyndis@kapsi.fi>
To: Krishna Reddy <vdumpa@nvidia.com>
Cc: linux-arm-kernel@lists.infradead.org,
iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
linux-tegra@vger.kernel.org, treding@nvidia.com, yhsu@nvidia.com,
snikam@nvidia.com, praithatha@nvidia.com, talho@nvidia.com,
avanbrunt@nvidia.com, thomasz@nvidia.com, olof@lixom.net,
jtukkinen@nvidia.com, mperttunen@nvidia.com
Subject: Re: [PATCH 6/7] arm64: tegra: Add DT node for T194 SMMU
Date: Fri, 30 Aug 2019 15:09:32 +0300 [thread overview]
Message-ID: <ba06d6b8-c6b9-f9bd-c2c1-d5e39292f67d@kapsi.fi> (raw)
In-Reply-To: <1567118827-26358-7-git-send-email-vdumpa@nvidia.com>
On 30.8.2019 1.47, Krishna Reddy wrote:
> Add DT node for T194 SMMU to enable SMMU support.
>
> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 75 ++++++++++++++++++++++++++++++++
> 1 file changed, 75 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index d906958..ad509bb 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -1401,6 +1401,81 @@
> 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
> };
>
> + smmu: iommu@12000000 {
> + compatible = "nvidia,smmu-v2";
Should we have a compatibility string like "nvidia,tegra194-smmu" so
that we can have other chips with SMMUv2 that could be different?
Mikko
> + reg = <0 0x12000000 0 0x800000>,
> + <0 0x11000000 0 0x800000>,
> + <0 0x10000000 0 0x800000>;
> + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
> + stream-match-mask = <0x7f80>;
> + #global-interrupts = <1>;
> + #iommu-cells = <1>;
> + };
> +
> sysram@40000000 {
> compatible = "nvidia,tegra194-sysram", "mmio-sram";
> reg = <0x0 0x40000000 0x0 0x50000>;
>
WARNING: multiple messages have this Message-ID (diff)
From: Mikko Perttunen <cyndis@kapsi.fi>
To: Krishna Reddy <vdumpa@nvidia.com>
Cc: snikam@nvidia.com, thomasz@nvidia.com, jtukkinen@nvidia.com,
mperttunen@nvidia.com, praithatha@nvidia.com,
iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
talho@nvidia.com, yhsu@nvidia.com, linux-tegra@vger.kernel.org,
treding@nvidia.com, avanbrunt@nvidia.com,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 6/7] arm64: tegra: Add DT node for T194 SMMU
Date: Fri, 30 Aug 2019 15:09:32 +0300 [thread overview]
Message-ID: <ba06d6b8-c6b9-f9bd-c2c1-d5e39292f67d@kapsi.fi> (raw)
In-Reply-To: <1567118827-26358-7-git-send-email-vdumpa@nvidia.com>
On 30.8.2019 1.47, Krishna Reddy wrote:
> Add DT node for T194 SMMU to enable SMMU support.
>
> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 75 ++++++++++++++++++++++++++++++++
> 1 file changed, 75 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index d906958..ad509bb 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -1401,6 +1401,81 @@
> 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
> };
>
> + smmu: iommu@12000000 {
> + compatible = "nvidia,smmu-v2";
Should we have a compatibility string like "nvidia,tegra194-smmu" so
that we can have other chips with SMMUv2 that could be different?
Mikko
> + reg = <0 0x12000000 0 0x800000>,
> + <0 0x11000000 0 0x800000>,
> + <0 0x10000000 0 0x800000>;
> + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
> + stream-match-mask = <0x7f80>;
> + #global-interrupts = <1>;
> + #iommu-cells = <1>;
> + };
> +
> sysram@40000000 {
> compatible = "nvidia,tegra194-sysram", "mmio-sram";
> reg = <0x0 0x40000000 0x0 0x50000>;
>
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Mikko Perttunen <cyndis@kapsi.fi>
To: Krishna Reddy <vdumpa@nvidia.com>
Cc: snikam@nvidia.com, thomasz@nvidia.com, jtukkinen@nvidia.com,
mperttunen@nvidia.com, praithatha@nvidia.com,
iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
talho@nvidia.com, olof@lixom.net, yhsu@nvidia.com,
linux-tegra@vger.kernel.org, treding@nvidia.com,
avanbrunt@nvidia.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 6/7] arm64: tegra: Add DT node for T194 SMMU
Date: Fri, 30 Aug 2019 15:09:32 +0300 [thread overview]
Message-ID: <ba06d6b8-c6b9-f9bd-c2c1-d5e39292f67d@kapsi.fi> (raw)
In-Reply-To: <1567118827-26358-7-git-send-email-vdumpa@nvidia.com>
On 30.8.2019 1.47, Krishna Reddy wrote:
> Add DT node for T194 SMMU to enable SMMU support.
>
> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 75 ++++++++++++++++++++++++++++++++
> 1 file changed, 75 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index d906958..ad509bb 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -1401,6 +1401,81 @@
> 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
> };
>
> + smmu: iommu@12000000 {
> + compatible = "nvidia,smmu-v2";
Should we have a compatibility string like "nvidia,tegra194-smmu" so
that we can have other chips with SMMUv2 that could be different?
Mikko
> + reg = <0 0x12000000 0 0x800000>,
> + <0 0x11000000 0 0x800000>,
> + <0 0x10000000 0 0x800000>;
> + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
> + stream-match-mask = <0x7f80>;
> + #global-interrupts = <1>;
> + #iommu-cells = <1>;
> + };
> +
> sysram@40000000 {
> compatible = "nvidia,tegra194-sysram", "mmio-sram";
> reg = <0x0 0x40000000 0x0 0x50000>;
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-08-30 12:09 UTC|newest]
Thread overview: 122+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-29 22:47 [PATCH 0/7] Nvidia Arm SMMUv2 Implementation Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-29 22:47 ` [PATCH 1/7] iommu/arm-smmu: add Nvidia SMMUv2 implementation Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-30 15:02 ` Robin Murphy
2019-08-30 15:02 ` Robin Murphy
2019-08-30 15:02 ` Robin Murphy
2019-08-30 18:16 ` Krishna Reddy
2019-08-30 18:16 ` Krishna Reddy
2019-08-30 18:16 ` Krishna Reddy
2019-08-30 18:16 ` Krishna Reddy
[not found] ` <BYAPR12MB2710D045303BE89A7D3FF2C1B3BD0-ZGDeBxoHBPnlX2Hc6Vgn3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-09-02 13:39 ` Robin Murphy
2019-09-02 13:39 ` Robin Murphy
2019-09-02 13:39 ` Robin Murphy
2019-09-02 13:39 ` Robin Murphy
2019-09-03 1:07 ` Krishna Reddy
2019-09-03 1:07 ` Krishna Reddy
2019-09-03 1:07 ` Krishna Reddy
2019-09-03 1:07 ` Krishna Reddy
2019-08-29 22:47 ` [PATCH 2/7] dt-bindings: arm-smmu: Add binding for nvidia,smmu-v2 Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-30 12:07 ` Mikko Perttunen
2019-08-30 12:07 ` [PATCH 2/7] dt-bindings: arm-smmu: Add binding for nvidia, smmu-v2 Mikko Perttunen
2019-08-30 12:07 ` Mikko Perttunen
2019-08-30 15:13 ` [PATCH 2/7] dt-bindings: arm-smmu: Add binding for nvidia,smmu-v2 Robin Murphy
2019-08-30 15:13 ` [PATCH 2/7] dt-bindings: arm-smmu: Add binding for nvidia, smmu-v2 Robin Murphy
2019-08-30 15:13 ` Robin Murphy
2019-08-30 18:12 ` [PATCH 2/7] dt-bindings: arm-smmu: Add binding for nvidia,smmu-v2 Krishna Reddy
2019-08-30 18:12 ` [PATCH 2/7] dt-bindings: arm-smmu: Add binding for nvidia, smmu-v2 Krishna Reddy
2019-08-30 18:12 ` Krishna Reddy
2019-08-30 18:12 ` [PATCH 2/7] dt-bindings: arm-smmu: Add binding for nvidia,smmu-v2 Krishna Reddy
2019-09-02 7:38 ` Thierry Reding
2019-09-02 7:38 ` [PATCH 2/7] dt-bindings: arm-smmu: Add binding for nvidia, smmu-v2 Thierry Reding
2019-09-02 7:38 ` Thierry Reding
2019-09-02 7:38 ` [PATCH 2/7] dt-bindings: arm-smmu: Add binding for nvidia,smmu-v2 Thierry Reding
2019-08-29 22:47 ` [PATCH 3/7] iommu/arm-smmu: Add tlb_sync implementation hook Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-30 11:14 ` Thierry Reding
2019-08-30 11:14 ` Thierry Reding
2019-08-30 11:14 ` Thierry Reding
2019-08-30 19:00 ` Krishna Reddy
2019-08-30 19:00 ` Krishna Reddy
2019-08-30 19:00 ` Krishna Reddy
2019-08-30 19:00 ` Krishna Reddy
2019-08-30 15:23 ` Robin Murphy
2019-08-30 15:23 ` Robin Murphy
2019-08-30 15:23 ` Robin Murphy
2019-08-30 18:05 ` Krishna Reddy
2019-08-30 18:05 ` Krishna Reddy
2019-08-30 18:05 ` Krishna Reddy
2019-08-30 18:05 ` Krishna Reddy
2019-08-30 22:49 ` Krishna Reddy
2019-08-30 22:49 ` Krishna Reddy
2019-08-30 22:49 ` Krishna Reddy
2019-08-30 22:49 ` Krishna Reddy
2019-09-02 13:00 ` Robin Murphy
2019-09-02 13:00 ` Robin Murphy
2019-09-02 13:00 ` Robin Murphy
2019-09-02 13:00 ` Robin Murphy
2019-08-29 22:47 ` [PATCH 4/7] iommu/arm-smmu: Add global/context fault implementation hooks Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-30 11:17 ` Thierry Reding
2019-08-30 11:17 ` Thierry Reding
2019-08-30 11:17 ` Thierry Reding
2019-08-30 19:16 ` Krishna Reddy
2019-08-30 19:16 ` Krishna Reddy
2019-08-30 19:16 ` Krishna Reddy
2019-08-30 19:16 ` Krishna Reddy
2019-08-30 15:43 ` Robin Murphy
2019-08-30 15:43 ` Robin Murphy
2019-08-30 15:43 ` Robin Murphy
2019-08-30 17:43 ` Krishna Reddy
2019-08-30 17:43 ` Krishna Reddy
2019-08-30 17:43 ` Krishna Reddy
2019-08-30 17:43 ` Krishna Reddy
2019-08-29 22:47 ` [PATCH 5/7] arm64: tegra: Add Memory controller DT node on T194 Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-30 11:18 ` Thierry Reding
2019-08-30 11:18 ` Thierry Reding
2019-08-30 11:18 ` Thierry Reding
2019-08-29 22:47 ` [PATCH 6/7] arm64: tegra: Add DT node for T194 SMMU Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-30 12:09 ` Mikko Perttunen [this message]
2019-08-30 12:09 ` Mikko Perttunen
2019-08-30 12:09 ` Mikko Perttunen
2019-08-30 18:39 ` Krishna Reddy
2019-08-30 18:39 ` Krishna Reddy
2019-08-30 18:39 ` Krishna Reddy
2019-08-30 18:39 ` Krishna Reddy
2019-08-30 15:44 ` Robin Murphy
2019-08-30 15:44 ` Robin Murphy
2019-08-30 15:44 ` Robin Murphy
2019-08-30 17:25 ` Krishna Reddy
2019-08-30 17:25 ` Krishna Reddy
2019-08-30 17:25 ` Krishna Reddy
2019-08-30 17:25 ` Krishna Reddy
2019-08-30 17:45 ` Robin Murphy
2019-08-30 17:45 ` Robin Murphy
2019-08-30 17:45 ` Robin Murphy
2019-08-30 17:45 ` Robin Murphy
2019-08-30 18:35 ` Krishna Reddy
2019-08-30 18:35 ` Krishna Reddy
2019-08-30 18:35 ` Krishna Reddy
2019-08-30 18:35 ` Krishna Reddy
2019-08-29 22:47 ` [PATCH 7/7] arm64: tegra: enable SMMU for SDHCI and EQOS Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
2019-08-29 22:47 ` Krishna Reddy
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