[cip-dev] [PATCH 4.19.y-cip 00/10] Add support for [H]SCIF/SDHI/I2C/RWDT/MSIOF

[cip-dev] [PATCH 4.19.y-cip 00/10] Add support for [H]SCIF/SDHI/I2C/RWDT/MSIOF

[Biju Das]

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Add RZ/G2H SoC support for [H]SCIF/SDHI/I2C/RWDT/MSIOF on 4.19.y-cip kernel.

All the patches in this series are cherry-piced from ML, except [1] which is 
a new patch similar to the workdone for other similar SoC's

[1] mmc: renesas_sdhi_internal_dmac: Add r8a774e1 support

This patch series depend on [2]
[2] https://patchwork.kernel.org/project/cip-dev/list/?series=338235

Biju Das (1):
  mmc: renesas_sdhi_internal_dmac: Add r8a774e1 support

Lad Prabhakar (9):
  arm64: dts: renesas: r8a774e1: Add SCIF and HSCIF nodes
  arm64: dts: renesas: r8a774e1: Add SDHI nodes
  dt-bindings: i2c: renesas,i2c: Document r8a774e1 support
  dt-bindings: i2c: renesas,iic: Document r8a774e1 support
  arm64: dts: renesas: r8a774e1: Add I2C and IIC-DVFS support
  spi: renesas,sh-msiof: Add r8a774e1 support
  arm64: dts: renesas: r8a774e1: Add MSIOF nodes
  dt-bindings: watchdog: renesas,wdt: Document r8a774e1 support
  arm64: dts: renesas: r8a774e1: Add RWDT node

 .../devicetree/bindings/i2c/renesas,i2c.txt   |   1 +
 .../devicetree/bindings/i2c/renesas,iic.txt   |   1 +
 .../devicetree/bindings/spi/sh-msiof.txt      |   1 +
 .../bindings/watchdog/renesas,wdt.txt         |   1 +
 arch/arm64/boot/dts/renesas/r8a774e1.dtsi     | 390 +++++++++++++++++-
 drivers/mmc/host/renesas_sdhi_internal_dmac.c |   1 +
 6 files changed, 386 insertions(+), 9 deletions(-)

-- 
2.17.1


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[cip-dev] [PATCH 4.19.y-cip 01/10] arm64: dts: renesas: r8a774e1: Add SCIF and HSCIF nodes

[Biju Das]

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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit b9b491a70402f21eb47c10910438c9e0d10a0e17 upstream.

Add the device nodes for RZ/G2H SCIF and HSCIF serial ports,
including clocks, power domains and DMAs.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1594811350-14066-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 169 +++++++++++++++++++++-
 1 file changed, 168 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index af090cd90f5d..12e11bed3da8 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -633,10 +633,91 @@
 		};
 
 		hscif0: serial@e6540000 {
+			compatible = "renesas,hscif-r8a774e1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
 			reg = <0 0xe6540000 0 0x60>;
+			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 520>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+			       <&dmac2 0x31>, <&dmac2 0x30>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 520>;
 			status = "disabled";
+		};
 
-			/* placeholder */
+		hscif1: serial@e6550000 {
+			compatible = "renesas,hscif-r8a774e1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6550000 0 0x60>;
+			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 519>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+			       <&dmac2 0x33>, <&dmac2 0x32>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 519>;
+			status = "disabled";
+		};
+
+		hscif2: serial@e6560000 {
+			compatible = "renesas,hscif-r8a774e1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6560000 0 0x60>;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 518>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+			       <&dmac2 0x35>, <&dmac2 0x34>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 518>;
+			status = "disabled";
+		};
+
+		hscif3: serial@e66a0000 {
+			compatible = "renesas,hscif-r8a774e1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe66a0000 0 0x60>;
+			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 517>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 517>;
+			status = "disabled";
+		};
+
+		hscif4: serial@e66b0000 {
+			compatible = "renesas,hscif-r8a774e1",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe66b0000 0 0x60>;
+			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 516>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x39>, <&dmac0 0x38>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 516>;
+			status = "disabled";
 		};
 
 		hsusb: usb@e6590000 {
@@ -1012,6 +1093,40 @@
 			/* placeholder */
 		};
 
+		scif0: serial@e6e60000 {
+			compatible = "renesas,scif-r8a774e1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6e60000 0 0x40>;
+			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 207>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+			       <&dmac2 0x51>, <&dmac2 0x50>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 207>;
+			status = "disabled";
+		};
+
+		scif1: serial@e6e68000 {
+			compatible = "renesas,scif-r8a774e1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6e68000 0 0x40>;
+			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 206>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+			       <&dmac2 0x53>, <&dmac2 0x52>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 206>;
+			status = "disabled";
+		};
+
 		scif2: serial@e6e88000 {
 			compatible = "renesas,scif-r8a774e1",
 				     "renesas,rcar-gen3-scif", "renesas,scif";
@@ -1021,11 +1136,63 @@
 				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
 				 <&scif_clk>;
 			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x13>, <&dmac1 0x12>,
+			       <&dmac2 0x13>, <&dmac2 0x12>;
+			dma-names = "tx", "rx", "tx", "rx";
 			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 			resets = <&cpg 310>;
 			status = "disabled";
 		};
 
+		scif3: serial@e6c50000 {
+			compatible = "renesas,scif-r8a774e1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6c50000 0 0x40>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 204>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 204>;
+			status = "disabled";
+		};
+
+		scif4: serial@e6c40000 {
+			compatible = "renesas,scif-r8a774e1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6c40000 0 0x40>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 203>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 203>;
+			status = "disabled";
+		};
+
+		scif5: serial@e6f30000 {
+			compatible = "renesas,scif-r8a774e1",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6f30000 0 0x40>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 202>,
+				 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
+			       <&dmac2 0x5b>, <&dmac2 0x5a>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 202>;
+			status = "disabled";
+		};
+
 		rcar_sound: sound@ec500000 {
 			reg = <0 0xec500000 0 0x1000>, /* SCU */
 			      <0 0xec5a0000 0 0x100>,  /* ADG */
-- 
2.17.1


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[cip-dev] [PATCH 4.19.y-cip 02/10] mmc: renesas_sdhi_internal_dmac: Add r8a774e1 support

[Biju Das]

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This patch adds SDHI support for RZ/G2H (R8A774E1) SoC.
Based on the work done for R8A7795 SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/mmc/host/renesas_sdhi_internal_dmac.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
index d15615852de6..a492e226a262 100644
--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -302,6 +302,7 @@ static const struct soc_device_attribute gen3_soc_whitelist[] = {
 	{ .soc_id = "r8a774a1" },
 	{ .soc_id = "r8a774b1" },
 	{ .soc_id = "r8a774c0" },
+	{ .soc_id = "r8a774e1" },
 	{ .soc_id = "r8a7795" },
 	{ .soc_id = "r8a7796" },
 	{ .soc_id = "r8a77965" },
-- 
2.17.1


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[cip-dev] [PATCH 4.19.y-cip 03/10] arm64: dts: renesas: r8a774e1: Add SDHI nodes

[Biju Das]

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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 31941342888d4fa008fb27cef9d4ae5913df8792 upstream.

Add SDHI[0-2] device nodes to R8A774E1 SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1594811350-14066-11-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 32 ++++++++++++++++++++---
 1 file changed, 29 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 12e11bed3da8..838f8f0440cf 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1269,17 +1269,42 @@
 		};
 
 		sdhi0: mmc@ee100000 {
+			compatible = "renesas,sdhi-r8a774e1",
+				     "renesas,rcar-gen3-sdhi";
 			reg = <0 0xee100000 0 0x2000>;
+			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 314>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 314>;
+			iommus = <&ipmmu_ds1 32>;
 			status = "disabled";
+		};
 
-			/* placeholder */
+		sdhi1: mmc@ee120000 {
+			compatible = "renesas,sdhi-r8a774e1",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0 0xee120000 0 0x2000>;
+			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 313>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 313>;
+			iommus = <&ipmmu_ds1 33>;
+			status = "disabled";
 		};
 
 		sdhi2: mmc@ee140000 {
+			compatible = "renesas,sdhi-r8a774e1",
+				     "renesas,rcar-gen3-sdhi";
 			reg = <0 0xee140000 0 0x2000>;
+			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 312>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 312>;
+			iommus = <&ipmmu_ds1 34>;
 			status = "disabled";
-
-			/* placeholder */
 		};
 
 		sdhi3: mmc@ee160000 {
@@ -1291,6 +1316,7 @@
 			max-frequency = <200000000>;
 			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 			resets = <&cpg 311>;
+			iommus = <&ipmmu_ds1 35>;
 			status = "disabled";
 		};
 
-- 
2.17.1


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[cip-dev] [PATCH 4.19.y-cip 04/10] dt-bindings: i2c: renesas,i2c: Document r8a774e1 support

[Biju Das]

[-- Attachment #1: Type: text/plain, Size: 1470 bytes --]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 471fb8c55c24a1b50a07d7708aa2d7c202ec896e upstream.

Document i2c controller for RZ/G2H (R8A774E1) SoC, which is compatible
with R-Car Gen3 SoC family.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 Documentation/devicetree/bindings/i2c/renesas,i2c.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/i2c/renesas,i2c.txt b/Documentation/devicetree/bindings/i2c/renesas,i2c.txt
index efb1c11e3c30..fe0ecbfd9078 100644
--- a/Documentation/devicetree/bindings/i2c/renesas,i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/renesas,i2c.txt
@@ -7,6 +7,7 @@ Required properties:
 	"renesas,i2c-r8a774a1" if the device is a part of a R8A774A1 SoC.
 	"renesas,i2c-r8a774b1" if the device is a part of a R8A774B1 SoC.
 	"renesas,i2c-r8a774c0" if the device is a part of a R8A774C0 SoC.
+	"renesas,i2c-r8a774e1" if the device is a part of a R8A774E1 SoC.
 	"renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC.
 	"renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC.
 	"renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC.
-- 
2.17.1


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[cip-dev] [PATCH 4.19.y-cip 05/10] dt-bindings: i2c: renesas,iic: Document r8a774e1 support

[Biju Das]

[-- Attachment #1: Type: text/plain, Size: 1272 bytes --]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 99f0975d760b6320dd5490bd0bc3a31900284757 upstream.

Document IIC controller for RZ/G2H (R8A774E1) SoC, which is compatible
with R-Car Gen3 SoC family.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 Documentation/devicetree/bindings/i2c/renesas,iic.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/i2c/renesas,iic.txt b/Documentation/devicetree/bindings/i2c/renesas,iic.txt
index a139e58c180e..60985537ab68 100644
--- a/Documentation/devicetree/bindings/i2c/renesas,iic.txt
+++ b/Documentation/devicetree/bindings/i2c/renesas,iic.txt
@@ -9,6 +9,7 @@ Required properties:
 			- "renesas,iic-r8a774a1" (RZ/G2M)
 			- "renesas,iic-r8a774b1" (RZ/G2N)
 			- "renesas,iic-r8a774c0" (RZ/G2E)
+			- "renesas,iic-r8a774e1" (RZ/G2H)
 			- "renesas,iic-r8a7790" (R-Car H2)
 			- "renesas,iic-r8a7791" (R-Car M2-W)
 			- "renesas,iic-r8a7792" (R-Car V2H)
-- 
2.17.1


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[cip-dev] [PATCH 4.19.y-cip 06/10] arm64: dts: renesas: r8a774e1: Add I2C and IIC-DVFS support

[Biju Das]

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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 950a3a7951cdeb908798a49d57e5303ad7afd05a upstream.

Add the I2C[0-6] and IIC Bus Interface for DVFS (IIC for DVFS)
devices nodes to the r8a774e1 device tree.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1594811350-14066-14-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 119 +++++++++++++++++++++-
 1 file changed, 116 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 838f8f0440cf..f4d4a2a4e725 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -614,22 +614,135 @@
 			status = "disabled";
 		};
 
+		i2c0: i2c@e6500000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774e1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe6500000 0 0x40>;
+			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 931>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 931>;
+			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+			       <&dmac2 0x91>, <&dmac2 0x90>;
+			dma-names = "tx", "rx", "tx", "rx";
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@e6508000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774e1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe6508000 0 0x40>;
+			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 930>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 930>;
+			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+			       <&dmac2 0x93>, <&dmac2 0x92>;
+			dma-names = "tx", "rx", "tx", "rx";
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
 		i2c2: i2c@e6510000 {
-			reg = <0 0xe6510000 0 0x40>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774e1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe6510000 0 0x40>;
+			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 929>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 929>;
+			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+			       <&dmac2 0x95>, <&dmac2 0x94>;
+			dma-names = "tx", "rx", "tx", "rx";
+			i2c-scl-internal-delay-ns = <6>;
 			status = "disabled";
+		};
 
-			/* placeholder */
+		i2c3: i2c@e66d0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774e1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66d0000 0 0x40>;
+			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 928>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 928>;
+			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
 		};
 
 		i2c4: i2c@e66d8000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774e1",
+				     "renesas,rcar-gen3-i2c";
 			reg = <0 0xe66d8000 0 0x40>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 927>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 927>;
+			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <110>;
 			status = "disabled";
+		};
 
-			/* placeholder */
+		i2c5: i2c@e66e0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774e1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66e0000 0 0x40>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 919>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 919>;
+			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <110>;
+			status = "disabled";
+		};
+
+		i2c6: i2c@e66e8000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,i2c-r8a774e1",
+				     "renesas,rcar-gen3-i2c";
+			reg = <0 0xe66e8000 0 0x40>;
+			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 918>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 918>;
+			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
+			dma-names = "tx", "rx";
+			i2c-scl-internal-delay-ns = <6>;
+			status = "disabled";
+		};
+
+		i2c_dvfs: i2c@e60b0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,iic-r8a774e1",
+				     "renesas,rcar-gen3-iic",
+				     "renesas,rmobile-iic";
+			reg = <0 0xe60b0000 0 0x425>;
+			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 926>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 926>;
+			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
+			dma-names = "tx", "rx";
+			status = "disabled";
 		};
 
 		hscif0: serial@e6540000 {
-- 
2.17.1


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[cip-dev] [PATCH 4.19.y-cip 07/10] spi: renesas,sh-msiof: Add r8a774e1 support

[Biju Das]

[-- Attachment #1: Type: text/plain, Size: 1321 bytes --]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit b4f7f5f5470588e45e5d004f1dc4887af20f18c0 upstream.

Document RZ/G2H (R8A774E1) SoC bindings.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/1594811350-14066-15-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
[biju: Patched text version of bindings file]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 Documentation/devicetree/bindings/spi/sh-msiof.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt
index 5d6360dc8e51..ed6a9b407a0a 100644
--- a/Documentation/devicetree/bindings/spi/sh-msiof.txt
+++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt
@@ -6,6 +6,7 @@ Required properties:
 			 "renesas,msiof-r8a774a1" (RZ/G2M)
 			 "renesas,msiof-r8a774b1" (RZ/G2N)
 			 "renesas,msiof-r8a774c0" (RZ/G2E)
+			 "renesas,msiof-r8a774e1" (RZ/G2H)
 			 "renesas,msiof-r8a7790" (R-Car H2)
 			 "renesas,msiof-r8a7791" (R-Car M2-W)
 			 "renesas,msiof-r8a7792" (R-Car V2H)
-- 
2.17.1


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[cip-dev] [PATCH 4.19.y-cip 08/10] arm64: dts: renesas: r8a774e1: Add MSIOF nodes

[Biju Das]

[-- Attachment #1: Type: text/plain, Size: 3016 bytes --]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 05c79a8f0c843dfaae09cfde338c5e570f3d9b6b upstream.

Add the DT nodes needed by MSIOF[0123] interfaces to the SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1594811350-14066-16-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 62 +++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index f4d4a2a4e725..372f89e55887 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1306,6 +1306,68 @@
 			status = "disabled";
 		};
 
+		msiof0: spi@e6e90000 {
+			compatible = "renesas,msiof-r8a774e1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6e90000 0 0x0064>;
+			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 211>;
+			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
+			       <&dmac2 0x41>, <&dmac2 0x40>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 211>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof1: spi@e6ea0000 {
+			compatible = "renesas,msiof-r8a774e1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6ea0000 0 0x0064>;
+			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 210>;
+			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
+			       <&dmac2 0x43>, <&dmac2 0x42>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 210>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof2: spi@e6c00000 {
+			compatible = "renesas,msiof-r8a774e1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6c00000 0 0x0064>;
+			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 209>;
+			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 209>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof3: spi@e6c10000 {
+			compatible = "renesas,msiof-r8a774e1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6c10000 0 0x0064>;
+			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 208>;
+			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 208>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		rcar_sound: sound@ec500000 {
 			reg = <0 0xec500000 0 0x1000>, /* SCU */
 			      <0 0xec5a0000 0 0x100>,  /* ADG */
-- 
2.17.1


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[cip-dev] [PATCH 4.19.y-cip 09/10] dt-bindings: watchdog: renesas,wdt: Document r8a774e1 support

[Biju Das]

[-- Attachment #1: Type: text/plain, Size: 1525 bytes --]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit d821ab28dfd2fa85a9aed133e9bfd368c156cc04 upstream.

RZ/G2H (a.k.a. R8A774E1) watchdog implementation is compatible
with R-Car Gen3, therefore add the relevant documentation.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1594811350-14066-17-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
[biju: Patched text version of bindings file]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 Documentation/devicetree/bindings/watchdog/renesas,wdt.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
index 71f419d5c0c3..e673059667c3 100644
--- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
@@ -10,6 +10,7 @@ Required properties:
 		 - "renesas,r8a774a1-wdt" (RZ/G2M)
 		 - "renesas,r8a774b1-wdt" (RZ/G2N)
 		 - "renesas,r8a774c0-wdt" (RZ/G2E)
+		 - "renesas,r8a774e1-wdt" (RZ/G2H)
 	         - "renesas,r8a7790-wdt" (R-Car H2)
 	         - "renesas,r8a7791-wdt" (R-Car M2-W)
 	         - "renesas,r8a7792-wdt" (R-Car V2H)
-- 
2.17.1


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[cip-dev] [PATCH 4.19.y-cip 10/10] arm64: dts: renesas: r8a774e1: Add RWDT node

[Biju Das]

[-- Attachment #1: Type: text/plain, Size: 1366 bytes --]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 96ebdb7a87917fd6ee74f46024ca756cc3d3d1ce upstream.

Add a device node for the Watchdog Timer (RWDT) controller on the Renesas
RZ/G2H (r8a774e1) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1594811350-14066-18-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 372f89e55887..0f86cfd52425 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -297,10 +297,14 @@
 		ranges;
 
 		rwdt: watchdog@e6020000 {
+			compatible = "renesas,r8a774e1-wdt",
+				     "renesas,rcar-gen3-wdt";
 			reg = <0 0xe6020000 0 0x0c>;
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 402>;
+			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+			resets = <&cpg 402>;
 			status = "disabled";
-
-			/* placeholder */
 		};
 
 		gpio0: gpio@e6050000 {
-- 
2.17.1


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Re: [cip-dev] [PATCH 4.19.y-cip 00/10] Add support for [H]SCIF/SDHI/I2C/RWDT/MSIOF

[Pavel Machek]

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Hi!

> Add RZ/G2H SoC support for [H]SCIF/SDHI/I2C/RWDT/MSIOF on 4.19.y-cip kernel.
> 
> All the patches in this series are cherry-piced from ML, except [1] which is 
> a new patch similar to the workdone for other similar SoC's

Series looks good to me. (But gitlab testing does not seem to work,
and it would be good to test it before applying).

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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Re: [cip-dev] [PATCH 4.19.y-cip 00/10] Add support for [H]SCIF/SDHI/I2C/RWDT/MSIOF

[Biju Das]

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Hi Pavel,

Thanks for the feedback.

> Subject: Re: [PATCH 4.19.y-cip 00/10] Add support for
> [H]SCIF/SDHI/I2C/RWDT/MSIOF
>
> Hi!
>
> > Add RZ/G2H SoC support for [H]SCIF/SDHI/I2C/RWDT/MSIOF on 4.19.y-cip
> kernel.
> >
> > All the patches in this series are cherry-piced from ML, except [1]
> > which is a new patch similar to the workdone for other similar SoC's
>
> Series looks good to me. (But gitlab testing does not seem to work, and it
> would be good to test it before applying).

I am  not sure about the failure.  If it is related to testing on RZ/G2H board, then

I guess  RZ/G2H boards have enabled watchdog in u-boot with VLP 1.0.4.  So our RZ/G2H boards have enabled watchdog in u-boot.

The timeout is 60seconds. So if watchdog is not enabled in kernel or  Watchdog is enabled and there is no watchdog daemon, it will reboot after 60seconds.

In current case, watchdog is enabled by this series. So If you apply this series, then next thing you need to make sure is watchdog daemon is
running or stop the watchdog

or

For cip testing, we should disable watchdog in u-boot.

Cheers,
Biju




Renesas Electronics Europe GmbH, Geschaeftsfuehrer/President: Carsten Jauch, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany, Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647

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Re: [cip-dev] [PATCH 4.19.y-cip 00/10] Add support for [H]SCIF/SDHI/I2C/RWDT/MSIOF

[Pavel Machek]

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Hi!

> Thanks for the feedback.
> 
> > Subject: Re: [PATCH 4.19.y-cip 00/10] Add support for
> > [H]SCIF/SDHI/I2C/RWDT/MSIOF
> >
> > Hi!
> >
> > > Add RZ/G2H SoC support for [H]SCIF/SDHI/I2C/RWDT/MSIOF on 4.19.y-cip
> > kernel.
> > >
> > > All the patches in this series are cherry-piced from ML, except [1]
> > > which is a new patch similar to the workdone for other similar SoC's
> >
> > Series looks good to me. (But gitlab testing does not seem to work, and it
> > would be good to test it before applying).
> 
> I am  not sure about the failure.  If it is related to testing on RZ/G2H board, then

No, it is definitely not related to your boards. Nothing ever
builds... it can't be your fault or fault of your board, but it just
prevents testing :-(.

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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Re: [cip-dev] [PATCH 4.19.y-cip 00/10] Add support for [H]SCIF/SDHI/I2C/RWDT/MSIOF

[Biju Das]

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Hi Pavel,

Thanks for the feedback.

> Subject: Re: [PATCH 4.19.y-cip 00/10] Add support for
> [H]SCIF/SDHI/I2C/RWDT/MSIOF
>
> Hi!
>
> > Thanks for the feedback.
> >
> > > Subject: Re: [PATCH 4.19.y-cip 00/10] Add support for
> > > [H]SCIF/SDHI/I2C/RWDT/MSIOF
> > >
> > > Hi!
> > >
> > > > Add RZ/G2H SoC support for [H]SCIF/SDHI/I2C/RWDT/MSIOF on
> > > > 4.19.y-cip
> > > kernel.
> > > >
> > > > All the patches in this series are cherry-piced from ML, except
> > > > [1] which is a new patch similar to the workdone for other similar
> > > > SoC's
> > >
> > > Series looks good to me. (But gitlab testing does not seem to work,
> > > and it would be good to test it before applying).
> >
> > I am  not sure about the failure.  If it is related to testing on
> > RZ/G2H board, then
>
> No, it is definitely not related to your boards. Nothing ever builds... it can't be
> your fault or fault of your board, but it just prevents testing :-(.

I have applied the entire series and it builds fine in my environment with linux-4.19.y-cip(4.19.138-cip32).
What is the build issue related to gitlab testing?

Cheers,
Biju


Renesas Electronics Europe GmbH, Geschaeftsfuehrer/President: Carsten Jauch, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany, Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647

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Re: [cip-dev] [PATCH 4.19.y-cip 00/10] Add support for [H]SCIF/SDHI/I2C/RWDT/MSIOF

[Nobuhiro Iwamatsu]

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Hi,

> -----Original Message-----
> From: Biju Das [mailto:biju.das.jz@bp.renesas.com]
> Sent: Thursday, August 27, 2020 4:07 PM
> To: Pavel Machek <pavel@denx.de>
> Cc: Chris Paterson <Chris.Paterson2@renesas.com>; cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □Ｓ
> ＷＣ◯ＡＣＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: RE: [PATCH 4.19.y-cip 00/10] Add support for [H]SCIF/SDHI/I2C/RWDT/MSIOF
> 
> Hi Pavel,
> 
> Thanks for the feedback.
> 
> > Subject: Re: [PATCH 4.19.y-cip 00/10] Add support for
> > [H]SCIF/SDHI/I2C/RWDT/MSIOF
> >
> > Hi!
> >
> > > Thanks for the feedback.
> > >
> > > > Subject: Re: [PATCH 4.19.y-cip 00/10] Add support for
> > > > [H]SCIF/SDHI/I2C/RWDT/MSIOF
> > > >
> > > > Hi!
> > > >
> > > > > Add RZ/G2H SoC support for [H]SCIF/SDHI/I2C/RWDT/MSIOF on
> > > > > 4.19.y-cip
> > > > kernel.
> > > > >
> > > > > All the patches in this series are cherry-piced from ML, except
> > > > > [1] which is a new patch similar to the workdone for other similar
> > > > > SoC's
> > > >
> > > > Series looks good to me. (But gitlab testing does not seem to work,
> > > > and it would be good to test it before applying).
> > >
> > > I am  not sure about the failure.  If it is related to testing on
> > > RZ/G2H board, then
> >
> > No, it is definitely not related to your boards. Nothing ever builds... it can't be
> > your fault or fault of your board, but it just prevents testing :-(.
> 
> I have applied the entire series and it builds fine in my environment with linux-4.19.y-cip(4.19.138-cip32).
> What is the build issue related to gitlab testing?
> 
As I write other mail, this seems to be a issue in the environment that runs gitlab runner.

> Cheers,
> Biju
> 

Best regards,
  Nobuhiro

> 
> Renesas Electronics Europe GmbH, Geschaeftsfuehrer/President: Carsten Jauch, Sitz der Gesellschaft/Registered office:
> Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany, Handelsregister/Commercial Register: Duesseldorf, HRB 3708
> USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647

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Re: [cip-dev] [PATCH 4.19.y-cip 00/10] Add support for [H]SCIF/SDHI/I2C/RWDT/MSIOF

[Biju Das]

[-- Attachment #1: Type: text/plain, Size: 2414 bytes --]

Hi Nobuhiro,

Thanks for the feedback.

> Subject: RE: [PATCH 4.19.y-cip 00/10] Add support for
> [H]SCIF/SDHI/I2C/RWDT/MSIOF
>
> Hi,
>
> > -----Original Message-----
> > From: Biju Das [mailto:biju.das.jz@bp.renesas.com]
> > Sent: Thursday, August 27, 2020 4:07 PM
> > To: Pavel Machek <pavel@denx.de>
> > Cc: Chris Paterson <Chris.Paterson2@renesas.com>;
> > cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □Ｓ
> > ＷＣ◯ＡＣＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Prabhakar
> Mahadev Lad
> > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Subject: RE: [PATCH 4.19.y-cip 00/10] Add support for
> > [H]SCIF/SDHI/I2C/RWDT/MSIOF
> >
> > Hi Pavel,
> >
> > Thanks for the feedback.
> >
> > > Subject: Re: [PATCH 4.19.y-cip 00/10] Add support for
> > > [H]SCIF/SDHI/I2C/RWDT/MSIOF
> > >
> > > Hi!
> > >
> > > > Thanks for the feedback.
> > > >
> > > > > Subject: Re: [PATCH 4.19.y-cip 00/10] Add support for
> > > > > [H]SCIF/SDHI/I2C/RWDT/MSIOF
> > > > >
> > > > > Hi!
> > > > >
> > > > > > Add RZ/G2H SoC support for [H]SCIF/SDHI/I2C/RWDT/MSIOF on
> > > > > > 4.19.y-cip
> > > > > kernel.
> > > > > >
> > > > > > All the patches in this series are cherry-piced from ML,
> > > > > > except [1] which is a new patch similar to the workdone for
> > > > > > other similar SoC's
> > > > >
> > > > > Series looks good to me. (But gitlab testing does not seem to
> > > > > work, and it would be good to test it before applying).
> > > >
> > > > I am  not sure about the failure.  If it is related to testing on
> > > > RZ/G2H board, then
> > >
> > > No, it is definitely not related to your boards. Nothing ever
> > > builds... it can't be your fault or fault of your board, but it just prevents
> testing :-(.
> >
> > I have applied the entire series and it builds fine in my environment with
> linux-4.19.y-cip(4.19.138-cip32).
> > What is the build issue related to gitlab testing?
> >
> As I write other mail, this seems to be a issue in the environment that runs
> gitlab runner.

Ok.

Cheers,
Biju


Renesas Electronics Europe GmbH, Geschaeftsfuehrer/President: Carsten Jauch, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany, Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647

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Re: [cip-dev] [PATCH 4.19.y-cip 00/10] Add support for [H]SCIF/SDHI/I2C/RWDT/MSIOF

[Nobuhiro Iwamatsu]

[-- Attachment #1: Type: text/plain, Size: 2081 bytes --]

Hi,

> -----Original Message-----
> From: Biju Das [mailto:biju.das.jz@bp.renesas.com]
> Sent: Wednesday, August 26, 2020 8:21 PM
> To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>
> Cc: Chris Paterson <chris.paterson2@renesas.com>; Biju Das <biju.das.jz@bp.renesas.com>; Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: [PATCH 4.19.y-cip 00/10] Add support for [H]SCIF/SDHI/I2C/RWDT/MSIOF
> 
> Add RZ/G2H SoC support for [H]SCIF/SDHI/I2C/RWDT/MSIOF on 4.19.y-cip kernel.
> 
> All the patches in this series are cherry-piced from ML, except [1] which is
> a new patch similar to the workdone for other similar SoC's
> 
> [1] mmc: renesas_sdhi_internal_dmac: Add r8a774e1 support
> 
> This patch series depend on [2]
> [2] https://patchwork.kernel.org/project/cip-dev/list/?series=338235
> 
> Biju Das (1):
>   mmc: renesas_sdhi_internal_dmac: Add r8a774e1 support
> 
> Lad Prabhakar (9):
>   arm64: dts: renesas: r8a774e1: Add SCIF and HSCIF nodes
>   arm64: dts: renesas: r8a774e1: Add SDHI nodes
>   dt-bindings: i2c: renesas,i2c: Document r8a774e1 support
>   dt-bindings: i2c: renesas,iic: Document r8a774e1 support
>   arm64: dts: renesas: r8a774e1: Add I2C and IIC-DVFS support
>   spi: renesas,sh-msiof: Add r8a774e1 support
>   arm64: dts: renesas: r8a774e1: Add MSIOF nodes
>   dt-bindings: watchdog: renesas,wdt: Document r8a774e1 support
>   arm64: dts: renesas: r8a774e1: Add RWDT node
> 
>  .../devicetree/bindings/i2c/renesas,i2c.txt   |   1 +
>  .../devicetree/bindings/i2c/renesas,iic.txt   |   1 +
>  .../devicetree/bindings/spi/sh-msiof.txt      |   1 +
>  .../bindings/watchdog/renesas,wdt.txt         |   1 +
>  arch/arm64/boot/dts/renesas/r8a774e1.dtsi     | 390 +++++++++++++++++-
>  drivers/mmc/host/renesas_sdhi_internal_dmac.c |   1 +
>  6 files changed, 386 insertions(+), 9 deletions(-)
> 	

I reviwed this patch series, looks good to me.

Best regards,
  Nobuhiro


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Re: [cip-dev] [PATCH 4.19.y-cip 00/10] Add support for [H]SCIF/SDHI/I2C/RWDT/MSIOF

[Pavel Machek]

[-- Attachment #1.1: Type: text/plain, Size: 461 bytes --]

Hi!

> Add RZ/G2H SoC support for [H]SCIF/SDHI/I2C/RWDT/MSIOF on 4.19.y-cip kernel.
> 
> All the patches in this series are cherry-piced from ML, except [1] which is 
> a new patch similar to the workdone for other similar SoC's

Thanks, applied and pushed out.

Best regards,
									Pavel
									
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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