* [isar-cip-core][PATCH v4 1/8] make reason for disabling wdog on arm more precise
2023-03-03 12:48 [isar-cip-core][PATCH v4 0/8] Add swupdate support for riscv64 Felix Moessbauer
@ 2023-03-03 12:48 ` Felix Moessbauer
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 2/8] fix efibootguard for riscv64 Felix Moessbauer
` (7 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Felix Moessbauer @ 2023-03-03 12:48 UTC (permalink / raw)
To: cip-dev
Cc: daniel.bovensiepen, jan.kiszka, quirin.gylstorff, Felix Moessbauer
This patch reworks the comment describing why the watchdog is disabled
for arm and arm64. Previously it was stated that the watchdog is armed
by u-boot, but technically it simply never was supported to have a
watchdog on these platforms when using the start-qemu script.
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
---
conf/machine/qemu-arm.conf | 2 +-
conf/machine/qemu-arm64.conf | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/conf/machine/qemu-arm.conf b/conf/machine/qemu-arm.conf
index aa3a6b4..d2dd81f 100644
--- a/conf/machine/qemu-arm.conf
+++ b/conf/machine/qemu-arm.conf
@@ -13,7 +13,7 @@ IMAGE_FSTYPES ?= "ext4"
USE_CIP_KERNEL_CONFIG = "1"
KERNEL_DEFCONFIG ?= "cip-kernel-config/${KERNEL_DEFCONFIG_VERSION}/arm/qemu_arm_defconfig"
-# for SWUpdate setups: watchdog is configured in U-Boot
+# watchdog is not yet supported in our QEMU executor for this platform, disable it
WDOG_TIMEOUT = "0"
PREFERRED_PROVIDER_u-boot-${MACHINE} = "u-boot-qemu-arm"
diff --git a/conf/machine/qemu-arm64.conf b/conf/machine/qemu-arm64.conf
index 7f42369..7acf107 100644
--- a/conf/machine/qemu-arm64.conf
+++ b/conf/machine/qemu-arm64.conf
@@ -12,7 +12,7 @@ IMAGE_FSTYPES ?= "ext4"
USE_CIP_KERNEL_CONFIG = "1"
KERNEL_DEFCONFIG ?= "cip-kernel-config/${KERNEL_DEFCONFIG_VERSION}/arm64/qemu_arm64_defconfig"
-# for SWUpdate setups: watchdog is configured in U-Boot
+# watchdog is not yet supported in our QEMU executor for this platform, disable it
WDOG_TIMEOUT = "0"
PREFERRED_PROVIDER_u-boot-${MACHINE} = "u-boot-qemu-arm64"
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [isar-cip-core][PATCH v4 2/8] fix efibootguard for riscv64
2023-03-03 12:48 [isar-cip-core][PATCH v4 0/8] Add swupdate support for riscv64 Felix Moessbauer
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 1/8] make reason for disabling wdog on arm more precise Felix Moessbauer
@ 2023-03-03 12:48 ` Felix Moessbauer
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 3/8] wic(ebg): add support " Felix Moessbauer
` (6 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Felix Moessbauer @ 2023-03-03 12:48 UTC (permalink / raw)
To: cip-dev
Cc: daniel.bovensiepen, jan.kiszka, quirin.gylstorff, Felix Moessbauer
This commit backports an upstream patch for efibootguard that
fixes the riscv64 install location. As it is not yet in an
EBG release, we add it as a patch here. No internal logic of EBG is
changed, hence no dedicated release is needed.
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
---
recipes-bsp/efibootguard/efibootguard_0.13.bb | 3 ++
...01-add-machine-type-name-for-riscv64.patch | 39 +++++++++++++++++++
2 files changed, 42 insertions(+)
create mode 100644 recipes-bsp/efibootguard/files/0001-add-machine-type-name-for-riscv64.patch
diff --git a/recipes-bsp/efibootguard/efibootguard_0.13.bb b/recipes-bsp/efibootguard/efibootguard_0.13.bb
index 3279854..dd76198 100644
--- a/recipes-bsp/efibootguard/efibootguard_0.13.bb
+++ b/recipes-bsp/efibootguard/efibootguard_0.13.bb
@@ -21,6 +21,9 @@ SRC_URI = " \
file://debian \
"
SRC_URI[sha256sum] = "639a6d8f687cb099b2e9b01eb08ad1494267fe26b5d903b4d405d0737feb989b"
+# add riscv64 support
+SRC_URI += "file://0001-add-machine-type-name-for-riscv64.patch"
+CHANGELOG_V = "${PV}+cip"
PROVIDES = "${PN}"
PROVIDES += "${PN}-dev"
diff --git a/recipes-bsp/efibootguard/files/0001-add-machine-type-name-for-riscv64.patch b/recipes-bsp/efibootguard/files/0001-add-machine-type-name-for-riscv64.patch
new file mode 100644
index 0000000..adc7962
--- /dev/null
+++ b/recipes-bsp/efibootguard/files/0001-add-machine-type-name-for-riscv64.patch
@@ -0,0 +1,39 @@
+From 391dd5e04b17be6f5184afb2de4853795f1d5620 Mon Sep 17 00:00:00 2001
+From: Felix Moessbauer <felix.moessbauer@siemens.com>
+Date: Tue, 31 Jan 2023 09:27:31 +0100
+Subject: [PATCH 1/1] add machine type name for riscv64
+
+By adding the machine type name, the generated efi binary for
+riscv64 is suffixed with the corresponding efi machine name.
+
+Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
+Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+---
+ configure.ac | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/configure.ac b/configure.ac
+index d8f9d3a..90d70b0 100644
+--- a/configure.ac
++++ b/configure.ac
+@@ -87,6 +87,7 @@ SET_ARCH(X86_64, x86_64*)
+ SET_ARCH(IA64, ia64*)
+ SET_ARCH(AARCH64, aarch64*)
+ SET_ARCH(ARM, arm*)
++SET_ARCH(RISCV64, riscv64*)
+
+ ARCH=$(echo $host | sed "s/\(-\).*$//")
+
+@@ -103,6 +104,9 @@ AM_COND_IF(ARCH_AARCH64, [
+ AM_COND_IF(ARCH_ARM, [
+ MACHINE_TYPE_NAME=arm])
+
++AM_COND_IF(ARCH_RISCV64, [
++ MACHINE_TYPE_NAME=riscv64])
++
+ AC_SUBST([ARCH])
+ AC_SUBST([MACHINE_TYPE_NAME])
+ AM_CONDITIONAL([ARCH_IS_X86], [test "$ARCH" = "ia32" -o "$ARCH" = "x86_64"])
+--
+2.30.2
+
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [isar-cip-core][PATCH v4 3/8] wic(ebg): add support for riscv64
2023-03-03 12:48 [isar-cip-core][PATCH v4 0/8] Add swupdate support for riscv64 Felix Moessbauer
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 1/8] make reason for disabling wdog on arm more precise Felix Moessbauer
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 2/8] fix efibootguard for riscv64 Felix Moessbauer
@ 2023-03-03 12:48 ` Felix Moessbauer
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 4/8] add opensbi with u-boot payload " Felix Moessbauer
` (5 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Felix Moessbauer @ 2023-03-03 12:48 UTC (permalink / raw)
To: cip-dev
Cc: daniel.bovensiepen, jan.kiszka, quirin.gylstorff, Felix Moessbauer
This patch adds the mapping between the efi architecture and the distro
architecture for riscv64.
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
---
scripts/lib/wic/plugins/source/efibootguard-boot.py | 6 ++++--
scripts/lib/wic/plugins/source/efibootguard-efi.py | 6 ++++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/scripts/lib/wic/plugins/source/efibootguard-boot.py b/scripts/lib/wic/plugins/source/efibootguard-boot.py
index 3d6b2d7..0de28ca 100644
--- a/scripts/lib/wic/plugins/source/efibootguard-boot.py
+++ b/scripts/lib/wic/plugins/source/efibootguard-boot.py
@@ -185,13 +185,15 @@ class EfibootguardBootPlugin(SourcePlugin):
"amd64": "x64",
"arm64": "aa64",
"armhf": "arm",
- "i386": "ia32"
+ "i386": "ia32",
+ "riscv64" : "riscv64"
}
distro_to_lib_arch = {
"amd64": "x86_64-linux-gnu",
"arm64": "aarch64-linux-gnu",
"armhf": "arm-linux-gnueabihf",
- "i386": "i386-linux-gnu"
+ "i386": "i386-linux-gnu",
+ "riscv64": "riscv64-linux-gnu",
}
rootfs_path = rootfs_dir.get('ROOTFS_DIR')
distro_arch = get_bitbake_var("DISTRO_ARCH")
diff --git a/scripts/lib/wic/plugins/source/efibootguard-efi.py b/scripts/lib/wic/plugins/source/efibootguard-efi.py
index 2d16fe3..d6cdf0f 100644
--- a/scripts/lib/wic/plugins/source/efibootguard-efi.py
+++ b/scripts/lib/wic/plugins/source/efibootguard-efi.py
@@ -56,14 +56,16 @@ class EfibootguardEFIPlugin(SourcePlugin):
"amd64": "x64",
"arm64": "aa64",
"armhf": "arm",
- "i386": "ia32"
+ "i386": "ia32",
+ "riscv64" : "riscv64"
}
distro_to_lib_arch = {
"amd64": "x86_64-linux-gnu",
"arm64": "aarch64-linux-gnu",
"armhf": "arm-linux-gnueabihf",
- "i386": "i386-linux-gnu"
+ "i386": "i386-linux-gnu",
+ "riscv64": "riscv64-linux-gnu",
}
distro_arch = get_bitbake_var("DISTRO_ARCH")
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [isar-cip-core][PATCH v4 4/8] add opensbi with u-boot payload for riscv64
2023-03-03 12:48 [isar-cip-core][PATCH v4 0/8] Add swupdate support for riscv64 Felix Moessbauer
` (2 preceding siblings ...)
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 3/8] wic(ebg): add support " Felix Moessbauer
@ 2023-03-03 12:48 ` Felix Moessbauer
2023-03-04 8:35 ` Jan Kiszka
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 5/8] enhance qemu-riscv64 machine to be testable Felix Moessbauer
` (4 subsequent siblings)
8 siblings, 1 reply; 12+ messages in thread
From: Felix Moessbauer @ 2023-03-03 12:48 UTC (permalink / raw)
To: cip-dev
Cc: daniel.bovensiepen, jan.kiszka, quirin.gylstorff, Felix Moessbauer
This patch adds the opensbi firmware with u-boot payload (smode) for the
qemu-riscv64 machine. Using that, the generated riscv64 images can be
booted on qemu.
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
---
recipes-bsp/opensbi/files/qemu-riscv64-rules | 12 ++++
.../opensbi/opensbi-qemu-riscv64_1.2.bb | 8 +++
recipes-bsp/opensbi/opensbi.inc | 45 +++++++++++++++
...iscv-Fix-build-against-binutils-2.38.patch | 55 +++++++++++++++++++
.../u-boot/u-boot-qemu-riscv64_2022.07.bb | 22 ++++++++
5 files changed, 142 insertions(+)
create mode 100644 recipes-bsp/opensbi/files/qemu-riscv64-rules
create mode 100644 recipes-bsp/opensbi/opensbi-qemu-riscv64_1.2.bb
create mode 100644 recipes-bsp/opensbi/opensbi.inc
create mode 100644 recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch
create mode 100644 recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb
diff --git a/recipes-bsp/opensbi/files/qemu-riscv64-rules b/recipes-bsp/opensbi/files/qemu-riscv64-rules
new file mode 100644
index 0000000..960e10c
--- /dev/null
+++ b/recipes-bsp/opensbi/files/qemu-riscv64-rules
@@ -0,0 +1,12 @@
+#!/usr/bin/make -f
+
+ifneq ($(DEB_BUILD_GNU_TYPE),$(DEB_HOST_GNU_TYPE))
+export CROSS_COMPILE=$(DEB_HOST_GNU_TYPE)-
+endif
+
+override_dh_auto_build:
+ CFLAGS= LDFLAGS= $(MAKE) $(PARALLEL_MAKE) PLATFORM=generic \
+ FW_PAYLOAD_PATH=/usr/lib/u-boot/qemu-riscv64/u-boot.bin
+
+%:
+ dh $@
diff --git a/recipes-bsp/opensbi/opensbi-qemu-riscv64_1.2.bb b/recipes-bsp/opensbi/opensbi-qemu-riscv64_1.2.bb
new file mode 100644
index 0000000..b503afc
--- /dev/null
+++ b/recipes-bsp/opensbi/opensbi-qemu-riscv64_1.2.bb
@@ -0,0 +1,8 @@
+#
+# Copyright (c) Siemens AG, 2023
+#
+# SPDX-License-Identifier: MIT
+
+include opensbi.inc
+
+SRC_URI[opensbi.sha256sum] = "8fcbce598a73acc2c7f7d5607d46b9d5107d3ecbede8f68f42631dcfc25ef2b2"
diff --git a/recipes-bsp/opensbi/opensbi.inc b/recipes-bsp/opensbi/opensbi.inc
new file mode 100644
index 0000000..b41a8bb
--- /dev/null
+++ b/recipes-bsp/opensbi/opensbi.inc
@@ -0,0 +1,45 @@
+#
+# Copyright (c) Siemens AG, 2023
+#
+# SPDX-License-Identifier: MIT
+
+inherit dpkg
+
+U_BOOT_PACKAGE ?= "u-boot-${MACHINE}"
+PLATFORM ?= "generic"
+
+DEPLOYDIR_FIRMWARE = "${WORKDIR}/deploy-fw"
+SSTATETASKS += "do_deploy"
+
+SRC_URI = " \
+ https://github.com/riscv/opensbi/archive/v${PV}.tar.gz;downloadfilename=opensbi-${PV}.tar.gz;name=opensbi \
+ file://${MACHINE}-rules"
+
+S = "${WORKDIR}/opensbi-${PV}"
+
+DEPENDS += "${U_BOOT_PACKAGE}"
+DEBIAN_BUILD_DEPENDS .= ",${U_BOOT_PACKAGE}"
+
+do_prepare_build[cleandirs] += "${S}/debian"
+do_prepare_build() {
+ cp ${WORKDIR}/${MACHINE}-rules ${WORKDIR}/rules
+ deb_debianize
+
+ echo "build/platform/${PLATFORM}/firmware/fw_payload.bin /usr/lib/opensbi/${MACHINE}/" > ${S}/debian/install
+}
+
+do_deploy[cleandirs] += "${DEPLOYDIR_FIRMWARE}"
+do_deploy[sstate-inputdirs] = "${DEPLOYDIR_FIRMWARE}"
+do_deploy[sstate-outputdirs] = "${DEPLOY_DIR_IMAGE}"
+do_deploy() {
+ dpkg --fsys-tarfile "${WORKDIR}/${PN}_${PV}_${DISTRO_ARCH}.deb" | \
+ tar xOf - "./usr/lib/opensbi/${MACHINE}/fw_payload.bin" \
+ > "${DEPLOYDIR_FIRMWARE}/fw_payload.bin"
+}
+
+python do_deploy_setscene () {
+ sstate_setscene(d)
+}
+addtask do_deploy_setscene
+
+addtask deploy after do_dpkg_build before do_deploy_deb
diff --git a/recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch b/recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch
new file mode 100644
index 0000000..6f8a2ae
--- /dev/null
+++ b/recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch
@@ -0,0 +1,55 @@
+From 5df4b2299f86933fa79aa3bc6a3986fc7e55b7e0 Mon Sep 17 00:00:00 2001
+From: Alexandre Ghiti <alexandre.ghiti@canonical.com>
+Date: Mon, 3 Oct 2022 18:07:54 +0200
+Subject: [PATCH 1/2] riscv: Fix build against binutils 2.38
+
+The following description is copied from the equivalent patch for the
+Linux Kernel proposed by Aurelien Jarno:
+
+>From version 2.38, binutils default to ISA spec version 20191213. This
+means that the csr read/write (csrr*/csrw*) instructions and fence.i
+instruction has separated from the `I` extension, become two standalone
+extensions: Zicsr and Zifencei. As the kernel uses those instruction,
+this causes the following build failure:
+
+arch/riscv/cpu/mtrap.S: Assembler messages:
+arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
+arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
+arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
+arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
+
+Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+Tested-by: Heiko Stuebner <heiko@sntech.de>
+Tested-by: Christian Stewart <christian@paral.in>
+Reviewed-by: Rick Chen <rick@andestech.com>
+---
+ arch/riscv/Makefile | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
+index 0b80eb8d86..53d1194ffb 100644
+--- a/arch/riscv/Makefile
++++ b/arch/riscv/Makefile
+@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
+ CMODEL = medany
+ endif
+
+-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
++RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
++
++# Newer binutils versions default to ISA spec version 20191213 which moves some
++# instructions from the I extension to the Zicsr and Zifencei extensions.
++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
++ifeq ($(toolchain-need-zicsr-zifencei),y)
++ RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
++endif
++
++ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
+ -mcmodel=$(CMODEL)
+
+ PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
+--
+2.30.2
+
diff --git a/recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb b/recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb
new file mode 100644
index 0000000..8dfac45
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb
@@ -0,0 +1,22 @@
+#
+# CIP Core, generic profile
+#
+# Copyright (c) Siemens AG, 2022
+#
+# Authors:
+# Jan Kiszka <jan.kiszka@siemens.com>
+#
+# SPDX-License-Identifier: MIT
+#
+
+require u-boot-qemu-common.inc
+
+# we run as OpenSBI payload, hence use smode
+U_BOOT_CONFIG = "${MACHINE}_smode_defconfig"
+
+EFI_ARCH = "riscv64"
+
+SRC_URI += " \
+ file://riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch"
+
+U_BOOT_BIN = "u-boot.bin"
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [isar-cip-core][PATCH v4 4/8] add opensbi with u-boot payload for riscv64
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 4/8] add opensbi with u-boot payload " Felix Moessbauer
@ 2023-03-04 8:35 ` Jan Kiszka
0 siblings, 0 replies; 12+ messages in thread
From: Jan Kiszka @ 2023-03-04 8:35 UTC (permalink / raw)
To: Felix Moessbauer, cip-dev; +Cc: daniel.bovensiepen, quirin.gylstorff
On 03.03.23 13:48, Felix Moessbauer wrote:
> This patch adds the opensbi firmware with u-boot payload (smode) for the
> qemu-riscv64 machine. Using that, the generated riscv64 images can be
> booted on qemu.
>
> Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
> ---
> recipes-bsp/opensbi/files/qemu-riscv64-rules | 12 ++++
> .../opensbi/opensbi-qemu-riscv64_1.2.bb | 8 +++
> recipes-bsp/opensbi/opensbi.inc | 45 +++++++++++++++
> ...iscv-Fix-build-against-binutils-2.38.patch | 55 +++++++++++++++++++
> .../u-boot/u-boot-qemu-riscv64_2022.07.bb | 22 ++++++++
> 5 files changed, 142 insertions(+)
> create mode 100644 recipes-bsp/opensbi/files/qemu-riscv64-rules
> create mode 100644 recipes-bsp/opensbi/opensbi-qemu-riscv64_1.2.bb
> create mode 100644 recipes-bsp/opensbi/opensbi.inc
> create mode 100644 recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch
> create mode 100644 recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb
>
> diff --git a/recipes-bsp/opensbi/files/qemu-riscv64-rules b/recipes-bsp/opensbi/files/qemu-riscv64-rules
> new file mode 100644
> index 0000000..960e10c
> --- /dev/null
> +++ b/recipes-bsp/opensbi/files/qemu-riscv64-rules
> @@ -0,0 +1,12 @@
> +#!/usr/bin/make -f
> +
> +ifneq ($(DEB_BUILD_GNU_TYPE),$(DEB_HOST_GNU_TYPE))
> +export CROSS_COMPILE=$(DEB_HOST_GNU_TYPE)-
> +endif
> +
> +override_dh_auto_build:
> + CFLAGS= LDFLAGS= $(MAKE) $(PARALLEL_MAKE) PLATFORM=generic \
> + FW_PAYLOAD_PATH=/usr/lib/u-boot/qemu-riscv64/u-boot.bin
> +
> +%:
> + dh $@
> diff --git a/recipes-bsp/opensbi/opensbi-qemu-riscv64_1.2.bb b/recipes-bsp/opensbi/opensbi-qemu-riscv64_1.2.bb
> new file mode 100644
> index 0000000..b503afc
> --- /dev/null
> +++ b/recipes-bsp/opensbi/opensbi-qemu-riscv64_1.2.bb
> @@ -0,0 +1,8 @@
> +#
> +# Copyright (c) Siemens AG, 2023
> +#
> +# SPDX-License-Identifier: MIT
> +
> +include opensbi.inc
> +
> +SRC_URI[opensbi.sha256sum] = "8fcbce598a73acc2c7f7d5607d46b9d5107d3ecbede8f68f42631dcfc25ef2b2"
> diff --git a/recipes-bsp/opensbi/opensbi.inc b/recipes-bsp/opensbi/opensbi.inc
> new file mode 100644
> index 0000000..b41a8bb
> --- /dev/null
> +++ b/recipes-bsp/opensbi/opensbi.inc
> @@ -0,0 +1,45 @@
> +#
> +# Copyright (c) Siemens AG, 2023
> +#
> +# SPDX-License-Identifier: MIT
> +
> +inherit dpkg
> +
> +U_BOOT_PACKAGE ?= "u-boot-${MACHINE}"
> +PLATFORM ?= "generic"
> +
> +DEPLOYDIR_FIRMWARE = "${WORKDIR}/deploy-fw"
> +SSTATETASKS += "do_deploy"
> +
> +SRC_URI = " \
> + https://github.com/riscv/opensbi/archive/v${PV}.tar.gz;downloadfilename=opensbi-${PV}.tar.gz;name=opensbi \
> + file://${MACHINE}-rules"
This triggers fetcher warnings for other machines. Moving to the
machine-specific recipe.
Jan
> +
> +S = "${WORKDIR}/opensbi-${PV}"
> +
> +DEPENDS += "${U_BOOT_PACKAGE}"
> +DEBIAN_BUILD_DEPENDS .= ",${U_BOOT_PACKAGE}"
> +
> +do_prepare_build[cleandirs] += "${S}/debian"
> +do_prepare_build() {
> + cp ${WORKDIR}/${MACHINE}-rules ${WORKDIR}/rules
> + deb_debianize
> +
> + echo "build/platform/${PLATFORM}/firmware/fw_payload.bin /usr/lib/opensbi/${MACHINE}/" > ${S}/debian/install
> +}
> +
> +do_deploy[cleandirs] += "${DEPLOYDIR_FIRMWARE}"
> +do_deploy[sstate-inputdirs] = "${DEPLOYDIR_FIRMWARE}"
> +do_deploy[sstate-outputdirs] = "${DEPLOY_DIR_IMAGE}"
> +do_deploy() {
> + dpkg --fsys-tarfile "${WORKDIR}/${PN}_${PV}_${DISTRO_ARCH}.deb" | \
> + tar xOf - "./usr/lib/opensbi/${MACHINE}/fw_payload.bin" \
> + > "${DEPLOYDIR_FIRMWARE}/fw_payload.bin"
> +}
> +
> +python do_deploy_setscene () {
> + sstate_setscene(d)
> +}
> +addtask do_deploy_setscene
> +
> +addtask deploy after do_dpkg_build before do_deploy_deb
> diff --git a/recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch b/recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch
> new file mode 100644
> index 0000000..6f8a2ae
> --- /dev/null
> +++ b/recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch
> @@ -0,0 +1,55 @@
> +From 5df4b2299f86933fa79aa3bc6a3986fc7e55b7e0 Mon Sep 17 00:00:00 2001
> +From: Alexandre Ghiti <alexandre.ghiti@canonical.com>
> +Date: Mon, 3 Oct 2022 18:07:54 +0200
> +Subject: [PATCH 1/2] riscv: Fix build against binutils 2.38
> +
> +The following description is copied from the equivalent patch for the
> +Linux Kernel proposed by Aurelien Jarno:
> +
> +>From version 2.38, binutils default to ISA spec version 20191213. This
> +means that the csr read/write (csrr*/csrw*) instructions and fence.i
> +instruction has separated from the `I` extension, become two standalone
> +extensions: Zicsr and Zifencei. As the kernel uses those instruction,
> +this causes the following build failure:
> +
> +arch/riscv/cpu/mtrap.S: Assembler messages:
> +arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
> +arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
> +arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
> +arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
> +
> +Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
> +Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> +Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> +Tested-by: Heiko Stuebner <heiko@sntech.de>
> +Tested-by: Christian Stewart <christian@paral.in>
> +Reviewed-by: Rick Chen <rick@andestech.com>
> +---
> + arch/riscv/Makefile | 11 ++++++++++-
> + 1 file changed, 10 insertions(+), 1 deletion(-)
> +
> +diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> +index 0b80eb8d86..53d1194ffb 100644
> +--- a/arch/riscv/Makefile
> ++++ b/arch/riscv/Makefile
> +@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
> + CMODEL = medany
> + endif
> +
> +-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
> ++RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
> ++
> ++# Newer binutils versions default to ISA spec version 20191213 which moves some
> ++# instructions from the I extension to the Zicsr and Zifencei extensions.
> ++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
> ++ifeq ($(toolchain-need-zicsr-zifencei),y)
> ++ RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
> ++endif
> ++
> ++ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
> + -mcmodel=$(CMODEL)
> +
> + PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
> +--
> +2.30.2
> +
> diff --git a/recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb b/recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb
> new file mode 100644
> index 0000000..8dfac45
> --- /dev/null
> +++ b/recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb
> @@ -0,0 +1,22 @@
> +#
> +# CIP Core, generic profile
> +#
> +# Copyright (c) Siemens AG, 2022
> +#
> +# Authors:
> +# Jan Kiszka <jan.kiszka@siemens.com>
> +#
> +# SPDX-License-Identifier: MIT
> +#
> +
> +require u-boot-qemu-common.inc
> +
> +# we run as OpenSBI payload, hence use smode
> +U_BOOT_CONFIG = "${MACHINE}_smode_defconfig"
> +
> +EFI_ARCH = "riscv64"
> +
> +SRC_URI += " \
> + file://riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch"
> +
> +U_BOOT_BIN = "u-boot.bin"
--
Siemens AG, Technology
Competence Center Embedded Linux
^ permalink raw reply [flat|nested] 12+ messages in thread
* [isar-cip-core][PATCH v4 5/8] enhance qemu-riscv64 machine to be testable
2023-03-03 12:48 [isar-cip-core][PATCH v4 0/8] Add swupdate support for riscv64 Felix Moessbauer
` (3 preceding siblings ...)
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 4/8] add opensbi with u-boot payload " Felix Moessbauer
@ 2023-03-03 12:48 ` Felix Moessbauer
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 6/8] add linux 6.1 mainline kernel Felix Moessbauer
` (3 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Felix Moessbauer @ 2023-03-03 12:48 UTC (permalink / raw)
To: cip-dev
Cc: daniel.bovensiepen, jan.kiszka, quirin.gylstorff, Felix Moessbauer
This patch enhances the qemu-riscv64 machine by adding a reference to
u-boot. Further, we now use the qemu_riscv64 defconfig from
cip-kernel-config.
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
---
conf/machine/qemu-riscv64.conf | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/conf/machine/qemu-riscv64.conf b/conf/machine/qemu-riscv64.conf
index f1f3e87..02bb60a 100644
--- a/conf/machine/qemu-riscv64.conf
+++ b/conf/machine/qemu-riscv64.conf
@@ -12,4 +12,11 @@
DISTRO_ARCH = "riscv64"
IMAGE_FSTYPES ?= "ext4"
-KERNEL_DEFCONFIG ?= "defconfig"
+USE_CIP_KERNEL_CONFIG = "1"
+
+KERNEL_DEFCONFIG ?= "cip-kernel-config/${KERNEL_DEFCONFIG_VERSION}/riscv/qemu_riscv64_defconfig"
+
+# watchdog is not yet supported in our QEMU executor for this platform, disable it
+WDOG_TIMEOUT = "0"
+
+PREFERRED_PROVIDER_u-boot-${MACHINE} = "u-boot-qemu-riscv64"
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [isar-cip-core][PATCH v4 6/8] add linux 6.1 mainline kernel
2023-03-03 12:48 [isar-cip-core][PATCH v4 0/8] Add swupdate support for riscv64 Felix Moessbauer
` (4 preceding siblings ...)
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 5/8] enhance qemu-riscv64 machine to be testable Felix Moessbauer
@ 2023-03-03 12:48 ` Felix Moessbauer
2023-03-04 8:12 ` Jan Kiszka
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 7/8] add swupdate support for qemu-riscv64 Felix Moessbauer
` (2 subsequent siblings)
8 siblings, 1 reply; 12+ messages in thread
From: Felix Moessbauer @ 2023-03-03 12:48 UTC (permalink / raw)
To: cip-dev
Cc: daniel.bovensiepen, jan.kiszka, quirin.gylstorff, Felix Moessbauer
This patch adds the vanilla 6.1 linux kernel for testing and for boards
which need a more recent kernel than what CIP can offer.
The kernel can be selected from the menu, similar to the other kernels.
As defconfig, we always use the kernels internal configuration, because
there is no cip-kernel-config for that version yet. In addition, the
squashfs knob is selected to support the swupdate pattern without any
modifications.
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
---
Kconfig | 4 ++++
kas/opt/6.1-mainline.yml | 18 ++++++++++++++++++
recipes-kernel/linux/files/squashfs.cfg | 1 +
recipes-kernel/linux/linux-mainline_6.1.bb | 18 ++++++++++++++++++
4 files changed, 41 insertions(+)
create mode 100644 kas/opt/6.1-mainline.yml
create mode 100644 recipes-kernel/linux/files/squashfs.cfg
create mode 100644 recipes-kernel/linux/linux-mainline_6.1.bb
diff --git a/Kconfig b/Kconfig
index cd24ce2..a932bbe 100644
--- a/Kconfig
+++ b/Kconfig
@@ -97,6 +97,9 @@ config KERNEL_4_19
config KERNEL_5_10
bool "Kernel 5.10.x-cip"
+config KERNEL_6_1_MAINLINE
+ bool "Kernel 6.1.x-mainline"
+
endchoice
config KAS_INCLUDE_KERNEL
@@ -104,6 +107,7 @@ config KAS_INCLUDE_KERNEL
default "kas/opt/4.4.yml" if KERNEL_4_4
default "kas/opt/4.19.yml" if KERNEL_4_19
default "kas/opt/5.10.yml" if KERNEL_5_10
+ default "kas/opt/6.1-mainline.yml" if KERNEL_6_1_MAINLINE
config KERNEL_RT
bool "Real-time CIP kernel"
diff --git a/kas/opt/6.1-mainline.yml b/kas/opt/6.1-mainline.yml
new file mode 100644
index 0000000..84d12b0
--- /dev/null
+++ b/kas/opt/6.1-mainline.yml
@@ -0,0 +1,18 @@
+#
+# CIP Core, generic profile
+#
+# Copyright (c) Siemens AG, 2023
+#
+# Authors:
+# Felix Moessbauer <felix.moessbauer@siemens.com>
+#
+# SPDX-License-Identifier: MIT
+#
+
+header:
+ version: 12
+
+local_conf_header:
+ kernel-version: |
+ KERNEL_DEFCONFIG = ""
+ KERNEL_NAME = "mainline"
diff --git a/recipes-kernel/linux/files/squashfs.cfg b/recipes-kernel/linux/files/squashfs.cfg
new file mode 100644
index 0000000..7a89d00
--- /dev/null
+++ b/recipes-kernel/linux/files/squashfs.cfg
@@ -0,0 +1 @@
+CONFIG_SQUASHFS=y
diff --git a/recipes-kernel/linux/linux-mainline_6.1.bb b/recipes-kernel/linux/linux-mainline_6.1.bb
new file mode 100644
index 0000000..8a879a0
--- /dev/null
+++ b/recipes-kernel/linux/linux-mainline_6.1.bb
@@ -0,0 +1,18 @@
+# Example recipe for building the mainline kernel
+#
+# This software is a part of ISAR.
+# Copyright (c) Siemens AG, 2018-2020
+#
+# SPDX-License-Identifier: MIT
+
+require recipes-kernel/linux/linux-custom.inc
+
+ARCHIVE_VERSION = "${@ d.getVar('PV')[:-2] if d.getVar('PV').endswith('.0') else d.getVar('PV') }"
+
+SRC_URI += " \
+ https://cdn.kernel.org/pub/linux/kernel/v6.x/linux-${ARCHIVE_VERSION}.tar.xz \
+ file://squashfs.cfg"
+
+SRC_URI[sha256sum] = "2ca1f17051a430f6fed1196e4952717507171acfd97d96577212502703b25deb"
+
+S = "${WORKDIR}/linux-${ARCHIVE_VERSION}"
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [isar-cip-core][PATCH v4 6/8] add linux 6.1 mainline kernel
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 6/8] add linux 6.1 mainline kernel Felix Moessbauer
@ 2023-03-04 8:12 ` Jan Kiszka
0 siblings, 0 replies; 12+ messages in thread
From: Jan Kiszka @ 2023-03-04 8:12 UTC (permalink / raw)
To: Felix Moessbauer, cip-dev; +Cc: daniel.bovensiepen, quirin.gylstorff
On 03.03.23 13:48, Felix Moessbauer wrote:
> This patch adds the vanilla 6.1 linux kernel for testing and for boards
> which need a more recent kernel than what CIP can offer.
> The kernel can be selected from the menu, similar to the other kernels.
> As defconfig, we always use the kernels internal configuration, because
> there is no cip-kernel-config for that version yet. In addition, the
> squashfs knob is selected to support the swupdate pattern without any
> modifications.
>
> Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
> ---
> Kconfig | 4 ++++
> kas/opt/6.1-mainline.yml | 18 ++++++++++++++++++
> recipes-kernel/linux/files/squashfs.cfg | 1 +
> recipes-kernel/linux/linux-mainline_6.1.bb | 18 ++++++++++++++++++
> 4 files changed, 41 insertions(+)
> create mode 100644 kas/opt/6.1-mainline.yml
> create mode 100644 recipes-kernel/linux/files/squashfs.cfg
> create mode 100644 recipes-kernel/linux/linux-mainline_6.1.bb
>
> diff --git a/Kconfig b/Kconfig
> index cd24ce2..a932bbe 100644
> --- a/Kconfig
> +++ b/Kconfig
> @@ -97,6 +97,9 @@ config KERNEL_4_19
> config KERNEL_5_10
> bool "Kernel 5.10.x-cip"
>
> +config KERNEL_6_1_MAINLINE
> + bool "Kernel 6.1.x-mainline"
> +
> endchoice
>
> config KAS_INCLUDE_KERNEL
> @@ -104,6 +107,7 @@ config KAS_INCLUDE_KERNEL
> default "kas/opt/4.4.yml" if KERNEL_4_4
> default "kas/opt/4.19.yml" if KERNEL_4_19
> default "kas/opt/5.10.yml" if KERNEL_5_10
> + default "kas/opt/6.1-mainline.yml" if KERNEL_6_1_MAINLINE
>
> config KERNEL_RT
> bool "Real-time CIP kernel"
> diff --git a/kas/opt/6.1-mainline.yml b/kas/opt/6.1-mainline.yml
> new file mode 100644
> index 0000000..84d12b0
> --- /dev/null
> +++ b/kas/opt/6.1-mainline.yml
> @@ -0,0 +1,18 @@
> +#
> +# CIP Core, generic profile
> +#
> +# Copyright (c) Siemens AG, 2023
> +#
> +# Authors:
> +# Felix Moessbauer <felix.moessbauer@siemens.com>
> +#
> +# SPDX-License-Identifier: MIT
> +#
> +
> +header:
> + version: 12
> +
> +local_conf_header:
> + kernel-version: |
> + KERNEL_DEFCONFIG = ""
> + KERNEL_NAME = "mainline"
> diff --git a/recipes-kernel/linux/files/squashfs.cfg b/recipes-kernel/linux/files/squashfs.cfg
> new file mode 100644
> index 0000000..7a89d00
> --- /dev/null
> +++ b/recipes-kernel/linux/files/squashfs.cfg
> @@ -0,0 +1 @@
> +CONFIG_SQUASHFS=y
> diff --git a/recipes-kernel/linux/linux-mainline_6.1.bb b/recipes-kernel/linux/linux-mainline_6.1.bb
> new file mode 100644
> index 0000000..8a879a0
> --- /dev/null
> +++ b/recipes-kernel/linux/linux-mainline_6.1.bb
> @@ -0,0 +1,18 @@
> +# Example recipe for building the mainline kernel
> +#
> +# This software is a part of ISAR.
> +# Copyright (c) Siemens AG, 2018-2020
> +#
> +# SPDX-License-Identifier: MIT
> +
> +require recipes-kernel/linux/linux-custom.inc
> +
> +ARCHIVE_VERSION = "${@ d.getVar('PV')[:-2] if d.getVar('PV').endswith('.0') else d.getVar('PV') }"
> +
> +SRC_URI += " \
> + https://cdn.kernel.org/pub/linux/kernel/v6.x/linux-${ARCHIVE_VERSION}.tar.xz \
> + file://squashfs.cfg"
> +
> +SRC_URI[sha256sum] = "2ca1f17051a430f6fed1196e4952717507171acfd97d96577212502703b25deb"
> +
> +S = "${WORKDIR}/linux-${ARCHIVE_VERSION}"
This is still the outdated 6.1 base releasing. Fixing on merge.
Jan
--
Siemens AG, Technology
Competence Center Embedded Linux
^ permalink raw reply [flat|nested] 12+ messages in thread
* [isar-cip-core][PATCH v4 7/8] add swupdate support for qemu-riscv64
2023-03-03 12:48 [isar-cip-core][PATCH v4 0/8] Add swupdate support for riscv64 Felix Moessbauer
` (5 preceding siblings ...)
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 6/8] add linux 6.1 mainline kernel Felix Moessbauer
@ 2023-03-03 12:48 ` Felix Moessbauer
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 8/8] start-qemu: add support for swupdate on RISC-V Felix Moessbauer
2023-03-06 6:10 ` [isar-cip-core][PATCH v4 0/8] Add swupdate support for riscv64 Jan Kiszka
8 siblings, 0 replies; 12+ messages in thread
From: Felix Moessbauer @ 2023-03-03 12:48 UTC (permalink / raw)
To: cip-dev
Cc: daniel.bovensiepen, jan.kiszka, quirin.gylstorff, Felix Moessbauer
This patch enables the swupdate KConfig entry for the qemu-riscv64
board. For that, we also duplicate the qemu-arm64-efibootguard.wks
template for qemu-riscv64. As this is the first riscv64 board, we do not
symlink but create a copy.
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
---
Kconfig | 2 +-
kas/opt/ebg-swu.yml | 1 +
wic/qemu-riscv64-efibootguard.wks.in | 13 +++++++++++++
3 files changed, 15 insertions(+), 1 deletion(-)
create mode 100644 wic/qemu-riscv64-efibootguard.wks.in
diff --git a/Kconfig b/Kconfig
index a932bbe..7d72094 100644
--- a/Kconfig
+++ b/Kconfig
@@ -181,7 +181,7 @@ if IMAGE_FLASH && !KERNEL_4_4 && !KERNEL_4_19
config IMAGE_SWUPDATE
bool "SWUpdate support for root partition"
- depends on TARGET_QEMU_AMD64 || TARGET_SIMATIC_IPC227E || TARGET_QEMU_ARM64 || TARGET_QEMU_ARM || TARGET_BBB
+ depends on TARGET_QEMU_AMD64 || TARGET_SIMATIC_IPC227E || TARGET_QEMU_ARM64 || TARGET_QEMU_ARM || TARGET_BBB || ( TARGET_QEMU_RISCV64 && KERNEL_6_1_MAINLINE )
config IMAGE_SECURE_BOOT
bool "Secure boot support"
diff --git a/kas/opt/ebg-swu.yml b/kas/opt/ebg-swu.yml
index 6bc893b..203a6b9 100644
--- a/kas/opt/ebg-swu.yml
+++ b/kas/opt/ebg-swu.yml
@@ -32,3 +32,4 @@ local_conf_header:
# Add U-Boot for qemu
IMAGER_BUILD_DEPS:append:qemu-arm64 = " u-boot-qemu-arm64"
IMAGER_BUILD_DEPS:append:qemu-arm = " u-boot-qemu-arm"
+ IMAGER_BUILD_DEPS:append:qemu-riscv64 = " opensbi-qemu-riscv64"
diff --git a/wic/qemu-riscv64-efibootguard.wks.in b/wic/qemu-riscv64-efibootguard.wks.in
new file mode 100644
index 0000000..d63fc3a
--- /dev/null
+++ b/wic/qemu-riscv64-efibootguard.wks.in
@@ -0,0 +1,13 @@
+# short-description: riscv64 with EFI Boot Guard and SWUpdate
+# long-description: Disk image for riscv64 machines with EFI Boot Guard and SWUpdate
+
+include ebg-sysparts.inc
+
+part --source rawcopy --sourceparams "file=${IMAGE_FULLNAME}.squashfs" --align 1024 --fixed-size 1G --uuid "${ABROOTFS_PART_UUID_A}"
+part --source empty --align 1024 --fixed-size 1G --uuid "${ABROOTFS_PART_UUID_B}"
+
+# home and var are extra partitions
+part /home --source rootfs --rootfs-dir=${IMAGE_ROOTFS}/home --fstype=ext4 --label home --align 1024 --size 1G
+part /var --source rootfs --rootfs-dir=${IMAGE_ROOTFS}/var --fstype=ext4 --label var --align 1024 --size 2G
+
+bootloader --ptable gpt
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [isar-cip-core][PATCH v4 8/8] start-qemu: add support for swupdate on RISC-V
2023-03-03 12:48 [isar-cip-core][PATCH v4 0/8] Add swupdate support for riscv64 Felix Moessbauer
` (6 preceding siblings ...)
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 7/8] add swupdate support for qemu-riscv64 Felix Moessbauer
@ 2023-03-03 12:48 ` Felix Moessbauer
2023-03-06 6:10 ` [isar-cip-core][PATCH v4 0/8] Add swupdate support for riscv64 Jan Kiszka
8 siblings, 0 replies; 12+ messages in thread
From: Felix Moessbauer @ 2023-03-03 12:48 UTC (permalink / raw)
To: cip-dev
Cc: daniel.bovensiepen, jan.kiszka, quirin.gylstorff, Felix Moessbauer
This patch adds support to run swupdate images for RISC-V64 on qemu. As
firmware, we use OpenSBI with u-boot payload in s-mode.
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
---
start-qemu.sh | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/start-qemu.sh b/start-qemu.sh
index cccc51e..fcfbc5b 100755
--- a/start-qemu.sh
+++ b/start-qemu.sh
@@ -176,6 +176,14 @@ if [ -n "${SECURE_BOOT}${SWUPDATE_BOOT}" ]; then
-bios ${u_boot_bin} \
${QEMU_COMMON_OPTIONS} "$@"
;;
+ rv64|riscv64)
+ opensbi_bin=${FIRMWARE_BIN:-./build/tmp/deploy/images/qemu-${QEMU_ARCH}/fw_payload.bin}
+
+ ${QEMU_PATH}${QEMU} \
+ -drive file=${IMAGE_PREFIX}.wic,discard=unmap,if=none,id=disk,format=raw \
+ -bios ${opensbi_bin} \
+ ${QEMU_COMMON_OPTIONS} "$@"
+ ;;
*)
echo "Unsupported architecture: ${arch}"
exit 1
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [isar-cip-core][PATCH v4 0/8] Add swupdate support for riscv64
2023-03-03 12:48 [isar-cip-core][PATCH v4 0/8] Add swupdate support for riscv64 Felix Moessbauer
` (7 preceding siblings ...)
2023-03-03 12:48 ` [isar-cip-core][PATCH v4 8/8] start-qemu: add support for swupdate on RISC-V Felix Moessbauer
@ 2023-03-06 6:10 ` Jan Kiszka
8 siblings, 0 replies; 12+ messages in thread
From: Jan Kiszka @ 2023-03-06 6:10 UTC (permalink / raw)
To: Felix Moessbauer, cip-dev; +Cc: daniel.bovensiepen, quirin.gylstorff
On 03.03.23 13:48, Felix Moessbauer wrote:
> Changes since v3:
>
> - rebased onto next
> - add patch to clarify situation around watchdog on arm*
> - u-boot: remove irrelevant patch around FPU
>
> Changes since v2:
>
> The v2 adds the required infrastructure to test the swupdate support
> in qemu-riscv64. This includes the following additions:
>
> - update of cip kernel config for qemu-riscv64 machine (for non swu case)
> - refactoring of u-boot deploy logic as preparation for next patches
> - u-boot + opensbi firmware for qemu
> - addition of linux 6.1 mainline kernel to support EFI boot of riscv64
> in qemu
> - extension of start-qemu script to boot riscv64 with swupdate support
>
> Changes since v1:
>
> - rebased onto next
> - ebg: fix changelog version (no <orig-version>)
> - add swupdate support for qemu-riscv64
>
> Please note: The EBG support in cip-core needs a major rework to be in
> sync with the upstream debian package names. Currently, sid cannot be
> updated to a more recent revision, as this breaks the build (multiple
> packages with different names provide the same binary).
>
> Best regards,
> Felix Moessbauer
> Siemens AG
>
> Felix Moessbauer (8):
> make reason for disabling wdog on arm more precise
> fix efibootguard for riscv64
> wic(ebg): add support for riscv64
> add opensbi with u-boot payload for riscv64
> enhance qemu-riscv64 machine to be testable
> add linux 6.1 mainline kernel
> add swupdate support for qemu-riscv64
> start-qemu: add support for swupdate on RISC-V
>
> Kconfig | 6 +-
> conf/machine/qemu-arm.conf | 2 +-
> conf/machine/qemu-arm64.conf | 2 +-
> conf/machine/qemu-riscv64.conf | 9 ++-
> kas/opt/6.1-mainline.yml | 18 ++++++
> kas/opt/ebg-swu.yml | 1 +
> recipes-bsp/efibootguard/efibootguard_0.13.bb | 3 +
> ...01-add-machine-type-name-for-riscv64.patch | 39 +++++++++++++
> recipes-bsp/opensbi/files/qemu-riscv64-rules | 12 ++++
> .../opensbi/opensbi-qemu-riscv64_1.2.bb | 8 +++
> recipes-bsp/opensbi/opensbi.inc | 45 +++++++++++++++
> ...iscv-Fix-build-against-binutils-2.38.patch | 55 +++++++++++++++++++
> .../u-boot/u-boot-qemu-riscv64_2022.07.bb | 22 ++++++++
> recipes-kernel/linux/files/squashfs.cfg | 1 +
> recipes-kernel/linux/linux-mainline_6.1.bb | 18 ++++++
> .../wic/plugins/source/efibootguard-boot.py | 6 +-
> .../wic/plugins/source/efibootguard-efi.py | 6 +-
> start-qemu.sh | 8 +++
> wic/qemu-riscv64-efibootguard.wks.in | 13 +++++
> 19 files changed, 266 insertions(+), 8 deletions(-)
> create mode 100644 kas/opt/6.1-mainline.yml
> create mode 100644 recipes-bsp/efibootguard/files/0001-add-machine-type-name-for-riscv64.patch
> create mode 100644 recipes-bsp/opensbi/files/qemu-riscv64-rules
> create mode 100644 recipes-bsp/opensbi/opensbi-qemu-riscv64_1.2.bb
> create mode 100644 recipes-bsp/opensbi/opensbi.inc
> create mode 100644 recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch
> create mode 100644 recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb
> create mode 100644 recipes-kernel/linux/files/squashfs.cfg
> create mode 100644 recipes-kernel/linux/linux-mainline_6.1.bb
> create mode 100644 wic/qemu-riscv64-efibootguard.wks.in
>
Thanks, applied to next with the mentioned adjustments.
Jan
--
Siemens AG, Technology
Competence Center Embedded Linux
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