dmaengine Archive on lore.kernel.org
 help / color / Atom feed
* [PATCH v1] dmaengine: hsu: Revert "set HSU_CH_MTSR to memory width"
@ 2019-06-13 13:32 Andy Shevchenko
  2019-06-24 12:00 ` Vinod Koul
  0 siblings, 1 reply; 2+ messages in thread
From: Andy Shevchenko @ 2019-06-13 13:32 UTC (permalink / raw)
  To: Vinod Koul, dmaengine, Dan Williams; +Cc: Andy Shevchenko

The commit

  080edf75d337 ("dmaengine: hsu: set HSU_CH_MTSR to memory width")

has been mistakenly submitted. The further investigations show that
the original code does better job since the memory side transfer size
has never been configured by DMA users.

As per latest revision of documentation: "Channel minimum transfer size
(CHnMTSR)... For IOSF UART, maximum value that can be programmed is 64 and
minimum value that can be programmed is 1."

This reverts commit 080edf75d337d35faa6fc3df99342b10d2848d16.

Fixes: 080edf75d337 ("dmaengine: hsu: set HSU_CH_MTSR to memory width")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/dma/hsu/hsu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/hsu/hsu.c b/drivers/dma/hsu/hsu.c
index e06f20272fd7..dfabc64c2ab0 100644
--- a/drivers/dma/hsu/hsu.c
+++ b/drivers/dma/hsu/hsu.c
@@ -64,10 +64,10 @@ static void hsu_dma_chan_start(struct hsu_dma_chan *hsuc)
 
 	if (hsuc->direction == DMA_MEM_TO_DEV) {
 		bsr = config->dst_maxburst;
-		mtsr = config->src_addr_width;
+		mtsr = config->dst_addr_width;
 	} else if (hsuc->direction == DMA_DEV_TO_MEM) {
 		bsr = config->src_maxburst;
-		mtsr = config->dst_addr_width;
+		mtsr = config->src_addr_width;
 	}
 
 	hsu_chan_disable(hsuc);
-- 
2.20.1


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH v1] dmaengine: hsu: Revert "set HSU_CH_MTSR to memory width"
  2019-06-13 13:32 [PATCH v1] dmaengine: hsu: Revert "set HSU_CH_MTSR to memory width" Andy Shevchenko
@ 2019-06-24 12:00 ` Vinod Koul
  0 siblings, 0 replies; 2+ messages in thread
From: Vinod Koul @ 2019-06-24 12:00 UTC (permalink / raw)
  To: Andy Shevchenko; +Cc: dmaengine, Dan Williams

On 13-06-19, 16:32, Andy Shevchenko wrote:
> The commit
> 
>   080edf75d337 ("dmaengine: hsu: set HSU_CH_MTSR to memory width")
> 
> has been mistakenly submitted. The further investigations show that
> the original code does better job since the memory side transfer size
> has never been configured by DMA users.
> 
> As per latest revision of documentation: "Channel minimum transfer size
> (CHnMTSR)... For IOSF UART, maximum value that can be programmed is 64 and
> minimum value that can be programmed is 1."

Applied, thanks

-- 
~Vinod

^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, back to index

Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-13 13:32 [PATCH v1] dmaengine: hsu: Revert "set HSU_CH_MTSR to memory width" Andy Shevchenko
2019-06-24 12:00 ` Vinod Koul

dmaengine Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/dmaengine/0 dmaengine/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 dmaengine dmaengine/ https://lore.kernel.org/dmaengine \
		dmaengine@vger.kernel.org
	public-inbox-index dmaengine

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.dmaengine


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git