* [PATCH v6 1/3] drm/fourcc: Add 64 bpp half float formats
2019-03-13 0:38 [PATCH v6 0/3] Support 64 bpp half float formats Kevin Strasser
@ 2019-03-13 0:38 ` Kevin Strasser
2019-03-13 0:38 ` [PATCH v6 2/3] drm/i915: Refactor icl_is_hdr_plane Kevin Strasser
2019-03-13 0:38 ` [PATCH v6 3/3] drm/i915/icl: Implement half float formats Kevin Strasser
2 siblings, 0 replies; 6+ messages in thread
From: Kevin Strasser @ 2019-03-13 0:38 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: David Airlie, Daniel Vetter, Adam Jackson
Add 64 bpp 16:16:16:16 half float pixel formats. Each 16 bit component is
formatted in IEEE-754 half-precision float (binary16) 1:5:10
MSb-sign:exponent:fraction form.
This patch attempts to address the feedback provided when 2 of these
formats were previosly proposed:
https://patchwork.kernel.org/patch/10072545/
v2:
- Fixed cpp (Ville)
- Added detail pixel formatting (Ville)
- Ordered formats in header (Ville)
v5:
- .depth should be 0 for new formats (Maarten)
Cc: Tina Zhang <tina.zhang@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
---
drivers/gpu/drm/drm_fourcc.c | 4 ++++
include/uapi/drm/drm_fourcc.h | 11 +++++++++++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 3684c49..b914b16 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -198,6 +198,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_RGBA8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_RGB888_A8, .depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_BGR888_A8, .depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_XRGB8888_A8, .depth = 32, .num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index dc99e7f..5010b47 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -144,6 +144,17 @@ extern "C" {
#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
+/*
+ * Floating point 64bpp RGB
+ * IEEE 754-2008 binary16 half-precision float
+ * [15:0] sign:exponent:mantissa 1:5:10
+ */
+#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
+
+#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
+
/* packed YCbCr */
#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
--
2.7.4
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v6 2/3] drm/i915: Refactor icl_is_hdr_plane
2019-03-13 0:38 [PATCH v6 0/3] Support 64 bpp half float formats Kevin Strasser
2019-03-13 0:38 ` [PATCH v6 1/3] drm/fourcc: Add " Kevin Strasser
@ 2019-03-13 0:38 ` Kevin Strasser
2019-03-13 0:38 ` [PATCH v6 3/3] drm/i915/icl: Implement half float formats Kevin Strasser
2 siblings, 0 replies; 6+ messages in thread
From: Kevin Strasser @ 2019-03-13 0:38 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: David Airlie, Daniel Vetter, Adam Jackson
Change the api in order to enable callers that can't supply a valid
intel_plane pointer, as would be the case prior to calling
drm_universal_plane_init.
v4:
- Rename variables and move a declaration (Ville)
v6:
- Rebase and fix merge conflict
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
---
drivers/gpu/drm/i915/intel_atomic.c | 3 ++-
drivers/gpu/drm/i915/intel_display.c | 7 +++++--
drivers/gpu/drm/i915/intel_drv.h | 7 ++++---
drivers/gpu/drm/i915/intel_sprite.c | 6 +++---
4 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index da419e1..b844e88 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -235,10 +235,11 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
if (plane_state && plane_state->base.fb &&
plane_state->base.fb->format->is_yuv &&
plane_state->base.fb->format->num_planes > 1) {
+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
if (IS_GEN(dev_priv, 9) &&
!IS_GEMINILAKE(dev_priv)) {
mode = SKL_PS_SCALER_MODE_NV12;
- } else if (icl_is_hdr_plane(to_intel_plane(plane_state->base.plane))) {
+ } else if (icl_is_hdr_plane(dev_priv, plane->id)) {
/*
* On gen11+'s HDR planes we only use the scaler for
* scaling. They have a dedicated chroma upsampler, so
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d11cec1..60fbe3a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3781,6 +3781,8 @@ u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->base.plane->dev);
const struct drm_framebuffer *fb = plane_state->base.fb;
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
u32 plane_color_ctl = 0;
@@ -3788,7 +3790,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
- if (fb->format->is_yuv && !icl_is_hdr_plane(plane)) {
+ if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
else
@@ -5101,13 +5103,14 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
{
struct intel_plane *intel_plane =
to_intel_plane(plane_state->base.plane);
+ struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
struct drm_framebuffer *fb = plane_state->base.fb;
int ret;
bool force_detach = !fb || !plane_state->base.visible;
bool need_scaler = false;
/* Pre-gen11 and SDR planes always need a scaler for planar formats. */
- if (!icl_is_hdr_plane(intel_plane) &&
+ if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
fb && is_planar_yuv_format(fb->format->format))
need_scaler = true;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 40ebc94..a26c2cb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2436,12 +2436,13 @@ static inline bool icl_is_nv12_y_plane(enum plane_id id)
return false;
}
-static inline bool icl_is_hdr_plane(struct intel_plane *plane)
+static inline bool icl_is_hdr_plane(struct drm_i915_private *dev_priv,
+ enum plane_id plane_id)
{
- if (INTEL_GEN(to_i915(plane->base.dev)) < 11)
+ if (INTEL_GEN(dev_priv) < 11)
return false;
- return plane->id < PLANE_SPRITE2;
+ return plane_id < PLANE_SPRITE2;
}
/* intel_tv.c */
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 89d7bf7..622669f 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -349,7 +349,7 @@ skl_program_scaler(struct intel_plane *plane,
/* TODO: handle sub-pixel coordinates */
if (is_planar_yuv_format(plane_state->base.fb->format->format) &&
- !icl_is_hdr_plane(plane)) {
+ !icl_is_hdr_plane(dev_priv, plane->id)) {
y_hphase = skl_scaler_calc_phase(1, hscale, false);
y_vphase = skl_scaler_calc_phase(1, vscale, false);
@@ -531,7 +531,7 @@ skl_program_plane(struct intel_plane *plane,
I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
(plane_state->color_plane[1].offset - surf_addr) | aux_stride);
- if (icl_is_hdr_plane(plane)) {
+ if (icl_is_hdr_plane(dev_priv, plane_id)) {
u32 cus_ctl = 0;
if (linked) {
@@ -555,7 +555,7 @@ skl_program_plane(struct intel_plane *plane,
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
- if (fb->format->is_yuv && icl_is_hdr_plane(plane))
+ if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
skl_write_plane_wm(plane, crtc_state);
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v6 3/3] drm/i915/icl: Implement half float formats
2019-03-13 0:38 [PATCH v6 0/3] Support 64 bpp half float formats Kevin Strasser
2019-03-13 0:38 ` [PATCH v6 1/3] drm/fourcc: Add " Kevin Strasser
2019-03-13 0:38 ` [PATCH v6 2/3] drm/i915: Refactor icl_is_hdr_plane Kevin Strasser
@ 2019-03-13 0:38 ` Kevin Strasser
2019-03-13 7:25 ` Maarten Lankhorst
2 siblings, 1 reply; 6+ messages in thread
From: Kevin Strasser @ 2019-03-13 0:38 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: David Airlie, Daniel Vetter, Adam Jackson
64 bpp half float formats are supported on hdr planes only and are subject
to the following restrictions:
* 90/270 rotation not supported
* Yf Tiling not supported
* Frame Buffer Compression not supported
* Color Keying not supported
v2:
- Drop handling pixel normalize register
- Don't use icl_is_hdr_plane too early
v3:
- Use refactored icl_is_hdr_plane (Ville)
- Use u32 instead of uint32_t (Ville)
v6:
- Rebase and fix merge conflicts
- Reorganize switch statements to keep RGB grouped separately from YUV
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
---
drivers/gpu/drm/i915/intel_display.c | 22 +++++++++++
drivers/gpu/drm/i915/intel_sprite.c | 72 ++++++++++++++++++++++++++++++++++--
2 files changed, 91 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 60fbe3a..eaedf91 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2680,6 +2680,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
return DRM_FORMAT_XBGR2101010;
else
return DRM_FORMAT_XRGB2101010;
+ case PLANE_CTL_FORMAT_XRGB_16161616F:
+ if (rgb_order) {
+ if (alpha)
+ return DRM_FORMAT_ABGR16161616F;
+ else
+ return DRM_FORMAT_XBGR16161616F;
+ } else {
+ if (alpha)
+ return DRM_FORMAT_ARGB16161616F;
+ else
+ return DRM_FORMAT_XRGB16161616F;
+ }
}
}
@@ -3575,6 +3587,12 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
return PLANE_CTL_FORMAT_XRGB_2101010;
case DRM_FORMAT_XBGR2101010:
return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_ARGB16161616F:
+ return PLANE_CTL_FORMAT_XRGB_16161616F;
case DRM_FORMAT_YUYV:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
case DRM_FORMAT_YVYU:
@@ -5143,6 +5161,10 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_ARGB16161616F:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 622669f..e00559d 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1508,8 +1508,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
/*
* 90/270 is not allowed with RGB64 16:16:16:16 and
* Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
- * TBD: Add RGB64 case once its added in supported format
- * list.
*/
switch (fb->format->format) {
case DRM_FORMAT_RGB565:
@@ -1517,6 +1515,10 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
break;
/* fall through */
case DRM_FORMAT_C8:
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ARGB16161616F:
+ case DRM_FORMAT_ABGR16161616F:
DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
drm_get_format_name(fb->format->format,
&format_name));
@@ -1837,6 +1839,31 @@ static const uint32_t icl_plane_formats[] = {
DRM_FORMAT_Y416,
};
+static const uint32_t icl_hdr_plane_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_XBGR16161616F,
+ DRM_FORMAT_ARGB16161616F,
+ DRM_FORMAT_ABGR16161616F,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_Y210,
+ DRM_FORMAT_Y212,
+ DRM_FORMAT_Y216,
+ DRM_FORMAT_Y410,
+ DRM_FORMAT_Y412,
+ DRM_FORMAT_Y416,
+};
+
static const u32 skl_planar_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
@@ -1897,6 +1924,35 @@ static const uint32_t icl_planar_formats[] = {
DRM_FORMAT_Y416,
};
+static const uint32_t icl_hdr_planar_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_XBGR16161616F,
+ DRM_FORMAT_ARGB16161616F,
+ DRM_FORMAT_ABGR16161616F,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_P010,
+ DRM_FORMAT_P012,
+ DRM_FORMAT_P016,
+ DRM_FORMAT_Y210,
+ DRM_FORMAT_Y212,
+ DRM_FORMAT_Y216,
+ DRM_FORMAT_Y410,
+ DRM_FORMAT_Y412,
+ DRM_FORMAT_Y416,
+};
+
static const u64 skl_plane_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -2049,6 +2105,10 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
return true;
/* fall through */
case DRM_FORMAT_C8:
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_ARGB16161616F:
if (modifier == DRM_FORMAT_MOD_LINEAR ||
modifier == I915_FORMAT_MOD_X_TILED ||
modifier == I915_FORMAT_MOD_Y_TILED)
@@ -2185,7 +2245,10 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->update_slave = icl_update_slave;
if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (icl_is_hdr_plane(dev_priv, plane_id)) {
+ formats = icl_hdr_planar_formats;
+ num_formats = ARRAY_SIZE(icl_hdr_planar_formats);
+ } else if (INTEL_GEN(dev_priv) >= 11) {
formats = icl_planar_formats;
num_formats = ARRAY_SIZE(icl_planar_formats);
} else if (INTEL_GEN(dev_priv) == 10 || IS_GEMINILAKE(dev_priv)) {
@@ -2195,6 +2258,9 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
formats = skl_planar_formats;
num_formats = ARRAY_SIZE(skl_planar_formats);
}
+ } else if (icl_is_hdr_plane(dev_priv, plane_id)) {
+ formats = icl_hdr_plane_formats;
+ num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
} else if (INTEL_GEN(dev_priv) >= 11) {
formats = icl_plane_formats;
num_formats = ARRAY_SIZE(icl_plane_formats);
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v6 3/3] drm/i915/icl: Implement half float formats
2019-03-13 0:38 ` [PATCH v6 3/3] drm/i915/icl: Implement half float formats Kevin Strasser
@ 2019-03-13 7:25 ` Maarten Lankhorst
2019-03-13 11:17 ` Maarten Lankhorst
0 siblings, 1 reply; 6+ messages in thread
From: Maarten Lankhorst @ 2019-03-13 7:25 UTC (permalink / raw)
To: Kevin Strasser, dri-devel, intel-gfx
Cc: David Airlie, Daniel Vetter, Uma Shankar
Op 13-03-2019 om 01:38 schreef Kevin Strasser:
> 64 bpp half float formats are supported on hdr planes only and are subject
> to the following restrictions:
> * 90/270 rotation not supported
> * Yf Tiling not supported
> * Frame Buffer Compression not supported
> * Color Keying not supported
>
> v2:
> - Drop handling pixel normalize register
> - Don't use icl_is_hdr_plane too early
>
> v3:
> - Use refactored icl_is_hdr_plane (Ville)
> - Use u32 instead of uint32_t (Ville)
>
> v6:
> - Rebase and fix merge conflicts
> - Reorganize switch statements to keep RGB grouped separately from YUV
>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Shashank Sharma <shashank.sharma@intel.com>
> Cc: David Airlie <airlied@linux.ie>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Reviewed-by: Adam Jackson <ajax@redhat.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 22 +++++++++++
> drivers/gpu/drm/i915/intel_sprite.c | 72 ++++++++++++++++++++++++++++++++++--
> 2 files changed, 91 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 60fbe3a..eaedf91 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2680,6 +2680,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> return DRM_FORMAT_XBGR2101010;
> else
> return DRM_FORMAT_XRGB2101010;
> + case PLANE_CTL_FORMAT_XRGB_16161616F:
> + if (rgb_order) {
> + if (alpha)
> + return DRM_FORMAT_ABGR16161616F;
> + else
> + return DRM_FORMAT_XBGR16161616F;
> + } else {
> + if (alpha)
> + return DRM_FORMAT_ARGB16161616F;
> + else
> + return DRM_FORMAT_XRGB16161616F;
> + }
> }
> }
>
> @@ -3575,6 +3587,12 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
> return PLANE_CTL_FORMAT_XRGB_2101010;
> case DRM_FORMAT_XBGR2101010:
> return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
> + case DRM_FORMAT_XBGR16161616F:
> + case DRM_FORMAT_ABGR16161616F:
> + return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
> + case DRM_FORMAT_XRGB16161616F:
> + case DRM_FORMAT_ARGB16161616F:
> + return PLANE_CTL_FORMAT_XRGB_16161616F;
> case DRM_FORMAT_YUYV:
> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
> case DRM_FORMAT_YVYU:
> @@ -5143,6 +5161,10 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
> case DRM_FORMAT_ARGB8888:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
> + case DRM_FORMAT_XBGR16161616F:
> + case DRM_FORMAT_ABGR16161616F:
> + case DRM_FORMAT_XRGB16161616F:
> + case DRM_FORMAT_ARGB16161616F:
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 622669f..e00559d 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1508,8 +1508,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> /*
> * 90/270 is not allowed with RGB64 16:16:16:16 and
> * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
> - * TBD: Add RGB64 case once its added in supported format
> - * list.
> */
> switch (fb->format->format) {
> case DRM_FORMAT_RGB565:
> @@ -1517,6 +1515,10 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> break;
> /* fall through */
> case DRM_FORMAT_C8:
> + case DRM_FORMAT_XRGB16161616F:
> + case DRM_FORMAT_XBGR16161616F:
> + case DRM_FORMAT_ARGB16161616F:
> + case DRM_FORMAT_ABGR16161616F:
> DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
> drm_get_format_name(fb->format->format,
> &format_name));
> @@ -1837,6 +1839,31 @@ static const uint32_t icl_plane_formats[] = {
> DRM_FORMAT_Y416,
> };
>
> +static const uint32_t icl_hdr_plane_formats[] = {
> + DRM_FORMAT_C8,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_XRGB16161616F,
> + DRM_FORMAT_XBGR16161616F,
> + DRM_FORMAT_ARGB16161616F,
> + DRM_FORMAT_ABGR16161616F,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_VYUY,
> + DRM_FORMAT_Y210,
> + DRM_FORMAT_Y212,
> + DRM_FORMAT_Y216,
> + DRM_FORMAT_Y410,
> + DRM_FORMAT_Y412,
> + DRM_FORMAT_Y416,
> +};
> +
> static const u32 skl_planar_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
> @@ -1897,6 +1924,35 @@ static const uint32_t icl_planar_formats[] = {
> DRM_FORMAT_Y416,
> };
>
> +static const uint32_t icl_hdr_planar_formats[] = {
> + DRM_FORMAT_C8,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_XRGB16161616F,
> + DRM_FORMAT_XBGR16161616F,
> + DRM_FORMAT_ARGB16161616F,
> + DRM_FORMAT_ABGR16161616F,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_VYUY,
> + DRM_FORMAT_NV12,
> + DRM_FORMAT_P010,
> + DRM_FORMAT_P012,
> + DRM_FORMAT_P016,
> + DRM_FORMAT_Y210,
> + DRM_FORMAT_Y212,
> + DRM_FORMAT_Y216,
> + DRM_FORMAT_Y410,
> + DRM_FORMAT_Y412,
> + DRM_FORMAT_Y416,
> +};
> +
> static const u64 skl_plane_format_modifiers_noccs[] = {
> I915_FORMAT_MOD_Yf_TILED,
> I915_FORMAT_MOD_Y_TILED,
> @@ -2049,6 +2105,10 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> return true;
> /* fall through */
> case DRM_FORMAT_C8:
> + case DRM_FORMAT_XBGR16161616F:
> + case DRM_FORMAT_ABGR16161616F:
> + case DRM_FORMAT_XRGB16161616F:
> + case DRM_FORMAT_ARGB16161616F:
> if (modifier == DRM_FORMAT_MOD_LINEAR ||
> modifier == I915_FORMAT_MOD_X_TILED ||
> modifier == I915_FORMAT_MOD_Y_TILED)
> @@ -2185,7 +2245,10 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> plane->update_slave = icl_update_slave;
>
> if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
> - if (INTEL_GEN(dev_priv) >= 11) {
> + if (icl_is_hdr_plane(dev_priv, plane_id)) {
> + formats = icl_hdr_planar_formats;
> + num_formats = ARRAY_SIZE(icl_hdr_planar_formats);
> + } else if (INTEL_GEN(dev_priv) >= 11) {
> formats = icl_planar_formats;
> num_formats = ARRAY_SIZE(icl_planar_formats);
> } else if (INTEL_GEN(dev_priv) == 10 || IS_GEMINILAKE(dev_priv)) {
> @@ -2195,6 +2258,9 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> formats = skl_planar_formats;
> num_formats = ARRAY_SIZE(skl_planar_formats);
> }
> + } else if (icl_is_hdr_plane(dev_priv, plane_id)) {
> + formats = icl_hdr_plane_formats;
> + num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
This hunk is unreachable because is_hdr_plane is a subset of skl_plane_has_planar, I will drop it and commit. :)
Thanks,
~Maarten
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v6 3/3] drm/i915/icl: Implement half float formats
2019-03-13 7:25 ` Maarten Lankhorst
@ 2019-03-13 11:17 ` Maarten Lankhorst
0 siblings, 0 replies; 6+ messages in thread
From: Maarten Lankhorst @ 2019-03-13 11:17 UTC (permalink / raw)
To: Kevin Strasser, dri-devel, intel-gfx
Cc: David Airlie, Daniel Vetter, Adam Jackson
Op 13-03-2019 om 08:25 schreef Maarten Lankhorst:
> Op 13-03-2019 om 01:38 schreef Kevin Strasser:
>> 64 bpp half float formats are supported on hdr planes only and are subject
>> to the following restrictions:
>> * 90/270 rotation not supported
>> * Yf Tiling not supported
>> * Frame Buffer Compression not supported
>> * Color Keying not supported
>>
>> v2:
>> - Drop handling pixel normalize register
>> - Don't use icl_is_hdr_plane too early
>>
>> v3:
>> - Use refactored icl_is_hdr_plane (Ville)
>> - Use u32 instead of uint32_t (Ville)
>>
>> v6:
>> - Rebase and fix merge conflicts
>> - Reorganize switch statements to keep RGB grouped separately from YUV
>>
>> Cc: Uma Shankar <uma.shankar@intel.com>
>> Cc: Shashank Sharma <shashank.sharma@intel.com>
>> Cc: David Airlie <airlied@linux.ie>
>> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
>> Cc: dri-devel@lists.freedesktop.org
>> Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> Reviewed-by: Adam Jackson <ajax@redhat.com>
>> ---
>> drivers/gpu/drm/i915/intel_display.c | 22 +++++++++++
>> drivers/gpu/drm/i915/intel_sprite.c | 72 ++++++++++++++++++++++++++++++++++--
>> 2 files changed, 91 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 60fbe3a..eaedf91 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -2680,6 +2680,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
>> return DRM_FORMAT_XBGR2101010;
>> else
>> return DRM_FORMAT_XRGB2101010;
>> + case PLANE_CTL_FORMAT_XRGB_16161616F:
>> + if (rgb_order) {
>> + if (alpha)
>> + return DRM_FORMAT_ABGR16161616F;
>> + else
>> + return DRM_FORMAT_XBGR16161616F;
>> + } else {
>> + if (alpha)
>> + return DRM_FORMAT_ARGB16161616F;
>> + else
>> + return DRM_FORMAT_XRGB16161616F;
>> + }
>> }
>> }
>>
>> @@ -3575,6 +3587,12 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
>> return PLANE_CTL_FORMAT_XRGB_2101010;
>> case DRM_FORMAT_XBGR2101010:
>> return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
>> + case DRM_FORMAT_XBGR16161616F:
>> + case DRM_FORMAT_ABGR16161616F:
>> + return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
>> + case DRM_FORMAT_XRGB16161616F:
>> + case DRM_FORMAT_ARGB16161616F:
>> + return PLANE_CTL_FORMAT_XRGB_16161616F;
>> case DRM_FORMAT_YUYV:
>> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
>> case DRM_FORMAT_YVYU:
>> @@ -5143,6 +5161,10 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
>> case DRM_FORMAT_ARGB8888:
>> case DRM_FORMAT_XRGB2101010:
>> case DRM_FORMAT_XBGR2101010:
>> + case DRM_FORMAT_XBGR16161616F:
>> + case DRM_FORMAT_ABGR16161616F:
>> + case DRM_FORMAT_XRGB16161616F:
>> + case DRM_FORMAT_ARGB16161616F:
>> case DRM_FORMAT_YUYV:
>> case DRM_FORMAT_YVYU:
>> case DRM_FORMAT_UYVY:
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
>> index 622669f..e00559d 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -1508,8 +1508,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>> /*
>> * 90/270 is not allowed with RGB64 16:16:16:16 and
>> * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
>> - * TBD: Add RGB64 case once its added in supported format
>> - * list.
>> */
>> switch (fb->format->format) {
>> case DRM_FORMAT_RGB565:
>> @@ -1517,6 +1515,10 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>> break;
>> /* fall through */
>> case DRM_FORMAT_C8:
>> + case DRM_FORMAT_XRGB16161616F:
>> + case DRM_FORMAT_XBGR16161616F:
>> + case DRM_FORMAT_ARGB16161616F:
>> + case DRM_FORMAT_ABGR16161616F:
>> DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
>> drm_get_format_name(fb->format->format,
>> &format_name));
>> @@ -1837,6 +1839,31 @@ static const uint32_t icl_plane_formats[] = {
>> DRM_FORMAT_Y416,
>> };
>>
>> +static const uint32_t icl_hdr_plane_formats[] = {
>> + DRM_FORMAT_C8,
>> + DRM_FORMAT_RGB565,
>> + DRM_FORMAT_XRGB8888,
>> + DRM_FORMAT_XBGR8888,
>> + DRM_FORMAT_ARGB8888,
>> + DRM_FORMAT_ABGR8888,
>> + DRM_FORMAT_XRGB2101010,
>> + DRM_FORMAT_XBGR2101010,
>> + DRM_FORMAT_XRGB16161616F,
>> + DRM_FORMAT_XBGR16161616F,
>> + DRM_FORMAT_ARGB16161616F,
>> + DRM_FORMAT_ABGR16161616F,
>> + DRM_FORMAT_YUYV,
>> + DRM_FORMAT_YVYU,
>> + DRM_FORMAT_UYVY,
>> + DRM_FORMAT_VYUY,
>> + DRM_FORMAT_Y210,
>> + DRM_FORMAT_Y212,
>> + DRM_FORMAT_Y216,
>> + DRM_FORMAT_Y410,
>> + DRM_FORMAT_Y412,
>> + DRM_FORMAT_Y416,
>> +};
>> +
>> static const u32 skl_planar_formats[] = {
>> DRM_FORMAT_C8,
>> DRM_FORMAT_RGB565,
>> @@ -1897,6 +1924,35 @@ static const uint32_t icl_planar_formats[] = {
>> DRM_FORMAT_Y416,
>> };
>>
>> +static const uint32_t icl_hdr_planar_formats[] = {
>> + DRM_FORMAT_C8,
>> + DRM_FORMAT_RGB565,
>> + DRM_FORMAT_XRGB8888,
>> + DRM_FORMAT_XBGR8888,
>> + DRM_FORMAT_ARGB8888,
>> + DRM_FORMAT_ABGR8888,
>> + DRM_FORMAT_XRGB2101010,
>> + DRM_FORMAT_XBGR2101010,
>> + DRM_FORMAT_XRGB16161616F,
>> + DRM_FORMAT_XBGR16161616F,
>> + DRM_FORMAT_ARGB16161616F,
>> + DRM_FORMAT_ABGR16161616F,
>> + DRM_FORMAT_YUYV,
>> + DRM_FORMAT_YVYU,
>> + DRM_FORMAT_UYVY,
>> + DRM_FORMAT_VYUY,
>> + DRM_FORMAT_NV12,
>> + DRM_FORMAT_P010,
>> + DRM_FORMAT_P012,
>> + DRM_FORMAT_P016,
>> + DRM_FORMAT_Y210,
>> + DRM_FORMAT_Y212,
>> + DRM_FORMAT_Y216,
>> + DRM_FORMAT_Y410,
>> + DRM_FORMAT_Y412,
>> + DRM_FORMAT_Y416,
>> +};
>> +
>> static const u64 skl_plane_format_modifiers_noccs[] = {
>> I915_FORMAT_MOD_Yf_TILED,
>> I915_FORMAT_MOD_Y_TILED,
>> @@ -2049,6 +2105,10 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>> return true;
>> /* fall through */
>> case DRM_FORMAT_C8:
>> + case DRM_FORMAT_XBGR16161616F:
>> + case DRM_FORMAT_ABGR16161616F:
>> + case DRM_FORMAT_XRGB16161616F:
>> + case DRM_FORMAT_ARGB16161616F:
>> if (modifier == DRM_FORMAT_MOD_LINEAR ||
>> modifier == I915_FORMAT_MOD_X_TILED ||
>> modifier == I915_FORMAT_MOD_Y_TILED)
>> @@ -2185,7 +2245,10 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>> plane->update_slave = icl_update_slave;
>>
>> if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
>> - if (INTEL_GEN(dev_priv) >= 11) {
>> + if (icl_is_hdr_plane(dev_priv, plane_id)) {
>> + formats = icl_hdr_planar_formats;
>> + num_formats = ARRAY_SIZE(icl_hdr_planar_formats);
>> + } else if (INTEL_GEN(dev_priv) >= 11) {
>> formats = icl_planar_formats;
>> num_formats = ARRAY_SIZE(icl_planar_formats);
>> } else if (INTEL_GEN(dev_priv) == 10 || IS_GEMINILAKE(dev_priv)) {
>> @@ -2195,6 +2258,9 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>> formats = skl_planar_formats;
>> num_formats = ARRAY_SIZE(skl_planar_formats);
>> }
>> + } else if (icl_is_hdr_plane(dev_priv, plane_id)) {
>> + formats = icl_hdr_plane_formats;
>> + num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
> This hunk is unreachable because is_hdr_plane is a subset of skl_plane_has_planar, I will drop it and commit. :)
Left it here for now, we might have to disable planar formats for testing.
Thanks for the patches, pushed. :)
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^ permalink raw reply [flat|nested] 6+ messages in thread