From: Tomi Valkeinen <tomi.valkeinen@ti.com>
To: Archit Taneja <architt@codeaurora.org>,
Andrzej Hajda <a.hajda@samsung.com>,
dri-devel@lists.freedesktop.org,
Andrey Gusakov <andrey.gusakov@cogentembedded.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Subject: [PATCH 3/7] drm/bridge: tc358767: fix single lane configuration
Date: Mon, 29 Oct 2018 13:46:57 +0200 [thread overview]
Message-ID: <20181029114701.26409-4-tomi.valkeinen@ti.com> (raw)
In-Reply-To: <20181029114701.26409-1-tomi.valkeinen@ti.com>
PHY_2LANE bit is always set in DP_PHY_CTRL, breaking 1 lane use.
Set PHY_2LANE only when 2 lanes are used.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
drivers/gpu/drm/bridge/tc358767.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index 5f0a666db2fd..fee53422c31f 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -543,6 +543,7 @@ static int tc_aux_link_setup(struct tc_data *tc)
unsigned long rate;
u32 value;
int ret;
+ u32 dp_phy_ctrl;
rate = clk_get_rate(tc->refclk);
switch (rate) {
@@ -567,7 +568,10 @@ static int tc_aux_link_setup(struct tc_data *tc)
value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
tc_write(SYS_PLLPARAM, value);
- tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | PHY_2LANE | PHY_A0_EN);
+ dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN;
+ if (tc->link.base.num_lanes == 2)
+ dp_phy_ctrl |= PHY_2LANE;
+ tc_write(DP_PHY_CTRL, dp_phy_ctrl);
/*
* Initially PLLs are in bypass. Force PLL parameter update,
@@ -860,7 +864,9 @@ static int tc_main_link_setup(struct tc_data *tc)
tc_write(SYS_PLLPARAM, value);
/* Setup Main Link */
- dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_2LANE | PHY_A0_EN | PHY_M0_EN;
+ dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
+ if (tc->link.base.num_lanes == 2)
+ dp_phy_ctrl |= PHY_2LANE;
tc_write(DP_PHY_CTRL, dp_phy_ctrl);
msleep(100);
--
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next prev parent reply other threads:[~2018-10-29 11:47 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-29 11:46 [PATCH 0/7] drm/bridge: tc358767: small fixes Tomi Valkeinen
2018-10-29 11:46 ` [PATCH 1/7] drm/bridge: tc358767: add bus flags Tomi Valkeinen
2018-11-19 7:37 ` Andrzej Hajda
2018-10-29 11:46 ` [PATCH 2/7] drm/bridge: tc358767: add defines for DP1_SRCCTRL & PHY_2LANE Tomi Valkeinen
2018-11-19 7:37 ` Andrzej Hajda
2018-10-29 11:46 ` Tomi Valkeinen [this message]
2018-11-19 7:36 ` [PATCH 3/7] drm/bridge: tc358767: fix single lane configuration Andrzej Hajda
2018-10-29 11:46 ` [PATCH 4/7] drm/bridge: tc358767: fix initial DP0/1_SRCCTRL value Tomi Valkeinen
2018-11-19 7:29 ` Andrzej Hajda
2018-11-27 11:38 ` Tomi Valkeinen
2018-10-29 11:46 ` [PATCH 5/7] drm/bridge: tc358767: reject modes which require too much BW Tomi Valkeinen
2018-11-19 7:36 ` Andrzej Hajda
2018-11-27 11:45 ` Tomi Valkeinen
2018-10-29 11:47 ` [PATCH 6/7] drm/bridge: tc358767: fix output H/V syncs Tomi Valkeinen
2018-11-19 7:33 ` Andrzej Hajda
2018-11-27 11:56 ` Tomi Valkeinen
2018-10-29 11:47 ` [PATCH 7/7] drm/bridge: tc358767: use DP connector if no panel set Tomi Valkeinen
2018-11-19 7:34 ` Andrzej Hajda
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