From: Tomi Valkeinen <tomi.valkeinen@ti.com>
To: Archit Taneja <architt@codeaurora.org>,
Andrzej Hajda <a.hajda@samsung.com>,
dri-devel@lists.freedesktop.org,
Andrey Gusakov <andrey.gusakov@cogentembedded.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Subject: [PATCH 4/7] drm/bridge: tc358767: fix initial DP0/1_SRCCTRL value
Date: Mon, 29 Oct 2018 13:46:58 +0200 [thread overview]
Message-ID: <20181029114701.26409-5-tomi.valkeinen@ti.com> (raw)
In-Reply-To: <20181029114701.26409-1-tomi.valkeinen@ti.com>
Initially DP0_SRCCTRL is set to a static value which includes
DP0_SRCCTRL_LANES_2 and DP0_SRCCTRL_BW27, even when only 1 lane of
1.62Gbps speed is used. DP1_SRCCTRL is configured to a magic number.
This patch changes the configuration as follows:
Configure DP0_SRCCTRL by using tc_srcctrl() which provides the correct
value.
DP1_SRCCTRL needs to bits to be set to the same value as DP0_SRCCTRL:
SSCG and BW27. All other bits can be zero.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
drivers/gpu/drm/bridge/tc358767.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index fee53422c31f..ab299f4debfa 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -836,12 +836,11 @@ static int tc_main_link_setup(struct tc_data *tc)
if (!tc->mode)
return -EINVAL;
- /* from excel file - DP0_SrcCtrl */
- tc_write(DP0_SRCCTRL, DP0_SRCCTRL_SCRMBLDIS | DP0_SRCCTRL_EN810B |
- DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_LANES_2 |
- DP0_SRCCTRL_BW27 | DP0_SRCCTRL_AUTOCORRECT);
- /* from excel file - DP1_SrcCtrl */
- tc_write(DP1_SRCCTRL, 0x00003083);
+ tc_write(DP0_SRCCTRL, tc_srcctrl(tc));
+ /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
+ tc_write(DP1_SRCCTRL,
+ (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
+ ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
rate = clk_get_rate(tc->refclk);
switch (rate) {
--
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next prev parent reply other threads:[~2018-10-29 11:47 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-29 11:46 [PATCH 0/7] drm/bridge: tc358767: small fixes Tomi Valkeinen
2018-10-29 11:46 ` [PATCH 1/7] drm/bridge: tc358767: add bus flags Tomi Valkeinen
2018-11-19 7:37 ` Andrzej Hajda
2018-10-29 11:46 ` [PATCH 2/7] drm/bridge: tc358767: add defines for DP1_SRCCTRL & PHY_2LANE Tomi Valkeinen
2018-11-19 7:37 ` Andrzej Hajda
2018-10-29 11:46 ` [PATCH 3/7] drm/bridge: tc358767: fix single lane configuration Tomi Valkeinen
2018-11-19 7:36 ` Andrzej Hajda
2018-10-29 11:46 ` Tomi Valkeinen [this message]
2018-11-19 7:29 ` [PATCH 4/7] drm/bridge: tc358767: fix initial DP0/1_SRCCTRL value Andrzej Hajda
2018-11-27 11:38 ` Tomi Valkeinen
2018-10-29 11:46 ` [PATCH 5/7] drm/bridge: tc358767: reject modes which require too much BW Tomi Valkeinen
2018-11-19 7:36 ` Andrzej Hajda
2018-11-27 11:45 ` Tomi Valkeinen
2018-10-29 11:47 ` [PATCH 6/7] drm/bridge: tc358767: fix output H/V syncs Tomi Valkeinen
2018-11-19 7:33 ` Andrzej Hajda
2018-11-27 11:56 ` Tomi Valkeinen
2018-10-29 11:47 ` [PATCH 7/7] drm/bridge: tc358767: use DP connector if no panel set Tomi Valkeinen
2018-11-19 7:34 ` Andrzej Hajda
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