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From: Naveen Naidu <naveennaidu479@gmail.com>
To: bhelgaas@google.com
Cc: Naveen Naidu <naveennaidu479@gmail.com>,
	linux-kernel-mentees@lists.linuxfoundation.org,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	skhan@linuxfoundation.org
Subject: [PATCH v4 16/25] PCI/ERR: Use PCI_POSSIBLE_ERROR() to check read from hardware
Date: Thu, 18 Nov 2021 19:33:26 +0530	[thread overview]
Message-ID: <f4d18d470cb90f9cb52ea155b01528ba2e76e8d6.1637243717.git.naveennaidu479@gmail.com> (raw)
In-Reply-To: <cover.1637243717.git.naveennaidu479@gmail.com>

An MMIO read from a PCI device that doesn't exist or doesn't respond
causes a PCI error.  There's no real data to return to satisfy the
CPU read, so most hardware fabricates ~0 data.

Use PCI_POSSIBLE_ERROR() to check the response we get when we read
data from hardware.

This unifies PCI error response checking and make error checks
consistent and easier to find.

Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
---
 drivers/pci/pci.c   | 10 +++++-----
 drivers/pci/probe.c | 10 +++++-----
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 3d2fb394986a..bc82699ed105 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1115,7 +1115,7 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
 		return -EIO;
 
 	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
-	if (pmcsr == (u16) ~0) {
+	if (PCI_POSSIBLE_ERROR(pmcsr)) {
 		pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n",
 			pci_power_name(dev->current_state),
 			pci_power_name(state));
@@ -1271,16 +1271,16 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
 	 * After reset, the device should not silently discard config
 	 * requests, but it may still indicate that it needs more time by
 	 * responding to them with CRS completions.  The Root Port will
-	 * generally synthesize ~0 data to complete the read (except when
-	 * CRS SV is enabled and the read was for the Vendor ID; in that
-	 * case it synthesizes 0x0001 data).
+	 * generally synthesize ~0 (PCI_ERROR_RESPONSE) data to complete
+	 * the read (except when CRS SV is enabled and the read was for the
+	 * Vendor ID; in that case it synthesizes 0x0001 data).
 	 *
 	 * Wait for the device to return a non-CRS completion.  Read the
 	 * Command register instead of Vendor ID so we don't have to
 	 * contend with the CRS SV value.
 	 */
 	pci_read_config_dword(dev, PCI_COMMAND, &id);
-	while (id == ~0) {
+	while (PCI_POSSIBLE_ERROR(id)) {
 		if (delay > timeout) {
 			pci_warn(dev, "not ready %dms after %s; giving up\n",
 				 delay - 1, reset_type);
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 087d3658f75c..c48fe1ab1961 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -206,14 +206,14 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
 	 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
 	 * 1 must be clear.
 	 */
-	if (sz == 0xffffffff)
+	if (PCI_POSSIBLE_ERROR(sz))
 		sz = 0;
 
 	/*
 	 * I don't know how l can have all bits set.  Copied from old code.
 	 * Maybe it fixes a bug on some ancient platform.
 	 */
-	if (l == 0xffffffff)
+	if (PCI_POSSIBLE_ERROR(l))
 		l = 0;
 
 	if (type == pci_bar_unknown) {
@@ -1683,7 +1683,7 @@ static int pci_cfg_space_size_ext(struct pci_dev *dev)
 
 	if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
 		return PCI_CFG_SPACE_SIZE;
-	if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
+	if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev))
 		return PCI_CFG_SPACE_SIZE;
 
 	return PCI_CFG_SPACE_EXP_SIZE;
@@ -2371,8 +2371,8 @@ bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
 	if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
 		return false;
 
-	/* Some broken boards return 0 or ~0 if a slot is empty: */
-	if (*l == 0xffffffff || *l == 0x00000000 ||
+	/* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */
+	if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 ||
 	    *l == 0x0000ffff || *l == 0xffff0000)
 		return false;
 
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Naveen Naidu <naveennaidu479@gmail.com>
To: bhelgaas@google.com
Cc: linux-kernel-mentees@lists.linuxfoundation.org,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org
Subject: [PATCH v4 16/25] PCI/ERR: Use PCI_POSSIBLE_ERROR() to check read from hardware
Date: Thu, 18 Nov 2021 19:33:26 +0530	[thread overview]
Message-ID: <f4d18d470cb90f9cb52ea155b01528ba2e76e8d6.1637243717.git.naveennaidu479@gmail.com> (raw)
In-Reply-To: <cover.1637243717.git.naveennaidu479@gmail.com>

An MMIO read from a PCI device that doesn't exist or doesn't respond
causes a PCI error.  There's no real data to return to satisfy the
CPU read, so most hardware fabricates ~0 data.

Use PCI_POSSIBLE_ERROR() to check the response we get when we read
data from hardware.

This unifies PCI error response checking and make error checks
consistent and easier to find.

Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
---
 drivers/pci/pci.c   | 10 +++++-----
 drivers/pci/probe.c | 10 +++++-----
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 3d2fb394986a..bc82699ed105 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1115,7 +1115,7 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
 		return -EIO;
 
 	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
-	if (pmcsr == (u16) ~0) {
+	if (PCI_POSSIBLE_ERROR(pmcsr)) {
 		pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n",
 			pci_power_name(dev->current_state),
 			pci_power_name(state));
@@ -1271,16 +1271,16 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
 	 * After reset, the device should not silently discard config
 	 * requests, but it may still indicate that it needs more time by
 	 * responding to them with CRS completions.  The Root Port will
-	 * generally synthesize ~0 data to complete the read (except when
-	 * CRS SV is enabled and the read was for the Vendor ID; in that
-	 * case it synthesizes 0x0001 data).
+	 * generally synthesize ~0 (PCI_ERROR_RESPONSE) data to complete
+	 * the read (except when CRS SV is enabled and the read was for the
+	 * Vendor ID; in that case it synthesizes 0x0001 data).
 	 *
 	 * Wait for the device to return a non-CRS completion.  Read the
 	 * Command register instead of Vendor ID so we don't have to
 	 * contend with the CRS SV value.
 	 */
 	pci_read_config_dword(dev, PCI_COMMAND, &id);
-	while (id == ~0) {
+	while (PCI_POSSIBLE_ERROR(id)) {
 		if (delay > timeout) {
 			pci_warn(dev, "not ready %dms after %s; giving up\n",
 				 delay - 1, reset_type);
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 087d3658f75c..c48fe1ab1961 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -206,14 +206,14 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
 	 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
 	 * 1 must be clear.
 	 */
-	if (sz == 0xffffffff)
+	if (PCI_POSSIBLE_ERROR(sz))
 		sz = 0;
 
 	/*
 	 * I don't know how l can have all bits set.  Copied from old code.
 	 * Maybe it fixes a bug on some ancient platform.
 	 */
-	if (l == 0xffffffff)
+	if (PCI_POSSIBLE_ERROR(l))
 		l = 0;
 
 	if (type == pci_bar_unknown) {
@@ -1683,7 +1683,7 @@ static int pci_cfg_space_size_ext(struct pci_dev *dev)
 
 	if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
 		return PCI_CFG_SPACE_SIZE;
-	if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
+	if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev))
 		return PCI_CFG_SPACE_SIZE;
 
 	return PCI_CFG_SPACE_EXP_SIZE;
@@ -2371,8 +2371,8 @@ bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
 	if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
 		return false;
 
-	/* Some broken boards return 0 or ~0 if a slot is empty: */
-	if (*l == 0xffffffff || *l == 0x00000000 ||
+	/* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */
+	if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 ||
 	    *l == 0x0000ffff || *l == 0xffff0000)
 		return false;
 
-- 
2.25.1

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  parent reply	other threads:[~2021-11-18 14:08 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-18 14:03 [PATCH v4 00/25] Unify PCI error response checking Naveen Naidu
2021-11-18 14:03 ` Naveen Naidu
2021-11-18 14:03 ` Naveen Naidu
2021-11-18 14:03 ` Naveen Naidu
2021-11-18 14:03 ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 01/25] PCI: Add PCI_ERROR_RESPONSE and it's related definitions Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 02/25] PCI: Set error response in config access defines when ops->read() fails Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 03/25] PCI: Use PCI_SET_ERROR_RESPONSE() when device not found Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 04/25] PCI: Remove redundant error fabrication when device read fails Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 05/25] PCI: thunder: " Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 06/25] PCI: iproc: " Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 07/25] PCI: mediatek: " Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 08/25] PCI: exynos: " Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 09/25] PCI: histb: " Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 10/25] PCI: kirin: " Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 11/25] PCI: aardvark: " Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 12/25] PCI: mvebu: " Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 13/25] PCI: altera: " Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 14/25] PCI: rcar: " Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 15/25] PCI: rockchip: " Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` Naveen Naidu [this message]
2021-11-18 14:03   ` [PATCH v4 16/25] PCI/ERR: Use PCI_POSSIBLE_ERROR() to check read from hardware Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 17/25] PCI: vmd: " Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 18/25] PCI: pciehp: " Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 19/25] PCI/DPC: " Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 20/25] PCI/PME: " Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 21/25] PCI: cpqphp: " Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 22/25] PCI: Use PCI_ERROR_RESPONSE to specify hardware error Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 23/25] PCI: keystone: " Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 24/25] PCI: hv: Use PCI_ERROR_RESPONSE to specify hardware read error Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03 ` [PATCH v4 25/25] PCI: xgene: Use PCI_ERROR_RESPONSE to specify hardware error Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 14:03   ` Naveen Naidu
2021-11-18 20:44 ` [PATCH v4 00/25] Unify PCI error response checking Bjorn Helgaas
2021-11-18 20:44   ` Bjorn Helgaas
2021-11-18 20:44   ` Bjorn Helgaas
2021-11-18 20:44   ` Bjorn Helgaas
2021-11-18 20:44   ` Bjorn Helgaas

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