From: Josh Poimboeuf <jpoimboe@redhat.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: [patch V5 00/14] MDS basics 0
Date: Wed, 27 Feb 2019 19:04:24 -0600 [thread overview]
Message-ID: <20190228010424.dk273xj7qa7trvqr@treble> (raw)
In-Reply-To: <alpine.DEB.2.21.1902272157370.1644@nanos.tec.linutronix.de>
On Wed, Feb 27, 2019 at 10:04:33PM +0100, speck for Thomas Gleixner wrote:
> On Wed, 27 Feb 2019, speck for Thomas Gleixner wrote:
>
> > Changes since V4:
> >
> > - Fix SSB whitelist. Needs to go upstream independently.
> >
> > - Consolidate whitelists before adding another one.
> >
> > - Use an inline helper for the exit to user mitigation.
> >
> > - Add VMX/VMENTER mitigation when CPU is not affected by L1TF.
> >
> > - Remove 'auto' command line option.
> >
> > - Rework the mitigation documentation so the handling of special
> > exceptions is clear.
> >
> > - Adjust the virt mitigation admin documentation.
> >
> > - Fix typos and address review comments
> >
> > Available from git:
> >
> > cvs.ou.linutronix.de:linux/speck/linux WIP.mds
>
> Pushed out a new tree which contains the fixups for the consolidated table
> and the documentation for VMX.
>
> Delta patch below.
Your last update had a bunch of issues: didn't compile, missing entries,
typos, whitespace.
The below fixed it for me (on top of your bad patch):
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 7b34ac46f4db..0558e9ee1fec 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -955,39 +955,40 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
#define NO_MDS BIT(4)
#define VULNWL(vendor, family, model, whitelist) \
- { X86_VENDOR_##vendor, number, model, X86_FEATURE_ANY, whitelist)
+ { X86_VENDOR_##vendor, family, model, X86_FEATURE_ANY, whitelist }
static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
- VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION },
- VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION },
- VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION },
- VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION },
- VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SALTWELL, NO_SPECULATION },
- VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SALTWELL_TABLET, NO_SPECULATION },
- VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SALTWELL_MID, NO_SPECULATION },
- VULNWL(INTEL, 6, INTEL_FAM6_ATOM_BONELL, NO_SPECULATION },
-
- VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT, NO_SSB | NO_L1TF },
- VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_, NO_SSB | NO_L1TF },
- VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF },
- VULNWL(INTEL, 6, INTEL_FAM6_ATOM_AIRMONT, NO_SSB | NO_L1TF },
- VULNWL(INTEL, 6, INTEL_FAM6_ATOM_AIRMONT_MID, NO_SSB | NO_L1TF },
- VULNWL(INTEL, 6, INTEL_FAM6_CORE_YONAH, NO_SSB | NO_L1TF },
- VULNWL(INTEL, 6, INTEL_FAM6_XEON_PHI_KNL, NO_SSB | NO_L1TF },
- VULNWL(INTEL, 6, INTEL_FAM6_XEON_PHI_KNM, NO_SSB | NO_L1TF },
-
- VULNWL(INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT, NO_MDS | NO_L1TF },
- VULNWL(INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT_X, NO_MDS | NO_L1TF },
- VULNWL(INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF },
-
- VULNWL(AMD, 0x0f, X86_MODEL_ANY, NO_MELTDOWN | NO_SSB | NO_L1TF },
- VULNWL(AMD, 0x10, X86_MODEL_ANY, NO_MELTDOWN | NO_SSB | NO_L1TF },
- VULNWL(AMD, 0x11, X86_MODEL_ANY, NO_MELTDOWN | NO_SSB | NO_L1TF },
- VULNWL(AMD, 0x12, X86_MODEL_ANY, NO_MELTDOWN | NO_SSB | NO_L1TF },
+ VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
+ VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
+ VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
+ VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
+ VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SALTWELL, NO_SPECULATION),
+ VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SALTWELL_TABLET, NO_SPECULATION),
+ VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SALTWELL_MID, NO_SPECULATION),
+ VULNWL(INTEL, 6, INTEL_FAM6_ATOM_BONNELL, NO_SPECULATION),
+ VULNWL(INTEL, 6, INTEL_FAM6_ATOM_BONNELL_MID, NO_SPECULATION),
+
+ VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT, NO_SSB | NO_L1TF),
+ VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_X, NO_SSB | NO_L1TF),
+ VULNWL(INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF),
+ VULNWL(INTEL, 6, INTEL_FAM6_ATOM_AIRMONT, NO_SSB | NO_L1TF),
+ VULNWL(INTEL, 6, INTEL_FAM6_ATOM_AIRMONT_MID, NO_SSB | NO_L1TF),
+ VULNWL(INTEL, 6, INTEL_FAM6_CORE_YONAH, NO_SSB | NO_L1TF),
+ VULNWL(INTEL, 6, INTEL_FAM6_XEON_PHI_KNL, NO_SSB | NO_L1TF),
+ VULNWL(INTEL, 6, INTEL_FAM6_XEON_PHI_KNM, NO_SSB | NO_L1TF),
+
+ VULNWL(INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT, NO_MDS | NO_L1TF),
+ VULNWL(INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT_X, NO_MDS | NO_L1TF),
+ VULNWL(INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF),
+
+ VULNWL(AMD, 0x0f, X86_MODEL_ANY, NO_MELTDOWN | NO_SSB | NO_L1TF),
+ VULNWL(AMD, 0x10, X86_MODEL_ANY, NO_MELTDOWN | NO_SSB | NO_L1TF),
+ VULNWL(AMD, 0x11, X86_MODEL_ANY, NO_MELTDOWN | NO_SSB | NO_L1TF),
+ VULNWL(AMD, 0x12, X86_MODEL_ANY, NO_MELTDOWN | NO_SSB | NO_L1TF),
/* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
- VULNWL(AMD, X86_FAMILY_ANY, X86_MODEL_ANY, NO_MELTDOWN | NO_L1TF },
- VULNWL(HYGON, X86_FAMILY_ANY, X86_MODEL_ANY, NO_MELTDOWN | NO_L1TF },
+ VULNWL(AMD, X86_FAMILY_ANY, X86_MODEL_ANY, NO_MELTDOWN | NO_L1TF),
+ VULNWL(HYGON, X86_FAMILY_ANY, X86_MODEL_ANY, NO_MELTDOWN | NO_L1TF),
{}
};
next prev parent reply other threads:[~2019-02-28 1:04 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-27 15:09 [patch V5 00/14] MDS basics 0 Thomas Gleixner
2019-02-27 15:09 ` [patch V5 01/14] MDS basics 1 Thomas Gleixner
2019-02-28 13:08 ` Thomas Gleixner
2019-02-27 15:09 ` [patch V5 02/14] MDS basics 2 Thomas Gleixner
2019-02-28 13:55 ` [MODERATED] " Josh Poimboeuf
2019-02-28 14:09 ` Thomas Gleixner
2019-02-28 20:23 ` [MODERATED] " Josh Poimboeuf
2019-03-01 16:04 ` Thomas Gleixner
2019-02-27 15:09 ` [patch V5 03/14] MDS basics 3 Thomas Gleixner
2019-02-27 16:34 ` [MODERATED] " Greg KH
2019-02-27 15:09 ` [patch V5 04/14] MDS basics 4 Thomas Gleixner
2019-02-27 15:09 ` [patch V5 05/14] MDS basics 5 Thomas Gleixner
2019-02-27 15:09 ` [patch V5 06/14] MDS basics 6 Thomas Gleixner
2019-02-27 15:09 ` [patch V5 07/14] MDS basics 7 Thomas Gleixner
2019-02-27 17:07 ` [MODERATED] " Greg KH
2019-02-27 15:09 ` [patch V5 08/14] MDS basics 8 Thomas Gleixner
2019-02-28 8:11 ` [MODERATED] " Greg KH
2019-02-27 15:09 ` [patch V5 09/14] MDS basics 9 Thomas Gleixner
2019-03-01 14:04 ` [MODERATED] " Josh Poimboeuf
2019-03-01 16:03 ` Thomas Gleixner
2019-03-01 16:40 ` [MODERATED] " Josh Poimboeuf
2019-03-01 18:39 ` Josh Poimboeuf
2019-03-01 19:15 ` Thomas Gleixner
2019-03-01 22:38 ` [MODERATED] " Andrea Arcangeli
2019-03-01 22:58 ` Thomas Gleixner
2019-03-02 19:22 ` [MODERATED] Re: [SPAM] " Dave Hansen
2019-03-02 20:39 ` Thomas Gleixner
2019-02-27 15:09 ` [patch V5 10/14] MDS basics 10 Thomas Gleixner
2019-02-27 15:09 ` [patch V5 11/14] MDS basics 11 Thomas Gleixner
2019-02-27 15:09 ` [patch V5 12/14] MDS basics 12 Thomas Gleixner
2019-03-01 22:00 ` [MODERATED] " mark gross
2019-02-27 15:09 ` [patch V5 13/14] MDS basics 13 Thomas Gleixner
2019-03-01 22:04 ` [MODERATED] " mark gross
2019-02-27 15:09 ` [patch V5 14/14] MDS basics 14 Thomas Gleixner
2019-02-27 17:49 ` Thomas Gleixner
2019-02-27 16:26 ` [MODERATED] Re: [patch V5 00/14] MDS basics 0 Linus Torvalds
2019-02-27 17:51 ` Thomas Gleixner
2019-02-27 18:13 ` Thomas Gleixner
2019-02-27 19:50 ` [MODERATED] " Linus Torvalds
2019-02-27 20:05 ` Thomas Gleixner
2019-02-27 21:04 ` Thomas Gleixner
2019-02-28 1:04 ` Josh Poimboeuf [this message]
2019-02-27 23:06 ` [MODERATED] " mark gross
2019-02-28 6:58 ` Thomas Gleixner
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