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* [Intel-gfx] [PATCH] drm/i915/gt: Ensure 'ENABLE_BOOT_FETCH' is enabled before ppGTT
@ 2020-02-13 15:47 Chris Wilson
  2020-02-13 17:38 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork
  2020-02-13 17:57 ` [Intel-gfx] [PATCH] " Ville Syrjälä
  0 siblings, 2 replies; 4+ messages in thread
From: Chris Wilson @ 2020-02-13 15:47 UTC (permalink / raw)
  To: intel-gfx

Cryptic notes in bspec say that "The MBC Driver Boot Enable bit in MBCTL
register must be set before this register is written to upon boot up
(including S3 exit)."

We tried adding it to our list of verified workarounds, but our
self checks spot that the bit does not stick. It's only meant to be
cleared after a FLR. As it fails our verification, just blindly apply
the bit prior to loading the ppGTT.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ring_submission.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index f70b903a98bc..e41a329d435a 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -642,6 +642,9 @@ static void set_pp_dir(struct intel_engine_cs *engine)
 	if (vm) {
 		struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 
+		intel_uncore_rmw(engine->uncore, GEN6_MBCTL,
+				 0, GEN6_MBCTL_ENABLE_BOOT_FETCH)
+
 		ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
 		ENGINE_WRITE(engine, RING_PP_DIR_BASE,
 			     px_base(ppgtt->pd)->ggtt_offset << 10);
-- 
2.25.0

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^ permalink raw reply	[flat|nested] 4+ messages in thread

* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/gt: Ensure 'ENABLE_BOOT_FETCH' is enabled before ppGTT
  2020-02-13 15:47 [Intel-gfx] [PATCH] drm/i915/gt: Ensure 'ENABLE_BOOT_FETCH' is enabled before ppGTT Chris Wilson
@ 2020-02-13 17:38 ` " Patchwork
  2020-02-13 17:57 ` [Intel-gfx] [PATCH] " Ville Syrjälä
  1 sibling, 0 replies; 4+ messages in thread
From: Patchwork @ 2020-02-13 17:38 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/gt: Ensure 'ENABLE_BOOT_FETCH' is enabled before ppGTT
URL   : https://patchwork.freedesktop.org/series/73416/
State : failure

== Summary ==

CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  DESCEND  objtool
  CHK     include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/gt/intel_ring_submission.o
In file included from ./drivers/gpu/drm/i915/i915_drv.h:82:0,
                 from ./drivers/gpu/drm/i915/gem/i915_gem_context.h:14,
                 from drivers/gpu/drm/i915/gt/intel_ring_submission.c:34:
drivers/gpu/drm/i915/gt/intel_ring_submission.c: In function ‘set_pp_dir’:
./drivers/gpu/drm/i915/gt/intel_engine.h:53:2: error: expected ‘;’ before ‘intel_uncore_write’
  intel_uncore_##op__((engine__)->uncore, __VA_ARGS__)
  ^
./drivers/gpu/drm/i915/gt/intel_engine.h:73:2: note: in expansion of macro ‘__ENGINE_REG_OP’
  __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base), (val__))
  ^~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/gt/intel_engine.h:76:27: note: in expansion of macro ‘__ENGINE_WRITE_OP’
 #define ENGINE_WRITE(...) __ENGINE_WRITE_OP(write, __VA_ARGS__)
                           ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gt/intel_ring_submission.c:648:3: note: in expansion of macro ‘ENGINE_WRITE’
   ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
   ^~~~~~~~~~~~
scripts/Makefile.build:267: recipe for target 'drivers/gpu/drm/i915/gt/intel_ring_submission.o' failed
make[4]: *** [drivers/gpu/drm/i915/gt/intel_ring_submission.o] Error 1
scripts/Makefile.build:505: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:505: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:505: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1681: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/gt: Ensure 'ENABLE_BOOT_FETCH' is enabled before ppGTT
  2020-02-13 15:47 [Intel-gfx] [PATCH] drm/i915/gt: Ensure 'ENABLE_BOOT_FETCH' is enabled before ppGTT Chris Wilson
  2020-02-13 17:38 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork
@ 2020-02-13 17:57 ` " Ville Syrjälä
  2020-02-13 18:07   ` Chris Wilson
  1 sibling, 1 reply; 4+ messages in thread
From: Ville Syrjälä @ 2020-02-13 17:57 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

On Thu, Feb 13, 2020 at 03:47:59PM +0000, Chris Wilson wrote:
> Cryptic notes in bspec say that "The MBC Driver Boot Enable bit in MBCTL
> register must be set before this register is written to upon boot up
> (including S3 exit)."
> 
> We tried adding it to our list of verified workarounds, but our
> self checks spot that the bit does not stick. It's only meant to be
> cleared after a FLR. As it fails our verification, just blindly apply
> the bit prior to loading the ppGTT.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_ring_submission.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index f70b903a98bc..e41a329d435a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -642,6 +642,9 @@ static void set_pp_dir(struct intel_engine_cs *engine)
>  	if (vm) {
>  		struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
>  
> +		intel_uncore_rmw(engine->uncore, GEN6_MBCTL,
> +				 0, GEN6_MBCTL_ENABLE_BOOT_FETCH)

Wasn't setting this bit implicated in some regressions long ago?

> +
>  		ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
>  		ENGINE_WRITE(engine, RING_PP_DIR_BASE,
>  			     px_base(ppgtt->pd)->ggtt_offset << 10);
> -- 
> 2.25.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/gt: Ensure 'ENABLE_BOOT_FETCH' is enabled before ppGTT
  2020-02-13 17:57 ` [Intel-gfx] [PATCH] " Ville Syrjälä
@ 2020-02-13 18:07   ` Chris Wilson
  0 siblings, 0 replies; 4+ messages in thread
From: Chris Wilson @ 2020-02-13 18:07 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

Quoting Ville Syrjälä (2020-02-13 17:57:56)
> On Thu, Feb 13, 2020 at 03:47:59PM +0000, Chris Wilson wrote:
> > Cryptic notes in bspec say that "The MBC Driver Boot Enable bit in MBCTL
> > register must be set before this register is written to upon boot up
> > (including S3 exit)."
> > 
> > We tried adding it to our list of verified workarounds, but our
> > self checks spot that the bit does not stick. It's only meant to be
> > cleared after a FLR. As it fails our verification, just blindly apply
> > the bit prior to loading the ppGTT.
> > 
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_ring_submission.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > index f70b903a98bc..e41a329d435a 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > @@ -642,6 +642,9 @@ static void set_pp_dir(struct intel_engine_cs *engine)
> >       if (vm) {
> >               struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
> >  
> > +             intel_uncore_rmw(engine->uncore, GEN6_MBCTL,
> > +                              0, GEN6_MBCTL_ENABLE_BOOT_FETCH)
> 
> Wasn't setting this bit implicated in some regressions long ago?

commit 3414caf63421762e57b26aa999e5187b42ee1606
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date:   Wed Aug 21 08:08:55 2013 -0700

    drm/i915: drop WaMbcDriverBootEnable workaround

    Turns out the BIOS will do this for us as needed, and if we try to do it
    again we risk hangs or other bad behavior.

    Note that this seems to break libva on ChromeOS after resumes (but
    strangely _not_ after booting up).

    This essentially reverts

    commit b4ae3f22d238617ca11610b29fde16cf8c0bc6e0
    Author: Jesse Barnes <jbarnes@virtuousgeek.org>
    Date:   Thu Jun 14 11:04:48 2012 -0700

        drm/i915: load boot context at driver init time

    and

    commit b3bf076697a68a8577f4a5f7407de0bb2b3b56ac
    Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
    Date:   Tue Nov 20 13:27:44 2012 -0200

        drm/i915: implement WaMbcDriverBootEnable on Haswell

    Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
    Reported-and-Tested-by: Stéphane Marchesin <marcheu@chromium.org>
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^ permalink raw reply	[flat|nested] 4+ messages in thread

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2020-02-13 15:47 [Intel-gfx] [PATCH] drm/i915/gt: Ensure 'ENABLE_BOOT_FETCH' is enabled before ppGTT Chris Wilson
2020-02-13 17:38 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork
2020-02-13 17:57 ` [Intel-gfx] [PATCH] " Ville Syrjälä
2020-02-13 18:07   ` Chris Wilson

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