From: Patchwork <patchwork@emeril.freedesktop.org>
To: "Lucas De Marchi" <lucas.demarchi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1
Date: Fri, 24 Jul 2020 21:45:49 -0000 [thread overview]
Message-ID: <159562714991.15334.3889107571859098310@emeril.freedesktop.org> (raw)
In-Reply-To: <20200724213918.27424-1-lucas.demarchi@intel.com>
== Series Details ==
Series: Introduce DG1
URL : https://patchwork.freedesktop.org/series/79863/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8f74e276b41a drm/i915/dg1: Initialize RAWCLK properly
c2699a393ba3 drm/i915/dg1: Define MOCS table for DG1
da0e39cc42f3 drm/i915/dg1: Add DG1 power wells
bff25189ad22 drm/i915/dg1: Increase mmio size to 4MB
6763f3077f0d drm/i915/dg1: Wait for pcode/uncore handshake at startup
e18904ffdb23 drm/i915/dg1: Add DPLL macros for DG1
4b251c381b35 drm/i915/dg1: Add and setup DPLLs for DG1
fe51b026ee82 drm/i915/dg1: Enable DPLL for DG1
cbbc5366d85e drm/i915/dg1: add hpd interrupt handling
c0b3de1be1a6 drm/i915/dg1: invert HPD pins
d24c8e3696f3 drm/i915/dg1: gmbus pin mapping
85111a9da7b5 drm/i915/dg1: Enable first 2 ports for DG1
73800c5e78e4 drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
4933a57b9c0a drm/i915/dg1: Update comp master/slave relationships for PHYs
bcab535050e1 drm/i915/dg1: Update voltage swing tables for DP
72f10411364c drm/i915/dg1: provide port/phy mapping for vbt
4c68f89318f4 drm/i915/dg1: map/unmap pll clocks
-:244: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy' - possible side-effects?
#244: FILE: drivers/gpu/drm/i915/i915_reg.h:10340:
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy) \
+ ((((val) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)) >> ((phy % 2) * 2)) + (2 * (phy / 2)))
total: 0 errors, 0 warnings, 1 checks, 204 lines checked
472d90a048b8 drm/i915/dg1: enable PORT C/D aka D/E
2d1e6fca5292 drm/i915/dg1: Load DMC
f463503a1825 drm/i915/dg1: Add initial DG1 workarounds
5e4111a18707 drm/i915/dg1: DG1 does not support DC6
a9a8a1141462 drm/i915/dg1: Change DMC_DEBUG{1, 2} registers
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next prev parent reply other threads:[~2020-07-24 21:45 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-24 21:38 [Intel-gfx] [PATCH v5 00/22] Introduce DG1 Lucas De Marchi
2020-07-24 21:38 ` [Intel-gfx] [PATCH v5 01/22] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
2020-07-28 16:35 ` Souza, Jose
2020-07-24 21:38 ` [Intel-gfx] [PATCH v5 02/22] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
2020-07-28 19:38 ` Matt Roper
2020-07-24 21:38 ` [Intel-gfx] [PATCH v5 03/22] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-07-28 20:51 ` Matt Roper
2020-08-13 7:59 ` Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 04/22] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
2020-07-28 21:48 ` Matt Roper
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 05/22] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
2020-08-03 23:24 ` Souza, Jose
2020-08-24 19:24 ` Lucas De Marchi
2020-08-24 19:29 ` Souza, Jose
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 06/22] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-07-28 21:54 ` Matt Roper
2020-08-13 8:07 ` Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 07/22] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-07-28 22:14 ` Matt Roper
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 08/22] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 09/22] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 10/22] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 11/22] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 12/22] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 13/22] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 14/22] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 15/22] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
2020-08-03 23:48 ` Souza, Jose
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 16/22] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 17/22] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 18/22] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 19/22] drm/i915/dg1: Load DMC Lucas De Marchi
2020-08-03 23:27 ` Souza, Jose
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 20/22] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 21/22] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
2020-08-03 23:33 ` Souza, Jose
2020-08-24 21:26 ` Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers Lucas De Marchi
2020-08-03 23:31 ` Souza, Jose
2020-08-07 13:14 ` Anshuman Gupta
2020-08-07 17:26 ` Souza, Jose
2020-08-10 5:48 ` Anshuman Gupta
2020-08-13 7:56 ` Lucas De Marchi
2020-07-24 21:45 ` Patchwork [this message]
2020-07-24 21:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce DG1 Patchwork
2020-07-24 22:08 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2020-10-12 21:29 [Intel-gfx] [PATCH v7 00/15] " Lucas De Marchi
2020-10-12 21:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-09-30 6:42 [Intel-gfx] [PATCH v6 00/24] " Lucas De Marchi
2020-09-30 7:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-05-21 0:37 [Intel-gfx] [PATCH 00/37] " Lucas De Marchi
2020-05-21 1:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
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