[Intel-gfx] [PATCH v5 10/22] drm/i915/dg1: invert HPD pins

[Lucas De Marchi <lucas.demarchi@intel.com>]

From: Clinton A Taylor <clinton.a.taylor@intel.com>

HPD pins are inverted for DG1 platform.

Bspec: 49956
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 9 +++++++++
 drivers/gpu/drm/i915/i915_reg.h | 4 ++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e8bdc52c94bb..93367221d208 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3181,6 +3181,15 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
 
 static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
+	u32 val;
+
+	val = I915_READ(SOUTH_CHICKEN1);
+	val |= (INVERT_DDIA_HPD |
+		INVERT_DDIB_HPD |
+		INVERT_DDIC_HPD |
+		INVERT_DDID_HPD);
+	I915_WRITE(SOUTH_CHICKEN1, val);
+
 	icp_hpd_irq_setup(dev_priv,
 			  SDE_DDI_MASK_DG1, 0,
 			  DG1_DDI_HPD_ENABLE_MASK, 0);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9d0756efe915..bbaa64336ada 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8716,6 +8716,10 @@ enum {
 #define SOUTH_CHICKEN1		_MMIO(0xc2000)
 #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
 #define  FDIA_PHASE_SYNC_SHIFT_EN	18
+#define  INVERT_DDID_HPD			(1 << 18)
+#define  INVERT_DDIC_HPD			(1 << 17)
+#define  INVERT_DDIB_HPD			(1 << 16)
+#define  INVERT_DDIA_HPD			(1 << 15)
 #define  FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
 #define  FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
 #define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
-- 
2.26.2

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