From: "Souza, Jose" <jose.souza@intel.com>
To: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"De Marchi, Lucas" <lucas.demarchi@intel.com>
Subject: Re: [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers
Date: Mon, 3 Aug 2020 23:31:37 +0000 [thread overview]
Message-ID: <b74c416a220331321552464c33bb06080dd99baa.camel@intel.com> (raw)
In-Reply-To: <20200724213918.27424-23-lucas.demarchi@intel.com>
On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> From: Anshuman Gupta <
> anshuman.gupta@intel.com
> >
>
> DGFX devices have different DMC_DEBUG* counter MMIO address
> offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
> counter and handle i915_dmc_info accordingly.
>
> Cc: Uma Shankar <
> uma.shankar@intel.com
> >
> Signed-off-by: Anshuman Gupta <
> anshuman.gupta@intel.com
> >
> Signed-off-by: Lucas De Marchi <
> lucas.demarchi@intel.com
> >
> ---
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++++++--
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 3644752cc5ec..e3536edcb394 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> CSR_VERSION_MINOR(csr->version));
>
> if (INTEL_GEN(dev_priv) >= 12) {
> - dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> - dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> + if (IS_DG1(dev_priv)) {
> + dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> + } else {
> + dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> + dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> + }
> +
> /*
> * NOTE: DMC_DEBUG3 is a general purpose reg.
> * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4e95312eba24..78bdce67da08 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7549,6 +7549,8 @@ enum {
> #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
> #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
> #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
> +#define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
> +#define DG1_DMC_DEBUG_DC6_COUNT _MMIO(0x134158)
DG1_DMC_DEBUG_DC6_COUNT is not used as DG1 do not support DC6.
Removing it:
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> #define DMC_DEBUG3 _MMIO(0x101090)
>
>
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next prev parent reply other threads:[~2020-08-03 23:31 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-24 21:38 [Intel-gfx] [PATCH v5 00/22] Introduce DG1 Lucas De Marchi
2020-07-24 21:38 ` [Intel-gfx] [PATCH v5 01/22] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
2020-07-28 16:35 ` Souza, Jose
2020-07-24 21:38 ` [Intel-gfx] [PATCH v5 02/22] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
2020-07-28 19:38 ` Matt Roper
2020-07-24 21:38 ` [Intel-gfx] [PATCH v5 03/22] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-07-28 20:51 ` Matt Roper
2020-08-13 7:59 ` Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 04/22] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
2020-07-28 21:48 ` Matt Roper
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 05/22] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
2020-08-03 23:24 ` Souza, Jose
2020-08-24 19:24 ` Lucas De Marchi
2020-08-24 19:29 ` Souza, Jose
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 06/22] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-07-28 21:54 ` Matt Roper
2020-08-13 8:07 ` Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 07/22] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-07-28 22:14 ` Matt Roper
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 08/22] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 09/22] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 10/22] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 11/22] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 12/22] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 13/22] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 14/22] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 15/22] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
2020-08-03 23:48 ` Souza, Jose
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 16/22] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 17/22] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 18/22] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 19/22] drm/i915/dg1: Load DMC Lucas De Marchi
2020-08-03 23:27 ` Souza, Jose
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 20/22] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 21/22] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
2020-08-03 23:33 ` Souza, Jose
2020-08-24 21:26 ` Lucas De Marchi
2020-07-24 21:39 ` [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers Lucas De Marchi
2020-08-03 23:31 ` Souza, Jose [this message]
2020-08-07 13:14 ` Anshuman Gupta
2020-08-07 17:26 ` Souza, Jose
2020-08-10 5:48 ` Anshuman Gupta
2020-08-13 7:56 ` Lucas De Marchi
2020-07-24 21:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 Patchwork
2020-07-24 21:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-24 22:08 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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