* [Intel-gfx] [PATCH 0/1] drm/i915/gt: Introduce timeslicing for userspace
@ 2021-05-25 13:55 Tejas Upadhyay
2021-05-25 13:55 ` [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING Tejas Upadhyay
2021-05-25 15:48 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/gt: Introduce timeslicing for userspace Patchwork
0 siblings, 2 replies; 14+ messages in thread
From: Tejas Upadhyay @ 2021-05-25 13:55 UTC (permalink / raw)
To: intel-gfx, mahesh.meena
Test-with: 20210524124806.241439-1-tejaskumarx.surendrakumar.upadhyay@intel.com
Tejas Upadhyay (1):
Let userspace know if they can trust timeslicing by including it as
part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING
drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 +
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 2 insertions(+)
--
2.31.1
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^ permalink raw reply [flat|nested] 14+ messages in thread* [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING 2021-05-25 13:55 [Intel-gfx] [PATCH 0/1] drm/i915/gt: Introduce timeslicing for userspace Tejas Upadhyay @ 2021-05-25 13:55 ` Tejas Upadhyay 2021-05-25 14:19 ` Tvrtko Ursulin 2021-05-25 15:48 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/gt: Introduce timeslicing for userspace Patchwork 1 sibling, 1 reply; 14+ messages in thread From: Tejas Upadhyay @ 2021-05-25 13:55 UTC (permalink / raw) To: intel-gfx, mahesh.meena v2: Only declare timeslicing if we can safely preempt userspace. Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 + include/uapi/drm/i915_drm.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 3cca7ea2d6ea..12d165566ed2 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -98,6 +98,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915) MAP(HAS_PREEMPTION, PREEMPTION), MAP(HAS_SEMAPHORES, SEMAPHORES), MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS), + MAP(TIMESLICE_BIT, TIMESLICING), #undef MAP }; struct intel_engine_cs *engine; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index c2c7759b7d2e..af2212d6113c 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -572,6 +572,7 @@ typedef struct drm_i915_irq_wait { #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5) #define I915_PARAM_HUC_STATUS 42 -- 2.31.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING 2021-05-25 13:55 ` [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING Tejas Upadhyay @ 2021-05-25 14:19 ` Tvrtko Ursulin 2021-05-25 14:47 ` Daniel Vetter 0 siblings, 1 reply; 14+ messages in thread From: Tvrtko Ursulin @ 2021-05-25 14:19 UTC (permalink / raw) To: Tejas Upadhyay, intel-gfx, mahesh.meena, DRI Development + dri-devel as per process On 25/05/2021 14:55, Tejas Upadhyay wrote: > v2: Only declare timeslicing if we can safely preempt userspace. Commit message got butchered up somehow so you'll need to fix that at some point. Regards, Tvrtko > Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing") > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 + > include/uapi/drm/i915_drm.h | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c > index 3cca7ea2d6ea..12d165566ed2 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c > @@ -98,6 +98,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915) > MAP(HAS_PREEMPTION, PREEMPTION), > MAP(HAS_SEMAPHORES, SEMAPHORES), > MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS), > + MAP(TIMESLICE_BIT, TIMESLICING), > #undef MAP > }; > struct intel_engine_cs *engine; > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > index c2c7759b7d2e..af2212d6113c 100644 > --- a/include/uapi/drm/i915_drm.h > +++ b/include/uapi/drm/i915_drm.h > @@ -572,6 +572,7 @@ typedef struct drm_i915_irq_wait { > #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) > #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) > #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) > +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5) > > #define I915_PARAM_HUC_STATUS 42 > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING 2021-05-25 14:19 ` Tvrtko Ursulin @ 2021-05-25 14:47 ` Daniel Vetter 2021-05-26 10:20 ` Tvrtko Ursulin 0 siblings, 1 reply; 14+ messages in thread From: Daniel Vetter @ 2021-05-25 14:47 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx, DRI Development, mahesh.meena On Tue, May 25, 2021 at 03:19:47PM +0100, Tvrtko Ursulin wrote: > > + dri-devel as per process > > On 25/05/2021 14:55, Tejas Upadhyay wrote: > > v2: Only declare timeslicing if we can safely preempt userspace. > > Commit message got butchered up somehow so you'll need to fix that at some > point. > > Regards, > > Tvrtko > > > Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing") > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 + > > include/uapi/drm/i915_drm.h | 1 + > > 2 files changed, 2 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c > > index 3cca7ea2d6ea..12d165566ed2 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c > > @@ -98,6 +98,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915) > > MAP(HAS_PREEMPTION, PREEMPTION), > > MAP(HAS_SEMAPHORES, SEMAPHORES), > > MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS), > > + MAP(TIMESLICE_BIT, TIMESLICING), > > #undef MAP > > }; > > struct intel_engine_cs *engine; > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > > index c2c7759b7d2e..af2212d6113c 100644 > > --- a/include/uapi/drm/i915_drm.h > > +++ b/include/uapi/drm/i915_drm.h > > @@ -572,6 +572,7 @@ typedef struct drm_i915_irq_wait { > > #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) > > #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) > > #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) > > +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5) Since this is uapi I think we should at least have some nice kerneldoc that explains what exactly this is, what for (link to userspace) and all that. Ideally also minimally filing in the gaps in our uapi docs for stuff this references. -Daniel > > #define I915_PARAM_HUC_STATUS 42 > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING 2021-05-25 14:47 ` Daniel Vetter @ 2021-05-26 10:20 ` Tvrtko Ursulin 2021-05-27 10:13 ` Daniel Vetter 0 siblings, 1 reply; 14+ messages in thread From: Tvrtko Ursulin @ 2021-05-26 10:20 UTC (permalink / raw) To: Daniel Vetter; +Cc: intel-gfx, DRI Development, mahesh.meena On 25/05/2021 15:47, Daniel Vetter wrote: > On Tue, May 25, 2021 at 03:19:47PM +0100, Tvrtko Ursulin wrote: >> >> + dri-devel as per process >> >> On 25/05/2021 14:55, Tejas Upadhyay wrote: >>> v2: Only declare timeslicing if we can safely preempt userspace. >> >> Commit message got butchered up somehow so you'll need to fix that at some >> point. >> >> Regards, >> >> Tvrtko >> >>> Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing") >>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> >>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>> --- >>> drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 + >>> include/uapi/drm/i915_drm.h | 1 + >>> 2 files changed, 2 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c >>> index 3cca7ea2d6ea..12d165566ed2 100644 >>> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c >>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c >>> @@ -98,6 +98,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915) >>> MAP(HAS_PREEMPTION, PREEMPTION), >>> MAP(HAS_SEMAPHORES, SEMAPHORES), >>> MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS), >>> + MAP(TIMESLICE_BIT, TIMESLICING), >>> #undef MAP >>> }; >>> struct intel_engine_cs *engine; >>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h >>> index c2c7759b7d2e..af2212d6113c 100644 >>> --- a/include/uapi/drm/i915_drm.h >>> +++ b/include/uapi/drm/i915_drm.h >>> @@ -572,6 +572,7 @@ typedef struct drm_i915_irq_wait { >>> #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) >>> #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) >>> #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) >>> +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5) > > Since this is uapi I think we should at least have some nice kerneldoc > that explains what exactly this is, what for (link to userspace) and all > that. Ideally also minimally filing in the gaps in our uapi docs for stuff > this references. IIUC there is no userspace apart from IGT needing it not to fail scheduling tests on ADL. Current tests use "has preemption + has semaphores" as a proxy to answer the "does the kernel support timeslicing" question. This stops working with the Guc backend because GuC decided not to support semaphores (for reasons yet unknown, see other thread), so explicit "has timeslicing" flag is needed in order for tests to know that GuC is supposed to support timeslicing, even if it doesn't use semaphores for inter-ring synchronisation. Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING 2021-05-26 10:20 ` Tvrtko Ursulin @ 2021-05-27 10:13 ` Daniel Vetter 2021-05-27 10:22 ` Tvrtko Ursulin 0 siblings, 1 reply; 14+ messages in thread From: Daniel Vetter @ 2021-05-27 10:13 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx, DRI Development, mahesh.meena On Wed, May 26, 2021 at 11:20:13AM +0100, Tvrtko Ursulin wrote: > > On 25/05/2021 15:47, Daniel Vetter wrote: > > On Tue, May 25, 2021 at 03:19:47PM +0100, Tvrtko Ursulin wrote: > > > > > > + dri-devel as per process > > > > > > On 25/05/2021 14:55, Tejas Upadhyay wrote: > > > > v2: Only declare timeslicing if we can safely preempt userspace. > > > > > > Commit message got butchered up somehow so you'll need to fix that at some > > > point. > > > > > > Regards, > > > > > > Tvrtko > > > > > > > Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing") > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > > > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 + > > > > include/uapi/drm/i915_drm.h | 1 + > > > > 2 files changed, 2 insertions(+) > > > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c > > > > index 3cca7ea2d6ea..12d165566ed2 100644 > > > > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c > > > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c > > > > @@ -98,6 +98,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915) > > > > MAP(HAS_PREEMPTION, PREEMPTION), > > > > MAP(HAS_SEMAPHORES, SEMAPHORES), > > > > MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS), > > > > + MAP(TIMESLICE_BIT, TIMESLICING), > > > > #undef MAP > > > > }; > > > > struct intel_engine_cs *engine; > > > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > > > > index c2c7759b7d2e..af2212d6113c 100644 > > > > --- a/include/uapi/drm/i915_drm.h > > > > +++ b/include/uapi/drm/i915_drm.h > > > > @@ -572,6 +572,7 @@ typedef struct drm_i915_irq_wait { > > > > #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) > > > > #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) > > > > #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) > > > > +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5) > > > > Since this is uapi I think we should at least have some nice kerneldoc > > that explains what exactly this is, what for (link to userspace) and all > > that. Ideally also minimally filing in the gaps in our uapi docs for stuff > > this references. > > IIUC there is no userspace apart from IGT needing it not to fail scheduling > tests on ADL. > > Current tests use "has preemption + has semaphores" as a proxy to answer the > "does the kernel support timeslicing" question. This stops working with the > Guc backend because GuC decided not to support semaphores (for reasons yet > unknown, see other thread), so explicit "has timeslicing" flag is needed in > order for tests to know that GuC is supposed to support timeslicing, even if > it doesn't use semaphores for inter-ring synchronisation. Since this if for igt only: Cant we do just extend the check in igt with an || GEN >= 12? I really hope that our future hw will continue to support timeslicing ... Also if it's not there yet, a shared helper to check for that (like we're adding for relocations and stuff like that right now). -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING 2021-05-27 10:13 ` Daniel Vetter @ 2021-05-27 10:22 ` Tvrtko Ursulin 2021-05-27 10:27 ` Daniel Vetter 2021-06-04 12:53 ` Tvrtko Ursulin 0 siblings, 2 replies; 14+ messages in thread From: Tvrtko Ursulin @ 2021-05-27 10:22 UTC (permalink / raw) To: Daniel Vetter; +Cc: intel-gfx, DRI Development, mahesh.meena On 27/05/2021 11:13, Daniel Vetter wrote: > On Wed, May 26, 2021 at 11:20:13AM +0100, Tvrtko Ursulin wrote: >> >> On 25/05/2021 15:47, Daniel Vetter wrote: >>> On Tue, May 25, 2021 at 03:19:47PM +0100, Tvrtko Ursulin wrote: >>>> >>>> + dri-devel as per process >>>> >>>> On 25/05/2021 14:55, Tejas Upadhyay wrote: >>>>> v2: Only declare timeslicing if we can safely preempt userspace. >>>> >>>> Commit message got butchered up somehow so you'll need to fix that at some >>>> point. >>>> >>>> Regards, >>>> >>>> Tvrtko >>>> >>>>> Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing") >>>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> >>>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>>>> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>>>> --- >>>>> drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 + >>>>> include/uapi/drm/i915_drm.h | 1 + >>>>> 2 files changed, 2 insertions(+) >>>>> >>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c >>>>> index 3cca7ea2d6ea..12d165566ed2 100644 >>>>> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c >>>>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c >>>>> @@ -98,6 +98,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915) >>>>> MAP(HAS_PREEMPTION, PREEMPTION), >>>>> MAP(HAS_SEMAPHORES, SEMAPHORES), >>>>> MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS), >>>>> + MAP(TIMESLICE_BIT, TIMESLICING), >>>>> #undef MAP >>>>> }; >>>>> struct intel_engine_cs *engine; >>>>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h >>>>> index c2c7759b7d2e..af2212d6113c 100644 >>>>> --- a/include/uapi/drm/i915_drm.h >>>>> +++ b/include/uapi/drm/i915_drm.h >>>>> @@ -572,6 +572,7 @@ typedef struct drm_i915_irq_wait { >>>>> #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) >>>>> #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) >>>>> #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) >>>>> +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5) >>> >>> Since this is uapi I think we should at least have some nice kerneldoc >>> that explains what exactly this is, what for (link to userspace) and all >>> that. Ideally also minimally filing in the gaps in our uapi docs for stuff >>> this references. >> >> IIUC there is no userspace apart from IGT needing it not to fail scheduling >> tests on ADL. >> >> Current tests use "has preemption + has semaphores" as a proxy to answer the >> "does the kernel support timeslicing" question. This stops working with the >> Guc backend because GuC decided not to support semaphores (for reasons yet >> unknown, see other thread), so explicit "has timeslicing" flag is needed in >> order for tests to know that GuC is supposed to support timeslicing, even if >> it doesn't use semaphores for inter-ring synchronisation. > > Since this if for igt only: Cant we do just extend the check in igt with > an || GEN >= 12? I really hope that our future hw will continue to support > timeslicing ... Not the gen 12 check, but possible I think. Explicit feature test would be better, but if definitely not allowed then along the lines of: has_timeslicing = (has_preemption && has_semaphores) || uses_guc_submission; Regards, Tvrtko > Also if it's not there yet, a shared helper to check for that (like we're > adding for relocations and stuff like that right now). > -Daniel > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING 2021-05-27 10:22 ` Tvrtko Ursulin @ 2021-05-27 10:27 ` Daniel Vetter 2021-05-27 12:13 ` Tvrtko Ursulin 2021-06-01 10:09 ` Tvrtko Ursulin 2021-06-04 12:53 ` Tvrtko Ursulin 1 sibling, 2 replies; 14+ messages in thread From: Daniel Vetter @ 2021-05-27 10:27 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx, DRI Development, mahesh.meena On Thu, May 27, 2021 at 11:22:16AM +0100, Tvrtko Ursulin wrote: > > On 27/05/2021 11:13, Daniel Vetter wrote: > > On Wed, May 26, 2021 at 11:20:13AM +0100, Tvrtko Ursulin wrote: > > > > > > On 25/05/2021 15:47, Daniel Vetter wrote: > > > > On Tue, May 25, 2021 at 03:19:47PM +0100, Tvrtko Ursulin wrote: > > > > > > > > > > + dri-devel as per process > > > > > > > > > > On 25/05/2021 14:55, Tejas Upadhyay wrote: > > > > > > v2: Only declare timeslicing if we can safely preempt userspace. > > > > > > > > > > Commit message got butchered up somehow so you'll need to fix that at some > > > > > point. > > > > > > > > > > Regards, > > > > > > > > > > Tvrtko > > > > > > > > > > > Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing") > > > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > > > > > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > > > > > --- > > > > > > drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 + > > > > > > include/uapi/drm/i915_drm.h | 1 + > > > > > > 2 files changed, 2 insertions(+) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c > > > > > > index 3cca7ea2d6ea..12d165566ed2 100644 > > > > > > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c > > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c > > > > > > @@ -98,6 +98,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915) > > > > > > MAP(HAS_PREEMPTION, PREEMPTION), > > > > > > MAP(HAS_SEMAPHORES, SEMAPHORES), > > > > > > MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS), > > > > > > + MAP(TIMESLICE_BIT, TIMESLICING), > > > > > > #undef MAP > > > > > > }; > > > > > > struct intel_engine_cs *engine; > > > > > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > > > > > > index c2c7759b7d2e..af2212d6113c 100644 > > > > > > --- a/include/uapi/drm/i915_drm.h > > > > > > +++ b/include/uapi/drm/i915_drm.h > > > > > > @@ -572,6 +572,7 @@ typedef struct drm_i915_irq_wait { > > > > > > #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) > > > > > > #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) > > > > > > #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) > > > > > > +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5) > > > > > > > > Since this is uapi I think we should at least have some nice kerneldoc > > > > that explains what exactly this is, what for (link to userspace) and all > > > > that. Ideally also minimally filing in the gaps in our uapi docs for stuff > > > > this references. > > > > > > IIUC there is no userspace apart from IGT needing it not to fail scheduling > > > tests on ADL. > > > > > > Current tests use "has preemption + has semaphores" as a proxy to answer the > > > "does the kernel support timeslicing" question. This stops working with the > > > Guc backend because GuC decided not to support semaphores (for reasons yet > > > unknown, see other thread), so explicit "has timeslicing" flag is needed in > > > order for tests to know that GuC is supposed to support timeslicing, even if > > > it doesn't use semaphores for inter-ring synchronisation. > > > > Since this if for igt only: Cant we do just extend the check in igt with > > an || GEN >= 12? I really hope that our future hw will continue to support > > timeslicing ... > > Not the gen 12 check, but possible I think. Explicit feature test would be better, but if definitely not allowed then along the lines of: > > has_timeslicing = > (has_preemption && has_semaphores) || uses_guc_submission; That works too. Otoh what exactly is the "uses guc submission" flag and why do we have that? I've seen media use it as a stand-in for "does the kernel want bonded or parallel ctx?". Maybe another thing to check. Another option, if you really think the feature flag is the best approach (because future hw will drop timeslicing for some reason), then debugfs is the place of igt-only api. -Daniel > > Regards, > > Tvrtko > > Also if it's not there yet, a shared helper to check for that (like we're > > adding for relocations and stuff like that right now). > > -Daniel > > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING 2021-05-27 10:27 ` Daniel Vetter @ 2021-05-27 12:13 ` Tvrtko Ursulin 2021-06-01 10:09 ` Tvrtko Ursulin 1 sibling, 0 replies; 14+ messages in thread From: Tvrtko Ursulin @ 2021-05-27 12:13 UTC (permalink / raw) To: Daniel Vetter; +Cc: intel-gfx, DRI Development, mahesh.meena On 27/05/2021 11:27, Daniel Vetter wrote: > On Thu, May 27, 2021 at 11:22:16AM +0100, Tvrtko Ursulin wrote: >> >> On 27/05/2021 11:13, Daniel Vetter wrote: >>> On Wed, May 26, 2021 at 11:20:13AM +0100, Tvrtko Ursulin wrote: >>>> >>>> On 25/05/2021 15:47, Daniel Vetter wrote: >>>>> On Tue, May 25, 2021 at 03:19:47PM +0100, Tvrtko Ursulin wrote: >>>>>> >>>>>> + dri-devel as per process >>>>>> >>>>>> On 25/05/2021 14:55, Tejas Upadhyay wrote: >>>>>>> v2: Only declare timeslicing if we can safely preempt userspace. >>>>>> >>>>>> Commit message got butchered up somehow so you'll need to fix that at some >>>>>> point. >>>>>> >>>>>> Regards, >>>>>> >>>>>> Tvrtko >>>>>> >>>>>>> Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing") >>>>>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> >>>>>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>>>>>> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>>>>>> --- >>>>>>> drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 + >>>>>>> include/uapi/drm/i915_drm.h | 1 + >>>>>>> 2 files changed, 2 insertions(+) >>>>>>> >>>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c >>>>>>> index 3cca7ea2d6ea..12d165566ed2 100644 >>>>>>> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c >>>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c >>>>>>> @@ -98,6 +98,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915) >>>>>>> MAP(HAS_PREEMPTION, PREEMPTION), >>>>>>> MAP(HAS_SEMAPHORES, SEMAPHORES), >>>>>>> MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS), >>>>>>> + MAP(TIMESLICE_BIT, TIMESLICING), >>>>>>> #undef MAP >>>>>>> }; >>>>>>> struct intel_engine_cs *engine; >>>>>>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h >>>>>>> index c2c7759b7d2e..af2212d6113c 100644 >>>>>>> --- a/include/uapi/drm/i915_drm.h >>>>>>> +++ b/include/uapi/drm/i915_drm.h >>>>>>> @@ -572,6 +572,7 @@ typedef struct drm_i915_irq_wait { >>>>>>> #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) >>>>>>> #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) >>>>>>> #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) >>>>>>> +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5) >>>>> >>>>> Since this is uapi I think we should at least have some nice kerneldoc >>>>> that explains what exactly this is, what for (link to userspace) and all >>>>> that. Ideally also minimally filing in the gaps in our uapi docs for stuff >>>>> this references. >>>> >>>> IIUC there is no userspace apart from IGT needing it not to fail scheduling >>>> tests on ADL. >>>> >>>> Current tests use "has preemption + has semaphores" as a proxy to answer the >>>> "does the kernel support timeslicing" question. This stops working with the >>>> Guc backend because GuC decided not to support semaphores (for reasons yet >>>> unknown, see other thread), so explicit "has timeslicing" flag is needed in >>>> order for tests to know that GuC is supposed to support timeslicing, even if >>>> it doesn't use semaphores for inter-ring synchronisation. >>> >>> Since this if for igt only: Cant we do just extend the check in igt with >>> an || GEN >= 12? I really hope that our future hw will continue to support >>> timeslicing ... >> >> Not the gen 12 check, but possible I think. Explicit feature test would be better, but if definitely not allowed then along the lines of: >> >> has_timeslicing = >> (has_preemption && has_semaphores) || uses_guc_submission; > > That works too. Otoh what exactly is the "uses guc submission" flag and > why do we have that? I've seen media use it as a stand-in for "does the > kernel want bonded or parallel ctx?". Maybe another thing to check. IGT derives it from the enable_guc modparam and logs it during test start (some tests). It's called actuall gem_submission_method(_..). It's useful to have as long as there are platforms where submission backend can be picked at runtime. Afterwards not so much I guess. Regards, Tvrtko > Another option, if you really think the feature flag is the best approach > (because future hw will drop timeslicing for some reason), then debugfs is > the place of igt-only api. > -Daniel > >> >> Regards, >> >> Tvrtko >>> Also if it's not there yet, a shared helper to check for that (like we're >>> adding for relocations and stuff like that right now). >>> -Daniel >>> > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING 2021-05-27 10:27 ` Daniel Vetter 2021-05-27 12:13 ` Tvrtko Ursulin @ 2021-06-01 10:09 ` Tvrtko Ursulin 2021-06-01 14:25 ` Daniel Vetter 1 sibling, 1 reply; 14+ messages in thread From: Tvrtko Ursulin @ 2021-06-01 10:09 UTC (permalink / raw) To: Daniel Vetter; +Cc: intel-gfx, DRI Development, mahesh.meena On 27/05/2021 11:27, Daniel Vetter wrote: > On Thu, May 27, 2021 at 11:22:16AM +0100, Tvrtko Ursulin wrote: >> >> On 27/05/2021 11:13, Daniel Vetter wrote: >>> On Wed, May 26, 2021 at 11:20:13AM +0100, Tvrtko Ursulin wrote: >>>> >>>> On 25/05/2021 15:47, Daniel Vetter wrote: >>>>> On Tue, May 25, 2021 at 03:19:47PM +0100, Tvrtko Ursulin wrote: >>>>>> >>>>>> + dri-devel as per process >>>>>> >>>>>> On 25/05/2021 14:55, Tejas Upadhyay wrote: >>>>>>> v2: Only declare timeslicing if we can safely preempt userspace. >>>>>> >>>>>> Commit message got butchered up somehow so you'll need to fix that at some >>>>>> point. >>>>>> >>>>>> Regards, >>>>>> >>>>>> Tvrtko >>>>>> >>>>>>> Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing") >>>>>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> >>>>>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>>>>>> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>>>>>> --- >>>>>>> drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 + >>>>>>> include/uapi/drm/i915_drm.h | 1 + >>>>>>> 2 files changed, 2 insertions(+) >>>>>>> >>>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c >>>>>>> index 3cca7ea2d6ea..12d165566ed2 100644 >>>>>>> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c >>>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c >>>>>>> @@ -98,6 +98,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915) >>>>>>> MAP(HAS_PREEMPTION, PREEMPTION), >>>>>>> MAP(HAS_SEMAPHORES, SEMAPHORES), >>>>>>> MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS), >>>>>>> + MAP(TIMESLICE_BIT, TIMESLICING), >>>>>>> #undef MAP >>>>>>> }; >>>>>>> struct intel_engine_cs *engine; >>>>>>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h >>>>>>> index c2c7759b7d2e..af2212d6113c 100644 >>>>>>> --- a/include/uapi/drm/i915_drm.h >>>>>>> +++ b/include/uapi/drm/i915_drm.h >>>>>>> @@ -572,6 +572,7 @@ typedef struct drm_i915_irq_wait { >>>>>>> #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) >>>>>>> #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) >>>>>>> #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) >>>>>>> +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5) >>>>> >>>>> Since this is uapi I think we should at least have some nice kerneldoc >>>>> that explains what exactly this is, what for (link to userspace) and all >>>>> that. Ideally also minimally filing in the gaps in our uapi docs for stuff >>>>> this references. >>>> >>>> IIUC there is no userspace apart from IGT needing it not to fail scheduling >>>> tests on ADL. >>>> >>>> Current tests use "has preemption + has semaphores" as a proxy to answer the >>>> "does the kernel support timeslicing" question. This stops working with the >>>> Guc backend because GuC decided not to support semaphores (for reasons yet >>>> unknown, see other thread), so explicit "has timeslicing" flag is needed in >>>> order for tests to know that GuC is supposed to support timeslicing, even if >>>> it doesn't use semaphores for inter-ring synchronisation. >>> >>> Since this if for igt only: Cant we do just extend the check in igt with >>> an || GEN >= 12? I really hope that our future hw will continue to support >>> timeslicing ... >> >> Not the gen 12 check, but possible I think. Explicit feature test would be better, but if definitely not allowed then along the lines of: >> >> has_timeslicing = >> (has_preemption && has_semaphores) || uses_guc_submission; > > That works too. Otoh what exactly is the "uses guc submission" flag and > why do we have that? I've seen media use it as a stand-in for "does the > kernel want bonded or parallel ctx?". Maybe another thing to check. > > Another option, if you really think the feature flag is the best approach > (because future hw will drop timeslicing for some reason), then debugfs is > the place of igt-only api. Maybe check and potentially remove all I915_SCHEDULER_CAP_.. flags. It could be another easy pickings with a lot of IGT work type endeavour. Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING 2021-06-01 10:09 ` Tvrtko Ursulin @ 2021-06-01 14:25 ` Daniel Vetter 0 siblings, 0 replies; 14+ messages in thread From: Daniel Vetter @ 2021-06-01 14:25 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx, DRI Development, mahesh.meena On Tue, Jun 01, 2021 at 11:09:47AM +0100, Tvrtko Ursulin wrote: > > On 27/05/2021 11:27, Daniel Vetter wrote: > > On Thu, May 27, 2021 at 11:22:16AM +0100, Tvrtko Ursulin wrote: > > > > > > On 27/05/2021 11:13, Daniel Vetter wrote: > > > > On Wed, May 26, 2021 at 11:20:13AM +0100, Tvrtko Ursulin wrote: > > > > > > > > > > On 25/05/2021 15:47, Daniel Vetter wrote: > > > > > > On Tue, May 25, 2021 at 03:19:47PM +0100, Tvrtko Ursulin wrote: > > > > > > > > > > > > > > + dri-devel as per process > > > > > > > > > > > > > > On 25/05/2021 14:55, Tejas Upadhyay wrote: > > > > > > > > v2: Only declare timeslicing if we can safely preempt userspace. > > > > > > > > > > > > > > Commit message got butchered up somehow so you'll need to fix that at some > > > > > > > point. > > > > > > > > > > > > > > Regards, > > > > > > > > > > > > > > Tvrtko > > > > > > > > > > > > > > > Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing") > > > > > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > > > > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > > > > > > > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > > > > > > > --- > > > > > > > > drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 + > > > > > > > > include/uapi/drm/i915_drm.h | 1 + > > > > > > > > 2 files changed, 2 insertions(+) > > > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c > > > > > > > > index 3cca7ea2d6ea..12d165566ed2 100644 > > > > > > > > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c > > > > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c > > > > > > > > @@ -98,6 +98,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915) > > > > > > > > MAP(HAS_PREEMPTION, PREEMPTION), > > > > > > > > MAP(HAS_SEMAPHORES, SEMAPHORES), > > > > > > > > MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS), > > > > > > > > + MAP(TIMESLICE_BIT, TIMESLICING), > > > > > > > > #undef MAP > > > > > > > > }; > > > > > > > > struct intel_engine_cs *engine; > > > > > > > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > > > > > > > > index c2c7759b7d2e..af2212d6113c 100644 > > > > > > > > --- a/include/uapi/drm/i915_drm.h > > > > > > > > +++ b/include/uapi/drm/i915_drm.h > > > > > > > > @@ -572,6 +572,7 @@ typedef struct drm_i915_irq_wait { > > > > > > > > #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) > > > > > > > > #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) > > > > > > > > #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) > > > > > > > > +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5) > > > > > > > > > > > > Since this is uapi I think we should at least have some nice kerneldoc > > > > > > that explains what exactly this is, what for (link to userspace) and all > > > > > > that. Ideally also minimally filing in the gaps in our uapi docs for stuff > > > > > > this references. > > > > > > > > > > IIUC there is no userspace apart from IGT needing it not to fail scheduling > > > > > tests on ADL. > > > > > > > > > > Current tests use "has preemption + has semaphores" as a proxy to answer the > > > > > "does the kernel support timeslicing" question. This stops working with the > > > > > Guc backend because GuC decided not to support semaphores (for reasons yet > > > > > unknown, see other thread), so explicit "has timeslicing" flag is needed in > > > > > order for tests to know that GuC is supposed to support timeslicing, even if > > > > > it doesn't use semaphores for inter-ring synchronisation. > > > > > > > > Since this if for igt only: Cant we do just extend the check in igt with > > > > an || GEN >= 12? I really hope that our future hw will continue to support > > > > timeslicing ... > > > > > > Not the gen 12 check, but possible I think. Explicit feature test would be better, but if definitely not allowed then along the lines of: > > > > > > has_timeslicing = > > > (has_preemption && has_semaphores) || uses_guc_submission; > > > > That works too. Otoh what exactly is the "uses guc submission" flag and > > why do we have that? I've seen media use it as a stand-in for "does the > > kernel want bonded or parallel ctx?". Maybe another thing to check. > > > > Another option, if you really think the feature flag is the best approach > > (because future hw will drop timeslicing for some reason), then debugfs is > > the place of igt-only api. > > Maybe check and potentially remove all I915_SCHEDULER_CAP_.. flags. It could > be another easy pickings with a lot of IGT work type endeavour. Yeah there's a lot unfortunately. I'll make a note internally that we need to look at this again maybe next year, but for now we're going to only concentrate on stuff that has actual architecture/design impact. In the grand scheme of things exporting a bunch of flags for igt in the uapi is mostly harmless. There's much bigger fish to fry were we allow igt to make changes to objects that should be all immutable. Those need to be worked out first. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING 2021-05-27 10:22 ` Tvrtko Ursulin 2021-05-27 10:27 ` Daniel Vetter @ 2021-06-04 12:53 ` Tvrtko Ursulin 1 sibling, 0 replies; 14+ messages in thread From: Tvrtko Ursulin @ 2021-06-04 12:53 UTC (permalink / raw) To: Daniel Vetter; +Cc: intel-gfx, DRI Development, mahesh.meena On 27/05/2021 11:22, Tvrtko Ursulin wrote: > > On 27/05/2021 11:13, Daniel Vetter wrote: >> On Wed, May 26, 2021 at 11:20:13AM +0100, Tvrtko Ursulin wrote: >>> >>> On 25/05/2021 15:47, Daniel Vetter wrote: >>>> On Tue, May 25, 2021 at 03:19:47PM +0100, Tvrtko Ursulin wrote: >>>>> >>>>> + dri-devel as per process >>>>> >>>>> On 25/05/2021 14:55, Tejas Upadhyay wrote: >>>>>> v2: Only declare timeslicing if we can safely preempt userspace. >>>>> >>>>> Commit message got butchered up somehow so you'll need to fix that >>>>> at some >>>>> point. >>>>> >>>>> Regards, >>>>> >>>>> Tvrtko >>>>> >>>>>> Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing") >>>>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> >>>>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>>>>> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>>>>> --- >>>>>> drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 + >>>>>> include/uapi/drm/i915_drm.h | 1 + >>>>>> 2 files changed, 2 insertions(+) >>>>>> >>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c >>>>>> b/drivers/gpu/drm/i915/gt/intel_engine_user.c >>>>>> index 3cca7ea2d6ea..12d165566ed2 100644 >>>>>> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c >>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c >>>>>> @@ -98,6 +98,7 @@ static void set_scheduler_caps(struct >>>>>> drm_i915_private *i915) >>>>>> MAP(HAS_PREEMPTION, PREEMPTION), >>>>>> MAP(HAS_SEMAPHORES, SEMAPHORES), >>>>>> MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS), >>>>>> + MAP(TIMESLICE_BIT, TIMESLICING), >>>>>> #undef MAP >>>>>> }; >>>>>> struct intel_engine_cs *engine; >>>>>> diff --git a/include/uapi/drm/i915_drm.h >>>>>> b/include/uapi/drm/i915_drm.h >>>>>> index c2c7759b7d2e..af2212d6113c 100644 >>>>>> --- a/include/uapi/drm/i915_drm.h >>>>>> +++ b/include/uapi/drm/i915_drm.h >>>>>> @@ -572,6 +572,7 @@ typedef struct drm_i915_irq_wait { >>>>>> #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) >>>>>> #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) >>>>>> #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) >>>>>> +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5) >>>> >>>> Since this is uapi I think we should at least have some nice kerneldoc >>>> that explains what exactly this is, what for (link to userspace) and >>>> all >>>> that. Ideally also minimally filing in the gaps in our uapi docs for >>>> stuff >>>> this references. >>> >>> IIUC there is no userspace apart from IGT needing it not to fail >>> scheduling >>> tests on ADL. >>> >>> Current tests use "has preemption + has semaphores" as a proxy to >>> answer the >>> "does the kernel support timeslicing" question. This stops working >>> with the >>> Guc backend because GuC decided not to support semaphores (for >>> reasons yet >>> unknown, see other thread), so explicit "has timeslicing" flag is >>> needed in >>> order for tests to know that GuC is supposed to support timeslicing, >>> even if >>> it doesn't use semaphores for inter-ring synchronisation. >> >> Since this if for igt only: Cant we do just extend the check in igt with >> an || GEN >= 12? I really hope that our future hw will continue to >> support >> timeslicing ... > > Not the gen 12 check, but possible I think. Explicit feature test would > be better, but if definitely not allowed then along the lines of: > > has_timeslicing = > (has_preemption && has_semaphores) || uses_guc_submission; One catch is that timeslicing in GuC will be disabled both if at compile time CONFIG_DRM_I915_TIMESLICE_DURATION is set to zero, or if at runtime engine->props.timeslice_duration_ms is equally set to zero. So I think what is needed on top of the above check is to walk all engines in sysfs and check that timeslicing hasn't explicitly been disabled for any one of them. If we are talking about the global flag at least. Per engine tests could do better I guess, but I don't think that complication is worth the effort. Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/gt: Introduce timeslicing for userspace 2021-05-25 13:55 [Intel-gfx] [PATCH 0/1] drm/i915/gt: Introduce timeslicing for userspace Tejas Upadhyay 2021-05-25 13:55 ` [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING Tejas Upadhyay @ 2021-05-25 15:48 ` Patchwork 1 sibling, 0 replies; 14+ messages in thread From: Patchwork @ 2021-05-25 15:48 UTC (permalink / raw) To: Tejas Upadhyay; +Cc: intel-gfx == Series Details == Series: drm/i915/gt: Introduce timeslicing for userspace URL : https://patchwork.freedesktop.org/series/90538/ State : failure == Summary == CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/gt/intel_engine_user.o In file included from ./include/linux/kernel.h:13, from ./include/linux/list.h:9, from drivers/gpu/drm/i915/gt/intel_engine_user.c:6: drivers/gpu/drm/i915/gt/intel_engine_user.c: In function ‘set_scheduler_caps’: drivers/gpu/drm/i915/gt/intel_engine_user.c:97:27: error: ‘I915_ENGINE_TIMESLICE_BIT’ undeclared (first use in this function); did you mean ‘I915_ENGINE_HAS_TIMESLICES’? #define MAP(x, y) { ilog2(I915_ENGINE_##x), ilog2(I915_SCHEDULER_CAP_##y) } ^~~~~~~~~~~~ ./include/linux/log2.h:158:23: note: in definition of macro ‘ilog2’ __builtin_constant_p(n) ? \ ^ drivers/gpu/drm/i915/gt/intel_engine_user.c:101:3: note: in expansion of macro ‘MAP’ MAP(TIMESLICE_BIT, TIMESLICING), ^~~ drivers/gpu/drm/i915/gt/intel_engine_user.c:97:27: note: each undeclared identifier is reported only once for each function it appears in #define MAP(x, y) { ilog2(I915_ENGINE_##x), ilog2(I915_SCHEDULER_CAP_##y) } ^~~~~~~~~~~~ ./include/linux/log2.h:158:23: note: in definition of macro ‘ilog2’ __builtin_constant_p(n) ? \ ^ drivers/gpu/drm/i915/gt/intel_engine_user.c:101:3: note: in expansion of macro ‘MAP’ MAP(TIMESLICE_BIT, TIMESLICING), ^~~ scripts/Makefile.build:272: recipe for target 'drivers/gpu/drm/i915/gt/intel_engine_user.o' failed make[4]: *** [drivers/gpu/drm/i915/gt/intel_engine_user.o] Error 1 scripts/Makefile.build:515: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:515: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:515: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1839: recipe for target 'drivers' failed make: *** [drivers] Error 2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 0/1] drm/i915/gt: Introduce timeslicing for userspace @ 2021-05-25 14:01 Tejas Upadhyay 2021-05-25 15:51 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork 0 siblings, 1 reply; 14+ messages in thread From: Tejas Upadhyay @ 2021-05-25 14:01 UTC (permalink / raw) To: intel-gfx, mahesh.meena Test-with: 20210524124806.241439-1-tejaskumarx.surendrakumar.upadhyay@intel.com Tejas Upadhyay (1): drm/i915/gt: Declare when we enabled timeslicing drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 + include/uapi/drm/i915_drm.h | 1 + 2 files changed, 2 insertions(+) -- 2.31.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/gt: Introduce timeslicing for userspace 2021-05-25 14:01 [Intel-gfx] [PATCH 0/1] " Tejas Upadhyay @ 2021-05-25 15:51 ` Patchwork 0 siblings, 0 replies; 14+ messages in thread From: Patchwork @ 2021-05-25 15:51 UTC (permalink / raw) To: Tejas Upadhyay; +Cc: intel-gfx == Series Details == Series: drm/i915/gt: Introduce timeslicing for userspace URL : https://patchwork.freedesktop.org/series/90539/ State : failure == Summary == CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/gt/intel_engine_user.o In file included from ./include/linux/kernel.h:13, from ./include/linux/list.h:9, from drivers/gpu/drm/i915/gt/intel_engine_user.c:6: drivers/gpu/drm/i915/gt/intel_engine_user.c: In function ‘set_scheduler_caps’: drivers/gpu/drm/i915/gt/intel_engine_user.c:97:27: error: ‘I915_ENGINE_TIMESLICE_BIT’ undeclared (first use in this function); did you mean ‘I915_ENGINE_HAS_TIMESLICES’? #define MAP(x, y) { ilog2(I915_ENGINE_##x), ilog2(I915_SCHEDULER_CAP_##y) } ^~~~~~~~~~~~ ./include/linux/log2.h:158:23: note: in definition of macro ‘ilog2’ __builtin_constant_p(n) ? \ ^ drivers/gpu/drm/i915/gt/intel_engine_user.c:101:3: note: in expansion of macro ‘MAP’ MAP(TIMESLICE_BIT, TIMESLICING), ^~~ drivers/gpu/drm/i915/gt/intel_engine_user.c:97:27: note: each undeclared identifier is reported only once for each function it appears in #define MAP(x, y) { ilog2(I915_ENGINE_##x), ilog2(I915_SCHEDULER_CAP_##y) } ^~~~~~~~~~~~ ./include/linux/log2.h:158:23: note: in definition of macro ‘ilog2’ __builtin_constant_p(n) ? \ ^ drivers/gpu/drm/i915/gt/intel_engine_user.c:101:3: note: in expansion of macro ‘MAP’ MAP(TIMESLICE_BIT, TIMESLICING), ^~~ scripts/Makefile.build:272: recipe for target 'drivers/gpu/drm/i915/gt/intel_engine_user.o' failed make[4]: *** [drivers/gpu/drm/i915/gt/intel_engine_user.o] Error 1 scripts/Makefile.build:515: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:515: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:515: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1839: recipe for target 'drivers' failed make: *** [drivers] Error 2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2021-06-04 12:53 UTC | newest] Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-05-25 13:55 [Intel-gfx] [PATCH 0/1] drm/i915/gt: Introduce timeslicing for userspace Tejas Upadhyay 2021-05-25 13:55 ` [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING Tejas Upadhyay 2021-05-25 14:19 ` Tvrtko Ursulin 2021-05-25 14:47 ` Daniel Vetter 2021-05-26 10:20 ` Tvrtko Ursulin 2021-05-27 10:13 ` Daniel Vetter 2021-05-27 10:22 ` Tvrtko Ursulin 2021-05-27 10:27 ` Daniel Vetter 2021-05-27 12:13 ` Tvrtko Ursulin 2021-06-01 10:09 ` Tvrtko Ursulin 2021-06-01 14:25 ` Daniel Vetter 2021-06-04 12:53 ` Tvrtko Ursulin 2021-05-25 15:48 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/gt: Introduce timeslicing for userspace Patchwork 2021-05-25 14:01 [Intel-gfx] [PATCH 0/1] " Tejas Upadhyay 2021-05-25 15:51 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork
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