[PATCH] drm/i915: Use pci_resource functions for BARs.

* [PATCH] drm/i915: Use pci_resource functions for BARs.
@ 2012-11-19 20:04 Ben Widawsky
  2012-11-19 20:23 ` [PATCH v2] " Ben Widawsky
  0 siblings, 1 reply; 4+ messages in thread
From: Ben Widawsky @ 2012-11-19 20:04 UTC (permalink / raw)
  To: intel-gfx; +Cc: Ben Widawsky

This was leftover crap from kill-agp. The current code is theoretically
broken for 64b bars. (I resist removing theoretically because I am too
lazy to test).

We still need to ioremap things ourselves because we want to ioremap_wc
the PTEs.

CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 35fec1e..06e14f1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -638,12 +638,9 @@ int i915_gem_gtt_init(struct drm_device *dev)
 	if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
 		pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
 
-	pci_read_config_dword(dev->pdev, PCI_BASE_ADDRESS_0, &tmp);
 	/* For GEN6+ the PTEs for the ggtt live at 2MB + BAR0 */
-	gtt_bus_addr = (tmp & PCI_BASE_ADDRESS_MEM_MASK) + (2<<20);
-
-	pci_read_config_dword(dev->pdev, PCI_BASE_ADDRESS_2, &tmp);
-	dev_priv->mm.gtt->gma_bus_addr = tmp & PCI_BASE_ADDRESS_MEM_MASK;
+	gtt_bus_addr = pci_resource_start(dev->pdev, 0) + (2<<20);
+	dev_priv->mm.gtt->gma_bus_addr = pci_resource_start(dev->pdev, 2);
 
 	/* i9xx_setup */
 	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
-- 
1.8.0

^ permalink raw reply related	[flat|nested] 4+ messages in thread