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From: Keith Packard <keithp@keithp.com>
To: Kenneth Graunke <kenneth@whitecape.org>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/3] drm/i915: Fix MI_DISPLAY_FLIP plane select offset on Ivybridge.
Date: Tue, 07 Jun 2011 16:14:38 -0700
Message-ID: <yuntyc1xmht.fsf@aiko.keithp.com> (raw)
In-Reply-To: <1307487281-3015-1-git-send-email-kenneth@whitecape.org>

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On Tue,  7 Jun 2011 15:54:39 -0700, Kenneth Graunke <kenneth@whitecape.org> wrote:
> According to BSpec volume 1c.4 section 3.2.9, Display (Plane) Select is
> now at bits 21:19 instead of 21:20.
> 
> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

I will note that the docs have an obvious bug -- 21:8 are 'reserved' on
IVB while 21:19 are 'Display (Plane) Select'. I trust you've actually
tried this on hardware and noticed that it works better now?


> +
> +	case 7:
> +		OUT_RING(MI_DISPLAY_FLIP | (intel_crtc->plane << 19));
> +		OUT_RING(fb->pitch | obj->tiling_mode);
> +		OUT_RING(obj->gtt_offset);
> +
> +		pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
> +		pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
> +		OUT_RING(pf | pipesrc);

What's this last DWORD supposed to be for? The IVB spec says length
should be '1' and there should be only 3 DWORDS in this command.

-- 
keith.packard@intel.com

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  parent reply index

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-06-07 22:54 Kenneth Graunke
2011-06-07 22:54 ` [PATCH 2/3] drm/i915: Remove HAS_BLT/HAS_BSD checks from ivybridge_irq_postinstall Kenneth Graunke
2011-06-07 23:16   ` Keith Packard
2011-06-08  9:29   ` Chris Wilson
2011-06-07 22:54 ` [PATCH 3/3] drm/i915: Enable GPU reset on Ivybridge Kenneth Graunke
2011-06-07 23:18   ` Keith Packard
2011-06-07 23:14 ` Keith Packard [this message]
2011-06-08  0:55   ` [PATCH 1/3] drm/i915: Fix MI_DISPLAY_FLIP plane select offset " Kenneth Graunke
2011-06-08  1:09     ` Keith Packard
2011-06-08  9:36     ` Chris Wilson
2011-06-08  9:54       ` Kenneth Graunke
2011-06-08 10:57         ` Chris Wilson

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