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From: Cathy Zhang <cathy.zhang@intel.com>
To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org
Cc: pbonzini@redhat.com, sean.j.christopherson@intel.com,
	vkuznets@redhat.com, wanpengli@tencent.com, jmattson@google.com,
	joro@8bytes.org, tglx@linutronix.de, mingo@redhat.com,
	bp@alien8.de, hpa@zytor.com,
	ricardo.neri-calderon@linux.intel.com, kyung.min.park@intel.com,
	jpoimboe@redhat.com, gregkh@linuxfoundation.org,
	ak@linux.intel.com, dave.hansen@intel.com, tony.luck@intel.com,
	ravi.v.shankar@intel.com, Cathy Zhang <cathy.zhang@intel.com>
Subject: [PATCH v2 2/4] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions
Date: Tue,  7 Jul 2020 10:16:21 +0800	[thread overview]
Message-ID: <1594088183-7187-3-git-send-email-cathy.zhang@intel.com> (raw)
In-Reply-To: <1594088183-7187-1-git-send-email-cathy.zhang@intel.com>

Intel TSX suspend load tracking instructions aim to give a way to
choose which memory accesses do not need to be tracked in the TSX
read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK
for enumeration.

A processor supports Intel TSX suspend load address tracking if
CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK
are available when this feature is present.

The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo.

Detailed information on the instructions and CPUID feature flag TSXLDTRK
can be found in the latest Intel Architecture Instruction Set Extensions
and Future Features Programming Reference and Intel 64 and IA-32
Architectures Software Developer's Manual.

Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index adf45cf..34b66d7 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -366,6 +366,7 @@
 #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */
 #define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */
 #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
+#define X86_FEATURE_TSX_LDTRK           (18*32+16) /* TSX Suspend Load Address Tracking */
 #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
 #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */
 #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */
-- 
1.8.3.1


  parent reply	other threads:[~2020-07-07  2:21 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-07  2:16 [PATCH v2 0/4] Expose new features for intel processor Cathy Zhang
2020-07-07  2:16 ` [PATCH v2 1/4] x86/cpufeatures: Add enumeration for SERIALIZE instruction Cathy Zhang
2020-07-07 16:36   ` Andy Lutomirski
2020-07-08  2:21     ` Ricardo Neri
2020-07-22 23:02       ` Thomas Gleixner
2020-07-24  2:03         ` Ricardo Neri
2020-08-18  7:14         ` Paolo Bonzini
2020-07-07  2:16 ` Cathy Zhang [this message]
2020-07-07  2:36   ` [PATCH v2 2/4] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions Kyung Min Park
2020-07-07  9:40   ` Greg KH
2020-07-08  8:33     ` Zhang, Cathy
2020-07-07  2:16 ` [PATCH v2 3/4] x86: Expose SERIALIZE for supported cpuid Cathy Zhang
2020-07-14  3:00   ` Sean Christopherson
2020-07-14 22:42     ` Zhang, Cathy
2020-07-14 23:05       ` hpa
2020-07-15  0:03         ` Zhang, Cathy
2020-07-15  4:18           ` hpa
2020-07-07  2:16 ` [PATCH v2 4/4] x86: Expose TSX Suspend Load Address Tracking Cathy Zhang
2020-07-07 23:22 ` [PATCH v2 0/4] Expose new features for intel processor Luck, Tony

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