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From: Sean Christopherson <sean.j.christopherson@intel.com>
To: Cathy Zhang <cathy.zhang@intel.com>
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
	x86@kernel.org, pbonzini@redhat.com, vkuznets@redhat.com,
	wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org,
	tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
	hpa@zytor.com, ricardo.neri-calderon@linux.intel.com,
	kyung.min.park@intel.com, jpoimboe@redhat.com,
	gregkh@linuxfoundation.org, ak@linux.intel.com,
	dave.hansen@intel.com, tony.luck@intel.com,
	ravi.v.shankar@intel.com
Subject: Re: [PATCH v2 3/4] x86: Expose SERIALIZE for supported cpuid
Date: Mon, 13 Jul 2020 20:00:47 -0700	[thread overview]
Message-ID: <20200714030047.GA12592@linux.intel.com> (raw)
In-Reply-To: <1594088183-7187-4-git-send-email-cathy.zhang@intel.com>

On Tue, Jul 07, 2020 at 10:16:22AM +0800, Cathy Zhang wrote:
> SERIALIZE instruction is supported by intel processors,
> like Sapphire Rapids. Expose it in KVM supported cpuid.

Providing at least a rough overview of the instruction, e.g. its enumeration,
usage, fault rules, controls, etc... would be nice.  In isolation, the
changelog isn't remotely helpful in understanding the correctness of the
patch.

> Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
> ---
>  arch/x86/kvm/cpuid.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> index 8a294f9..e603aeb 100644
> --- a/arch/x86/kvm/cpuid.c
> +++ b/arch/x86/kvm/cpuid.c
> @@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void)
>  	kvm_cpu_cap_mask(CPUID_7_EDX,
>  		F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
>  		F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
> -		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM)
> +		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
> +		F(SERIALIZE)
>  	);
>  
>  	/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
> -- 
> 1.8.3.1
> 

  reply	other threads:[~2020-07-14  3:00 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-07  2:16 [PATCH v2 0/4] Expose new features for intel processor Cathy Zhang
2020-07-07  2:16 ` [PATCH v2 1/4] x86/cpufeatures: Add enumeration for SERIALIZE instruction Cathy Zhang
2020-07-07 16:36   ` Andy Lutomirski
2020-07-08  2:21     ` Ricardo Neri
2020-07-22 23:02       ` Thomas Gleixner
2020-07-24  2:03         ` Ricardo Neri
2020-08-18  7:14         ` Paolo Bonzini
2020-07-07  2:16 ` [PATCH v2 2/4] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions Cathy Zhang
2020-07-07  2:36   ` Kyung Min Park
2020-07-07  9:40   ` Greg KH
2020-07-08  8:33     ` Zhang, Cathy
2020-07-07  2:16 ` [PATCH v2 3/4] x86: Expose SERIALIZE for supported cpuid Cathy Zhang
2020-07-14  3:00   ` Sean Christopherson [this message]
2020-07-14 22:42     ` Zhang, Cathy
2020-07-14 23:05       ` hpa
2020-07-15  0:03         ` Zhang, Cathy
2020-07-15  4:18           ` hpa
2020-07-07  2:16 ` [PATCH v2 4/4] x86: Expose TSX Suspend Load Address Tracking Cathy Zhang
2020-07-07 23:22 ` [PATCH v2 0/4] Expose new features for intel processor Luck, Tony

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