From: Paolo Bonzini <pbonzini@redhat.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Ricardo Neri <ricardo.neri-calderon@linux.intel.com>,
Andy Lutomirski <luto@kernel.org>
Cc: Cathy Zhang <cathy.zhang@intel.com>,
kvm list <kvm@vger.kernel.org>,
LKML <linux-kernel@vger.kernel.org>, X86 ML <x86@kernel.org>,
"Christopherson, Sean J" <sean.j.christopherson@intel.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
"H. Peter Anvin" <hpa@zytor.com>,
Kyung Min Park <kyung.min.park@intel.com>,
Josh Poimboeuf <jpoimboe@redhat.com>,
Greg KH <gregkh@linuxfoundation.org>,
Andi Kleen <ak@linux.intel.com>,
Dave Hansen <dave.hansen@intel.com>,
Tony Luck <tony.luck@intel.com>,
"Ravi V. Shankar" <ravi.v.shankar@intel.com>,
fenghua.yu@intel.com
Subject: Re: [PATCH v2 1/4] x86/cpufeatures: Add enumeration for SERIALIZE instruction
Date: Tue, 18 Aug 2020 09:14:58 +0200 [thread overview]
Message-ID: <be322917-0f10-de4c-9b7c-308d667277eb@redhat.com> (raw)
In-Reply-To: <87eep3ywz0.fsf@nanos.tec.linutronix.de>
On 23/07/20 01:02, Thomas Gleixner wrote:
>> I am cc'ing Fenghua, who has volunteered to work on this. Addind support
>> for SERIALIZE in sync_core() should not block merging these patches,
>> correct?
> Come on. We are not serving KVM first before making this usable on bare
> metal.
This in the end was merged in 5.9, but: why not? It is just an
instruction with no other support code needed in the kernel (or KVM for
that matter except for marking the CPUID bit as supported). It is
common to run hosts with an older kernel than the guests, and by this
line of reasoning, we should not even have enabled support for FSGSBASE
in KVM.
Paolo
next prev parent reply other threads:[~2020-08-18 7:15 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-07 2:16 [PATCH v2 0/4] Expose new features for intel processor Cathy Zhang
2020-07-07 2:16 ` [PATCH v2 1/4] x86/cpufeatures: Add enumeration for SERIALIZE instruction Cathy Zhang
2020-07-07 16:36 ` Andy Lutomirski
2020-07-08 2:21 ` Ricardo Neri
2020-07-22 23:02 ` Thomas Gleixner
2020-07-24 2:03 ` Ricardo Neri
2020-08-18 7:14 ` Paolo Bonzini [this message]
2020-07-07 2:16 ` [PATCH v2 2/4] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions Cathy Zhang
2020-07-07 2:36 ` Kyung Min Park
2020-07-07 9:40 ` Greg KH
2020-07-08 8:33 ` Zhang, Cathy
2020-07-07 2:16 ` [PATCH v2 3/4] x86: Expose SERIALIZE for supported cpuid Cathy Zhang
2020-07-14 3:00 ` Sean Christopherson
2020-07-14 22:42 ` Zhang, Cathy
2020-07-14 23:05 ` hpa
2020-07-15 0:03 ` Zhang, Cathy
2020-07-15 4:18 ` hpa
2020-07-07 2:16 ` [PATCH v2 4/4] x86: Expose TSX Suspend Load Address Tracking Cathy Zhang
2020-07-07 23:22 ` [PATCH v2 0/4] Expose new features for intel processor Luck, Tony
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