From: "Zhang, Cathy" <cathy.zhang@intel.com>
To: Greg KH <gregkh@linuxfoundation.org>
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
x86@kernel.org, pbonzini@redhat.com,
sean.j.christopherson@intel.com, vkuznets@redhat.com,
wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org,
tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
hpa@zytor.com, ricardo.neri-calderon@linux.intel.com,
kyung.min.park@intel.com, jpoimboe@redhat.com,
ak@linux.intel.com, dave.hansen@intel.com, tony.luck@intel.com,
ravi.v.shankar@intel.com
Subject: Re: [PATCH v2 2/4] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions
Date: Wed, 8 Jul 2020 16:33:29 +0800 [thread overview]
Message-ID: <78a3edfe-0a6b-4b23-f41d-cebe7dce67cf@intel.com> (raw)
In-Reply-To: <20200707094019.GA2639362@kroah.com>
On 7/7/2020 5:40 PM, Greg KH wrote:
> On Tue, Jul 07, 2020 at 10:16:21AM +0800, Cathy Zhang wrote:
>> Intel TSX suspend load tracking instructions aim to give a way to
>> choose which memory accesses do not need to be tracked in the TSX
>> read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK
>> for enumeration.
>>
>> A processor supports Intel TSX suspend load address tracking if
>> CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK
>> are available when this feature is present.
>>
>> The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo.
>>
>> Detailed information on the instructions and CPUID feature flag TSXLDTRK
>> can be found in the latest Intel Architecture Instruction Set Extensions
>> and Future Features Programming Reference and Intel 64 and IA-32
>> Architectures Software Developer's Manual.
>>
>> Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
>> Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
>> ---
>> arch/x86/include/asm/cpufeatures.h | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
>> index adf45cf..34b66d7 100644
>> --- a/arch/x86/include/asm/cpufeatures.h
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -366,6 +366,7 @@
>> #define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */
>> #define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */
>> #define X86_FEATURE_SERIALIZE (18*32+14) /* SERIALIZE instruction */
>> +#define X86_FEATURE_TSX_LDTRK (18*32+16) /* TSX Suspend Load Address Tracking */
> No tabs?
>
> :(
Sorry, it's my fault. I wrongly pick up an older kernel patch version,
the latest one has no such issue. It will be addressed in next version.
next prev parent reply other threads:[~2020-07-08 8:33 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-07 2:16 [PATCH v2 0/4] Expose new features for intel processor Cathy Zhang
2020-07-07 2:16 ` [PATCH v2 1/4] x86/cpufeatures: Add enumeration for SERIALIZE instruction Cathy Zhang
2020-07-07 16:36 ` Andy Lutomirski
2020-07-08 2:21 ` Ricardo Neri
2020-07-22 23:02 ` Thomas Gleixner
2020-07-24 2:03 ` Ricardo Neri
2020-08-18 7:14 ` Paolo Bonzini
2020-07-07 2:16 ` [PATCH v2 2/4] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions Cathy Zhang
2020-07-07 2:36 ` Kyung Min Park
2020-07-07 9:40 ` Greg KH
2020-07-08 8:33 ` Zhang, Cathy [this message]
2020-07-07 2:16 ` [PATCH v2 3/4] x86: Expose SERIALIZE for supported cpuid Cathy Zhang
2020-07-14 3:00 ` Sean Christopherson
2020-07-14 22:42 ` Zhang, Cathy
2020-07-14 23:05 ` hpa
2020-07-15 0:03 ` Zhang, Cathy
2020-07-15 4:18 ` hpa
2020-07-07 2:16 ` [PATCH v2 4/4] x86: Expose TSX Suspend Load Address Tracking Cathy Zhang
2020-07-07 23:22 ` [PATCH v2 0/4] Expose new features for intel processor Luck, Tony
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