From: Jingyi Wang <wangjingyi11@huawei.com> To: <drjones@redhat.com>, <kvm@vger.kernel.org>, <kvmarm@lists.cs.columbia.edu> Cc: maz@kernel.org, prime.zeng@hisilicon.com Subject: [kvm-unit-tests PATCH v3 03/10] arm64: microbench: gic: Add ipi latency test for gicv4.1 support kvm Date: Fri, 31 Jul 2020 15:42:37 +0800 [thread overview] Message-ID: <20200731074244.20432-4-wangjingyi11@huawei.com> (raw) In-Reply-To: <20200731074244.20432-1-wangjingyi11@huawei.com> If gicv4.1(sgi hardware injection) is supported in kvm, we test ipi injection via hw/sw way separately. Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com> --- arm/micro-bench.c | 62 ++++++++++++++++++++++++++++++++++++++------ lib/arm/asm/gic-v3.h | 3 +++ lib/arm/asm/gic.h | 1 + 3 files changed, 58 insertions(+), 8 deletions(-) diff --git a/arm/micro-bench.c b/arm/micro-bench.c index fc4d356..f8314db 100644 --- a/arm/micro-bench.c +++ b/arm/micro-bench.c @@ -26,6 +26,8 @@ static u32 cntfrq; static volatile bool irq_ready, irq_received; +static int nr_ipi_received; + static void *vgic_dist_base; static void (*write_eoir)(u32 irqstat); @@ -91,15 +93,55 @@ static void gic_prep_common(void) assert(irq_ready); } -static void ipi_prep(void) +static bool ipi_prep(void) +{ + u32 val; + + val = readl(vgic_dist_base + GICD_CTLR); + if (readl(vgic_dist_base + GICD_TYPER2) & GICD_TYPER2_nASSGIcap) { + /* nASSGIreq can be changed only when GICD is disabled */ + val &= ~GICD_CTLR_ENABLE_G1A; + val &= ~GICD_CTLR_nASSGIreq; + writel(val, vgic_dist_base + GICD_CTLR); + gicv3_dist_wait_for_rwp(); + + val |= GICD_CTLR_ENABLE_G1A; + writel(val, vgic_dist_base + GICD_CTLR); + gicv3_dist_wait_for_rwp(); + } + + nr_ipi_received = 0; + gic_prep_common(); + return true; +} + +static bool ipi_hw_prep(void) { + u32 val; + + val = readl(vgic_dist_base + GICD_CTLR); + if (readl(vgic_dist_base + GICD_TYPER2) & GICD_TYPER2_nASSGIcap) { + /* nASSGIreq can be changed only when GICD is disabled */ + val &= ~GICD_CTLR_ENABLE_G1A; + val |= GICD_CTLR_nASSGIreq; + writel(val, vgic_dist_base + GICD_CTLR); + gicv3_dist_wait_for_rwp(); + + val |= GICD_CTLR_ENABLE_G1A; + writel(val, vgic_dist_base + GICD_CTLR); + gicv3_dist_wait_for_rwp(); + } else { + return false; + } + + nr_ipi_received = 0; gic_prep_common(); + return true; } static void ipi_exec(void) { unsigned tries = 1 << 28; - static int received = 0; irq_received = false; @@ -109,9 +151,9 @@ static void ipi_exec(void) cpu_relax(); if (irq_received) - ++received; + ++nr_ipi_received; - assert_msg(irq_received, "failed to receive IPI in time, but received %d successfully\n", received); + assert_msg(irq_received, "failed to receive IPI in time, but received %d successfully\n", nr_ipi_received); } static void hvc_exec(void) @@ -147,7 +189,7 @@ static void eoi_exec(void) struct exit_test { const char *name; - void (*prep)(void); + bool (*prep)(void); void (*exec)(void); bool run; }; @@ -158,6 +200,7 @@ static struct exit_test tests[] = { {"mmio_read_vgic", NULL, mmio_read_vgic_exec, true}, {"eoi", NULL, eoi_exec, true}, {"ipi", ipi_prep, ipi_exec, true}, + {"ipi_hw", ipi_hw_prep, ipi_exec, true}, }; struct ns_time { @@ -181,9 +224,12 @@ static void loop_test(struct exit_test *test) uint64_t start, end, total_ticks, ntimes = NTIMES; struct ns_time total_ns, avg_ns; - if (test->prep) - test->prep(); - + if (test->prep) { + if(!test->prep()) { + printf("%s test skipped\n", test->name); + return; + } + } isb(); start = read_sysreg(cntpct_el0); while (ntimes--) diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index cb72922..b4ce130 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -20,10 +20,13 @@ */ #define GICD_CTLR 0x0000 #define GICD_CTLR_RWP (1U << 31) +#define GICD_CTLR_nASSGIreq (1U << 8) #define GICD_CTLR_ARE_NS (1U << 4) #define GICD_CTLR_ENABLE_G1A (1U << 1) #define GICD_CTLR_ENABLE_G1 (1U << 0) +#define GICD_TYPER2_nASSGIcap (1U << 8) + /* Re-Distributor registers, offsets from RD_base */ #define GICR_TYPER 0x0008 diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index 38e79b2..1898400 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -13,6 +13,7 @@ #define GICD_CTLR 0x0000 #define GICD_TYPER 0x0004 #define GICD_IIDR 0x0008 +#define GICD_TYPER2 0x000C #define GICD_IGROUPR 0x0080 #define GICD_ISENABLER 0x0100 #define GICD_ICENABLER 0x0180 -- 2.19.1 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
next prev parent reply other threads:[~2020-07-31 7:43 UTC|newest] Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-07-31 7:42 [kvm-unit-tests PATCH v3 00/10] arm/arm64: Add IPI/LPI/vtimer latency test Jingyi Wang 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 01/10] arm64: microbench: get correct ipi received num Jingyi Wang 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 02/10] arm64: microbench: Generalize ipi test names Jingyi Wang 2020-07-31 7:42 ` Jingyi Wang [this message] 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 04/10] arm64: its: Handle its command queue wrapping Jingyi Wang 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 05/10] arm64: microbench: its: Add LPI latency test Jingyi Wang 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 06/10] arm64: microbench: Allow each test to specify its running times Jingyi Wang 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 07/10] arm64: microbench: Add time limit for each individual test Jingyi Wang 2020-08-01 16:13 ` Andrew Jones 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 08/10] arm64: microbench: Add vtimer latency test Jingyi Wang 2020-08-01 16:22 ` Andrew Jones 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 09/10] arm64: microbench: Add test->post() to further process test results Jingyi Wang 2020-08-01 17:03 ` Andrew Jones 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 10/10] arm64: microbench: Add timer_post() to get actual PPI latency Jingyi Wang 2020-07-31 12:01 ` [kvm-unit-tests PATCH v3 00/10] arm/arm64: Add IPI/LPI/vtimer latency test Andrew Jones 2020-08-03 2:15 ` Jingyi Wang 2020-08-01 17:40 ` Andrew Jones 2020-08-05 11:54 ` Jingyi Wang 2020-08-05 12:13 ` Marc Zyngier 2020-08-11 1:48 ` Jingyi Wang 2020-08-11 7:49 ` Marc Zyngier 2020-08-17 1:46 ` Jingyi Wang 2020-08-17 8:26 ` Marc Zyngier
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