* [RFC PATCH 0/2] acpi: add support for CXL _OSC
@ 2022-03-17 0:27 Vishal Verma
2022-03-17 0:27 ` [RFC PATCH 1/2] PCI/ACPI: Use CXL _OSC instead of PCIe _OSC Vishal Verma
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Vishal Verma @ 2022-03-17 0:27 UTC (permalink / raw)
To: linux-cxl
Cc: linux-acpi, Jonathan Cameron, Dan Williams, Rafael J. Wysocki,
Robert Moore, Bjorn Helgaas, Vishal Verma
Add support for using the CXL definition of _OSC where applicable, and
negotiating CXL specific support and control bits.
Patch 1 adds the new CXL _OSC UUID, and uses it instead of the PCI UUID
when a root port is CXL enabled. It provides a fallback method for
CXL-1.1 devices that may not implement the CXL-2.0 _OSC.
Patch 2 performs negotiation for the CXL specific _OSC support and
control bits.
I've tested these against a custom qemu[1], which adds the CXL _OSC (in
addition to other CXL support). Specifically, _OSC support is added
here[2].
[1]: https://gitlab.com/jic23/qemu/-/tree/cxl-v7-draft-2-for-test
[2]: https://gitlab.com/jic23/qemu/-/commit/31c85054b84645dfbd9e9bb14aa35286141c14cf
Dan Williams (1):
PCI/ACPI: Use CXL _OSC instead of PCIe _OSC
Vishal Verma (1):
acpi/pci_root: negotiate CXL _OSC
include/linux/acpi.h | 11 +++
include/acpi/acpi_bus.h | 7 +-
drivers/acpi/pci_root.c | 201 ++++++++++++++++++++++++++++++++++------
3 files changed, 187 insertions(+), 32 deletions(-)
base-commit: 74be98774dfbc5b8b795db726bd772e735d2edd4
--
2.35.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [RFC PATCH 1/2] PCI/ACPI: Use CXL _OSC instead of PCIe _OSC
2022-03-17 0:27 [RFC PATCH 0/2] acpi: add support for CXL _OSC Vishal Verma
@ 2022-03-17 0:27 ` Vishal Verma
2022-03-17 1:47 ` Dan Williams
2022-03-17 0:27 ` [RFC PATCH 2/2] acpi/pci_root: negotiate CXL _OSC Vishal Verma
2022-03-17 15:19 ` [RFC PATCH 0/2] acpi: add support for " Jonathan Cameron
2 siblings, 1 reply; 11+ messages in thread
From: Vishal Verma @ 2022-03-17 0:27 UTC (permalink / raw)
To: linux-cxl
Cc: linux-acpi, Jonathan Cameron, Dan Williams, Rafael J. Wysocki,
Robert Moore, Bjorn Helgaas, Rafael J. Wysocki
From: Dan Williams <dan.j.williams@intel.com>
In preparation for negotiating OS control of CXL _OSC features, do the
minimal enabling to use CXL _OSC to handle the base PCIe feature
negotiation. Recall that CXL _OSC is a super-set of PCIe _OSC and the
CXL 2.0 specification mandates: "If a CXL Host Bridge device exposes CXL
_OSC, CXL aware OSPM shall evaluate CXL _OSC and not evaluate PCIe
_OSC."
A new ->cxl_osc_disable attribute is added for cases where platform
firmware publishes ACPI0016, but does not also publish CXL _OSC.
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: Robert Moore <robert.moore@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
include/acpi/acpi_bus.h | 1 +
drivers/acpi/pci_root.c | 62 +++++++++++++++++++++++++++++++----------
2 files changed, 48 insertions(+), 15 deletions(-)
diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h
index ca88c4706f2b..768ef1584055 100644
--- a/include/acpi/acpi_bus.h
+++ b/include/acpi/acpi_bus.h
@@ -585,6 +585,7 @@ struct acpi_pci_root {
struct acpi_device * device;
struct pci_bus *bus;
u16 segment;
+ bool cxl_osc_disable;
struct resource secondary; /* downstream bus range */
u32 osc_support_set; /* _OSC state of support bits */
diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
index b76db99cced3..2d834504096b 100644
--- a/drivers/acpi/pci_root.c
+++ b/drivers/acpi/pci_root.c
@@ -170,20 +170,47 @@ static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
ARRAY_SIZE(pci_osc_control_bit));
}
-static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766";
+static bool is_pcie(struct acpi_pci_root *root)
+{
+ return strcmp(acpi_device_hid(root->device), "PNP0A08") == 0;
+}
-static acpi_status acpi_pci_run_osc(acpi_handle handle,
+static bool is_cxl(struct acpi_pci_root *root)
+{
+ if (root->cxl_osc_disable)
+ return false;
+ return strcmp(acpi_device_hid(root->device), "ACPI0016") == 0;
+}
+
+static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766";
+static u8 cxl_osc_uuid_str[] = "68F2D50B-C469-4d8A-BD3D-941A103FD3FC";
+
+static char *to_uuid(struct acpi_pci_root *root)
+{
+ if (is_cxl(root))
+ return cxl_osc_uuid_str;
+ return pci_osc_uuid_str;
+}
+
+static int cap_length(struct acpi_pci_root *root)
+{
+ if (is_cxl(root))
+ return sizeof(u32) * 6;
+ return sizeof(u32) * 3;
+}
+
+static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root,
const u32 *capbuf, u32 *retval)
{
struct acpi_osc_context context = {
- .uuid_str = pci_osc_uuid_str,
+ .uuid_str = to_uuid(root),
.rev = 1,
- .cap.length = 12,
+ .cap.length = cap_length(root),
.cap.pointer = (void *)capbuf,
};
acpi_status status;
- status = acpi_run_osc(handle, &context);
+ status = acpi_run_osc(root->device->handle, &context);
if (ACPI_SUCCESS(status)) {
*retval = *((u32 *)(context.ret.pointer + 8));
kfree(context.ret.pointer);
@@ -196,7 +223,7 @@ static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root,
u32 *control)
{
acpi_status status;
- u32 result, capbuf[3];
+ u32 result, capbuf[6];
support |= root->osc_support_set;
@@ -204,10 +231,18 @@ static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root,
capbuf[OSC_SUPPORT_DWORD] = support;
capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set;
- status = acpi_pci_run_osc(root->device->handle, capbuf, &result);
+retry:
+ status = acpi_pci_run_osc(root, capbuf, &result);
if (ACPI_SUCCESS(status)) {
root->osc_support_set = support;
*control = result;
+ } else if (is_cxl(root)) {
+ /*
+ * CXL _OSC is optional on CXL 1.1 hosts. Fall back to PCIe _OSC
+ * upon any failure using CXL _OSC.
+ */
+ root->cxl_osc_disable = true;
+ goto retry;
}
return status;
}
@@ -338,7 +373,7 @@ static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 s
u32 req = OSC_PCI_EXPRESS_CAPABILITY_CONTROL;
struct acpi_pci_root *root;
acpi_status status;
- u32 ctrl, capbuf[3];
+ u32 ctrl, capbuf[6];
if (!mask)
return AE_BAD_PARAMETER;
@@ -375,7 +410,7 @@ static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 s
capbuf[OSC_QUERY_DWORD] = 0;
capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set;
capbuf[OSC_CONTROL_DWORD] = ctrl;
- status = acpi_pci_run_osc(handle, capbuf, mask);
+ status = acpi_pci_run_osc(root, capbuf, mask);
if (ACPI_FAILURE(status))
return status;
@@ -454,8 +489,7 @@ static bool os_control_query_checks(struct acpi_pci_root *root, u32 support)
return true;
}
-static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
- bool is_pcie)
+static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)
{
u32 support, control = 0, requested = 0;
acpi_status status;
@@ -506,7 +540,7 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
*no_aspm = 1;
/* _OSC is optional for PCI host bridges */
- if ((status == AE_NOT_FOUND) && !is_pcie)
+ if ((status == AE_NOT_FOUND) && !is_pcie(root))
return;
if (control) {
@@ -529,7 +563,6 @@ static int acpi_pci_root_add(struct acpi_device *device,
acpi_handle handle = device->handle;
int no_aspm = 0;
bool hotadd = system_state == SYSTEM_RUNNING;
- bool is_pcie;
root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL);
if (!root)
@@ -587,8 +620,7 @@ static int acpi_pci_root_add(struct acpi_device *device,
root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle);
- is_pcie = strcmp(acpi_device_hid(device), "PNP0A08") == 0;
- negotiate_os_control(root, &no_aspm, is_pcie);
+ negotiate_os_control(root, &no_aspm);
/*
* TBD: Need PCI interface for enumeration/configuration of roots.
--
2.35.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [RFC PATCH 2/2] acpi/pci_root: negotiate CXL _OSC
2022-03-17 0:27 [RFC PATCH 0/2] acpi: add support for CXL _OSC Vishal Verma
2022-03-17 0:27 ` [RFC PATCH 1/2] PCI/ACPI: Use CXL _OSC instead of PCIe _OSC Vishal Verma
@ 2022-03-17 0:27 ` Vishal Verma
2022-03-17 3:19 ` Dan Williams
2022-03-17 16:10 ` Jonathan Cameron
2022-03-17 15:19 ` [RFC PATCH 0/2] acpi: add support for " Jonathan Cameron
2 siblings, 2 replies; 11+ messages in thread
From: Vishal Verma @ 2022-03-17 0:27 UTC (permalink / raw)
To: linux-cxl
Cc: linux-acpi, Jonathan Cameron, Dan Williams, Rafael J. Wysocki,
Robert Moore, Bjorn Helgaas, Vishal Verma, Rafael J. Wysocki
Add full support for negotiating _OSC as defined in the CXL 2.0 spec, as
applicable to CXL-enabled platforms. Advertise support for the CXL
features we support - 'CXL 2.0 port/device register access', 'Protocol
Error Reporting', and 'CL Native Hot Plug'. Request control for 'CXL
Memory Error Reporting'. The requests are dependent on CONFIG_* based
pre-requisites, and prior PCI enabling, similar to how the standard PCI
_OSC bits are determined.
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: Robert Moore <robert.moore@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
---
include/linux/acpi.h | 11 +++
include/acpi/acpi_bus.h | 6 +-
drivers/acpi/pci_root.c | 147 ++++++++++++++++++++++++++++++++++------
3 files changed, 143 insertions(+), 21 deletions(-)
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 6274758648e3..1717ccc265d7 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -554,6 +554,8 @@ acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context);
#define OSC_QUERY_DWORD 0 /* DWORD 1 */
#define OSC_SUPPORT_DWORD 1 /* DWORD 2 */
#define OSC_CONTROL_DWORD 2 /* DWORD 3 */
+#define OSC_CXL_SUPPORT_DWORD 3 /* DWORD 4 */
+#define OSC_CXL_CONTROL_DWORD 4 /* DWORD 5 */
/* _OSC Capabilities DWORD 1: Query/Control and Error Returns (generic) */
#define OSC_QUERY_ENABLE 0x00000001 /* input */
@@ -607,6 +609,15 @@ extern u32 osc_sb_native_usb4_control;
#define OSC_PCI_EXPRESS_LTR_CONTROL 0x00000020
#define OSC_PCI_EXPRESS_DPC_CONTROL 0x00000080
+/* CXL _OSC: Capabilities DWORD 4: Support Field */
+#define OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT 0x00000001
+#define OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT 0x00000002
+#define OSC_CXL_PER_SUPPORT 0x00000004
+#define OSC_CXL_NATIVE_HP_SUPPORT 0x00000008
+
+/* CXL _OSC: Capabilities DWORD 5: Control Field */
+#define OSC_CXL_ERROR_REPORTING_CONTROL 0x00000001
+
#define ACPI_GSB_ACCESS_ATTRIB_QUICK 0x00000002
#define ACPI_GSB_ACCESS_ATTRIB_SEND_RCV 0x00000004
#define ACPI_GSB_ACCESS_ATTRIB_BYTE 0x00000006
diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h
index 768ef1584055..5776d4c1509a 100644
--- a/include/acpi/acpi_bus.h
+++ b/include/acpi/acpi_bus.h
@@ -588,8 +588,10 @@ struct acpi_pci_root {
bool cxl_osc_disable;
struct resource secondary; /* downstream bus range */
- u32 osc_support_set; /* _OSC state of support bits */
- u32 osc_control_set; /* _OSC state of control bits */
+ u32 osc_support_set; /* _OSC state of support bits */
+ u32 osc_control_set; /* _OSC state of control bits */
+ u32 cxl_osc_support_set; /* _OSC state of CXL support bits */
+ u32 cxl_osc_control_set; /* _OSC state of CXL control bits */
phys_addr_t mcfg_addr;
};
diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
index 2d834504096b..c916318b11a0 100644
--- a/drivers/acpi/pci_root.c
+++ b/drivers/acpi/pci_root.c
@@ -142,6 +142,17 @@ static struct pci_osc_bit_struct pci_osc_control_bit[] = {
{ OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" },
};
+static struct pci_osc_bit_struct cxl_osc_support_bit[] = {
+ { OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT, "CXL11PortRegAccess" },
+ { OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT, "CXL20PortDevRegAccess" },
+ { OSC_CXL_PER_SUPPORT, "CXLProtocolErrorReporting" },
+ { OSC_CXL_NATIVE_HP_SUPPORT, "CXLNativeHotPlug" },
+};
+
+static struct pci_osc_bit_struct cxl_osc_control_bit[] = {
+ { OSC_CXL_ERROR_REPORTING_CONTROL, "CXLMemErrorReporting" },
+};
+
static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word,
struct pci_osc_bit_struct *table, int size)
{
@@ -170,6 +181,18 @@ static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
ARRAY_SIZE(pci_osc_control_bit));
}
+static void decode_cxl_osc_support(struct acpi_pci_root *root, char *msg, u32 word)
+{
+ decode_osc_bits(root, msg, word, cxl_osc_support_bit,
+ ARRAY_SIZE(cxl_osc_support_bit));
+}
+
+static void decode_cxl_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
+{
+ decode_osc_bits(root, msg, word, cxl_osc_control_bit,
+ ARRAY_SIZE(cxl_osc_control_bit));
+}
+
static bool is_pcie(struct acpi_pci_root *root)
{
return strcmp(acpi_device_hid(root->device), "PNP0A08") == 0;
@@ -199,8 +222,19 @@ static int cap_length(struct acpi_pci_root *root)
return sizeof(u32) * 3;
}
+static u32 acpi_osc_ctx_get_pci_control(struct acpi_osc_context *context)
+{
+ return *((u32 *)(context->ret.pointer + 8));
+}
+
+static u32 acpi_osc_ctx_get_cxl_control(struct acpi_osc_context *context)
+{
+ return *((u32 *)(context->ret.pointer + 16));
+}
+
static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root,
- const u32 *capbuf, u32 *retval)
+ const u32 *capbuf, u32 *pci_control,
+ u32 *cxl_control)
{
struct acpi_osc_context context = {
.uuid_str = to_uuid(root),
@@ -212,18 +246,20 @@ static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root,
status = acpi_run_osc(root->device->handle, &context);
if (ACPI_SUCCESS(status)) {
- *retval = *((u32 *)(context.ret.pointer + 8));
+ *pci_control = acpi_osc_ctx_get_pci_control(&context);
+ if (is_cxl(root))
+ *cxl_control = acpi_osc_ctx_get_cxl_control(&context);
kfree(context.ret.pointer);
}
return status;
}
-static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root,
- u32 support,
- u32 *control)
+static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, u32 support,
+ u32 *control, u32 cxl_support,
+ u32 *cxl_control)
{
acpi_status status;
- u32 result, capbuf[6];
+ u32 pci_result, cxl_result, capbuf[8];
support |= root->osc_support_set;
@@ -231,11 +267,21 @@ static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root,
capbuf[OSC_SUPPORT_DWORD] = support;
capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set;
+ if (is_cxl(root)) {
+ cxl_support |= root->cxl_osc_support_set;
+ capbuf[OSC_CXL_SUPPORT_DWORD] = cxl_support;
+ capbuf[OSC_CXL_CONTROL_DWORD] = *cxl_control | root->cxl_osc_control_set;
+ }
+
retry:
- status = acpi_pci_run_osc(root, capbuf, &result);
+ status = acpi_pci_run_osc(root, capbuf, &pci_result, &cxl_result);
if (ACPI_SUCCESS(status)) {
root->osc_support_set = support;
- *control = result;
+ *control = pci_result;
+ if (is_cxl(root)) {
+ root->cxl_osc_support_set = cxl_support;
+ *cxl_control = cxl_result;
+ }
} else if (is_cxl(root)) {
/*
* CXL _OSC is optional on CXL 1.1 hosts. Fall back to PCIe _OSC
@@ -358,6 +404,8 @@ EXPORT_SYMBOL_GPL(acpi_get_pci_dev);
* @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex).
* @mask: Mask of _OSC bits to request control of, place to store control mask.
* @support: _OSC supported capability.
+ * @cxl_mask: Mask of CXL _OSC control bits, place to store control mask.
+ * @cxl_support: CXL _OSC supported capability.
*
* Run _OSC query for @mask and if that is successful, compare the returned
* mask of control bits with @req. If all of the @req bits are set in the
@@ -368,12 +416,14 @@ EXPORT_SYMBOL_GPL(acpi_get_pci_dev);
* _OSC bits the BIOS has granted control of, but its contents are meaningless
* on failure.
**/
-static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 support)
+static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask,
+ u32 support, u32 *cxl_mask,
+ u32 cxl_support)
{
u32 req = OSC_PCI_EXPRESS_CAPABILITY_CONTROL;
struct acpi_pci_root *root;
acpi_status status;
- u32 ctrl, capbuf[6];
+ u32 ctrl, cxl_ctrl, capbuf[8];
if (!mask)
return AE_BAD_PARAMETER;
@@ -385,20 +435,35 @@ static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 s
ctrl = *mask;
*mask |= root->osc_control_set;
+ if (is_cxl(root)) {
+ cxl_ctrl = *cxl_mask;
+ *mask |= root->osc_control_set;
+ }
+
/* Need to check the available controls bits before requesting them. */
do {
- status = acpi_pci_query_osc(root, support, mask);
+ status = acpi_pci_query_osc(root, support, mask, cxl_support,
+ cxl_mask);
if (ACPI_FAILURE(status))
return status;
- if (ctrl == *mask)
- break;
- decode_osc_control(root, "platform does not support",
- ctrl & ~(*mask));
+ if (is_cxl(root)) {
+ if ((ctrl == *mask) && (cxl_ctrl == *cxl_mask))
+ break;
+ decode_cxl_osc_control(root, "platform does not support",
+ cxl_ctrl & ~(*cxl_mask));
+ } else {
+ if (ctrl == *mask)
+ break;
+ decode_osc_control(root, "platform does not support",
+ ctrl & ~(*mask));
+ }
ctrl = *mask;
- } while (*mask);
+ cxl_ctrl = *cxl_mask;
+ } while (*mask || *cxl_mask);
/* No need to request _OSC if the control was already granted. */
- if ((root->osc_control_set & ctrl) == ctrl)
+ if (((root->osc_control_set & ctrl) == ctrl) &&
+ ((root->cxl_osc_control_set & cxl_ctrl) == cxl_ctrl))
return AE_OK;
if ((ctrl & req) != req) {
@@ -410,11 +475,17 @@ static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 s
capbuf[OSC_QUERY_DWORD] = 0;
capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set;
capbuf[OSC_CONTROL_DWORD] = ctrl;
- status = acpi_pci_run_osc(root, capbuf, mask);
+ if (is_cxl(root)) {
+ capbuf[OSC_CXL_SUPPORT_DWORD] = root->cxl_osc_support_set;
+ capbuf[OSC_CXL_CONTROL_DWORD] = cxl_ctrl;
+ }
+
+ status = acpi_pci_run_osc(root, capbuf, mask, cxl_mask);
if (ACPI_FAILURE(status))
return status;
root->osc_control_set = *mask;
+ root->cxl_osc_control_set = *cxl_mask;
return AE_OK;
}
@@ -440,6 +511,18 @@ static u32 calculate_support(void)
return support;
}
+static u32 calculate_cxl_support(void)
+{
+ u32 support;
+
+ support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT;
+ support |= OSC_CXL_PER_SUPPORT;
+ if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
+ support |= OSC_CXL_NATIVE_HP_SUPPORT;
+
+ return support;
+}
+
static u32 calculate_control(void)
{
u32 control;
@@ -471,6 +554,16 @@ static u32 calculate_control(void)
return control;
}
+static u32 calculate_cxl_control(void)
+{
+ u32 control;
+
+ if (pci_aer_available())
+ control |= OSC_CXL_ERROR_REPORTING_CONTROL;
+
+ return control;
+}
+
static bool os_control_query_checks(struct acpi_pci_root *root, u32 support)
{
struct acpi_device *device = root->device;
@@ -492,6 +585,7 @@ static bool os_control_query_checks(struct acpi_pci_root *root, u32 support)
static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)
{
u32 support, control = 0, requested = 0;
+ u32 cxl_support, cxl_control = 0, cxl_requested = 0;
acpi_status status;
struct acpi_device *device = root->device;
acpi_handle handle = device->handle;
@@ -515,10 +609,20 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)
if (os_control_query_checks(root, support))
requested = control = calculate_control();
- status = acpi_pci_osc_control_set(handle, &control, support);
+ if (is_cxl(root)) {
+ cxl_support = calculate_cxl_support();
+ decode_cxl_osc_support(root, "OS supports", cxl_support);
+ cxl_requested = cxl_control = calculate_cxl_control();
+ }
+
+ status = acpi_pci_osc_control_set(handle, &control, support,
+ &cxl_control, cxl_support);
if (ACPI_SUCCESS(status)) {
if (control)
decode_osc_control(root, "OS now controls", control);
+ if (cxl_control)
+ decode_cxl_osc_control(root, "OS now controls",
+ cxl_control);
if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
/*
@@ -547,6 +651,11 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)
decode_osc_control(root, "OS requested", requested);
decode_osc_control(root, "platform willing to grant", control);
}
+ if (cxl_control) {
+ decode_cxl_osc_control(root, "OS requested", cxl_requested);
+ decode_cxl_osc_control(root, "platform willing to grant",
+ cxl_control);
+ }
dev_info(&device->dev, "_OSC: platform retains control of PCIe features (%s)\n",
acpi_format_exception(status));
--
2.35.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [RFC PATCH 1/2] PCI/ACPI: Use CXL _OSC instead of PCIe _OSC
2022-03-17 0:27 ` [RFC PATCH 1/2] PCI/ACPI: Use CXL _OSC instead of PCIe _OSC Vishal Verma
@ 2022-03-17 1:47 ` Dan Williams
2022-03-17 15:40 ` Jonathan Cameron
0 siblings, 1 reply; 11+ messages in thread
From: Dan Williams @ 2022-03-17 1:47 UTC (permalink / raw)
To: Vishal Verma
Cc: linux-cxl, Linux ACPI, Jonathan Cameron, Rafael J. Wysocki,
Robert Moore, Bjorn Helgaas, Rafael J. Wysocki
On Wed, Mar 16, 2022 at 5:27 PM Vishal Verma <vishal.l.verma@intel.com> wrote:
>
> From: Dan Williams <dan.j.williams@intel.com>
>
> In preparation for negotiating OS control of CXL _OSC features, do the
> minimal enabling to use CXL _OSC to handle the base PCIe feature
> negotiation. Recall that CXL _OSC is a super-set of PCIe _OSC and the
> CXL 2.0 specification mandates: "If a CXL Host Bridge device exposes CXL
> _OSC, CXL aware OSPM shall evaluate CXL _OSC and not evaluate PCIe
> _OSC."
>
> A new ->cxl_osc_disable attribute is added for cases where platform
> firmware publishes ACPI0016, but does not also publish CXL _OSC.
It's been a couple weeks since I wrote this... looking at it now I
would rewrite this to:
Rather than pass a boolean flag alongside @root to all the helper
functions that need to consider PCIe specifics, add is_pcie() and
is_cxl() helper functions to check the flavor of @root. This also
allows for dynamic fallback to PCIe _OSC in cases where an attempt to
use CXL _OXC fails. This can happen on CXL 1.1 platforms that publish
ACPI0016 devices to indicate CXL host bridges, but do not publish the
optional CXL _OSC method. CXL _OSC is mandatory for CXL 2.0 hosts.
>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: "Rafael J. Wysocki" <rafael@kernel.org>
> Cc: Robert Moore <robert.moore@intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Always include your own sign-off when forwarding a patch.
> ---
> include/acpi/acpi_bus.h | 1 +
> drivers/acpi/pci_root.c | 62 +++++++++++++++++++++++++++++++----------
> 2 files changed, 48 insertions(+), 15 deletions(-)
>
> diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h
> index ca88c4706f2b..768ef1584055 100644
> --- a/include/acpi/acpi_bus.h
> +++ b/include/acpi/acpi_bus.h
> @@ -585,6 +585,7 @@ struct acpi_pci_root {
> struct acpi_device * device;
> struct pci_bus *bus;
> u16 segment;
> + bool cxl_osc_disable;
> struct resource secondary; /* downstream bus range */
>
> u32 osc_support_set; /* _OSC state of support bits */
> diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
> index b76db99cced3..2d834504096b 100644
> --- a/drivers/acpi/pci_root.c
> +++ b/drivers/acpi/pci_root.c
> @@ -170,20 +170,47 @@ static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
> ARRAY_SIZE(pci_osc_control_bit));
> }
>
> -static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766";
> +static bool is_pcie(struct acpi_pci_root *root)
> +{
> + return strcmp(acpi_device_hid(root->device), "PNP0A08") == 0;
> +}
>
> -static acpi_status acpi_pci_run_osc(acpi_handle handle,
> +static bool is_cxl(struct acpi_pci_root *root)
> +{
> + if (root->cxl_osc_disable)
> + return false;
> + return strcmp(acpi_device_hid(root->device), "ACPI0016") == 0;
> +}
> +
> +static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766";
> +static u8 cxl_osc_uuid_str[] = "68F2D50B-C469-4d8A-BD3D-941A103FD3FC";
> +
> +static char *to_uuid(struct acpi_pci_root *root)
> +{
> + if (is_cxl(root))
> + return cxl_osc_uuid_str;
> + return pci_osc_uuid_str;
> +}
> +
> +static int cap_length(struct acpi_pci_root *root)
> +{
> + if (is_cxl(root))
> + return sizeof(u32) * 6;
> + return sizeof(u32) * 3;
> +}
> +
> +static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root,
> const u32 *capbuf, u32 *retval)
> {
> struct acpi_osc_context context = {
> - .uuid_str = pci_osc_uuid_str,
> + .uuid_str = to_uuid(root),
> .rev = 1,
> - .cap.length = 12,
> + .cap.length = cap_length(root),
> .cap.pointer = (void *)capbuf,
> };
> acpi_status status;
>
> - status = acpi_run_osc(handle, &context);
> + status = acpi_run_osc(root->device->handle, &context);
> if (ACPI_SUCCESS(status)) {
> *retval = *((u32 *)(context.ret.pointer + 8));
> kfree(context.ret.pointer);
> @@ -196,7 +223,7 @@ static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root,
> u32 *control)
> {
> acpi_status status;
> - u32 result, capbuf[3];
> + u32 result, capbuf[6];
>
> support |= root->osc_support_set;
>
> @@ -204,10 +231,18 @@ static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root,
> capbuf[OSC_SUPPORT_DWORD] = support;
> capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set;
>
> - status = acpi_pci_run_osc(root->device->handle, capbuf, &result);
> +retry:
> + status = acpi_pci_run_osc(root, capbuf, &result);
> if (ACPI_SUCCESS(status)) {
> root->osc_support_set = support;
> *control = result;
> + } else if (is_cxl(root)) {
> + /*
> + * CXL _OSC is optional on CXL 1.1 hosts. Fall back to PCIe _OSC
> + * upon any failure using CXL _OSC.
> + */
> + root->cxl_osc_disable = true;
> + goto retry;
> }
> return status;
> }
> @@ -338,7 +373,7 @@ static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 s
> u32 req = OSC_PCI_EXPRESS_CAPABILITY_CONTROL;
> struct acpi_pci_root *root;
> acpi_status status;
> - u32 ctrl, capbuf[3];
> + u32 ctrl, capbuf[6];
>
> if (!mask)
> return AE_BAD_PARAMETER;
> @@ -375,7 +410,7 @@ static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 s
> capbuf[OSC_QUERY_DWORD] = 0;
> capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set;
> capbuf[OSC_CONTROL_DWORD] = ctrl;
> - status = acpi_pci_run_osc(handle, capbuf, mask);
> + status = acpi_pci_run_osc(root, capbuf, mask);
> if (ACPI_FAILURE(status))
> return status;
>
> @@ -454,8 +489,7 @@ static bool os_control_query_checks(struct acpi_pci_root *root, u32 support)
> return true;
> }
>
> -static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
> - bool is_pcie)
> +static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)
> {
> u32 support, control = 0, requested = 0;
> acpi_status status;
> @@ -506,7 +540,7 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
> *no_aspm = 1;
>
> /* _OSC is optional for PCI host bridges */
> - if ((status == AE_NOT_FOUND) && !is_pcie)
> + if ((status == AE_NOT_FOUND) && !is_pcie(root))
> return;
>
> if (control) {
> @@ -529,7 +563,6 @@ static int acpi_pci_root_add(struct acpi_device *device,
> acpi_handle handle = device->handle;
> int no_aspm = 0;
> bool hotadd = system_state == SYSTEM_RUNNING;
> - bool is_pcie;
>
> root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL);
> if (!root)
> @@ -587,8 +620,7 @@ static int acpi_pci_root_add(struct acpi_device *device,
>
> root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle);
>
> - is_pcie = strcmp(acpi_device_hid(device), "PNP0A08") == 0;
> - negotiate_os_control(root, &no_aspm, is_pcie);
> + negotiate_os_control(root, &no_aspm);
>
> /*
> * TBD: Need PCI interface for enumeration/configuration of roots.
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RFC PATCH 2/2] acpi/pci_root: negotiate CXL _OSC
2022-03-17 0:27 ` [RFC PATCH 2/2] acpi/pci_root: negotiate CXL _OSC Vishal Verma
@ 2022-03-17 3:19 ` Dan Williams
2022-03-17 3:49 ` Verma, Vishal L
2022-03-17 16:10 ` Jonathan Cameron
1 sibling, 1 reply; 11+ messages in thread
From: Dan Williams @ 2022-03-17 3:19 UTC (permalink / raw)
To: Vishal Verma
Cc: linux-cxl, Linux ACPI, Jonathan Cameron, Rafael J. Wysocki,
Robert Moore, Bjorn Helgaas, Rafael J. Wysocki
On Wed, Mar 16, 2022 at 5:27 PM Vishal Verma <vishal.l.verma@intel.com> wrote:
>
> Add full support for negotiating _OSC as defined in the CXL 2.0 spec, as
> applicable to CXL-enabled platforms. Advertise support for the CXL
> features we support - 'CXL 2.0 port/device register access', 'Protocol
> Error Reporting', and 'CL Native Hot Plug'. Request control for 'CXL
> Memory Error Reporting'. The requests are dependent on CONFIG_* based
> pre-requisites, and prior PCI enabling, similar to how the standard PCI
> _OSC bits are determined.
Might want to add a clarification here of why this just reflects the
PCIe support into the similar CXL fields. For example:
The CXL specification does not define any additional constraints on
the hotplug flow beyond PCIe native hotplug, so a kernel that supports
native PCIe hotplug, supports CXL hotplug. For error handling protocol
and link errors just use PCIe AER. There is nascent support for
amending AER events with CXL specific status [1], but there's
otherwise no additional OS responsibility for CXL errors beyond PCIe
AER. CXL Memory Errors behave the same as typical memory errors so
CONFIG_MEMORY_FAILURE is sufficient to indicate support to platform
firmware.
[1]: https://lore.kernel.org/linux-cxl/164740402242.3912056.8303625392871313860.stgit@dwillia2-desk3.amr.corp.intel.com/
>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: "Rafael J. Wysocki" <rafael@kernel.org>
> Cc: Robert Moore <robert.moore@intel.com>
> Cc: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
> ---
> include/linux/acpi.h | 11 +++
> include/acpi/acpi_bus.h | 6 +-
> drivers/acpi/pci_root.c | 147 ++++++++++++++++++++++++++++++++++------
> 3 files changed, 143 insertions(+), 21 deletions(-)
>
> diff --git a/include/linux/acpi.h b/include/linux/acpi.h
> index 6274758648e3..1717ccc265d7 100644
> --- a/include/linux/acpi.h
> +++ b/include/linux/acpi.h
> @@ -554,6 +554,8 @@ acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context);
> #define OSC_QUERY_DWORD 0 /* DWORD 1 */
> #define OSC_SUPPORT_DWORD 1 /* DWORD 2 */
> #define OSC_CONTROL_DWORD 2 /* DWORD 3 */
> +#define OSC_CXL_SUPPORT_DWORD 3 /* DWORD 4 */
> +#define OSC_CXL_CONTROL_DWORD 4 /* DWORD 5 */
>
> /* _OSC Capabilities DWORD 1: Query/Control and Error Returns (generic) */
> #define OSC_QUERY_ENABLE 0x00000001 /* input */
> @@ -607,6 +609,15 @@ extern u32 osc_sb_native_usb4_control;
> #define OSC_PCI_EXPRESS_LTR_CONTROL 0x00000020
> #define OSC_PCI_EXPRESS_DPC_CONTROL 0x00000080
>
> +/* CXL _OSC: Capabilities DWORD 4: Support Field */
> +#define OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT 0x00000001
> +#define OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT 0x00000002
> +#define OSC_CXL_PER_SUPPORT 0x00000004
> +#define OSC_CXL_NATIVE_HP_SUPPORT 0x00000008
> +
> +/* CXL _OSC: Capabilities DWORD 5: Control Field */
> +#define OSC_CXL_ERROR_REPORTING_CONTROL 0x00000001
> +
> #define ACPI_GSB_ACCESS_ATTRIB_QUICK 0x00000002
> #define ACPI_GSB_ACCESS_ATTRIB_SEND_RCV 0x00000004
> #define ACPI_GSB_ACCESS_ATTRIB_BYTE 0x00000006
> diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h
> index 768ef1584055..5776d4c1509a 100644
> --- a/include/acpi/acpi_bus.h
> +++ b/include/acpi/acpi_bus.h
> @@ -588,8 +588,10 @@ struct acpi_pci_root {
> bool cxl_osc_disable;
> struct resource secondary; /* downstream bus range */
>
> - u32 osc_support_set; /* _OSC state of support bits */
> - u32 osc_control_set; /* _OSC state of control bits */
> + u32 osc_support_set; /* _OSC state of support bits */
> + u32 osc_control_set; /* _OSC state of control bits */
> + u32 cxl_osc_support_set; /* _OSC state of CXL support bits */
> + u32 cxl_osc_control_set; /* _OSC state of CXL control bits */
> phys_addr_t mcfg_addr;
> };
>
> diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
> index 2d834504096b..c916318b11a0 100644
> --- a/drivers/acpi/pci_root.c
> +++ b/drivers/acpi/pci_root.c
> @@ -142,6 +142,17 @@ static struct pci_osc_bit_struct pci_osc_control_bit[] = {
> { OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" },
> };
>
> +static struct pci_osc_bit_struct cxl_osc_support_bit[] = {
> + { OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT, "CXL11PortRegAccess" },
> + { OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT, "CXL20PortDevRegAccess" },
> + { OSC_CXL_PER_SUPPORT, "CXLProtocolErrorReporting" },
> + { OSC_CXL_NATIVE_HP_SUPPORT, "CXLNativeHotPlug" },
> +};
> +
> +static struct pci_osc_bit_struct cxl_osc_control_bit[] = {
> + { OSC_CXL_ERROR_REPORTING_CONTROL, "CXLMemErrorReporting" },
> +};
> +
> static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word,
> struct pci_osc_bit_struct *table, int size)
> {
> @@ -170,6 +181,18 @@ static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
> ARRAY_SIZE(pci_osc_control_bit));
> }
>
> +static void decode_cxl_osc_support(struct acpi_pci_root *root, char *msg, u32 word)
> +{
> + decode_osc_bits(root, msg, word, cxl_osc_support_bit,
> + ARRAY_SIZE(cxl_osc_support_bit));
> +}
> +
> +static void decode_cxl_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
> +{
> + decode_osc_bits(root, msg, word, cxl_osc_control_bit,
> + ARRAY_SIZE(cxl_osc_control_bit));
> +}
> +
> static bool is_pcie(struct acpi_pci_root *root)
> {
> return strcmp(acpi_device_hid(root->device), "PNP0A08") == 0;
> @@ -199,8 +222,19 @@ static int cap_length(struct acpi_pci_root *root)
> return sizeof(u32) * 3;
> }
>
> +static u32 acpi_osc_ctx_get_pci_control(struct acpi_osc_context *context)
> +{
> + return *((u32 *)(context->ret.pointer + 8));
> +}
> +
> +static u32 acpi_osc_ctx_get_cxl_control(struct acpi_osc_context *context)
> +{
> + return *((u32 *)(context->ret.pointer + 16));
> +}
> +
> static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root,
> - const u32 *capbuf, u32 *retval)
> + const u32 *capbuf, u32 *pci_control,
> + u32 *cxl_control)
> {
> struct acpi_osc_context context = {
> .uuid_str = to_uuid(root),
> @@ -212,18 +246,20 @@ static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root,
>
> status = acpi_run_osc(root->device->handle, &context);
> if (ACPI_SUCCESS(status)) {
> - *retval = *((u32 *)(context.ret.pointer + 8));
> + *pci_control = acpi_osc_ctx_get_pci_control(&context);
> + if (is_cxl(root))
> + *cxl_control = acpi_osc_ctx_get_cxl_control(&context);
> kfree(context.ret.pointer);
> }
> return status;
> }
>
> -static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root,
> - u32 support,
> - u32 *control)
> +static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, u32 support,
> + u32 *control, u32 cxl_support,
> + u32 *cxl_control)
> {
> acpi_status status;
> - u32 result, capbuf[6];
> + u32 pci_result, cxl_result, capbuf[8];
>
> support |= root->osc_support_set;
>
> @@ -231,11 +267,21 @@ static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root,
> capbuf[OSC_SUPPORT_DWORD] = support;
> capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set;
>
> + if (is_cxl(root)) {
> + cxl_support |= root->cxl_osc_support_set;
> + capbuf[OSC_CXL_SUPPORT_DWORD] = cxl_support;
> + capbuf[OSC_CXL_CONTROL_DWORD] = *cxl_control | root->cxl_osc_control_set;
> + }
> +
> retry:
> - status = acpi_pci_run_osc(root, capbuf, &result);
> + status = acpi_pci_run_osc(root, capbuf, &pci_result, &cxl_result);
> if (ACPI_SUCCESS(status)) {
> root->osc_support_set = support;
> - *control = result;
> + *control = pci_result;
> + if (is_cxl(root)) {
> + root->cxl_osc_support_set = cxl_support;
> + *cxl_control = cxl_result;
> + }
> } else if (is_cxl(root)) {
> /*
> * CXL _OSC is optional on CXL 1.1 hosts. Fall back to PCIe _OSC
> @@ -358,6 +404,8 @@ EXPORT_SYMBOL_GPL(acpi_get_pci_dev);
> * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex).
> * @mask: Mask of _OSC bits to request control of, place to store control mask.
> * @support: _OSC supported capability.
> + * @cxl_mask: Mask of CXL _OSC control bits, place to store control mask.
> + * @cxl_support: CXL _OSC supported capability.
> *
> * Run _OSC query for @mask and if that is successful, compare the returned
> * mask of control bits with @req. If all of the @req bits are set in the
> @@ -368,12 +416,14 @@ EXPORT_SYMBOL_GPL(acpi_get_pci_dev);
> * _OSC bits the BIOS has granted control of, but its contents are meaningless
> * on failure.
> **/
> -static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 support)
> +static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask,
> + u32 support, u32 *cxl_mask,
> + u32 cxl_support)
> {
> u32 req = OSC_PCI_EXPRESS_CAPABILITY_CONTROL;
> struct acpi_pci_root *root;
> acpi_status status;
> - u32 ctrl, capbuf[6];
> + u32 ctrl, cxl_ctrl, capbuf[8];
>
> if (!mask)
> return AE_BAD_PARAMETER;
> @@ -385,20 +435,35 @@ static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 s
> ctrl = *mask;
> *mask |= root->osc_control_set;
>
> + if (is_cxl(root)) {
> + cxl_ctrl = *cxl_mask;
> + *mask |= root->osc_control_set;
> + }
> +
> /* Need to check the available controls bits before requesting them. */
> do {
> - status = acpi_pci_query_osc(root, support, mask);
> + status = acpi_pci_query_osc(root, support, mask, cxl_support,
> + cxl_mask);
> if (ACPI_FAILURE(status))
> return status;
> - if (ctrl == *mask)
> - break;
> - decode_osc_control(root, "platform does not support",
> - ctrl & ~(*mask));
> + if (is_cxl(root)) {
> + if ((ctrl == *mask) && (cxl_ctrl == *cxl_mask))
> + break;
> + decode_cxl_osc_control(root, "platform does not support",
> + cxl_ctrl & ~(*cxl_mask));
> + } else {
> + if (ctrl == *mask)
> + break;
> + decode_osc_control(root, "platform does not support",
> + ctrl & ~(*mask));
> + }
> ctrl = *mask;
> - } while (*mask);
> + cxl_ctrl = *cxl_mask;
> + } while (*mask || *cxl_mask);
>
> /* No need to request _OSC if the control was already granted. */
> - if ((root->osc_control_set & ctrl) == ctrl)
> + if (((root->osc_control_set & ctrl) == ctrl) &&
> + ((root->cxl_osc_control_set & cxl_ctrl) == cxl_ctrl))
> return AE_OK;
>
> if ((ctrl & req) != req) {
> @@ -410,11 +475,17 @@ static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 s
> capbuf[OSC_QUERY_DWORD] = 0;
> capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set;
> capbuf[OSC_CONTROL_DWORD] = ctrl;
> - status = acpi_pci_run_osc(root, capbuf, mask);
> + if (is_cxl(root)) {
> + capbuf[OSC_CXL_SUPPORT_DWORD] = root->cxl_osc_support_set;
> + capbuf[OSC_CXL_CONTROL_DWORD] = cxl_ctrl;
> + }
> +
> + status = acpi_pci_run_osc(root, capbuf, mask, cxl_mask);
> if (ACPI_FAILURE(status))
> return status;
>
> root->osc_control_set = *mask;
> + root->cxl_osc_control_set = *cxl_mask;
> return AE_OK;
> }
>
> @@ -440,6 +511,18 @@ static u32 calculate_support(void)
> return support;
> }
>
> +static u32 calculate_cxl_support(void)
> +{
> + u32 support;
> +
> + support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT;
> + support |= OSC_CXL_PER_SUPPORT;
I would expect this one to be gated by pci_aer_available() since these
errors are reported by PCIe AER.
Perhaps also s/PER/PORT_ERROR/? I keep reading PER like 'per' as in 'per-cpu'.
> + if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
> + support |= OSC_CXL_NATIVE_HP_SUPPORT;
> +
> + return support;
> +}
> +
> static u32 calculate_control(void)
> {
> u32 control;
> @@ -471,6 +554,16 @@ static u32 calculate_control(void)
> return control;
> }
>
> +static u32 calculate_cxl_control(void)
> +{
> + u32 control;
> +
> + if (pci_aer_available())
> + control |= OSC_CXL_ERROR_REPORTING_CONTROL;
In this case the error handling is for memory errors, so this one should be:
if (IS_ENABLED(CONFIG_MEMORY_FAILURE))
control |= OSC_CXL_ERROR_REPORTING_CONTROL;
...other than that looks good to me.
> +
> + return control;
> +}
> +
> static bool os_control_query_checks(struct acpi_pci_root *root, u32 support)
> {
> struct acpi_device *device = root->device;
> @@ -492,6 +585,7 @@ static bool os_control_query_checks(struct acpi_pci_root *root, u32 support)
> static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)
> {
> u32 support, control = 0, requested = 0;
> + u32 cxl_support, cxl_control = 0, cxl_requested = 0;
> acpi_status status;
> struct acpi_device *device = root->device;
> acpi_handle handle = device->handle;
> @@ -515,10 +609,20 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)
> if (os_control_query_checks(root, support))
> requested = control = calculate_control();
>
> - status = acpi_pci_osc_control_set(handle, &control, support);
> + if (is_cxl(root)) {
> + cxl_support = calculate_cxl_support();
> + decode_cxl_osc_support(root, "OS supports", cxl_support);
> + cxl_requested = cxl_control = calculate_cxl_control();
> + }
> +
> + status = acpi_pci_osc_control_set(handle, &control, support,
> + &cxl_control, cxl_support);
> if (ACPI_SUCCESS(status)) {
> if (control)
> decode_osc_control(root, "OS now controls", control);
> + if (cxl_control)
> + decode_cxl_osc_control(root, "OS now controls",
> + cxl_control);
>
> if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
> /*
> @@ -547,6 +651,11 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)
> decode_osc_control(root, "OS requested", requested);
> decode_osc_control(root, "platform willing to grant", control);
> }
> + if (cxl_control) {
> + decode_cxl_osc_control(root, "OS requested", cxl_requested);
> + decode_cxl_osc_control(root, "platform willing to grant",
> + cxl_control);
> + }
>
> dev_info(&device->dev, "_OSC: platform retains control of PCIe features (%s)\n",
> acpi_format_exception(status));
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RFC PATCH 2/2] acpi/pci_root: negotiate CXL _OSC
2022-03-17 3:19 ` Dan Williams
@ 2022-03-17 3:49 ` Verma, Vishal L
0 siblings, 0 replies; 11+ messages in thread
From: Verma, Vishal L @ 2022-03-17 3:49 UTC (permalink / raw)
To: Williams, Dan J
Cc: rafael, Moore, Robert, linux-cxl, Jonathan.Cameron, Wysocki,
Rafael J, bhelgaas, linux-acpi
On Wed, 2022-03-16 at 20:19 -0700, Dan Williams wrote:
> On Wed, Mar 16, 2022 at 5:27 PM Vishal Verma <vishal.l.verma@intel.com> wrote:
> >
> > Add full support for negotiating _OSC as defined in the CXL 2.0 spec, as
> > applicable to CXL-enabled platforms. Advertise support for the CXL
> > features we support - 'CXL 2.0 port/device register access', 'Protocol
> > Error Reporting', and 'CL Native Hot Plug'. Request control for 'CXL
> > Memory Error Reporting'. The requests are dependent on CONFIG_* based
> > pre-requisites, and prior PCI enabling, similar to how the standard PCI
> > _OSC bits are determined.
>
> Might want to add a clarification here of why this just reflects the
> PCIe support into the similar CXL fields. For example:
>
> The CXL specification does not define any additional constraints on
> the hotplug flow beyond PCIe native hotplug, so a kernel that supports
> native PCIe hotplug, supports CXL hotplug. For error handling protocol
> and link errors just use PCIe AER. There is nascent support for
> amending AER events with CXL specific status [1], but there's
> otherwise no additional OS responsibility for CXL errors beyond PCIe
> AER. CXL Memory Errors behave the same as typical memory errors so
> CONFIG_MEMORY_FAILURE is sufficient to indicate support to platform
> firmware.
>
> [1]: https://lore.kernel.org/linux-cxl/164740402242.3912056.8303625392871313860.stgit@dwillia2-desk3.amr.corp.intel.com/
Yes that sounds good, will add.
> >
[..]
> > @@ -440,6 +511,18 @@ static u32 calculate_support(void)
> > return support;
> > }
> >
> > +static u32 calculate_cxl_support(void)
> > +{
> > + u32 support;
> > +
> > + support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT;
> > + support |= OSC_CXL_PER_SUPPORT;
>
> I would expect this one to be gated by pci_aer_available() since these
> errors are reported by PCIe AER.
>
> Perhaps also s/PER/PORT_ERROR/? I keep reading PER like 'per' as in 'per-cpu'.
Expanding the acronym sounds good, though it is Protocol Error
Reporting, not Port.
>
> > + if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
> > + support |= OSC_CXL_NATIVE_HP_SUPPORT;
> > +
> > + return support;
> > +}
> > +
> > static u32 calculate_control(void)
> > {
> > u32 control;
> > @@ -471,6 +554,16 @@ static u32 calculate_control(void)
> > return control;
> > }
> >
> > +static u32 calculate_cxl_control(void)
> > +{
> > + u32 control;
> > +
> > + if (pci_aer_available())
> > + control |= OSC_CXL_ERROR_REPORTING_CONTROL;
>
> In this case the error handling is for memory errors, so this one should be:
>
> if (IS_ENABLED(CONFIG_MEMORY_FAILURE))
> control |= OSC_CXL_ERROR_REPORTING_CONTROL;
Makes sense, I'll change to this.
>
> ...other than that looks good to me.
Thanks for the review!
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RFC PATCH 0/2] acpi: add support for CXL _OSC
2022-03-17 0:27 [RFC PATCH 0/2] acpi: add support for CXL _OSC Vishal Verma
2022-03-17 0:27 ` [RFC PATCH 1/2] PCI/ACPI: Use CXL _OSC instead of PCIe _OSC Vishal Verma
2022-03-17 0:27 ` [RFC PATCH 2/2] acpi/pci_root: negotiate CXL _OSC Vishal Verma
@ 2022-03-17 15:19 ` Jonathan Cameron
2022-03-18 19:52 ` Verma, Vishal L
2 siblings, 1 reply; 11+ messages in thread
From: Jonathan Cameron @ 2022-03-17 15:19 UTC (permalink / raw)
To: Vishal Verma
Cc: linux-cxl, linux-acpi, Dan Williams, Rafael J. Wysocki,
Robert Moore, Bjorn Helgaas
On Wed, 16 Mar 2022 18:27:02 -0600
Vishal Verma <vishal.l.verma@intel.com> wrote:
> Add support for using the CXL definition of _OSC where applicable, and
> negotiating CXL specific support and control bits.
>
> Patch 1 adds the new CXL _OSC UUID, and uses it instead of the PCI UUID
> when a root port is CXL enabled. It provides a fallback method for
> CXL-1.1 devices that may not implement the CXL-2.0 _OSC.
_OSC is implemented by the firmware of a host not the device so perhaps
rephrase this.
>
> Patch 2 performs negotiation for the CXL specific _OSC support and
> control bits.
>
> I've tested these against a custom qemu[1], which adds the CXL _OSC (in
> addition to other CXL support). Specifically, _OSC support is added
> here[2].
>
> [1]: https://gitlab.com/jic23/qemu/-/tree/cxl-v7-draft-2-for-test
> [2]: https://gitlab.com/jic23/qemu/-/commit/31c85054b84645dfbd9e9bb14aa35286141c14cf
Glad that worked :) I was wondering if it was correct.
There are some issues with that code raised in a recent review, so good
to have this to test against it going forwards.
Thanks,
Jonathan
>
> Dan Williams (1):
> PCI/ACPI: Use CXL _OSC instead of PCIe _OSC
>
> Vishal Verma (1):
> acpi/pci_root: negotiate CXL _OSC
>
> include/linux/acpi.h | 11 +++
> include/acpi/acpi_bus.h | 7 +-
> drivers/acpi/pci_root.c | 201 ++++++++++++++++++++++++++++++++++------
> 3 files changed, 187 insertions(+), 32 deletions(-)
>
>
> base-commit: 74be98774dfbc5b8b795db726bd772e735d2edd4
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RFC PATCH 1/2] PCI/ACPI: Use CXL _OSC instead of PCIe _OSC
2022-03-17 1:47 ` Dan Williams
@ 2022-03-17 15:40 ` Jonathan Cameron
0 siblings, 0 replies; 11+ messages in thread
From: Jonathan Cameron @ 2022-03-17 15:40 UTC (permalink / raw)
To: Dan Williams
Cc: Vishal Verma, linux-cxl, Linux ACPI, Rafael J. Wysocki,
Robert Moore, Bjorn Helgaas, Rafael J. Wysocki
On Wed, 16 Mar 2022 18:47:11 -0700
Dan Williams <dan.j.williams@intel.com> wrote:
> On Wed, Mar 16, 2022 at 5:27 PM Vishal Verma <vishal.l.verma@intel.com> wrote:
> >
> > From: Dan Williams <dan.j.williams@intel.com>
> >
> > In preparation for negotiating OS control of CXL _OSC features, do the
> > minimal enabling to use CXL _OSC to handle the base PCIe feature
> > negotiation. Recall that CXL _OSC is a super-set of PCIe _OSC and the
> > CXL 2.0 specification mandates: "If a CXL Host Bridge device exposes CXL
> > _OSC, CXL aware OSPM shall evaluate CXL _OSC and not evaluate PCIe
> > _OSC."
> >
> > A new ->cxl_osc_disable attribute is added for cases where platform
> > firmware publishes ACPI0016, but does not also publish CXL _OSC.
>
> It's been a couple weeks since I wrote this... looking at it now I
> would rewrite this to:
>
> Rather than pass a boolean flag alongside @root to all the helper
> functions that need to consider PCIe specifics, add is_pcie() and
> is_cxl() helper functions to check the flavor of @root. This also
> allows for dynamic fallback to PCIe _OSC in cases where an attempt to
> use CXL _OXC fails. This can happen on CXL 1.1 platforms that publish
> ACPI0016 devices to indicate CXL host bridges, but do not publish the
> optional CXL _OSC method. CXL _OSC is mandatory for CXL 2.0 hosts.
>
> >
> > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > Cc: "Rafael J. Wysocki" <rafael@kernel.org>
> > Cc: Robert Moore <robert.moore@intel.com>
> > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
>
> Always include your own sign-off when forwarding a patch.
>
Subject to Dan's rewording above, this looks good to me.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> > ---
> > include/acpi/acpi_bus.h | 1 +
> > drivers/acpi/pci_root.c | 62 +++++++++++++++++++++++++++++++----------
> > 2 files changed, 48 insertions(+), 15 deletions(-)
> >
> > diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h
> > index ca88c4706f2b..768ef1584055 100644
> > --- a/include/acpi/acpi_bus.h
> > +++ b/include/acpi/acpi_bus.h
> > @@ -585,6 +585,7 @@ struct acpi_pci_root {
> > struct acpi_device * device;
> > struct pci_bus *bus;
> > u16 segment;
> > + bool cxl_osc_disable;
> > struct resource secondary; /* downstream bus range */
> >
> > u32 osc_support_set; /* _OSC state of support bits */
> > diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
> > index b76db99cced3..2d834504096b 100644
> > --- a/drivers/acpi/pci_root.c
> > +++ b/drivers/acpi/pci_root.c
> > @@ -170,20 +170,47 @@ static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
> > ARRAY_SIZE(pci_osc_control_bit));
> > }
> >
> > -static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766";
> > +static bool is_pcie(struct acpi_pci_root *root)
> > +{
> > + return strcmp(acpi_device_hid(root->device), "PNP0A08") == 0;
> > +}
> >
> > -static acpi_status acpi_pci_run_osc(acpi_handle handle,
> > +static bool is_cxl(struct acpi_pci_root *root)
> > +{
> > + if (root->cxl_osc_disable)
> > + return false;
> > + return strcmp(acpi_device_hid(root->device), "ACPI0016") == 0;
> > +}
> > +
> > +static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766";
> > +static u8 cxl_osc_uuid_str[] = "68F2D50B-C469-4d8A-BD3D-941A103FD3FC";
> > +
> > +static char *to_uuid(struct acpi_pci_root *root)
> > +{
> > + if (is_cxl(root))
> > + return cxl_osc_uuid_str;
> > + return pci_osc_uuid_str;
> > +}
> > +
> > +static int cap_length(struct acpi_pci_root *root)
> > +{
> > + if (is_cxl(root))
> > + return sizeof(u32) * 6;
> > + return sizeof(u32) * 3;
> > +}
> > +
> > +static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root,
> > const u32 *capbuf, u32 *retval)
> > {
> > struct acpi_osc_context context = {
> > - .uuid_str = pci_osc_uuid_str,
> > + .uuid_str = to_uuid(root),
> > .rev = 1,
> > - .cap.length = 12,
> > + .cap.length = cap_length(root),
> > .cap.pointer = (void *)capbuf,
> > };
> > acpi_status status;
> >
> > - status = acpi_run_osc(handle, &context);
> > + status = acpi_run_osc(root->device->handle, &context);
> > if (ACPI_SUCCESS(status)) {
> > *retval = *((u32 *)(context.ret.pointer + 8));
> > kfree(context.ret.pointer);
> > @@ -196,7 +223,7 @@ static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root,
> > u32 *control)
> > {
> > acpi_status status;
> > - u32 result, capbuf[3];
> > + u32 result, capbuf[6];
> >
> > support |= root->osc_support_set;
> >
> > @@ -204,10 +231,18 @@ static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root,
> > capbuf[OSC_SUPPORT_DWORD] = support;
> > capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set;
> >
> > - status = acpi_pci_run_osc(root->device->handle, capbuf, &result);
> > +retry:
> > + status = acpi_pci_run_osc(root, capbuf, &result);
> > if (ACPI_SUCCESS(status)) {
> > root->osc_support_set = support;
> > *control = result;
> > + } else if (is_cxl(root)) {
> > + /*
> > + * CXL _OSC is optional on CXL 1.1 hosts. Fall back to PCIe _OSC
> > + * upon any failure using CXL _OSC.
> > + */
> > + root->cxl_osc_disable = true;
> > + goto retry;
> > }
> > return status;
> > }
> > @@ -338,7 +373,7 @@ static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 s
> > u32 req = OSC_PCI_EXPRESS_CAPABILITY_CONTROL;
> > struct acpi_pci_root *root;
> > acpi_status status;
> > - u32 ctrl, capbuf[3];
> > + u32 ctrl, capbuf[6];
> >
> > if (!mask)
> > return AE_BAD_PARAMETER;
> > @@ -375,7 +410,7 @@ static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 s
> > capbuf[OSC_QUERY_DWORD] = 0;
> > capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set;
> > capbuf[OSC_CONTROL_DWORD] = ctrl;
> > - status = acpi_pci_run_osc(handle, capbuf, mask);
> > + status = acpi_pci_run_osc(root, capbuf, mask);
> > if (ACPI_FAILURE(status))
> > return status;
> >
> > @@ -454,8 +489,7 @@ static bool os_control_query_checks(struct acpi_pci_root *root, u32 support)
> > return true;
> > }
> >
> > -static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
> > - bool is_pcie)
> > +static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)
> > {
> > u32 support, control = 0, requested = 0;
> > acpi_status status;
> > @@ -506,7 +540,7 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
> > *no_aspm = 1;
> >
> > /* _OSC is optional for PCI host bridges */
> > - if ((status == AE_NOT_FOUND) && !is_pcie)
> > + if ((status == AE_NOT_FOUND) && !is_pcie(root))
> > return;
> >
> > if (control) {
> > @@ -529,7 +563,6 @@ static int acpi_pci_root_add(struct acpi_device *device,
> > acpi_handle handle = device->handle;
> > int no_aspm = 0;
> > bool hotadd = system_state == SYSTEM_RUNNING;
> > - bool is_pcie;
> >
> > root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL);
> > if (!root)
> > @@ -587,8 +620,7 @@ static int acpi_pci_root_add(struct acpi_device *device,
> >
> > root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle);
> >
> > - is_pcie = strcmp(acpi_device_hid(device), "PNP0A08") == 0;
> > - negotiate_os_control(root, &no_aspm, is_pcie);
> > + negotiate_os_control(root, &no_aspm);
> >
> > /*
> > * TBD: Need PCI interface for enumeration/configuration of roots.
> > --
> > 2.35.1
> >
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RFC PATCH 2/2] acpi/pci_root: negotiate CXL _OSC
2022-03-17 0:27 ` [RFC PATCH 2/2] acpi/pci_root: negotiate CXL _OSC Vishal Verma
2022-03-17 3:19 ` Dan Williams
@ 2022-03-17 16:10 ` Jonathan Cameron
2022-03-18 21:16 ` Verma, Vishal L
1 sibling, 1 reply; 11+ messages in thread
From: Jonathan Cameron @ 2022-03-17 16:10 UTC (permalink / raw)
To: Vishal Verma
Cc: linux-cxl, linux-acpi, Dan Williams, Rafael J. Wysocki,
Robert Moore, Bjorn Helgaas, Rafael J. Wysocki
On Wed, 16 Mar 2022 18:27:04 -0600
Vishal Verma <vishal.l.verma@intel.com> wrote:
> Add full support for negotiating _OSC as defined in the CXL 2.0 spec, as
> applicable to CXL-enabled platforms. Advertise support for the CXL
> features we support - 'CXL 2.0 port/device register access', 'Protocol
> Error Reporting', and 'CL Native Hot Plug'. Request control for 'CXL
> Memory Error Reporting'. The requests are dependent on CONFIG_* based
> pre-requisites, and prior PCI enabling, similar to how the standard PCI
> _OSC bits are determined.
>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: "Rafael J. Wysocki" <rafael@kernel.org>
> Cc: Robert Moore <robert.moore@intel.com>
> Cc: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
Hi Vishal,
A few minor queries inline.
Jonathan
> ---
> include/linux/acpi.h | 11 +++
> include/acpi/acpi_bus.h | 6 +-
> drivers/acpi/pci_root.c | 147 ++++++++++++++++++++++++++++++++++------
> 3 files changed, 143 insertions(+), 21 deletions(-)
>
> diff --git a/include/linux/acpi.h b/include/linux/acpi.h
> index 6274758648e3..1717ccc265d7 100644
> --- a/include/linux/acpi.h
> +++ b/include/linux/acpi.h
> @@ -554,6 +554,8 @@ acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context);
> #define OSC_QUERY_DWORD 0 /* DWORD 1 */
> #define OSC_SUPPORT_DWORD 1 /* DWORD 2 */
> #define OSC_CONTROL_DWORD 2 /* DWORD 3 */
> +#define OSC_CXL_SUPPORT_DWORD 3 /* DWORD 4 */
> +#define OSC_CXL_CONTROL_DWORD 4 /* DWORD 5 */
>
> /* _OSC Capabilities DWORD 1: Query/Control and Error Returns (generic) */
> #define OSC_QUERY_ENABLE 0x00000001 /* input */
> @@ -607,6 +609,15 @@ extern u32 osc_sb_native_usb4_control;
> #define OSC_PCI_EXPRESS_LTR_CONTROL 0x00000020
> #define OSC_PCI_EXPRESS_DPC_CONTROL 0x00000080
>
> +/* CXL _OSC: Capabilities DWORD 4: Support Field */
> +#define OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT 0x00000001
> +#define OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT 0x00000002
> +#define OSC_CXL_PER_SUPPORT 0x00000004
> +#define OSC_CXL_NATIVE_HP_SUPPORT 0x00000008
> +
> +/* CXL _OSC: Capabilities DWORD 5: Control Field */
> +#define OSC_CXL_ERROR_REPORTING_CONTROL 0x00000001
> +
> #define ACPI_GSB_ACCESS_ATTRIB_QUICK 0x00000002
> #define ACPI_GSB_ACCESS_ATTRIB_SEND_RCV 0x00000004
> #define ACPI_GSB_ACCESS_ATTRIB_BYTE 0x00000006
> diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h
> index 768ef1584055..5776d4c1509a 100644
> --- a/include/acpi/acpi_bus.h
> +++ b/include/acpi/acpi_bus.h
> @@ -588,8 +588,10 @@ struct acpi_pci_root {
> bool cxl_osc_disable;
> struct resource secondary; /* downstream bus range */
>
> - u32 osc_support_set; /* _OSC state of support bits */
> - u32 osc_control_set; /* _OSC state of control bits */
> + u32 osc_support_set; /* _OSC state of support bits */
> + u32 osc_control_set; /* _OSC state of control bits */
> + u32 cxl_osc_support_set; /* _OSC state of CXL support bits */
> + u32 cxl_osc_control_set; /* _OSC state of CXL control bits */
> phys_addr_t mcfg_addr;
> };
>
> diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
> index 2d834504096b..c916318b11a0 100644
> --- a/drivers/acpi/pci_root.c
> +++ b/drivers/acpi/pci_root.c
> @@ -142,6 +142,17 @@ static struct pci_osc_bit_struct pci_osc_control_bit[] = {
> { OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" },
> };
>
> +static struct pci_osc_bit_struct cxl_osc_support_bit[] = {
> + { OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT, "CXL11PortRegAccess" },
> + { OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT, "CXL20PortDevRegAccess" },
> + { OSC_CXL_PER_SUPPORT, "CXLProtocolErrorReporting" },
> + { OSC_CXL_NATIVE_HP_SUPPORT, "CXLNativeHotPlug" },
> +};
> +
> +static struct pci_osc_bit_struct cxl_osc_control_bit[] = {
> + { OSC_CXL_ERROR_REPORTING_CONTROL, "CXLMemErrorReporting" },
> +};
> +
> static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word,
> struct pci_osc_bit_struct *table, int size)
> {
> @@ -170,6 +181,18 @@ static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
> ARRAY_SIZE(pci_osc_control_bit));
> }
>
> +static void decode_cxl_osc_support(struct acpi_pci_root *root, char *msg, u32 word)
> +{
> + decode_osc_bits(root, msg, word, cxl_osc_support_bit,
> + ARRAY_SIZE(cxl_osc_support_bit));
> +}
> +
> +static void decode_cxl_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
> +{
> + decode_osc_bits(root, msg, word, cxl_osc_control_bit,
> + ARRAY_SIZE(cxl_osc_control_bit));
> +}
> +
> static bool is_pcie(struct acpi_pci_root *root)
> {
> return strcmp(acpi_device_hid(root->device), "PNP0A08") == 0;
> @@ -199,8 +222,19 @@ static int cap_length(struct acpi_pci_root *root)
> return sizeof(u32) * 3;
> }
>
> +static u32 acpi_osc_ctx_get_pci_control(struct acpi_osc_context *context)
> +{
> + return *((u32 *)(context->ret.pointer + 8));
Use the defines for the offsets? sizeof(u32) * OSC_CONTROL_DWORD for example
> +}
> +
> +static u32 acpi_osc_ctx_get_cxl_control(struct acpi_osc_context *context)
> +{
> + return *((u32 *)(context->ret.pointer + 16));
As above + sizeof(u32) * OSC_CXL_CONTROL_DWORD)
> +}
> +
> static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root,
> - const u32 *capbuf, u32 *retval)
> + const u32 *capbuf, u32 *pci_control,
> + u32 *cxl_control)
> {
> struct acpi_osc_context context = {
> .uuid_str = to_uuid(root),
> @@ -212,18 +246,20 @@ static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root,
>
> status = acpi_run_osc(root->device->handle, &context);
> if (ACPI_SUCCESS(status)) {
> - *retval = *((u32 *)(context.ret.pointer + 8));
> + *pci_control = acpi_osc_ctx_get_pci_control(&context);
> + if (is_cxl(root))
> + *cxl_control = acpi_osc_ctx_get_cxl_control(&context);
> kfree(context.ret.pointer);
> }
> return status;
> }
>
> -static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root,
> - u32 support,
> - u32 *control)
> +static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, u32 support,
> + u32 *control, u32 cxl_support,
> + u32 *cxl_control)
> {
> acpi_status status;
> - u32 result, capbuf[6];
> + u32 pci_result, cxl_result, capbuf[8];
Nice to set capbuf size off one of the defines if possible, though I'm not
sure why it is 8 (or why it was 6 before for that mater). I think it should be 5.
>
> support |= root->osc_support_set;
>
> @@ -231,11 +267,21 @@ static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root,
> capbuf[OSC_SUPPORT_DWORD] = support;
> capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set;
>
> + if (is_cxl(root)) {
> + cxl_support |= root->cxl_osc_support_set;
> + capbuf[OSC_CXL_SUPPORT_DWORD] = cxl_support;
> + capbuf[OSC_CXL_CONTROL_DWORD] = *cxl_control | root->cxl_osc_control_set;
> + }
> +
> retry:
> - status = acpi_pci_run_osc(root, capbuf, &result);
> + status = acpi_pci_run_osc(root, capbuf, &pci_result, &cxl_result);
> if (ACPI_SUCCESS(status)) {
> root->osc_support_set = support;
> - *control = result;
> + *control = pci_result;
> + if (is_cxl(root)) {
> + root->cxl_osc_support_set = cxl_support;
> + *cxl_control = cxl_result;
> + }
> } else if (is_cxl(root)) {
> /*
> * CXL _OSC is optional on CXL 1.1 hosts. Fall back to PCIe _OSC
> @@ -358,6 +404,8 @@ EXPORT_SYMBOL_GPL(acpi_get_pci_dev);
> * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex).
> * @mask: Mask of _OSC bits to request control of, place to store control mask.
> * @support: _OSC supported capability.
> + * @cxl_mask: Mask of CXL _OSC control bits, place to store control mask.
> + * @cxl_support: CXL _OSC supported capability.
> *
> * Run _OSC query for @mask and if that is successful, compare the returned
> * mask of control bits with @req. If all of the @req bits are set in the
> @@ -368,12 +416,14 @@ EXPORT_SYMBOL_GPL(acpi_get_pci_dev);
> * _OSC bits the BIOS has granted control of, but its contents are meaningless
> * on failure.
> **/
> -static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 support)
> +static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask,
> + u32 support, u32 *cxl_mask,
> + u32 cxl_support)
> {
> u32 req = OSC_PCI_EXPRESS_CAPABILITY_CONTROL;
> struct acpi_pci_root *root;
> acpi_status status;
> - u32 ctrl, capbuf[6];
> + u32 ctrl, cxl_ctrl, capbuf[8];
As above, why 8?
>
> if (!mask)
> return AE_BAD_PARAMETER;
> @@ -385,20 +435,35 @@ static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 s
> ctrl = *mask;
> *mask |= root->osc_control_set;
>
> + if (is_cxl(root)) {
> + cxl_ctrl = *cxl_mask;
Odd spacing
> + *mask |= root->osc_control_set;
> + }
> +
> /* Need to check the available controls bits before requesting them. */
> do {
> - status = acpi_pci_query_osc(root, support, mask);
> + status = acpi_pci_query_osc(root, support, mask, cxl_support,
> + cxl_mask);
> if (ACPI_FAILURE(status))
> return status;
> - if (ctrl == *mask)
> - break;
> - decode_osc_control(root, "platform does not support",
> - ctrl & ~(*mask));
> + if (is_cxl(root)) {
> + if ((ctrl == *mask) && (cxl_ctrl == *cxl_mask))
> + break;
> + decode_cxl_osc_control(root, "platform does not support",
> + cxl_ctrl & ~(*cxl_mask));
> + } else {
> + if (ctrl == *mask)
> + break;
> + decode_osc_control(root, "platform does not support",
> + ctrl & ~(*mask));
> + }
> ctrl = *mask;
> - } while (*mask);
> + cxl_ctrl = *cxl_mask;
> + } while (*mask || *cxl_mask);
>
> /* No need to request _OSC if the control was already granted. */
> - if ((root->osc_control_set & ctrl) == ctrl)
> + if (((root->osc_control_set & ctrl) == ctrl) &&
> + ((root->cxl_osc_control_set & cxl_ctrl) == cxl_ctrl))
> return AE_OK;
>
> if ((ctrl & req) != req) {
> @@ -410,11 +475,17 @@ static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 s
> capbuf[OSC_QUERY_DWORD] = 0;
> capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set;
> capbuf[OSC_CONTROL_DWORD] = ctrl;
> - status = acpi_pci_run_osc(root, capbuf, mask);
> + if (is_cxl(root)) {
> + capbuf[OSC_CXL_SUPPORT_DWORD] = root->cxl_osc_support_set;
> + capbuf[OSC_CXL_CONTROL_DWORD] = cxl_ctrl;
> + }
> +
> + status = acpi_pci_run_osc(root, capbuf, mask, cxl_mask);
> if (ACPI_FAILURE(status))
> return status;
>
> root->osc_control_set = *mask;
> + root->cxl_osc_control_set = *cxl_mask;
> return AE_OK;
> }
>
> @@ -440,6 +511,18 @@ static u32 calculate_support(void)
> return support;
> }
>
> +static u32 calculate_cxl_support(void)
> +{
> + u32 support;
> +
> + support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT;
> + support |= OSC_CXL_PER_SUPPORT;
> + if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
> + support |= OSC_CXL_NATIVE_HP_SUPPORT;
> +
> + return support;
> +}
> +
> static u32 calculate_control(void)
> {
> u32 control;
> @@ -471,6 +554,16 @@ static u32 calculate_control(void)
> return control;
> }
>
> +static u32 calculate_cxl_control(void)
> +{
> + u32 control;
> +
> + if (pci_aer_available())
> + control |= OSC_CXL_ERROR_REPORTING_CONTROL;
> +
> + return control;
> +}
> +
> static bool os_control_query_checks(struct acpi_pci_root *root, u32 support)
> {
> struct acpi_device *device = root->device;
> @@ -492,6 +585,7 @@ static bool os_control_query_checks(struct acpi_pci_root *root, u32 support)
> static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)
> {
> u32 support, control = 0, requested = 0;
> + u32 cxl_support, cxl_control = 0, cxl_requested = 0;
> acpi_status status;
> struct acpi_device *device = root->device;
> acpi_handle handle = device->handle;
> @@ -515,10 +609,20 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)
> if (os_control_query_checks(root, support))
> requested = control = calculate_control();
>
> - status = acpi_pci_osc_control_set(handle, &control, support);
> + if (is_cxl(root)) {
> + cxl_support = calculate_cxl_support();
> + decode_cxl_osc_support(root, "OS supports", cxl_support);
> + cxl_requested = cxl_control = calculate_cxl_control();
> + }
> +
> + status = acpi_pci_osc_control_set(handle, &control, support,
> + &cxl_control, cxl_support);
> if (ACPI_SUCCESS(status)) {
> if (control)
> decode_osc_control(root, "OS now controls", control);
> + if (cxl_control)
> + decode_cxl_osc_control(root, "OS now controls",
> + cxl_control);
>
> if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
> /*
> @@ -547,6 +651,11 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)
> decode_osc_control(root, "OS requested", requested);
> decode_osc_control(root, "platform willing to grant", control);
> }
> + if (cxl_control) {
> + decode_cxl_osc_control(root, "OS requested", cxl_requested);
> + decode_cxl_osc_control(root, "platform willing to grant",
> + cxl_control);
> + }
>
> dev_info(&device->dev, "_OSC: platform retains control of PCIe features (%s)\n",
> acpi_format_exception(status));
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RFC PATCH 0/2] acpi: add support for CXL _OSC
2022-03-17 15:19 ` [RFC PATCH 0/2] acpi: add support for " Jonathan Cameron
@ 2022-03-18 19:52 ` Verma, Vishal L
0 siblings, 0 replies; 11+ messages in thread
From: Verma, Vishal L @ 2022-03-18 19:52 UTC (permalink / raw)
To: Jonathan.Cameron
Cc: Williams, Dan J, Moore, Robert, linux-cxl, Wysocki, Rafael J,
bhelgaas, linux-acpi
On Thu, 2022-03-17 at 15:19 +0000, Jonathan Cameron wrote:
> On Wed, 16 Mar 2022 18:27:02 -0600
> Vishal Verma <vishal.l.verma@intel.com> wrote:
>
> > Add support for using the CXL definition of _OSC where applicable, and
> > negotiating CXL specific support and control bits.
> >
> > Patch 1 adds the new CXL _OSC UUID, and uses it instead of the PCI UUID
> > when a root port is CXL enabled. It provides a fallback method for
> > CXL-1.1 devices that may not implement the CXL-2.0 _OSC.
>
> _OSC is implemented by the firmware of a host not the device so perhaps
> rephrase this.
Yes good point - I'll reword to say "CXL-1.1 platforms"
>
> >
> > Patch 2 performs negotiation for the CXL specific _OSC support and
> > control bits.
> >
> > I've tested these against a custom qemu[1], which adds the CXL _OSC (in
> > addition to other CXL support). Specifically, _OSC support is added
> > here[2].
> >
> > [1]: https://gitlab.com/jic23/qemu/-/tree/cxl-v7-draft-2-for-test
> > [2]: https://gitlab.com/jic23/qemu/-/commit/31c85054b84645dfbd9e9bb14aa35286141c14cf
>
> Glad that worked :) I was wondering if it was correct.
> There are some issues with that code raised in a recent review, so good
> to have this to test against it going forwards.
Thanks for taking a look and moving the qemu series forward!
>
> Thanks,
>
> Jonathan
>
> >
> > Dan Williams (1):
> > PCI/ACPI: Use CXL _OSC instead of PCIe _OSC
> >
> > Vishal Verma (1):
> > acpi/pci_root: negotiate CXL _OSC
> >
> > include/linux/acpi.h | 11 +++
> > include/acpi/acpi_bus.h | 7 +-
> > drivers/acpi/pci_root.c | 201 ++++++++++++++++++++++++++++++++++------
> > 3 files changed, 187 insertions(+), 32 deletions(-)
> >
> >
> > base-commit: 74be98774dfbc5b8b795db726bd772e735d2edd4
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RFC PATCH 2/2] acpi/pci_root: negotiate CXL _OSC
2022-03-17 16:10 ` Jonathan Cameron
@ 2022-03-18 21:16 ` Verma, Vishal L
0 siblings, 0 replies; 11+ messages in thread
From: Verma, Vishal L @ 2022-03-18 21:16 UTC (permalink / raw)
To: Jonathan.Cameron
Cc: Williams, Dan J, Moore, Robert, linux-cxl, Wysocki, Rafael J,
rafael, bhelgaas, linux-acpi
On Thu, 2022-03-17 at 16:10 +0000, Jonathan Cameron wrote:
> On Wed, 16 Mar 2022 18:27:04 -0600
> Vishal Verma <vishal.l.verma@intel.com> wrote:
>
> > Add full support for negotiating _OSC as defined in the CXL 2.0 spec, as
> > applicable to CXL-enabled platforms. Advertise support for the CXL
> > features we support - 'CXL 2.0 port/device register access', 'Protocol
> > Error Reporting', and 'CL Native Hot Plug'. Request control for 'CXL
> > Memory Error Reporting'. The requests are dependent on CONFIG_* based
> > pre-requisites, and prior PCI enabling, similar to how the standard PCI
> > _OSC bits are determined.
> >
> > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > Cc: "Rafael J. Wysocki" <rafael@kernel.org>
> > Cc: Robert Moore <robert.moore@intel.com>
> > Cc: Dan Williams <dan.j.williams@intel.com>
> > Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
> Hi Vishal,
>
> A few minor queries inline.
>
> Jonathan
Thanks for reviewing Jonathan - fixed up most of the things, see below.
>
[..]
> >
> > +static u32 acpi_osc_ctx_get_pci_control(struct acpi_osc_context *context)
> > +{
> > + return *((u32 *)(context->ret.pointer + 8));
>
> Use the defines for the offsets? sizeof(u32) * OSC_CONTROL_DWORD for example
>
> > +}
> > +
> > +static u32 acpi_osc_ctx_get_cxl_control(struct acpi_osc_context *context)
> > +{
> > + return *((u32 *)(context->ret.pointer + 16));
>
> As above + sizeof(u32) * OSC_CXL_CONTROL_DWORD)
Makes sense, done.
>
> > +}
> > +
> > static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root,
> > - const u32 *capbuf, u32 *retval)
> > + const u32 *capbuf, u32 *pci_control,
> > + u32 *cxl_control)
> > {
> > struct acpi_osc_context context = {
> > .uuid_str = to_uuid(root),
> > @@ -212,18 +246,20 @@ static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root,
> >
> > status = acpi_run_osc(root->device->handle, &context);
> > if (ACPI_SUCCESS(status)) {
> > - *retval = *((u32 *)(context.ret.pointer + 8));
> > + *pci_control = acpi_osc_ctx_get_pci_control(&context);
> > + if (is_cxl(root))
> > + *cxl_control = acpi_osc_ctx_get_cxl_control(&context);
> > kfree(context.ret.pointer);
> > }
> > return status;
> > }
> >
> > -static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root,
> > - u32 support,
> > - u32 *control)
> > +static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, u32 support,
> > + u32 *control, u32 cxl_support,
> > + u32 *cxl_control)
> > {
> > acpi_status status;
> > - u32 result, capbuf[6];
> > + u32 pci_result, cxl_result, capbuf[8];
>
> Nice to set capbuf size off one of the defines if possible, though I'm not
> sure why it is 8 (or why it was 6 before for that mater). I think it should be 5.
Yep, I'm not sure why these were 6. I've added a new define and set it
to 5. Perhaps someone from ACPI might comment if there was a reason for
the extra padding. Rafael or Robert?
>
> >
> > support |= root->osc_support_set;
> >
> > @@ -231,11 +267,21 @@ static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root,
> > capbuf[OSC_SUPPORT_DWORD] = support;
> > capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set;
> >
> > + if (is_cxl(root)) {
> > + cxl_support |= root->cxl_osc_support_set;
> > + capbuf[OSC_CXL_SUPPORT_DWORD] = cxl_support;
> > + capbuf[OSC_CXL_CONTROL_DWORD] = *cxl_control | root->cxl_osc_control_set;
> > + }
> > +
> > retry:
> > - status = acpi_pci_run_osc(root, capbuf, &result);
> > + status = acpi_pci_run_osc(root, capbuf, &pci_result, &cxl_result);
> > if (ACPI_SUCCESS(status)) {
> > root->osc_support_set = support;
> > - *control = result;
> > + *control = pci_result;
> > + if (is_cxl(root)) {
> > + root->cxl_osc_support_set = cxl_support;
> > + *cxl_control = cxl_result;
> > + }
> > } else if (is_cxl(root)) {
> > /*
> > * CXL _OSC is optional on CXL 1.1 hosts. Fall back to PCIe _OSC
> > @@ -358,6 +404,8 @@ EXPORT_SYMBOL_GPL(acpi_get_pci_dev);
> > * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex).
> > * @mask: Mask of _OSC bits to request control of, place to store control mask.
> > * @support: _OSC supported capability.
> > + * @cxl_mask: Mask of CXL _OSC control bits, place to store control mask.
> > + * @cxl_support: CXL _OSC supported capability.
> > *
> > * Run _OSC query for @mask and if that is successful, compare the returned
> > * mask of control bits with @req. If all of the @req bits are set in the
> > @@ -368,12 +416,14 @@ EXPORT_SYMBOL_GPL(acpi_get_pci_dev);
> > * _OSC bits the BIOS has granted control of, but its contents are meaningless
> > * on failure.
> > **/
> > -static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 support)
> > +static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask,
> > + u32 support, u32 *cxl_mask,
> > + u32 cxl_support)
> > {
> > u32 req = OSC_PCI_EXPRESS_CAPABILITY_CONTROL;
> > struct acpi_pci_root *root;
> > acpi_status status;
> > - u32 ctrl, capbuf[6];
> > + u32 ctrl, cxl_ctrl, capbuf[8];
>
> As above, why 8?
>
> >
> > if (!mask)
> > return AE_BAD_PARAMETER;
> > @@ -385,20 +435,35 @@ static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 s
> > ctrl = *mask;
> > *mask |= root->osc_control_set;
> >
> > + if (is_cxl(root)) {
> > + cxl_ctrl = *cxl_mask;
>
> Odd spacing
Fixed.
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2022-03-18 21:16 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-17 0:27 [RFC PATCH 0/2] acpi: add support for CXL _OSC Vishal Verma
2022-03-17 0:27 ` [RFC PATCH 1/2] PCI/ACPI: Use CXL _OSC instead of PCIe _OSC Vishal Verma
2022-03-17 1:47 ` Dan Williams
2022-03-17 15:40 ` Jonathan Cameron
2022-03-17 0:27 ` [RFC PATCH 2/2] acpi/pci_root: negotiate CXL _OSC Vishal Verma
2022-03-17 3:19 ` Dan Williams
2022-03-17 3:49 ` Verma, Vishal L
2022-03-17 16:10 ` Jonathan Cameron
2022-03-18 21:16 ` Verma, Vishal L
2022-03-17 15:19 ` [RFC PATCH 0/2] acpi: add support for " Jonathan Cameron
2022-03-18 19:52 ` Verma, Vishal L
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