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From: Hans de Goede <hdegoede@redhat.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: "Thierry Reding" <thierry.reding@gmail.com>,
	"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
	"Jani Nikula" <jani.nikula@linux.intel.com>,
	"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
	"Rafael J . Wysocki" <rjw@rjwysocki.net>,
	"Len Brown" <lenb@kernel.org>,
	linux-pwm@vger.kernel.org,
	intel-gfx <intel-gfx@lists.freedesktop.org>,
	dri-devel@lists.freedesktop.org,
	"Mika Westerberg" <mika.westerberg@linux.intel.com>,
	linux-acpi@vger.kernel.org
Subject: Re: [PATCH v5 07/16] pwm: crc: Fix period / duty_cycle times being off by a factor of 256
Date: Tue, 28 Jul 2020 22:00:23 +0200
Message-ID: <a05f24ec-3be5-42c7-38b8-69e8a3a2b330@redhat.com> (raw)
In-Reply-To: <20200728193634.GD3703480@smile.fi.intel.com>

Hi,

On 7/28/20 9:36 PM, Andy Shevchenko wrote:
> On Fri, Jul 17, 2020 at 03:37:44PM +0200, Hans de Goede wrote:
>> While looking into adding atomic-pwm support to the pwm-crc driver I
>> noticed something odd, there is a PWM_BASE_CLK define of 6 MHz and
>> there is a clock-divider which divides this with a value between 1-128,
>> and there are 256 duty-cycle steps.
>>
>> The pwm-crc code before this commit assumed that a clock-divider
>> setting of 1 means that the PWM output is running at 6 MHZ, if that
>> is true, where do these 256 duty-cycle steps come from?
>>
>> This would require an internal frequency of 256 * 6 MHz = 1.5 GHz, that
>> seems unlikely for a PMIC which is using a silicon process optimized for
>> power-switching transistors. It is way more likely that there is an 8
>> bit counter for the duty cycle which acts as an extra fixed divider
>> wrt the PWM output frequency.
>>
>> The main user of the pwm-crc driver is the i915 GPU driver which uses it
>> for backlight control. Lets compare the PWM register values set by the
>> video-BIOS (the GOP), assuming the extra fixed divider is present versus
>> the PWM frequency specified in the Video-BIOS-Tables:
>>
>> Device:		PWM Hz set by BIOS	PWM Hz specified in VBT
>> Asus T100TA 	200			200
>> Asus T100HA 	200			200
>> Lenovo Miix 2 8	23437			20000
>> Toshiba WT8-A	23437			20000
>>
>> So as we can see if we assume the extra division by 256 then the register
>> values set by the GOP are an exact match for the VBT values, where as
>> otherwise the values would be of by a factor of 256.
>>
>> This commit fixes the period / duty_cycle calculations to take the
>> extra division by 256 into account.
> 
> So, base clock is 6MHz, then 7 bit divisor. That's what original values
> were for. On top of that there is 8-bit duty cycle control ("divide by 256"
> whatever it means) with the output range 23.437kHz..183Hz.

Right, so that range matches with a clock div of 1*256 (6 MHz/256 = 23437.5KHz)
to 128*256 (6 MHz/(128*256) = 183.1Hz) IOW this patch is correct.

Before this patch the code assumed a clkdiv of 1-128 (*), which leads to a
very different output frequency range.

Regards,

Hans


*) 0-127 really, that is fixed in a followup patch



> 
>>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> ---
>> Changes in v3:
>> - Use NSEC_PER_USEC instead of adding a new (non-sensical) NSEC_PER_MHZ define
>> ---
>>   drivers/pwm/pwm-crc.c | 6 +++---
>>   1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c
>> index 272eeb071147..c056eb9b858c 100644
>> --- a/drivers/pwm/pwm-crc.c
>> +++ b/drivers/pwm/pwm-crc.c
>> @@ -21,8 +21,8 @@
>>   
>>   #define PWM_MAX_LEVEL		0xFF
>>   
>> -#define PWM_BASE_CLK		6000000  /* 6 MHz */
>> -#define PWM_MAX_PERIOD_NS	21333    /* 46.875KHz */
>> +#define PWM_BASE_CLK_MHZ	6	/* 6 MHz */
>> +#define PWM_MAX_PERIOD_NS	5461333	/* 183 Hz */
>>   
>>   /**
>>    * struct crystalcove_pwm - Crystal Cove PWM controller
>> @@ -72,7 +72,7 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm,
>>   
>>   		/* changing the clk divisor, need to disable fisrt */
>>   		crc_pwm_disable(c, pwm);
>> -		clk_div = PWM_BASE_CLK * period_ns / NSEC_PER_SEC;
>> +		clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC);
>>   
>>   		regmap_write(crc_pwm->regmap, PWM0_CLK_DIV,
>>   					clk_div | PWM_OUTPUT_ENABLE);
>> -- 
>> 2.26.2
>>
> 


  reply index

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-17 13:37 [PATCH v5 00/16] acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Hans de Goede
2020-07-17 13:37 ` [PATCH v5 01/16] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase Hans de Goede
2020-07-17 13:37 ` [PATCH v5 02/16] ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) Hans de Goede
2020-07-17 13:37 ` [PATCH v5 03/16] pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() Hans de Goede
2020-07-17 13:37 ` [PATCH v5 04/16] pwm: lpss: Add range limit check for the base_unit register value Hans de Goede
2020-07-17 13:37 ` [PATCH v5 05/16] pwm: lpss: Add pwm_lpss_prepare_enable() helper Hans de Goede
2020-07-28 18:45   ` Andy Shevchenko
2020-07-28 19:49     ` Hans de Goede
2020-07-17 13:37 ` [PATCH v5 06/16] pwm: lpss: Use pwm_lpss_apply() when restoring state on resume Hans de Goede
2020-07-28 18:57   ` Andy Shevchenko
2020-07-28 19:55     ` Hans de Goede
2020-07-29  8:12       ` Andy Shevchenko
2020-08-02 20:51         ` Hans de Goede
2020-08-03  8:41           ` Andy Shevchenko
2020-07-17 13:37 ` [PATCH v5 07/16] pwm: crc: Fix period / duty_cycle times being off by a factor of 256 Hans de Goede
2020-07-28 19:36   ` Andy Shevchenko
2020-07-28 20:00     ` Hans de Goede [this message]
2020-07-29  8:13   ` Andy Shevchenko
2020-07-17 13:37 ` [PATCH v5 08/16] pwm: crc: Fix off-by-one error in the clock-divider calculations Hans de Goede
2020-07-29 10:28   ` Andy Shevchenko
2020-07-17 13:37 ` [PATCH v5 09/16] pwm: crc: Fix period changes not having any effect Hans de Goede
2020-07-29 10:30   ` Andy Shevchenko
2020-07-17 13:37 ` [PATCH v5 10/16] pwm: crc: Enable/disable PWM output on enable/disable Hans de Goede
2020-07-29 10:32   ` Andy Shevchenko
2020-07-17 13:37 ` [PATCH v5 11/16] pwm: crc: Implement apply() method to support the new atomic PWM API Hans de Goede
2020-07-29 10:51   ` Andy Shevchenko
2020-07-17 13:37 ` [PATCH v5 12/16] pwm: crc: Implement get_state() method Hans de Goede
2020-07-17 13:37 ` [PATCH v5 13/16] drm/i915: panel: Add get_vbt_pwm_freq() helper Hans de Goede
2020-07-17 13:37 ` [PATCH v5 14/16] drm/i915: panel: Honor the VBT PWM frequency for devs with an external PWM controller Hans de Goede
2020-07-17 13:44 ` [PATCH v5 15/16] drm/i915: panel: Honor the VBT PWM min setting " Hans de Goede
2020-07-17 13:44   ` [PATCH v5 16/16] drm/i915: panel: Use atomic PWM API " Hans de Goede
2020-07-27  7:41 ` [PATCH v5 00/16] acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Thierry Reding
2020-07-29  8:23   ` Andy Shevchenko
2020-07-29  9:32     ` Hans de Goede
2020-07-30  9:26       ` Thierry Reding
2020-08-01 14:33         ` Hans de Goede
2020-07-29 10:54 ` Andy Shevchenko
2020-08-01 14:38   ` Hans de Goede
2020-08-02 11:25     ` Andy Shevchenko
2020-08-02 19:43       ` Hans de Goede

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