Re: [PATCH] drivers/perf: hisi: update the sccl_id/ccl_id for certain HiSilicon platform

From: John Garry <john.garry@huawei.com>
To: Mark Rutland <mark.rutland@arm.com>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>,
	Will Deacon <will@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	Hanjun Guo <guohanjun@huawei.com>
Subject: Re: [PATCH] drivers/perf: hisi: update the sccl_id/ccl_id for certain HiSilicon platform
Date: Thu, 7 Nov 2019 12:06:24 +0000	[thread overview]
Message-ID: <14e778fb-7b71-3927-134a-415f9a83eae7@huawei.com> (raw)
In-Reply-To: <20191107115650.GA4948@lakrids.cambridge.arm.com>

On 07/11/2019 11:56, Mark Rutland wrote:
> On Thu, Nov 07, 2019 at 11:50:30AM +0000, John Garry wrote:
>> On 07/11/2019 11:40, Will Deacon wrote:
>>> Hi,
>>>
>>> On Thu, Nov 07, 2019 at 03:56:04PM +0800, Shaokun Zhang wrote:
>>>> @@ -338,8 +339,10 @@ void hisi_uncore_pmu_disable(struct pmu *pmu)
>>>>    /*
>>>>     * Read Super CPU cluster and CPU cluster ID from MPIDR_EL1.
>>>> - * If multi-threading is supported, CCL_ID is the low 3-bits in MPIDR[Aff2]
>>>> - * and SCCL_ID is the upper 5-bits of Aff2 field; if not, SCCL_ID
>>>> + * If multi-threading is supported, On Huawei Kunpeng 920 SoC whose cpu
>>>> + * core is tsv110, CCL_ID is the low 3-bits in MPIDR[Aff2] and SCCL_ID
>>>> + * is the upper 5-bits of Aff2 field; while for other cpu types, SCCL_ID
>>>> + * is in MPIDR[Aff3] and CCL_ID is in MPIDR[Aff2], if not, SCCL_ID
>>>>     * is in MPIDR[Aff2] and CCL_ID is in MPIDR[Aff1].
>>>>     */
>>>>    static void hisi_read_sccl_and_ccl_id(int *sccl_id, int *ccl_id)
>>>> @@ -347,12 +350,19 @@ static void hisi_read_sccl_and_ccl_id(int *sccl_id, int *ccl_id)
>>>>    	u64 mpidr = read_cpuid_mpidr();
>>>>    	if (mpidr & MPIDR_MT_BITMASK) {
>>>> -		int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
>>>> -
>>>> -		if (sccl_id)
>>>> -			*sccl_id = aff2 >> 3;
>>>> -		if (ccl_id)
>>>> -			*ccl_id = aff2 & 0x7;
>>>> +		if (read_cpuid_part_number() == HISI_CPU_PART_TSV110) {
>>>> +			int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
>>>> +
>>>> +			if (sccl_id)
>>>> +				*sccl_id = aff2 >> 3;
>>>> +			if (ccl_id)
>>>> +				*ccl_id = aff2 & 0x7;
>>>> +		} else {
>>>> +			if (sccl_id)
>>>> +				*sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 3);
>>>> +			if (ccl_id)
>>>> +				*ccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
>>>> +		}
>>>
>>> [I prefer Mark's version, so please reply to indicate whether or not it
>>>    works for you]
>>
>> Replying on Shaokun's behalf as he appears offline now.
>>
>> In response to "> If TSV110 is always MT, ":
>>
>> It isn't. There are 2 spins of Huawei Kunpeng 920 SoC which includes
>> TaishanV110 aka TSV110: one has the MT bit set and the other without.
> 
> Just to check, for the non-MT variant is the SCCL/CCL assignment
> Aff2/Aff1 as with other non-MT parts?

We don't support any other non-MT parts for this driver.

Thanks,
John

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel