From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Mark Rutland <mark.rutland@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Anshuman Khandual <anshuman.khandual@arm.com>,
linux-kernel@vger.kernel.org, James Morse <james.morse@arm.com>,
Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org>,
kvmarm@lists.cs.columbia.edu
Subject: [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes
Date: Tue, 28 Jan 2020 18:09:03 +0530 [thread overview]
Message-ID: <1580215149-21492-1-git-send-email-anshuman.khandual@arm.com> (raw)
This series is primarily motivated from an adhoc list from Mark Rutland
during our ID_ISAR6 discussion [1]. Besides, it also includes a patch
which does macro replacement for various open bits shift encodings in
various CPU ID registers. This series is based on linux-next 20200124.
[1] https://patchwork.kernel.org/patch/11287805/
Is there anything else apart from these changes which can be accommodated
in this series, please do let me know. Thank you.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-kernel@vger.kernel.org
Anshuman Khandual (6):
arm64/cpufeature: Introduce ID_PFR2 CPU register
arm64/cpufeature: Add DIT and CSV2 feature bits in ID_PFR0 register
arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register
arm64/cpufeature: Define an explicit ftr_id_isar0[] for ID_ISAR0 register
arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register
arm64/cpufeature: Replace all open bits shift encodings with macros
arch/arm64/include/asm/cpu.h | 1 +
arch/arm64/include/asm/sysreg.h | 51 +++++++++++++++++++
arch/arm64/kernel/cpufeature.c | 87 ++++++++++++++++++++++-----------
arch/arm64/kernel/cpuinfo.c | 1 +
arch/arm64/kvm/sys_regs.c | 2 +-
5 files changed, 112 insertions(+), 30 deletions(-)
--
2.20.1
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next reply other threads:[~2020-01-28 12:40 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-28 12:39 Anshuman Khandual [this message]
2020-01-28 12:39 ` [PATCH 1/6] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual
2020-03-20 18:03 ` Suzuki K Poulose
2020-04-09 12:54 ` Will Deacon
2020-04-13 3:32 ` Anshuman Khandual
2020-01-28 12:39 ` [PATCH 2/6] arm64/cpufeature: Add DIT and CSV2 feature bits in ID_PFR0 register Anshuman Khandual
2020-03-20 18:07 ` Suzuki K Poulose
2020-04-02 2:38 ` Anshuman Khandual
2020-04-09 12:55 ` Will Deacon
2020-04-13 3:35 ` Anshuman Khandual
2020-01-28 12:39 ` [PATCH 3/6] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register Anshuman Khandual
2020-03-20 18:11 ` Suzuki K Poulose
2020-04-02 2:38 ` Anshuman Khandual
2020-01-28 12:39 ` [PATCH 4/6] arm64/cpufeature: Define an explicit ftr_id_isar0[] for ID_ISAR0 register Anshuman Khandual
2020-03-20 18:16 ` Suzuki K Poulose
2020-01-28 12:39 ` [PATCH 5/6] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register Anshuman Khandual
2020-03-20 18:19 ` Suzuki K Poulose
2020-04-02 3:00 ` Anshuman Khandual
2020-04-09 12:53 ` Will Deacon
2020-04-13 3:39 ` Anshuman Khandual
2020-01-28 12:39 ` [PATCH 6/6] arm64/cpufeature: Replace all open bits shift encodings with macros Anshuman Khandual
2020-03-20 18:40 ` Suzuki K Poulose
2020-04-02 2:44 ` Anshuman Khandual
2020-02-14 4:23 ` [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes Anshuman Khandual
2020-02-14 15:58 ` Peter Maydell
2020-04-02 2:33 ` Anshuman Khandual
2020-03-20 18:49 ` Suzuki K Poulose
2020-04-06 17:09 ` Will Deacon
2020-04-07 8:50 ` Anshuman Khandual
2020-04-09 13:54 ` Will Deacon
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